An LDO frequency compensation circuit based on voltage-controlled current source

Abstract

The present invention relates to the field of analog integrated circuit technology, and discloses an LDO frequency compensation circuit based on a voltage-controlled current source. The circuit includes an input differential amplifier module, a power regulation module, a frequency compensation module, and a feedback voltage divider module. The output end of the input differential amplifier module is electrically connected to the input end of the frequency compensation module. The frequency compensation module includes a voltage-controlled current source and a compensation capacitor C1. The compensation capacitor C1 cooperates with the voltage-controlled current source to adjust the loop frequency response. Through a multi-stage current mirror plus Miller compensation network, the pole distribution is targetedly optimized. In conjunction with the Miller effect of the compensation capacitor C1, the main pole frequency can be actively lowered, the main pole is kept away from the high frequency region, the loop phase margin is guaranteed, and self-oscillation is fundamentally suppressed, so that the output voltage is stable and without fluctuations.

Description

Technical Field

[0001] The present invention relates to the technical field of analog integrated circuits, and in particular to an LDO frequency compensation circuit based on a voltage-controlled current source. Background Art

[0002] The traditional LDO circuit is mainly composed of a differential input stage, a power adjustment module, and a feedback voltage divider network. The core follows the closed-loop control logic of voltage feedback-error amplification-power adjustment. The differential input stage consists of a pair of differential pair tubes, and the gates are connected to the reference voltage Vref and the feedback voltage Vfb respectively. Using the differential amplification principle, the voltage difference between Vref and Vfb is converted into a current difference, and the error signal is preliminarily extracted. The power adjustment module is based on a large-size power MOS tube. The gate is controlled by the error signal output by the differential input stage. By adjusting the conduction degree of the power tube, the fluctuation of the output voltage Vout is compensated to maintain output stability. The feedback voltage divider network is composed of resistors R1 and R2 in series. The feedback voltage Vfb is obtained by dividing the Vout voltage to realize the sampling and feedback of the output voltage, allowing the LDO to form a negative feedback closed loop.

[0003] However, LDO circuits contain multiple stages of signal amplification and transmission, such as the differential input stage and the power transistor driver stage. The parasitic capacitance and load capacitance of the transistors in each stage introduce multiple high-frequency poles, which cause the signal phase to lag as the frequency increases. When the frequency rises to a certain critical value, the phase superposition of these multiple poles can reach 180°. If the loop gain is still greater than 0 at this point, the LDO circuit will enter a self-oscillation state, and the output voltage will experience continuous, irregular fluctuations.

[0004] Furthermore, traditional LDO circuits rely on single-stage differential amplification to extract error signals. This is affected by the MOS tube's process, temperature, and bias current. In actual circuits, the threshold voltage Vth and mobility μ of the current mirror MOS tube have process deviations. The overall loop gain is limited, and small output voltage changes cannot be accurately amplified. This results in low error signal recognition and delayed power tube adjustment, ultimately leading to poor voltage regulation accuracy.

[0005] Therefore, it is necessary to provide an LDO frequency compensation circuit based on a voltage-controlled current source to solve the above problems. Summary of the Invention

[0006] The purpose of the present invention is to provide a technical solution to solve the problems in the prior art raised in the above background technology.

[0007] To achieve the above object, the present invention adopts the following technical solutions:

[0008] An LDO frequency compensation circuit based on a voltage-controlled current source includes an input differential amplifier module, a power regulation module, a frequency compensation module, and a feedback voltage divider module;

[0009] The power regulation module includes a MOS transistor MP. The current signal output by the input differential amplifier module controls the gate voltage of the MOS transistor MP, thereby adjusting the conduction level of the MOS transistor MP. The source of the MOS transistor MP is the output voltage Vout. The feedback voltage divider module includes a resistor R1 and a resistor R2. The resistors R1 and R2 are connected in series. The resistor R1 is connected to the output voltage Vout. The resistor R2 is grounded.

[0010] The output end of the input differential amplifier module is electrically connected to the input end of the frequency compensation module. The frequency compensation module includes a voltage-controlled current source and a compensation capacitor C1. The compensation capacitor C1 cooperates with the voltage-controlled current source to adjust the loop frequency response.

[0011] The input differential amplifier module includes a differential input stage, a first current mirror, a second current mirror, and a bias circuit. The differential input stage is used to compare the reference voltage Vref with the feedback voltage Vfb and convert it into a current difference. The first current mirror cooperates with the differential input stage to preliminarily amplify the signal and provide a suitable current signal for the subsequent stage. The second current mirror and the bias circuit provide a stable bias current for the differential input stage to ensure that the circuit operates at a suitable static operating point.

[0012] Preferably, the differential input stage includes a MOS transistor M1 and a MOS transistor M2, wherein the MOS transistor M1 and the MOS transistor M2 are a differential pair of transistors, the gate of the MOS transistor M1 is connected to a reference voltage Vref, and the gate of the MOS transistor M2 is connected to a feedback voltage Vfb.

[0013] Preferably, the first current mirror includes a MOS transistor M3, a MOS transistor M4, a MOS transistor M5, and a MOS transistor M6. The MOS transistor M3 and the MOS transistor M4 constitute a first group of current mirrors, and the MOS transistor M5 and the MOS transistor M6 constitute a second group of current mirrors. The gate of the MOS transistor M3 and the gate of the MOS transistor M4 are commonly connected, the drain of the MOS transistor M3 is connected to the gate, and the drain of the MOS transistor M3 is connected to the source of the MOS transistor M1.

[0014] Preferably, the second current mirror includes a MOS transistor M7 and a MOS transistor M8. The source of the MOS transistor M7 and the MOS transistor M8 form a third current mirror group. The gates of the MOS transistor M7 and the MOS transistor M8 are connected in common. The source of the MOS transistor M7 and the source of the MOS transistor M8 are connected to the power bus VDD. The drain of the MOS transistor M7 is connected to the drain of the MOS transistor M4. The drain of the MOS transistor M8 is connected in common to the drain of the MOS transistor M6.

[0015] Preferably, the bias circuit includes a MOS transistor M11 and a MOS transistor M12, the source of the MOS transistor M12 is connected to the power bus VDD, the drain of the MOS transistor M12 is connected to the source of the MOS transistor M11, and the drain of the MOS transistor M11 is connected to the sources of the MOS transistor M1 and the MOS transistor M12 respectively;

[0016] The drain of the MOS transistor M8 is connected to the drain of the MOS transistor M6 and the gate of the MOS transistor MP.

[0017] Preferably, the voltage-controlled current source includes a MOS transistor M9 and a MOS transistor M10, the gate of the MOS transistor M9 is connected to the gate of the MOS transistor M10, the drain of the MOS transistor M9 is connected to the source of the MOS transistor M14, and the source of the transistor M14 is the output voltage Vout2;

[0018] The gate of the MOS transistor M14 is connected to the drain of the MOS transistor M8 and the drain of the MOS transistor M6. The source of the MOS transistor M14 is connected to the power bus VDD. The drain of the MOS transistor M10 and the drain of the MOS transistor M13 are commonly connected and are the feedback voltage signal Vfb. The source of the MOS transistor M13 is connected to the power bus VDD. The gate of the MOS transistor M13 is connected to the bias voltage Vb.

[0019] One end of the compensation capacitor C1 is connected to the drain of the MOS transistor M9 , and the other end of the compensation capacitor C1 is connected to the gate of the MOS transistor M9 .

[0020] Preferably, the voltage-controlled current source includes a MOS transistor M9 and a MOS transistor M10, the gate of the MOS transistor M9 and the gate of the MOS transistor M10 are connected in common, the drain of the MOS transistor M9 is connected to the source of the MOS transistor M14, one end of the compensation capacitor C1 is connected to the drain of the MOS transistor M9, and the other end of the compensation capacitor C1 is connected to the gate of the MOS transistor M9;

[0021] The source of the MOS transistor M14 is connected to the power bus VDD, the drain of the MOS transistor M10 and the drain of the MOS transistor M13 are connected in common and are the feedback voltage signal Vfb, the source of the MOS transistor M13 is connected to the power bus VDD, and the gate of the MOS transistor M13 is connected to the bias voltage Vb;

[0022] The gate of the MOS transistor M14 is connected to the output terminal of the operational amplifier OP, the inverting input terminal of the operational amplifier OP is connected to the output voltage Vout, and the non-inverting input terminal of the operational amplifier OP is connected to the output voltage Vout2.

[0023] Preferably, the voltage-controlled current source includes a MOS transistor M9 and a MOS transistor M10, the gate of the MOS transistor M9 is connected to the gate of the MOS transistor M10, the drain of the MOS transistor M9 is connected to the drain of the MOS transistor M14, the drain and the gate of the MOS transistor M9 are short-circuited, and the source of the transistor M14 is the output voltage Vout2;

[0024] The gate of the MOS transistor M14 is connected to the drain of the MOS transistor M8 and the drain of the MOS transistor M6. The source of the MOS transistor M14 is connected to the power bus VDD. The drain of the MOS transistor M10 and the drain of the MOS transistor M13 are commonly connected and are the feedback voltage signal Vfb. The source of the MOS transistor M13 is connected to the power bus VDD. The gate of the MOS transistor M13 is connected to the bias voltage Vb.

[0025] One end of the compensation capacitor C1 is connected to the output voltage Vout2 , and the other end of the compensation capacitor C1 is grounded.

[0026] Preferably, the voltage-controlled current source includes a MOS transistor M21 and a MOS transistor M22, the source of the MOS transistor M21 is connected to the gate of the MOS transistor M25, the drain of the MOS transistor M25 is connected to the drain of the MOS transistor M23, the source of the MOS transistor M25 is connected to the source of the MOS transistor M26, and then connected to the drain of the MOS transistor M33, the drain of the MOS transistor M26 is connected to the gate of the MOS transistor M22 and the drain of the MOS transistor M24, the drain of the MOS transistor M22 is connected to the drain of the MOS transistor M30, and the source of the MOS transistor M30 is connected. The MOS transistor M28 is connected to the drain of the MOS transistor M28, the gate of the MOS transistor M30 is connected to the gate of the MOS transistor M31, the gate of the MOS transistor M28 is connected to the gate of the MOS transistor M29, the drain of the MOS transistor M31 is connected to the drain of the MOS transistor M35, the gate of the MOS transistor M35 is connected to the gate of the MOS transistor M34, the source of the MOS transistor M35 is connected to the drain of the MOS transistor M37, the source of the MOS transistor M34 is connected to the drain of the MOS transistor M36, and the gate of the MOS transistor M36 is connected to the gate of the MOS transistor M37;

[0027] The drain of the MOS transistor M34 is connected to the gate of the MOS transistor M26 and the source of the MOS transistor M22 respectively, and the source of the MOS transistor M22 is connected to the compensation capacitor C1, and the other end of the compensation capacitor C1 is grounded.

[0028] Preferably, the drain of the MOS transistor M21 is connected to the power bus VDD, the sources of the MOS transistors M23, M24, M28, and M29 are all connected to the power bus VDD, the source of the MOS transistor M21 is also connected to the drain of the MOS transistor M32, and the sources of the MOS transistors M32, M33, M36, and M37 are grounded.

[0029] Technical effects and advantages of the present invention: Compared with the prior art, the LDO frequency compensation circuit based on a voltage-controlled current source proposed in the present invention has the following advantages:

[0030] 1. The present invention uses a multi-stage current mirror plus a Miller compensation network to optimize the pole distribution in a targeted manner. The multi-stage current mirror converts the differential current into a single-ended signal while blocking the reverse coupling of the subsequent stage noise, reducing the additional poles introduced by the parasitic capacitance. The high output impedance of the multi-stage current mirror, combined with the Miller effect of the compensation capacitor C1, can actively lower the main pole frequency, keeping the main pole away from the high frequency region. The compensation capacitor C1 is connected across the high impedance node and uses the equivalent large capacitance generated by the Miller effect to compensate for the phase lag of the multi-stage pole. When the signal frequency increases and the phase superposition approaches 180°, the compensation capacitor C1 provides an additional AC feedback path to ensure the loop phase margin, fundamentally suppressing self-oscillation and making the output voltage stable and without fluctuations.

[0031] 2. The present invention uses a multi-stage current mirror amplifier + operational amplifier OP to gradually amplify the error signal of the differential input stage, significantly improving the loop gain. Compared with traditional single-stage differential amplifiers, the gain can be increased by several times to several times. In addition, the operational amplifier OP, with its high gain and high input impedance characteristics, can amplify the tiny voltage difference between Vout and Vout2, generating a strong drive error signal and accurately controlling the power tube. At the same time, the operational amplifier OP can suppress MOS tube process deviations, such as Vth drift and the impact of temperature changes on gain, greatly improving the recognition of the error signal and making power tube adjustment more timely. Ultimately, the LDO circuit adapts to demanding scenarios with high frequency, high precision, and complex loads, such as RF power supply and high-end analog circuit power supply, significantly improving circuit reliability and performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 1 is a circuit diagram of Embodiment 1 and Embodiment 2 of the present invention;

[0033] Figure 2 1 is a circuit diagram of Embodiment 1 and Embodiment 3 of the present invention;

[0034] Figure 3 1 is a circuit diagram of Embodiment 1 and Embodiment 4 of the present invention;

[0035] Figure 41 and 2 are circuit diagrams of embodiments 1 and 5 of the present invention. DETAILED DESCRIPTION

[0036] The subject matter described herein will now be discussed with reference to exemplary embodiments. It should be understood that these embodiments are discussed solely to enable those skilled in the art to better understand and implement the subject matter described herein, and that the functions and arrangements of the elements discussed may be varied without departing from the scope of this specification. Various examples may omit, substitute, or add various processes or components as needed. Furthermore, features described for some examples may be combined in other examples.

[0037] See also Figures 1 to 4 , the embodiment provided by the present invention: Example 1

[0038] like Figure 1-Figure 4 As shown, an LDO frequency compensation circuit based on a voltage-controlled current source includes an input differential amplifier module, a power regulation module and a feedback voltage divider module;

[0039] The power regulation module includes a MOS transistor MP. The current signal output by the input differential amplifier module controls the gate voltage of the MOS transistor MP, thereby adjusting the conduction level of the MOS transistor MP. The source of the MOS transistor MP is the output voltage Vout. The input differential amplifier module includes a differential input stage, a first current mirror, a second current mirror, and a bias circuit. The differential input stage is used to compare the reference voltage Vref with the feedback voltage Vfb and convert it into a current difference. The first current mirror cooperates with the differential input stage to initially amplify the signal and provide a suitable current signal for the subsequent stage. The second current mirror and the bias circuit provide a stable bias current for the differential input stage to ensure that the circuit operates at a suitable static operating point.

[0040] Specifically, the differential input stage includes MOS transistors M1 and M2. MOS transistors M1 and M2 are a differential pair of transistors, forming an op amp differential input stage. The gate of MOS transistor M1 is connected to a reference voltage Vref, and the gate of MOS transistor M2 is connected to a feedback voltage Vfb. The voltage difference is converted into a current difference through differential amplification. When Vout changes, Vfb changes accordingly, generating a voltage difference ΔV=Vref-Vfb with Vref. This voltage difference causes a differential current ΔI to appear in the drain currents of MOS transistors M1 and M2.

[0041] The first current mirror includes MOS transistors M3, M4, M5, and M6. MOS transistors M3 and M4 constitute a first group of current mirrors, and MOS transistors M5 and M6 constitute a second group of current mirrors. The gate of MOS transistor M3 is connected to the gate of MOS transistor M4, the drain of MOS transistor M3 is connected to the gate, and the drain of MOS transistor M3 is connected to the source of MOS transistor M1. MOS transistors M3, M4, M5, and M6 convert the differential current difference ΔI into a single-ended voltage signal.

[0042] The second current mirror includes a MOS transistor M7 and a MOS transistor M8. The source of the MOS transistor M7 and the MOS transistor M8 form a third current mirror group. The gates of the MOS transistor M7 and the MOS transistor M8 are connected in common. The source of the MOS transistor M7 and the source of the MOS transistor M8 are connected to the power bus VDD. The drain of the MOS transistor M7 is connected to the drain of the MOS transistor M4. The drain of the MOS transistor M8 is connected in common to the drain of the MOS transistor M6.

[0043] The bias circuit includes a MOS transistor M11 and a MOS transistor M12. The source of the MOS transistor M12 is connected to the power bus VDD, the drain of the MOS transistor M12 is connected to the source of the MOS transistor M11, the drain of the MOS transistor M11 is connected to the source of the MOS transistor M1 and the source of the MOS transistor M12 respectively, and the drain of the MOS transistor M8 and the drain of the MOS transistor M6 are connected to the gate of the MOS transistor MP.

[0044] MOS transistors M7, M8, M11, and M12 form a multi-stage current mirror, which together constitute a high-gain amplifier stage, further amplifying the error signal of the differential input stage, thereby improving the overall gain of the operational amplifier.

[0045] The feedback voltage divider module includes resistors R1 and R2. Resistors R1 and R2 are connected in series. Resistor R1 is connected to the output voltage Vout, and resistor R2 is grounded. After the output voltage Vout is divided by resistors R1 and R2, a feedback voltage Vfb connected to the gate of the MOS transistor M2 is obtained. The obtained feedback voltage Vfb is then compared with a reference voltage Vref. If the output voltage Vout changes, such as an increase caused by load changes, Vfb changes accordingly, thereby adjusting the conduction level of the MOS transistor MP.

[0046] The output end of the input differential amplifier module is electrically connected to the input end of the frequency compensation module. The frequency compensation module includes a voltage-controlled current source and a compensation capacitor C1. The compensation capacitor C1 cooperates with the voltage-controlled current source to adjust the loop frequency response. Example 2

[0047] like Figure 1As shown, based on Example 1, due to the differential input stage and the intermediate amplifier stage in the input differential amplifier module, multiple poles are introduced, which may easily lead to insufficient phase margin and self-oscillation.

[0048] Therefore, the voltage-controlled current source includes a MOS transistor M9 and a MOS transistor M10. The gate of the MOS transistor M9 is commonly connected to the gate of the MOS transistor M10. The drain of the MOS transistor M9 is connected to the source of the MOS transistor M14. The source of the transistor M14 is the output voltage Vout2. The gate of the MOS transistor M14 is connected to the drain of the MOS transistor M8 and the drain of the MOS transistor M6. The source of the MOS transistor M14 is connected to the power bus VDD. The drain of the MOS transistor M10 is commonly connected to the drain of the MOS transistor M13 and is the feedback voltage signal Vfb. The source of the MOS transistor M13 is connected to the power bus VDD. The gate of the MOS transistor M13 is connected to the bias voltage Vb. One end of the compensation capacitor C1 is connected to the drain of the MOS transistor M9 and the drain of the MOS transistor M14. The other end of the compensation capacitor C1 is connected to the gate of the MOS transistor M9.

[0049] The compensation capacitor C1 is connected across the drain of MOS tube M14 and the gate of MOS tube M9. Through the Miller effect, the extremely small capacitor can be equivalent to C1×(1+ )( It is a large capacitor that increases the voltage gain of the MOS tube M9-MOS tube M14 stage, which brings the main pole closer to the low frequency and improves the phase margin. When the signal frequency in the circuit increases and the phase changes, the compensation capacitor C1 provides an additional AC feedback path to ensure sufficient phase margin.

[0050] MOS transistors M9 and M10 use a common-source common-gate structure to increase output impedance and enhance the effect of Miller compensation, allowing compensation capacitor C1 to adjust the pole more efficiently while isolating the impact of the subsequent load on the compensation network to ensure the stability of the pole position. The gate of M13 is connected to the bias voltage Vb, which can accurately set its own conduction state and provide a stable quiescent current for the frequency compensation network. This ensures the stability of the DC operating point of the frequency compensation module under different operating conditions and ensures the reliable operation of the compensation function. Example 3

[0051] like Figure 2 As shown, based on Example 1, in order to solve the problems of poor circuit accuracy, weak anti-interference, and slow dynamic response, the voltage-controlled current source includes a MOS transistor M9 and a MOS transistor M10. The gate of the MOS transistor M9 is connected to the gate of the MOS transistor M10, the drain of the MOS transistor M9 is connected to the source of the MOS transistor M14, one end of the compensation capacitor C1 is connected to the drain of the MOS transistor M9, and the other end of the compensation capacitor C1 is connected to the gate of the MOS transistor M9.

[0052] The source of the MOS transistor M14 is connected to the power bus VDD. The drain of the MOS transistor M10 and the drain of the MOS transistor M13 are connected in common and are the feedback voltage signal Vfb. The source of the MOS transistor M13 is connected to the power bus VDD. The gate of the MOS transistor M13 is connected to the bias voltage Vb.

[0053] The gate of the MOS transistor M14 is connected to the output terminal of the operational amplifier OP, the inverting input terminal of the operational amplifier OP is connected to the output voltage Vout, and the non-inverting input terminal of the operational amplifier OP is connected to the output voltage Vout2. The voltage difference between the two is compared in real time:

[0054] If Vout is not equal to Vout2, the output of the operational amplifier OP generates an error signal ΔV, which drives the gate of MOS transistor M14, adjusting the conduction level of M14 and, in turn, changing the current and voltage of the subsequent circuit to make Vout and Vout2 consistent. Due to the high gain of the operational amplifier OP, it can amplify small voltage differences, making error correction more sensitive and improving the voltage regulation accuracy of the entire loop.

[0055] According to Example 1, Vout is divided by resistors R1 and R2 to generate Vfb. At the same time, Vout and Vout2 are input to the operational amplifier OP for comparison. If Vout drifts due to load changes, the output of the operational amplifier OP drives the MOS transistor M14 to adjust the current. The current is then transferred to the Vfb node via the current mirror MOS transistors M9, M10, and M13 of the frequency compensation module, thereby correcting Vout back to the target value. At this time, the compensation capacitor C1 is approximately open-circuited and does not affect the DC bias. The high gain of the operational amplifier OP ensures voltage regulation accuracy.

[0056] When the load changes rapidly or there is high-frequency noise, Vout experiences high-frequency fluctuations. The operational amplifier OP responds quickly and outputs a high-frequency error signal to drive the MOS tube M14. This drives the drain current of the MOS tube M14 to change at high frequency, forming Miller compensation with the compensation capacitor C1, lowering the main pole frequency and compensating for phase lag, thereby preventing the loop from self-excited due to high-frequency phase superposition. Example 4

[0057] like Figure 3 As shown, based on Example 1, in order to be suitable for fast response and noise suppression, the voltage-controlled current source includes a MOS transistor M9 and a MOS transistor M10, the gate of the MOS transistor M9 is connected to the gate of the MOS transistor M10, the drain of the MOS transistor M9 is connected to the drain of the MOS transistor M14, and the source of the transistor M14 is the output voltage Vout2;

[0058] The gate of the MOS transistor M14 is connected to the drain of the MOS transistor M8 and the drain of the MOS transistor M6. The source of the MOS transistor M14 is connected to the power bus VDD. The drain of the MOS transistor M10 and the drain of the MOS transistor M13 are connected in common and are the feedback voltage signal Vfb. The source of the MOS transistor M13 is connected to the power bus VDD. The gate of the MOS transistor M13 is connected to the bias voltage Vb.

[0059] The difference from Example 2 is that the drain and gate of the MOS transistor M9 are short-circuited, one end of the compensation capacitor C1 is connected to the output voltage Vout2, and the other end of the compensation capacitor C1 is grounded. The gate and drain of the MOS transistor M9 are short-circuited, so that when operating in the saturation region, Vgs9 is equal to Vds9, which is equivalent to a diode-connected MOS transistor. The gate-drain short-circuit of the MOS transistor M9 allows the Vgs of the MOS transistor M9 to dynamically change with Vout2. One end of the compensation capacitor C1 is connected to Vout2, and the other end is grounded, becoming the load capacitance of the Vout2 node. For high-frequency signals, the compensation capacitor C1 provides a low-impedance path, directly lowering the high-frequency pole frequency of the Vout2 node, thereby suppressing high-frequency noise and phase mutation. Example 5

[0060] like Figure 4 As shown, based on Example 1, in order to improve the anti-interference ability and output stability of the circuit, the voltage-controlled current source includes a MOS transistor M21 and a MOS transistor M22. The source of the MOS transistor M21 is connected to the gate of the MOS transistor M25, the drain of the MOS transistor M25 is connected to the drain of the MOS transistor M23, the source of the MOS transistor M25 is connected to the source of the MOS transistor M26, and then connected to the drain of the MOS transistor M33. The drain of the MOS transistor M26 is connected to the gate of the MOS transistor M22 and the drain of the MOS transistor M24. The drain of the MOS transistor M22 is connected to the drain of the MOS transistor M30. The drain of the MOS tube M30 is connected to the drain of the MOS tube M28, the gate of the MOS tube M30 is connected to the gate of the MOS tube M31, the gate of the MOS tube M28 is connected to the gate of the MOS tube M29, the drain of the MOS tube M31 is connected to the drain of the MOS tube M35, the gate of the MOS tube M35 is connected to the gate of the MOS tube M34, the source of the MOS tube M35 is connected to the drain of the MOS tube M37, the source of the MOS tube M34 is connected to the drain of the MOS tube M36, and the gate of the MOS tube M36 is connected to the gate of the MOS tube M37;

[0061] The drain of the MOS transistor M34 is connected to the gate of the MOS transistor M26 and the source of the MOS transistor M22 respectively, and the source of the MOS transistor M22 is connected to the compensation capacitor C1 , and the other end of the compensation capacitor C1 is grounded.

[0062] The drain of the MOS transistor M21 is connected to the power bus VDD. The sources of the MOS transistors M23, M24, M28, and M29 are all connected to the power bus VDD. The source of the MOS transistor M21 is also connected to the drain of the MOS transistor M32. The sources of the MOS transistors M32, M33, M36, and M37 are grounded.

[0063] MOS transistor M21 is an input-stage MOS transistor. The error signal of the differential amplifier module is input to the gate of MOS transistor M21. If the output voltage Vout increases, the gate voltage of MOS transistor M21 changes, which in turn causes the source current of MOS transistor M21 to change, thereby triggering the current change of the first-stage current mirror composed of the subsequent MOS transistors M25, MOS transistor M26, MOS transistor M23, and MOS transistor M24.

[0064] The source current change of the MOS transistor M25 is mirrored to the MOS transistor M26, driving the gate of the MOS transistor M22. Since the drain of the MOS transistor M22 is connected to the drain of the MOS transistor M30, the MOS transistors M30, MOS transistors M31, MOS transistors M28, and MOS transistors M29 form a two-stage current mirror. As a result, the mirrored currents of the MOS transistors M30 and MOS transistors M31 are transmitted to the final current mirror of the MOS transistors M34, MOS transistors M35, MOS transistors M36, and MOS transistors M37. The function of each stage of the current mirror is to copy and amplify the current, so that the tiny current change of the MOS transistor M21 generates a significant current in the subsequent stage.

[0065] If the output voltage Vout increases, the current at the Vfb node is pulled down through the subsequent current regulation of the MOS transistor M21, the first-stage current mirror, the MOS transistor M22, the second-stage current mirror, and the last-stage current mirror. This allows the differential amplifier module to detect the Vfb change and correct the output voltage Vout back to a stable value.

[0066] Among them, one end of the compensation capacitor C1 is connected to the source of the MOS tube M22, and the other end is grounded. By using the Miller effect, the source of the MOS tube M22 is a high impedance node. Because the MOS tube M22 is an amplifier tube, the drain is connected to the current mirror, and the source equivalent impedance is high, making the compensation capacitor C1 equivalent to a "multiplier capacitor", Ceq≈C1×(1+ ), It is the voltage gain of the MOS tube M22, which can greatly reduce the main pole frequency, make the main pole closer to the low frequency, suppress the phase superposition of high-frequency signals, compensate for the high-frequency pole phase lag of the multi-stage amplifier circuit, and improve the loop phase margin.

[0067] When high-frequency noise or rapid load changes are present in the circuit, compensation capacitor C1 provides a ground path for the high-frequency current, reducing the high-frequency impedance of the source of MOS transistor M22. This suppresses the interference of high-frequency noise on the Vfb node, ensures the purity of the feedback signal Vfb, and allows the front-stage differential amplifier module to accurately correct the output voltage Vout.

[0068] The above describes the embodiments of the present invention, but the present invention is not limited to the above specific implementation methods. The above specific implementation methods are merely illustrative and not restrictive. Ordinary technicians in this field can also make many forms under the guidance of the present invention, all of which are protected by the present invention.

Claims

1. An LDO frequency compensation circuit based on a voltage-controlled current source, characterized in that: It includes an input differential amplifier module, a power regulation module, a frequency compensation module and a feedback voltage divider module; The power regulation module includes a MOS transistor MP. The current signal output by the input differential amplifier module controls the gate voltage of the MOS transistor MP, thereby adjusting the conduction level of the MOS transistor MP. The source of the MOS transistor MP is the output voltage Vout. The feedback voltage divider module includes a resistor R1 and a resistor R2. The resistors R1 and R2 are connected in series. The resistor R1 is connected to the output voltage Vout. The resistor R2 is grounded. The output end of the input differential amplifier module is electrically connected to the input end of the frequency compensation module. The frequency compensation module includes a voltage-controlled current source and a compensation capacitor C1. The compensation capacitor C1 cooperates with the voltage-controlled current source to adjust the loop frequency response. The input differential amplifier module includes a differential input stage, a first current mirror, a second current mirror, and a bias circuit. The differential input stage is used to compare the reference voltage Vref with the feedback voltage Vfb and convert it into a current difference. The first current mirror cooperates with the differential input stage to preliminarily amplify the signal and provide a suitable current signal for the subsequent stage. The second current mirror and the bias circuit provide a stable bias current for the differential input stage to ensure that the circuit operates at a suitable static operating point. The differential input stage includes a MOS transistor M1 and a MOS transistor M2, wherein the MOS transistor M1 and the MOS transistor M2 are a differential pair of transistors, the gate of the MOS transistor M1 is connected to a reference voltage Vref, and the gate of the MOS transistor M2 is connected to a feedback voltage Vfb; The first current mirror includes a MOS transistor M3, a MOS transistor M4, a MOS transistor M5, and a MOS transistor M6. The MOS transistors M3 and M4 constitute a first group of current mirrors, and the MOS transistors M5 and M6 constitute a second group of current mirrors. The gate of the MOS transistor M3 is connected to the gate of the MOS transistor M4, the drain of the MOS transistor M3 is connected to the gate, and the drain of the MOS transistor M3 is connected to the source of the MOS transistor M1. The second current mirror includes a MOS transistor M7 and a MOS transistor M8. The source of the MOS transistor M7 and the MOS transistor M8 form a third current mirror group. The gates of the MOS transistor M7 and the MOS transistor M8 are connected in common. The source of the MOS transistor M7 and the source of the MOS transistor M8 are connected to the power bus VDD. The drain of the MOS transistor M7 is connected to the drain of the MOS transistor M4. The drain of the MOS transistor M8 is connected in common to the drain of the MOS transistor M6. The bias circuit includes a MOS transistor M11 and a MOS transistor M12. The source of the MOS transistor M12 is connected to the power bus VDD, the drain of the MOS transistor M12 is connected to the source of the MOS transistor M11, and the drain of the MOS transistor M11 is connected to the source of the MOS transistor M1 and the source of the MOS transistor M12 respectively. The drain of the MOS transistor M8 is connected to the drain of the MOS transistor M6 and the gate of the MOS transistor MP.

2. The LDO frequency compensation circuit based on a voltage-controlled current source according to claim 1, characterized in that: The voltage-controlled current source includes a MOS transistor M9 and a MOS transistor M10. The gate of the MOS transistor M9 is connected to the gate of the MOS transistor M10. The drain of the MOS transistor M9 is connected to the source of the MOS transistor M14. The source of the transistor M14 is the output voltage Vout2. The gate of the MOS transistor M14 is connected to the drain of the MOS transistor M8 and the drain of the MOS transistor M6. The source of the MOS transistor M14 is connected to the power bus VDD. The drain of the MOS transistor M10 and the drain of the MOS transistor M13 are commonly connected and are the feedback voltage signal Vfb. The source of the MOS transistor M13 is connected to the power bus VDD. The gate of the MOS transistor M13 is connected to the bias voltage Vb. One end of the compensation capacitor C1 is connected to the drain of the MOS transistor M9 , and the other end of the compensation capacitor C1 is connected to the gate of the MOS transistor M9 .

3. The LDO frequency compensation circuit based on a voltage-controlled current source according to claim 1, characterized in that: The voltage-controlled current source includes a MOS transistor M9 and a MOS transistor M10. The gate of the MOS transistor M9 is connected to the gate of the MOS transistor M10, the drain of the MOS transistor M9 is connected to the source of the MOS transistor M14, one end of the compensation capacitor C1 is connected to the drain of the MOS transistor M9, and the other end of the compensation capacitor C1 is connected to the gate of the MOS transistor M9. The source of the MOS transistor M14 is connected to the power bus VDD, the drain of the MOS transistor M10 and the drain of the MOS transistor M13 are connected in common and are the feedback voltage signal Vfb, the source of the MOS transistor M13 is connected to the power bus VDD, and the gate of the MOS transistor M13 is connected to the bias voltage Vb; The gate of the MOS transistor M14 is connected to the output terminal of the operational amplifier OP, the inverting input terminal of the operational amplifier OP is connected to the output voltage Vout, and the non-inverting input terminal of the operational amplifier OP is connected to the output voltage Vout2.

4. The LDO frequency compensation circuit based on a voltage-controlled current source according to claim 1, characterized in that: The voltage-controlled current source includes a MOS transistor M9 and a MOS transistor M10. The gate of the MOS transistor M9 is connected to the gate of the MOS transistor M10. The drain of the MOS transistor M9 is connected to the drain of the MOS transistor M14. The drain and gate of the MOS transistor M9 are short-circuited. The source of the transistor M14 is the output voltage Vout2. The gate of the MOS transistor M14 is connected to the drain of the MOS transistor M8 and the drain of the MOS transistor M6. The source of the MOS transistor M14 is connected to the power bus VDD. The drain of the MOS transistor M10 and the drain of the MOS transistor M13 are commonly connected and are the feedback voltage signal Vfb. The source of the MOS transistor M13 is connected to the power bus VDD. The gate of the MOS transistor M13 is connected to the bias voltage Vb. One end of the compensation capacitor C1 is connected to the output voltage Vout2 , and the other end of the compensation capacitor C1 is grounded.

5. The LDO frequency compensation circuit based on a voltage-controlled current source according to claim 1, characterized in that: The voltage-controlled current source includes a MOS transistor M21 and a MOS transistor M22. The source of the MOS transistor M21 is connected to the gate of the MOS transistor M25. The drain of the MOS transistor M25 is connected to the drain of the MOS transistor M23. The source of the MOS transistor M25 is connected to the source of the MOS transistor M26 and then to the drain of the MOS transistor M33. The drain of the MOS transistor M26 is connected to the gate of the MOS transistor M22 and the drain of the MOS transistor M24. The drain of the MOS transistor M22 is connected to the drain of the MOS transistor M30. The source of the MOS transistor M30 is connected to the gate of the MOS transistor M22 and the drain of the MOS transistor M24. The drain of the MOS transistor M28 is connected, the gate of the MOS transistor M30 is connected to the gate of the MOS transistor M31, the gate of the MOS transistor M28 is connected to the gate of the MOS transistor M29, the drain of the MOS transistor M31 is connected to the drain of the MOS transistor M35, the gate of the MOS transistor M35 is connected to the gate of the MOS transistor M34, the source of the MOS transistor M35 is connected to the drain of the MOS transistor M37, the source of the MOS transistor M34 is connected to the drain of the MOS transistor M36, and the gate of the MOS transistor M36 is connected to the gate of the MOS transistor M37; The drain of the MOS transistor M34 is connected to the gate of the MOS transistor M26 and the source of the MOS transistor M22 respectively, and the source of the MOS transistor M22 is connected to the compensation capacitor C1, and the other end of the compensation capacitor C1 is grounded.

6. The LDO frequency compensation circuit based on a voltage-controlled current source according to claim 1, characterized in that: The drain of the MOS transistor M21 is connected to the power bus VDD. The sources of the MOS transistors M23, M24, M28, and M29 are all connected to the power bus VDD. The source of the MOS transistor M21 is also connected to the drain of the MOS transistor M32. The sources of the MOS transistors M32, M33, M36, and M37 are grounded.

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