Hard disk management system and method and server

Abstract

The invention discloses a hard disk management system and method and a server, and relates to the technical field of computers, when a plurality of hard disk backboards exist in the server, a backboard identification pin is arranged on an expander of each hard disk backboard, the backboard identification pin is connected to a level output end of a mainboard, and different hard disk backboards are connected with different level output ends. Therefore, the level output by the level output end to the backboard identification pin can only represent one hard disk backboard, and the backboard position is only determined according to the target level number output by the backboard identification pin, so that the accuracy of the backboard position can be improved, and the improvement of the hard disk address management accuracy is facilitated.

Description

Technical Field

[0001] This application relates to the field of computer technology, and particularly to a hard disk management system, method, and server. Background Art

[0002] A storage server is a device mainly used for storing data. To improve its storage capacity, a port expander can be used to expand its ports to connect multiple hard disks. An expander can provide multiple hard disk slots, and each hard disk slot can insert a hard disk in a hot-pluggable manner. The expander can manage these multiple hard disks through its backplane at the same time. A server can access multiple expanders simultaneously.

[0003] In related technologies, a hard disk controller on the motherboard of a storage server can sort multiple hard disk backplanes according to the backplane identifier to obtain the corresponding backplane positions of each hard disk backplane on the controller. Thus, address management is performed for the hard disks corresponding to the hard disk backplanes according to the backplane positions. However, this solution has the problem of incorrect address management. Summary of the Invention

[0004] This application provides a hard disk management system, method, and server to at least solve the problem of incorrect address management in related technologies.

[0005] This application provides a hard disk management system, including: a motherboard and multiple hard disk backplanes;

[0006] A hard disk controller is provided on the motherboard, an expander and a hard disk connector connected to the expander are provided on the hard disk backplane, the expander is connected to the hard disk controller, and the hard disk controller is used to manage the hard disks through the expander;

[0007] Backplane identification pins are provided on the expander, and corresponding level output terminals are also provided on the motherboard. The backplane identification pins are connected to the level output terminals, and the target level signal output from the level output terminals to the backplane identification pins is used to determine the backplane position of the hard disk backplane, and different hard disk backplanes are connected to different level output terminals.

[0008] This application also provides a hard disk management method, which is applied to a hard disk management system. The hard disk management system includes: a motherboard and multiple hard disk backplanes, a hard disk controller is provided on the motherboard, an expander and a hard disk connector connected to the expander are provided on the hard disk backplane, the expander is connected to the hard disk controller, and the backplane identification pins of the expander are connected to the level output terminals of the motherboard. The method includes:

[0009] The expander reads the target level signal of the backplane identification pins;

[0010] The expander reports the target level signal to the hard disk controller and receives the backplane position determined by the hard disk controller according to the target level signal;

[0011] The expander performs address management on the hard disks corresponding to the expander according to the backplane position.

[0012] This application also provides a server, including the foregoing hard disk management system.

[0013] Through this application, when there are multiple hard disk backplanes in the server, a backplane identification pin is set on the expander of each hard disk backplane, and the backplane identification pin is connected to the level output end of the main board, and the level output ends connected by different hard disk backplanes are different. In this way, the level output by the level output end to the backplane identification pin can uniquely represent a hard disk backplane, and the backplane position can be uniquely determined according to the target level signal output by the backplane identification pin, which can improve the accuracy of the backplane position, and thus help improve the accuracy of hard disk address management. Description of the Drawings

[0014] To more clearly illustrate the embodiments of this application, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings in the following description are only some embodiments of this application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0015] Figure 1 is a schematic diagram of hard disk expansion based on a hard disk backplane provided by an embodiment of this application;

[0016] Figure 2 is a schematic structural diagram of a hard disk management system provided by an embodiment of this application;

[0017] Figure 3 is a schematic structural diagram of a group of first level ends and second level ends respectively set for multiple hard disk backplanes provided by an embodiment of this application;

[0018] Figure 4 is a schematic structural diagram of multiple hard disk backplanes sharing the first level end and the second level end provided by an embodiment of this application;

[0019] Figure 5 is a step flowchart of a hard disk management method provided by an embodiment of this application;

[0020] Figure 6 is a step flowchart of another hard disk management method provided by an embodiment of this application. Detailed Embodiments

[0021] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0022] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variation thereof are intended to cover a non-exclusive inclusion, such that a process, method, article or device including a series of elements includes not only those elements but also other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0023] In some servers with storage functions, to improve their storage capacity, hard disk expansion can be performed on them so that the server is connected to multiple hard disks. A common solution is to use a hard disk backplane with an Expander to achieve port expansion. Here, the Expander is usually a Serial Attached SCSI (Small Computer System Interface) Expander (SAS Expander). A hard disk backplane can provide multiple hard disk slots, and each hard disk slot can insert a hard disk. In this way, a relatively large number of hard disks can be expanded to the server through the multiple hard disk slots of multiple hard disk backplanes.

[0024] Figure 1 It is a schematic diagram of hard disk expansion based on a hard disk backplane provided by an embodiment of the present application. Refer to Figure 1 As shown, an example of a hard disk backplane is exemplarily given. In actual applications, a server can have multiple such hard disk backplanes. Each hard disk backplane is connected to the motherboard, and the Expander on the hard disk backplane is connected to one or more hard disk connectors, and each hard disk connector can be connected to a hard disk. Figure 1 N2 hard disk connectors C_N1 to C_N2 are exemplarily given for each Expander. Each hard disk connector can be regarded as a hard disk slot for connecting a hard disk.

[0025] It can be understood that the number of hard disks that the server can expand is the sum of the hard disk slot numbers of all the hard disk backplanes on the server. When the hard disk slot numbers of each hard disk backplane are the same, the number of hard disks M that the server can expand is M = N1 × N2, where N1 is the number of hard disk backplanes and N2 is the number of hard disk slots of each hard disk backplane. For example, for a 4U (1U = 4.445 cm) to 5U high rack-mounted chassis, its commonly used hard disk backplane supports 36 to 60 hot-swappable 3.5-inch hard disk slots to connect 36 to 60 hard disks. When 3 hard disk backplanes are set at the same time, the number of hard disks that the server can expand is 108 to 180.

[0026] After expanding the hard disks through the above solution, it is necessary to manage the addresses of multiple hard disks on each hard disk backplane, that is, to assign addresses to each hard disk, so that the data on the hard disk can be accurately accessed or data can be written to the hard disk according to the hard disk address. The data here can be system data or user data.

[0027] Since multiple hard disk backplanes are connected to the motherboard in a cascaded manner, during the process of managing the addresses of hard disks, it is necessary to first identify the backplane positions corresponding to each of the multiple hard disk backplanes, and then determine the hard disk address range of each hard disk backplane according to the backplane position of each hard disk backplane, so that each hard disk backplane can assign addresses to the multiple hard disks on this hard disk backplane within its own hard disk address range. The backplane position here can also be understood as the physical level of the backplane. For example, when there are three cascaded hard disk backplanes B1, B2, and B3, if their physical levels are 0, 1, and 2 respectively, it means that the hard disk backplanes B1, B2, and B3 are cascaded in the order of their corresponding physical levels 0, 1, and 2, that is, the hard disk backplane B2 is cascaded after the hard disk backplane B1, and the hard disk backplane B3 is cascaded after the hard disk backplane B2. Therefore, the hard disk address range can be assigned to the hard disk backplanes in the order of the physical levels.

[0028] In the related art, the backplane position of a hard disk backplane is determined according to the backplane code (EID, Enclosure Identity) on the hard disk backplane. For example, for three hard disk backplanes B1, B2, and B3 with backplane codes EID1, EID2, and EID3 respectively, they can be sorted according to the backplane codes EID1, EID2, and EID3, and then the backplane position can be determined according to the sorting result. In this way, when the backplane codes of multiple hard disk backplanes in a server are different, the backplane position can be accurately determined according to the backplane code. For example, according to the above backplane codes, the backplane positions of the hard disk backplanes B1, B2, and B3 are respectively: the hard disk backplane B1 is the first backplane corresponding to port port0, corresponding to hard disks HDD0 to HDD34; the hard disk backplane B2 is the second backplane corresponding to port port1, corresponding to hard disks HDD35 to HDD69; the hard disk backplane B3 is the third backplane corresponding to port port2, corresponding to hard disks HDD70 to HDD104.

[0029] However, for the same model of hard disk backplane used when expanding the hard disks of a server, the same model of hard disk backplane has the same backplane code, and the hard disk backplanes with the same backplane code cannot be sorted according to the backplane code, resulting in an incorrect backplane position, and further resulting in an incorrect address management. For example, the hard disk backplane B2 is the first backplane corresponding to port port0, corresponding to hard disks HDD0 to HDD34; the hard disk backplane B1 is the second backplane corresponding to port port1, corresponding to hard disks HDD35 to HDD69; the hard disk backplane B3 is the third backplane corresponding to port port2, corresponding to hard disks HDD70 to HDD104. To correct the incorrect position of the hard disk backplane, it is necessary to manually swap the hard disk backplanes and power on again.

[0030] To solve the above technical problems, the present application sets a backplane identification pin on the expander of each hard disk backplane, and connects this backplane identification pin to the level output terminal of the main board, and different hard disk backplanes are connected to different level output terminals. In this way, the level output by the level output terminal to the backplane identification pin can uniquely represent a hard disk backplane. Determining the backplane position according to the level signal output by this backplane identification pin can improve the accuracy of the backplane position, and further help to improve the accuracy of hard disk address management.

[0031] To enable those skilled in the art of the present technology to better understand the solution of the present application, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0032] Figure 2 The following is a schematic structural diagram of a hard disk management system provided by an embodiment of the present application. As Figure 2 shown, an embodiment of the present application provides a hard disk management system, and a detailed description of this hard disk management system is as follows:

[0033] The hard disk management system of the present application includes a main board and one or more hard disk backplanes. When there are multiple hard disk backplanes, it is necessary to determine the backplane position of each hard disk backplane to determine the hard disk address range of each hard disk backplane. When there is only one hard disk backplane, it may not be necessary to determine the hard disk address range of the hard disk backplane according to the backplane position, and in this case, it will not cause address management errors.

[0034] A hard disk controller is provided on the main board, and an expander and a hard disk connector connected to the expander are provided on the hard disk backplane, and the hard disk connector is used to connect a hard disk. The expander is connected to the hard disk controller, and the hard disk controller is used to manage the hard disk through the expander. Figure 2 Exemplarily, each expander corresponds to N2 hard disk connectors C_1 to C_N2 to connect N2 hard disks.

[0035] A backplane identification pin PN is provided on the expander, and a level output terminal LO also corresponds on the main board. The backplane identification pin is connected to the level output terminal, and the target level signal output from the level output terminal to the backplane identification pin is used to determine the backplane position of the hard disk backplane, and different hard disk backplanes are connected to different level output terminals.

[0036] The above hard disk controller is usually a RAID (Redundant Array of Independent Disks) controller. The hard disk controller is connected to the expanders of multiple hard disk backplanes to manage all the hard disks of multiple hard disk backplanes through the expanders of multiple hard disk backplanes.

[0037] The above backplane identification pin is a pin used to uniquely indicate the hard disk backplane through the target level signal, and can be a GPIO (General-purpose input / output) pin. The present application sets one or more backplane identification pins for each hard disk backplane to connect to the level output terminal of the main board. In order to make the target level signal of the backplane identification pin of each hard disk backplane uniquely represent a hard disk backplane, the backplane identification pins of different hard disk backplanes need to be connected to different level output terminals so that the target level signals of the backplane identification pins of different hard disk backplanes are different.

[0038] When there is one backplane identification pin, at least two level output terminals can be provided on the motherboard. The level signals output by different level output terminals are different, and they can be the first level terminal that outputs a high level and the second level terminal that outputs a low level. At this time, for two hard disk backplanes, the backplane identification pins of the two hard disk backplanes can be respectively connected to these two level terminals. For example, for two hard disk backplanes B1 and B2, the backplane identification pin of hard disk backplane B1 can be connected to the level terminal with a high level, and the backplane identification pin of hard disk backplane B2 can be connected to the level terminal with a low level. Thus, the target level signals corresponding to hard disk backplanes B1 and B2 respectively represent 1 and 0, or the backplane identification pin of hard disk backplane B1 can be connected to the level terminal with a low level, and the backplane identification pin of hard disk backplane B2 can be connected to the level terminal with a high level. Thus, the target level signals corresponding to hard disk backplanes B1 and B2 respectively represent 0 and 1.

[0039] It can be seen that when there is 1 backplane identification pin as above, at most two hard disk backplanes can be distinguished. For the case where the number of hard disk backplanes is 2 or more, more than two hard disk backplanes cannot be distinguished by the target level signal of one backplane identification pin. Therefore, we can set multiple backplane identification pins for each expander to support the distinction of more hard disk backplanes.

[0040] When there are multiple backplane identification pins for each expander, the level output terminals that can be provided on the motherboard include multiple level terminals that output different level signals. In this way, the backplane identification pins of each expander can be connected to one or more of the multiple level terminals, and the combined results of the target level signals of the backplane identification pins of different expanders are different to represent different hard disk backplanes. For example, there are 2 backplane identification pins PN1 and PN2 for each expander, and the level output terminals are the first level terminal LO1 with a high level and the second level terminal LO2 with a low level. Then, the backplane identification pins PN1 and PN2 of the first hard disk backplane can both be connected to the second level terminal LO2, and the corresponding target level signal represents 00; the backplane identification pins PN1 and PN2 of the second hard disk backplane are respectively connected to the first level terminal LO1 and the second level terminal LO2, and the corresponding target level signal represents 01. The backplane identification pins PN1 and PN2 of the third hard disk backplane are respectively connected to the second level terminal LO2 and the first level terminal LO1, and the corresponding target level signal represents 10. The backplane identification pins PN1 and PN2 of the fourth hard disk backplane are both connected to the first level terminal LO1, and the corresponding target level signal represents 11.

[0041] It can be understood that the number of level terminals included in the level output terminal and the backplane identification pins can be flexibly set according to the number of hard disk backplanes. Usually, two level terminals are included in the level output terminal. We can expand the number of target level signals by increasing the number of backplane identifications of each hard disk backplane to distinguish more hard disk backplanes.

[0042] Based on the above backplane identification pins and level output terminals, after the server is started, the expander can read the target level signal output from the level output terminal to the backplane identification pin from its own backplane identification pin. Thus, the expander can report its own target level signal to the hard disk controller. The hard disk controller determines the backplane positions of each hard disk backplane according to the target level signals reported by the expanders on each hard disk backplane of the server and sends them to the expander. The expander can manage the addresses of the hard disks on the hard disk backplane according to the backplane positions and the seed files.

[0043] In some embodiments, the above level output terminal includes at least two level terminals for outputting different level signals, and the backplane identification pins of different expanders are connected to different level terminals. The level output terminal LO may include a first level terminal LO1 for outputting a high level signal and a second level terminal LO2 for outputting a low level signal. In this way, different hard disk backplanes can be distinguished by different combinations of the first level terminal LO1 and the second level terminal LO2. That is to say, in the present application, based on two level terminals, more hard disk backplanes can be distinguished by increasing the number of backplane identification pins. In this way, the circuit complexity of the main board can be reduced as much as possible.

[0044] In some embodiments, referring to Figure 3 As shown, the at least two level terminals include: a first level terminal LO1 connected to the power supply through a pull-up resistor R1 and a second level terminal LO2 grounded through a pull-down resistor R2. In the present application, two simple resistors can be used to implement two level terminals, and the hard disk backplanes can be distinguished with a relatively low circuit complexity.

[0045] One end of the pull-up resistor R1 is connected to the power supply, and the other end serves as the first level terminal LO1. At this time, the power supply pulls the level of the first level terminal LO1 to a high level through the pull-up resistor R1. Thus, the target level signal received by the backplane identification pin connected to the first level terminal LO1 is a high level signal, representing 1. One end of the pull-down resistor R2 is grounded, and the other end serves as the second level terminal LO2. At this time, the ground terminal pulls the level of the second level terminal LO2 to a low level through the pull-down resistor R2. Thus, the target level signal received by the backplane identification pin connected to the second level terminal LO2 is a low level signal, representing 0.

[0046] As can be seen from the above, the number of backplane identification pins of each expander is related to the number of level terminals included in the level output terminal and the number of hard disk backplanes. The number of backplane identification pins of each expander is negatively correlated with the number of level terminals included in the level output terminal and positively correlated with the number of hard disk backplanes. Thus, the number of backplane identification pins can be reasonably set according to the number of level terminals and the number of hard disk backplanes, avoiding setting too many backplane identification pins, which helps to reduce the redundancy of the motherboard circuit, or avoiding insufficient number of backplane identification pins set, resulting in the inability to fully distinguish multiple hard disk backplanes, and improving the accuracy of hard disk address management.

[0047] It can be understood that the number of backplane identification pins of each expander is negatively correlated with the number of level terminals included in the level output terminal and positively correlated with the number of hard disk backplanes, including: when the number of hard disk backplanes is larger and the number of level terminals included in the level output terminal is smaller, the number of backplane identification pins of each expander is larger; when the number of hard disk backplanes is smaller and the number of level terminals included in the level output terminal is larger, the number of backplane identification pins of each expander is smaller.

[0048] In a possible implementation manner, the above relationship between the number of backplane identification pins of each expander, the number of level terminals included in the level output terminal, and the number of hard disk backplanes can be expressed by the following formula:

[0049]

[0050] Where N1 is the number of hard disk backplanes, N3 is the number of backplane identification pins of each expander, and the number of level terminals is 2.

[0051] It can be seen that when the number of hard disk backplanes N1 is 10, 4 backplane identification pins need to be set.

[0052] Table 1 gives an example of the connection between a backplane identification pin and two level terminals.

[0053]

[0054] Table 1

[0055] It can be seen from Table 1 that when each expander has three backplane identification pins, 8 hard disk backplanes can be distinguished.

[0056] The first level terminal and the second level terminal on the above motherboard can be shared by multiple hard disk backplanes, or a set of the first level terminal and the second level terminal can be set for each hard disk backplane. Figure 3 It is a schematic structural diagram of a set of the first level terminal and the second level terminal respectively set for multiple hard disk backplanes provided by an embodiment of the present application. Figure 4 It is a schematic structural diagram of multiple hard disk backplanes sharing the first level terminal and the second level terminal provided by an embodiment of the present application.

[0057] Refer to Figure 3 and Figure 4 As shown, the server includes a main board and three hard disk backplanes. Two backplane identification pins PN1 and PN2 are provided on the expander of each hard disk backplane. The backplane identification pins PN1 and PN2 of the first hard disk backplane are both connected to the first level terminal LO2 of the main board, and the corresponding target level signal corresponds to 00. The backplane identification pin PN1 of the second hard disk backplane is connected to the first level terminal LO1 of the main board, and the backplane identification pin PN2 of the second hard disk backplane is connected to the second level terminal LO2 of the main board, and the corresponding target level signal corresponds to 01. The backplane identification pin PN1 of the third hard disk backplane is connected to the second level terminal LO2 of the main board, and the backplane identification pin PN2 of the third hard disk backplane is connected to the first level terminal LO1 of the main board, and the corresponding target level signal corresponds to 10.

[0058] The difference is that Figure 3 the main board in Figure 4 is provided with three groups of first level terminals LO1 and second level terminals LO2, and the expander of each hard disk backplane is respectively connected to its own first level terminal LO1 and second level terminal LO2.

[0059] It can be seen that Figure 3 there are some redundant circuit structures in Figure 3 For example, the first level terminal LO1 corresponding to the first hard disk backplane. Therefore, compared with Figure 4 the independent connection scheme shown in

[0060] Refer to Figure 3 or Figure 4 As shown, a first memory is also provided on the hard disk backplane. The first memory is connected to the expander, and the first memory is used to store a seed file, and the seed file includes the mapping relationship between the hard disk identifier managed by the expander and the slot identifier managed by the expander.

[0061] Among them, the first memory can be a memory independent of the expander. The first memory can be an EEPROM (Electrically Erasable Programmable Read Only Memory). The data in the first memory can be dynamically refreshed, and such refresh does not require restarting the server, nor restarting the expander and the hard disk backplane. Compared with writing the seed file into the expander which requires restarting the server to update the seed file, the seed file of the present application is written into the first memory. Thus, the seed file in the first memory can be flexibly updated.

[0062] The above hard disk identifier is used to uniquely represent a hard disk in the expander, and the slot identifier is used to uniquely represent a slot of the expander. When the hard disk is connected to the hard disk connector, the mapping relationship between the hard disk identifier and the slot identifier can be constructed.

[0063] The expander can determine the hard disk address range of each hard disk backplane based on the backplane positions of multiple hard disk backplanes, and then allocate addresses to each hard disk according to the mapping relationship between the hard disk identifiers managed by the expander and the slot identifiers managed by the expander in the seed file. For example, when the hard disk address range of the expander is from ADD_1 to ADD_N2, these N2 hard disk addresses can be allocated to N2 hard disks to obtain the hard disk address corresponding to each hard disk identifier. Specifically, the hard disk addresses can be allocated to each hard disk identifier in the order of the slot identifiers.

[0064] The expander can read the seed file from the above first memory and, in combination with the backplane position sent by the hard disk controller, perform address management on the hard disks on the hard disk backplane.

[0065] In a possible implementation, referring to Figure 3 or Figure 4 As shown, an access controller for the first memory is further provided on each hard disk backplane. The expander of the hard disk backplane and the first memory of the hard disk backplane are both connected to the access controller of the hard disk backplane. The access controller of the hard disk backplane is used to control the expander of the hard disk backplane and perform access control on the first memory. Thus, the orderly access of the first memory can be ensured, and access conflicts or access errors can be avoided.

[0066] Among them, the access controller can be implemented by a circuit with logical judgment. For example, a CPLD (Complex Programmable Logic Device) or an FPGA (Field Programmable Gate Array).

[0067] Specifically, after initially writing the seed file into the first memory, the access controller needs to switch the access permission of the first memory to the expander, so that the expander can read the seed file from the first memory.

[0068] After the seed file in the first memory is updated, the access controller needs to switch the access permission of the first memory to the expander, so that the expander can read the updated seed file.

[0069] In addition, the access controller can also control the expander to reset after reading the seed file from the first memory, so that the expander can allocate hard disk addresses according to the seed file.

[0070] In a possible implementation, referring to Figure 3 or Figure 4 As shown, a baseboard controller is also provided on the motherboard. The baseboard controller (Board Management Controller, BMC) is connected to the access controllers of all hard disk backplanes, and the baseboard controller is used to access the first memory of each hard disk backplane through the access controller. In this way, the seed file can be written or updated in the first memory through the baseboard controller, realizing the hot update of the seed file.

[0071] Specifically, the baseboard controller can generate and update the seed file according to actual needs. After generating or updating the seed file, the seed file is written into the first memory through the access controller. Before writing the seed file, the baseboard controller needs to first notify the access controller to switch the access permission of the first memory to the baseboard controller, and then the baseboard controller can write the initially generated seed file or the updated seed file into the first memory.

[0072] When the seed file written by the baseboard controller into the first memory is an updated seed file, in order to make the seed file take effect as soon as possible, the access controller also needs to control the expander to reset, so that the expander can read the updated seed file during the reset process and manage the hard disk addresses according to the updated seed file and the backplane position.

[0073] However, the reset of the expander in the embodiment of the present application does not directly restart the expander, but first tries to clear the physical layer link state of the expander. If clearing the physical layer link state of the expander fails to make the expander reload the seed file, then the access controller resets the internal state machine of the expander to make the expander reload the seed file; if resetting the internal state machine of the expander still cannot reload the seed file, at this time, the expander will be powered off and restarted to reload the seed file.

[0074] It can be seen that if clearing the physical layer link state of the expander can cause the expander to reload the seed file, then there is no need to reset the internal state machine of the expander, nor to restart the expander, and the seed file can be reloaded with the least impact on the operation of the expander.

[0075] If resetting the internal state machine of the expander can cause the expander to reload the seed file, then there is no need to restart the expander, and the seed file can also be reloaded with less impact on the operation of the expander.

[0076] If resetting the internal state machine of the expander cannot cause the expander to reload the seed file either, then the expander can be restarted to ensure successful loading of the seed file. In this way, the reset is implemented layer by layer, and the impact of resetting the expander can be minimized as much as possible.

[0077] The access controller of the hard disk backplane can be connected to the baseboard controller, the first memory, and the expander through I2C (Inter-Integrated Circuit, inter-integrated circuit bus).

[0078] In the embodiments of the present application, the functions of the access controller mainly include three: First, the access controller is used to arbitrate the access order of the baseboard controller and the expander to the first memory; Second, the access controller verifies the updated seed file and sends the verification result information to the baseboard controller; Third, control the expander to be reset and detect whether the expander is successfully reset.

[0079] In the above first function, the access controller acts as the main controller, adopts a multi-master competition arbitration mechanism to coordinate the I2C access conflict between the BMC and the expander. The priority of the baseboard controller writing the seed file to the first memory is higher than that of the expander reading the seed file, and a hardware interrupt trigger preemption mode is implemented. When the baseboard controller writes the seed file, the I2C mode is dynamically adjusted to the exclusive mode of the baseboard controller, and the access of the expander is suspended. After the baseboard controller finishes writing the seed file, the access permission is switched to the expander so that the expander can read the seed file.

[0080] Based on the above hard disk management system, the embodiments of the present application also provide a hard disk management method, which is applied to the aforementioned hard disk management system.

[0081] Figure 5 It is a step flowchart of a hard disk management method provided by the embodiments of the present application. Refer to Figure 5 As shown, the hard disk management method of the embodiments of the present application may include:

[0082] S201: The expander reads the target level signal of the backplane identification pin.

[0083] Specifically, when the expander of each hard disk backplane starts up with the baseboard controller, it reads the target level signals of all backplane identification pins on itself. One or more target level signals of each hard disk backplane form a binary sequence, and the length of the binary sequence is the same as the number of backplane identification pins on the hard disk backplane. When the number of backplane identification pins is 3, the target level signals of each hard disk backplane form a binary sequence with a length of 3. For example, 000, or 001, etc.

[0084] It should be noted that the target level signal of each backplane identification pin of the hard disk backplane corresponds to a bit position in the binary sequence. The bit positions of the target level signals of multiple backplane identification pins of the hard disk backplane in the binary sequence can be set flexibly, and the embodiments of the present application do not limit this.

[0085] S202: The expander reports the target level signal to the hard disk controller and receives the backplane position determined by the hard disk controller according to the target level signal.

[0086] The expander can report the target level signal to the hard disk controller through the bus connection between the expander and the hard disk controller. The hard disk controller can determine the backplane position according to the target level signal and send the backplane position to the expander through the bus connection between the expander and the hard disk controller. For example, as shown in Figure 3 The expander of the first hard disk backplane reports the target level signal 00 to the hard disk controller, the expander of the second hard disk backplane reports the target level signal 01 to the hard disk controller, and the expander of the third hard disk backplane reports the target level signal 10 to the hard disk controller. The hard disk controller determines its backplane position as the first physical layer corresponding to port port0 according to the target level signal 00 and sends it to the first expander. The hard disk controller determines its backplane position as the second physical layer corresponding to port port1 according to the target level signal 01 and sends it to the second expander. The hard disk controller determines its backplane position as the third physical layer corresponding to port port2 according to the target level signal 10 and sends it to the third expander.

[0087] In some possible implementation manners, the hard disk controller determines the backplane position according to the target level signal, including: the hard disk controller sorts multiple hard disk backplanes according to the target level signal and determines the backplane position according to the sorting result. In this way, there is no need to pre-record the mapping relationship between the target level signal and the backplane position, which can save the storage space of the hard disk controller.

[0088] The above sorting can be in ascending or descending order, that is, sorting the binary sequence in ascending or descending order to determine the backplane position according to the sorting result. For example, if the target level signals of three hard disk backplanes B1, B2, and B3 are 000, 001, and 010 respectively, then the sorting result can be obtained as hard disk backplanes B1, B2, and B3, and their backplane positions are the first physical level, the second physical level, and the third physical level respectively.

[0089] In one implementation, the hard disk controller determines the backplane position according to the target level signal, including: the hard disk controller obtains the backplane position corresponding to the target level signal from the preset mapping relationship stored locally, and the preset mapping relationship is used to indicate the mapping relationship between the backplane position and the target level signal. In this way, the hard disk controller can retrieve the backplane position from the mapping relationship, and the algorithm is relatively simple, so the circuit complexity of the hard disk controller can be reduced.

[0090] It can be understood that in practical applications, the method for determining the backplane position can be flexibly selected according to actual needs.

[0091] S203: The expander manages the addresses of the hard disks corresponding to the expander according to the backplane position.

[0092] Specifically, the expander first determines the hard disk address range of the expander according to the backplane position, and then allocates the addresses within this hard disk address range to each hard disk of the expander, so that each hard disk corresponds to a unique address.

[0093] In summary, the hard disk controller of the embodiment of the present application can distinguish each hard disk backplane according to the target level signal reported by the backplane identification pin of the hard disk backplane, so that the backplane position of the hard disk backplane can be accurately determined, which helps to improve the accuracy of the hard disk address range of the hard disk backplane and reduce the address management error rate.

[0094] In one implementation, a first memory connected to the expander of the hard disk backplane is further provided on each hard disk backplane, and a seed file is stored in the first memory. Therefore, the expander manages the addresses of the hard disks corresponding to the expander according to the backplane position, including: the expander reads the seed file from the first memory, and manages the addresses of the hard disks of the expander according to the seed file and the backplane position. The seed file includes the mapping relationship between the hard disk identifier and the slot identifier of the hard disks on the hard disk backplane, and the slot identifier is used to represent the slot of the hard disk on the hard disk backplane. In this way, the expander can further allocate the hard disk addresses more accurately in combination with the seed file, and the accuracy of the hard disk addresses can be improved.

[0095] In one example, the expander can sort the slot identifiers to obtain a slot sequence, and then assign each hard disk address in the hard disk address range corresponding to the backplane position to the hard disk one by one according to the slot sequence, and record the mapping relationship between the slot identifier, the hard disk identifier, and the hard disk address. For example, the hard disk address range is from ADD_1 to ADD_N2, with a total of N2 addresses, and the slot sequence includes C_1 to C_N2. Thus, the hard disk address ADD_1 can be assigned to the hard disk corresponding to the slot identifier C_1, and the mapping relationship between the hard disk address ADD_1, the slot identifier C_1, and the hard disk identifier D_1 is recorded. The hard disk address ADD_2 is assigned to the hard disk corresponding to the slot identifier C_2, and the mapping relationship between the hard disk address ADD_2, the slot identifier C_2, and the hard disk identifier D_2 is recorded,... The hard disk address ADD_N2 is assigned to the hard disk corresponding to the slot identifier C_N2, and the mapping relationship between the hard disk address ADD_N2, the slot identifier C_N2, and the hard disk identifier D_N2 is recorded.

[0096] In another example, the hard disk identifiers can also be sorted to obtain a hard disk identifier sequence, and then each hard disk address in the hard disk address range corresponding to the backplane position is assigned to the hard disk one by one according to the hard disk identifier sequence, and the mapping relationship between the slot identifier, the hard disk identifier, and the hard disk address is recorded. For example, the hard disk address range is from ADD_1 to ADD_N2, with a total of N2 addresses, and the hard disk identifier sequence includes D_1 to D_N2. Thus, the hard disk address ADD_1 can be assigned to the hard disk corresponding to the hard disk identifier D_1, and the mapping relationship between the hard disk address ADD_1, the slot identifier C_1, and the hard disk identifier D_1 is recorded. The hard disk address ADD_2 is assigned to the hard disk corresponding to the hard disk identifier D_2, and the mapping relationship between the hard disk address ADD_2, the slot identifier C_2, and the hard disk identifier D_2 is recorded,... The hard disk address ADD_N2 is assigned to the hard disk corresponding to the hard disk identifier D_N2, and the mapping relationship between the hard disk address ADD_N2, the slot identifier C_N2, and the hard disk identifier D_N2 is recorded.

[0097] In yet another example, a preset mapping algorithm can be called to calculate the hard disk address of each hard disk based on the hard disk identifier or the slot identifier and the hard disk range address, and record the mapping relationship between the hard disk identifier, the slot identifier, and the hard disk address.

[0098] In summary, the embodiments of the present application can distinguish the backplane positions of different hard disk backplanes through the target level signal output by the backplane identifier pin on the expander. When an error occurs in the backplane position of the hard disk backplane, the baseboard controller can be restarted to update the backplane position of the hard disk backplane, avoiding manual swapping of the hard disk backplane, which helps to improve service continuity.

[0099] In some embodiments, an access controller for the first memory is further provided on the hard disk backplane, and both the expander and the first memory are connected to the access controller. Therefore, for the expander to read the seed file from the first memory, the access controller switches the access permission of the first memory to the expander, enabling the expander to read the seed file from the first memory. In this way, the access to the first memory can be accurately controlled by the access controller, which helps to ensure the security of the seed file.

[0100] After detecting that the seed file in the first memory has been updated, the access controller can switch the access permission of the first memory to the expander. In this way, the reading of the seed file can be realized in real time, improving the real-time performance of the hot update of the seed file.

[0101] In a possible implementation, a baseboard controller is further provided on the motherboard, and the baseboard controller is connected to the above-mentioned access controller. Based on this, the hard disk address management method of the present application further includes: the baseboard controller generates a seed file; the baseboard controller obtains the access permission of the first memory through the access controller to write the seed file into the first memory. In this way, the security of the seed file in the first memory can be further improved.

[0102] After generating the seed file, the baseboard controller can notify the access controller to switch the permission. When the access controller replies with a successful permission switch message, the baseboard controller can write the seed file into the first memory.

[0103] To further improve the security of the seed file, the baseboard controller can encrypt the seed file and send the encrypted seed file to the first memory for storage. In addition, when the baseboard controller starts up, it can also detect whether there is a seed file in the first memory. If there is no seed file, it generates a seed file, encrypts the seed file and writes it into the first memory; if there is a seed file in the first memory, then there is no need to generate a seed file or write a seed file into the first memory, but the expander directly reads the seed file from the first memory for hard disk address management. In this way, the time consumed in the processes of generating, encrypting and writing the seed file can be saved, which helps to improve the server startup efficiency.

[0104] In the related art, the above-mentioned seed file is stored in the expander. When the seed file needs to be updated, the server needs to be restarted so that the expander reloads the seed file. However, during the process of restarting the server, the hard disk controller needs to re-initialize the physical link and re-determine the backplane position of the hard disk backplane, resulting in a long interruption of the services provided by the server and a greater impact. To solve this problem, in a possible implementation manner, after the system initially writes the seed file, the embodiments of the present application can also dynamically update the above-mentioned seed file to adjust the mapping relationship between the hard disk identifier and the slot identifier. Specifically, the baseboard controller updates the seed file to obtain the access permission of the first memory through the access controller, and writes the updated seed file into the first memory; then, the access controller controls the expander to reset, so that the expander performs address management on the hard disks of the expander according to the updated seed file. The embodiments of the present application can control the expander to reset after updating the seed file, so that the seed file takes effect in the expander, which not only realizes the hot update of the seed file, but also can take effect in real time. Since the seed file is stored in the first memory, it is not necessary to restart the entire server, but only the expander needs to be reset.

[0105] When the seed file is incorrect, the baseboard controller can update the seed file. Specifically, an update switch can be set on the baseboard controller. When the update switch is turned on, the baseboard controller can update the seed file. Of course, the update switch can be operated by the user, or the baseboard controller can monitor the seed file to automatically start the update of the seed file when an abnormality occurs.

[0106] It can be understood that the reset of the expander in the present application is used to make the seed file take effect. Therefore, it is not necessary to restart the entire expander, and only the process of controlling the expander to start reading the seed file again is required. In this way, the restart of the expander can be avoided as much as possible, the process of making the seed file take effect can be simplified, and time can be saved.

[0107] The above-mentioned access controller in the embodiments of the present application controls the access of the baseboard controller and the expander to the first memory based on the access priorities of the baseboard controller and the expander. Considering that the baseboard controller is used to write the seed file into the first memory, and the expander performs address management based on the seed file, the embodiments of the present application set the access priority of the baseboard controller to be higher than that of the expander.

[0108] In an implementation manner of the embodiment of the present application, the access controller switches the access right of the first memory to the expander, including: the access controller determines the first access state of the baseboard controller to the first memory, and when the first access state indicates that the baseboard controller is accessing the first memory, the access controller switches the access right of the first memory to the expander after the baseboard controller finishes accessing. In this way, it is realized that the seed file is written first and then read, which can shorten the effective delay of the seed file as much as possible, make the seed file take effect faster, and avoid the long time of hard disk address management error caused by the wrong seed file.

[0109] The above first access loading is used to indicate the access state of the baseboard controller to the first memory, and may include: accessing or not accessing. Accessing includes that the baseboard controller is writing a seed file into the first memory, and the written seed file may be a newly generated seed file or an updated seed file.

[0110] When the first access state indicates that the baseboard controller is not accessing the first memory, the access controller can immediately switch the access right of the first memory to the expander so that the expander can read the seed file in the first memory.

[0111] Of course, when the above expander is accessing the seed file of the first memory, if the baseboard controller needs to write a seed file into the first memory, the request of the baseboard controller to write the seed file can be preferentially processed. Specifically, the baseboard controller obtains the access right of the first memory through the access controller to write the updated seed file into the first memory, including: the access controller determines the second access state of the expander to the first memory; the access controller stops the access of the expander and switches the access right of the first memory to the baseboard controller; when the second access state indicates that the expander is accessing the seed file in the first memory, after writing the updated seed file into the first memory, the access controller switches the access right of the first memory to the expander. In this way, the seed file can be preferentially updated, and the access to the seed file can be immediately started after the seed file is updated, so that the effective delay of the seed file can be shortened as much as possible.

[0112] It can be understood that when the baseboard controller needs to access the first memory, regardless of whether the second access state indicates that the expander is accessing the seed file of the first memory or not accessing the seed file of the first memory, the access controller of the embodiment of the present application will stop the access of the expander and start the process of the baseboard controller writing the seed file. Compared with writing the seed file after the expander finishes accessing the seed file, the present application can save time.

[0113] After the updated seed file is written into the first memory, the access controller needs to control the expander to reset so that the expander can manage the addresses of the hard disks of the expander according to the updated seed file. This process specifically includes: First, the access controller obtains the first verification information from the baseboard controller and obtains the second verification information from the updated seed file in the first memory; Then, the access controller determines whether the update of the seed file is successful according to the first verification information and the second verification information; Then, after determining that the update of the seed file is successful, the access controller controls the expander to reset so that the expander reads the updated seed file; After determining that the update of the seed file fails, the access controller sends a failure message to the baseboard controller to return to the step of the baseboard controller to update the seed file, so as to write the re-updated seed file into the first memory until the update of the seed file is successful. In this way, the correct update of the seed file can be ensured through verification, thereby improving the accuracy of address allocation.

[0114] Among them, the first verification information can be generated by the baseboard controller according to the content of the updated seed file. The first verification information of different seed files is different, so that it can be verified whether the seed file is updated successfully according to the first verification information. The second verification information can be generated by the access controller according to the content of the updated seed file received in the first memory. When the algorithms for the baseboard controller to generate the first verification information and the access controller to generate the second verification information are the same, for the same seed file, its first verification information and second verification information are the same. When the baseboard controller generates the first verification information and the access controller generates the second verification information using a pair of algorithms, for the same seed file, there is a fixed conversion relationship between its first verification information and second verification information.

[0115] In one example, the above access controller determines whether the update of the seed file is successful according to the first verification information and the second verification information, which may include: If the first verification information and the second verification information are consistent, it means that the update of the seed file is successful; If the first verification information and the second verification information are inconsistent, it means that the update of the seed file fails.

[0116] In another example, the above access controller determines whether the update of the seed file is successful according to the first verification information and the second verification information, which may include: Performing an operation on the first verification information to obtain an operation result, and determining whether the operation result is consistent with the second verification information. If they are consistent, it means that the update of the seed file is successful; If they are inconsistent, it means that the update of the seed file fails.

[0117] In yet another example, for the above access controller to determine whether the update of the seed file is successful based on the first verification information and the second verification information, it may include: performing an operation on the second verification information to obtain an operation result, and determining whether the operation result is consistent with the first verification information. If they are consistent, it means that the update of the seed file is successful; if not, it means that the update of the seed file fails.

[0118] The process by which the above access controller controls the extender to reset may include: the access controller generates a reset signal to perform corresponding reset on the extender according to the level of the reset signal. Different levels of reset signals correspond to different degrees of reset. It can be understood that when the level of the reset signal is lower, the degree of reset is lower, and the impact of the reset on the operation of the extender is smaller; conversely, when the level of the reset signal is higher, the degree of reset is higher, and the impact of the reset on the operation of the extender is greater. In this way, different degrees of reset can be performed according to the actual situation, and a lower level of reset is preferably selected to reduce the impact of the reset on the operation of the extender.

[0119] Specifically, a reset signal of the lowest level can be preferably generated to perform the minimum degree of reset. After the reset fails, the level of the reset signal can be increased to perform a higher degree of reset. In this way, it loops continuously until the reset is successful. For example, a reset signal for clearing the physical layer link state can be preferably generated to first clear the physical layer link state to achieve reset; if the reset fails, a reset signal for resetting the internal state machine can be generated to reset the internal state machine of the extender to achieve reset; if the reset still fails, a reset signal for power-off restart can be generated to achieve reset by powering off and restarting the extender. It can be seen that after each reset fails, the degree of the next reset is higher, and the impact on the operation of the extender is greater.

[0120] To achieve the above step-by-step reset, after the access controller generates a reset signal each time to perform corresponding reset on the extender according to the level of the reset signal, the access controller also needs to determine whether it receives a reset success signal; then, when the access controller does not receive a reset success signal, it updates the reset signal according to the level of the reset signal and returns to the step of performing corresponding reset on the extender according to the level of the reset signal. In this way, the access controller can update the level of the reset signal after each reset fails to perform reset through a higher-level reset signal, achieving reset in a way of gradually increasing the level, so as to minimize the impact of the reset on the operation of the extender and shorten the reset duration.

[0121] Of course, when the access controller receives the reset success signal, it means that the extender has been successfully reset and the seed file takes effect in the extender. At this time, the access controller will no longer continue to generate the reset signal and stop further resetting. Specifically, after sending the reset signal to the extender, the access controller can wait for a period of time. If the reset success signal has not been received after the waiting time exceeds the preset time threshold, it means that the reset has failed. At this time, the reset signal can be updated.

[0122] In one implementation, the preset time threshold to be waited after sending the reset signal can be positively correlated with the level of the reset signal. When the level of the reset signal is lower, the preset time threshold is smaller; when the level of the reset signal is higher, the preset time threshold is larger. In this way, the waiting time can be flexibly set, and different waiting times can be performed for reset signals of different levels.

[0123] In some implementations, updating the reset signal according to the level of the reset signal includes: the access controller determines the target level of the reset signal according to the current level of the reset signal, and the target level is higher than the current level; then, the access controller generates a reset signal of the target level as the updated reset signal, and the pulse durations corresponding to reset signals of different levels are different. In this way, different levels of resets can be distinguished according to the pulse duration, different levels of reset signals can be distinguished more simply, and it helps to reduce the generation time of the reset signal.

[0124] Specifically, the process of updating the level of the reset signal can be to add an update step size to the level. For example, the update step size can be 1. When the current level is 1, the updated target level can be 1 + 1 = 2; when the current level is 2, the updated target level can be 2 + 1 = 3, and so on until the highest level is reached.

[0125] In the embodiments of the present application, after determining the target level, the pulse duration corresponding to the target level can be determined according to the mapping relationship between the level and the pulse duration, and then the updated reset signal can be generated according to the pulse duration. The pulse duration of a higher level is greater than that of a lower level.

[0126] The above reset signals of different levels include at least one of the following: a reset signal for clearing the physical layer link state, a reset signal for resetting the internal state machine, and a reset signal for power-off restart. Among them, the reset signal for clearing the physical layer link state is the lowest-level reset signal, the level of the reset signal for resetting the internal state machine is higher than that of the reset signal for clearing the physical layer link state, and the level of the reset signal for power-off restart is the highest. The embodiments of the present application can cover all levels of reset of the extender through three different levels of reset signals.

[0127] The above reset signal for clearing the physical layer link state is used to implement a physical layer reset, which can be referred to as a soft reset. It can re-initialize the SAS link and cause the expander to reload. The low-level pulse duration can be 5 microseconds (μs). When the expander reloads successfully, it will pull down the corresponding GPIO pin to notify the access controller. The pin through which the expander sends the reset success signal is different from the aforementioned backplane identification pin.

[0128] The reset signal for resetting the internal state machine can re-initialize the firmware of the Expander, and its low-level pulse duration can be 100 microseconds.

[0129] The reset signal for power-off restart can cut off the power of the expander to restart the expander. However, the first memory and the access controller on the hard disk backplane will not restart, so as to ensure that the seed file in the first memory will not be lost. The low-level pulse duration of the reset signal for power-off restart can be 2 milliseconds (ms).

[0130] In one example, the access controller can first generate a reset signal with a 5-microsecond low-level pulse to clear the physical layer link state of the expander, re-initialize the SAS link, and cause the expander to reload the seed file. If the reset success signal replied by the expander is not received within the preset duration, then a reset signal with a 100-microsecond low-level pulse is generated to reset the internal state machine of the expander and cause the expander to reload the seed file. If the reset success signal replied by the expander is not received within the preset duration, such as 5 seconds, then a reset signal with a 2-millisecond low-level pulse is generated to perform a power-off restart on the expander and cause the expander to load the seed file.

[0131] In summary, in the embodiments of the present application, in a server with multiple hard disk backplanes, a backplane identification pin is set for the expander of each hard disk backplane. The backplane identification pin is connected to the level output terminal on the motherboard, and the expanders of different hard disk backplanes are connected to different level output terminals. Thus, the expanders of different hard disk backplanes output different target level signals through the backplane identification pins, corresponding to different binary sequences, which are used to uniquely represent a hard disk backplane. Thus, after the expander is started, it reads the target level signal and reports it to the hard disk controller on the motherboard, so that the hard disk controller determines the backplane position according to the target level signal and accurately allocates the hard disk address range for the hard disk backplane.

[0132] Figure 6 is a flowchart of the steps of another hard disk management method provided by the embodiments of the present application. Refer to Figure 6 As shown, the above hard disk management method of the present application includes:

[0133] S301: The baseboard controller generates a seed file and obtains the access permission of the first memory through the access controller to write the seed file into the first memory.

[0134] S302: The expander reads the target level signal of the backplane identification pin and reports the target level signal to the hard disk controller.

[0135] S303: The hard disk controller sorts multiple hard disk backplanes according to the target level signal and determines the backplane positions according to the sorting results for sending to the expander.

[0136] S304: The hard disk controller obtains the backplane positions corresponding to the target level signal from the preset mapping relationship stored locally for sending to the expander.

[0137] Wherein, the preset mapping relationship is used to indicate the mapping relationship between the backplane positions and the target level signals.

[0138] After the hard disk controller determines the backplane positions according to S303 or S304, it sends the backplane positions to the expander.

[0139] S305: After the baseboard controller updates the seed file, the access controller determines the second access state of the expander to the first memory.

[0140] S306: When the second access state indicates being in access, the access controller stops the access of the expander and switches the access permission of the first memory to the baseboard controller to write the updated seed file into the first memory.

[0141] S307: The access controller obtains the first check information from the baseboard controller and obtains the second check information from the updated seed file in the first memory to determine whether the seed file update is successful according to the first check information and the second check information.

[0142] S308: When the seed file update fails, the access controller sends a failure message to the baseboard controller to return to the step of updating the seed file by the baseboard controller.

[0143] S309: When the seed file update is successful, the access controller generates a reset signal.

[0144] S310: The access controller performs corresponding reset on the expander according to the level of the reset signal, and different levels of reset signals correspond to different degrees of reset.

[0145] S311: When the access controller does not receive a reset success signal, it determines the target level of the reset signal according to the current level of the reset signal and generates a reset signal of the target level as the updated reset signal to return to the step of performing corresponding reset on the expander according to the level of the reset signal.

[0146] Among them, the pulse durations corresponding to reset signals of different levels are different, and the target level is higher than the current level.

[0147] Among them, the reset signal includes at least one of the following: a reset signal for clearing the physical layer link state, a reset signal for resetting the internal state machine, and a reset signal for power-off restart.

[0148] S312: When the access controller receives a reset success signal, it determines the first access state of the substrate controller to the first memory, and when the first access state indicates that it is accessing, after the substrate controller finishes accessing, it switches the access permission of the first memory to the expander.

[0149] S313: The expander performs address management on the hard disks of the expander according to the seed file and the backplane position.

[0150] Among them, the seed file includes the mapping relationship between the hard disk identifiers and the slot identifiers of the hard disks on the hard disk backplane, and the slot identifier is used to represent the slot of the hard disk on the hard disk backplane.

[0151] It can be understood that the order between the above steps is not fixed, and the order between the above steps can be flexibly adjusted when they are independent of each other.

[0152] The embodiment of the present application also provides a server, including the foregoing hard disk management system.

[0153] It can be understood that the server in the embodiment of the present application can be a storage server, or any other server with a large demand for storage space. The embodiment of the present application is not limited to the storage server.

[0154] The server of the present application can refer to the detailed description of the foregoing hard disk management system, and will not be elaborated here.

[0155] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0156] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0157] The above has introduced in detail a hard disk management system, method and server provided by the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of the present application, several improvements and modifications can also be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A hard disk management system, characterized in that, Including: A main board and a plurality of hard disk backplanes; A hard disk controller is provided on the main board, an expander and a hard disk connector connected to the expander are provided on the hard disk backplane, the expander is connected to the hard disk controller, and the hard disk controller is used to manage the hard disk through the expander; A backplane identification pin is provided on the expander, and a corresponding level output terminal is also provided on the main board. The backplane identification pin is connected to the level output terminal, and the target level signal output from the level output terminal to the backplane identification pin is used to determine the backplane position of the hard disk backplane. Different hard disk backplanes are connected to different level output terminals.

2. The system according to claim 1, wherein The level output terminal includes at least two level terminals for outputting different level signals, and the backplane identification pins of different expanders are connected to different level terminals.

3. The system according to claim 2, wherein At least two of the level terminals include: a first level terminal connected to the power supply through a pull-up resistor and a second level terminal grounded through a pull-down resistor.

4. The system according to claim 2, wherein The number of backplane identification pins of the expander is related to the number of level terminals included in the level output terminal and the number of hard disk backplanes. The number of backplane identification pins of each expander is negatively correlated with the number of level terminals included in the level output terminal and positively correlated with the number of hard disk backplanes.

5. The system according to any one of claims 1 to 4, characterized in that, A first memory is further provided on the hard disk backplane. The first memory is connected to the expander, and the first memory is used to store a seed file, and the seed file includes a mapping relationship between the hard disk identifier managed by the expander and the slot identifier managed by the expander.

6. The system according to claim 5, characterized in that, An access controller for the first memory is further provided on the hard disk backplane. The expander and the first memory are both connected to the access controller, and the access controller is used to control the expander and perform access control on the first memory.

7. The system according to claim 6, wherein A baseboard controller is further provided on the main board. The baseboard controller is connected to the access controller, and the baseboard controller is used to access the first memory through the access controller.

8. A hard disk management method, characterized in that, Applied to a hard disk management system, the hard disk management system includes: a main board and a plurality of hard disk backplanes. A hard disk controller is provided on the main board, an expander and a hard disk connector connected to the expander are provided on the hard disk backplane, the expander is connected to the hard disk controller, and the backplane identification pin of the expander is connected to the level output terminal of the main board. The method includes: The expander reads the target level signal of the backplane identification pin; The expander reports the target level signal to the hard disk controller and receives the backplane position determined by the hard disk controller according to the target level signal; The expander performs address management on the hard disk corresponding to the expander according to the backplane position.

9. The method according to claim 8, wherein The hard disk controller determines the backplane position according to the target level signal, including: The hard disk controller sorts the plurality of hard disk backplanes according to the target level signal and determines the backplane position according to the sorting result.

10. The method according to claim 8, wherein The hard disk controller determines the backplane position according to the target level signal, including: The hard disk controller obtains the backplane position corresponding to the target level signal from a preset mapping relationship stored locally, where the preset mapping relationship is used to indicate the mapping relationship between the backplane position and the target level signal.

11. The method according to claim 8, characterized in that, A first memory connected to the expander is further provided on the hard disk backplane; The expander performs address management on the hard disks corresponding to the expander according to the backplane position, including: The expander reads a seed file from the first memory, and performs address management on the hard disks of the expander according to the seed file and the backplane position. The seed file includes the mapping relationship between the hard disk identifiers and the slot identifiers of the hard disks on the hard disk backplane, and the slot identifier is used to represent the slot of the hard disk on the hard disk backplane.

12. The method according to claim 11, wherein An access controller for the first memory is further provided on the hard disk backplane. Both the expander and the first memory are connected to the access controller. The expander reads the seed file from the first memory, including: The access controller switches the access permission of the first memory to the expander, so that the expander reads the seed file from the first memory.

13. The method according to claim 12, wherein A baseboard controller is further provided on the motherboard. The baseboard controller is connected to the access controller. The method further includes: The baseboard controller generates the seed file; The baseboard controller obtains the access permission of the first memory through the access controller to write the seed file into the first memory.

14. The method according to claim 13, characterized in that, The method further includes: The baseboard controller updates the seed file; The baseboard controller obtains the access permission of the first memory through the access controller to write the updated seed file into the first memory; The access controller controls the expander to reset, so that the expander performs address management on the hard disks of the expander according to the updated seed file.

15. The method according to claim 14, wherein The access controller switches the access permission of the first memory to the expander, including: The access controller determines the first access state of the baseboard controller to the first memory; When the first access state indicates ongoing access, the access controller switches the access permission of the first memory to the expander after the baseboard controller finishes accessing.

16. The method according to claim 14, characterized in that, The baseboard controller obtains the access permission of the first memory through the access controller to write the updated seed file into the first memory, including: The access controller determines the second access state of the expander to the first memory; The access controller stops the access of the expander and switches the access permission of the first memory to the baseboard controller; When the second access state indicates ongoing access, after writing the updated seed file into the first memory, the access controller switches the access permission of the first memory to the expander.

17. The method according to claim 14, characterized in that The access controller controls the expander to reset, including: The access controller generates a reset signal to perform corresponding reset on the expander according to the level of the reset signal, and different levels of reset signals correspond to different degrees of reset.

18. The method according to claim 17, characterized in that, After the access controller generates a reset signal to perform corresponding reset on the expander according to the level of the reset signal, it further includes: The access controller determines whether a reset success signal is received; When the access controller does not receive the reset success signal, it updates the reset signal according to the level of the reset signal and returns to the step of performing corresponding reset on the expander according to the level of the reset signal.

19. The method according to claim 18, wherein The updating the reset signal according to the level of the reset signal includes: The access controller determines the target level of the reset signal according to the current level of the reset signal, and the target level is higher than the current level; The access controller generates a reset signal of the target level as the updated reset signal, and different levels of the reset signals correspond to different pulse durations.

20. The method according to claim 17, wherein The reset signal includes at least one of the following: a reset signal for clearing the physical layer link state, a reset signal for resetting the internal state machine, and a reset signal for power-off restart.

21. The method according to claim 14, wherein The access controller controls the expander to reset so that the expander performs address management on the hard disk of the expander according to the updated seed file, including: The access controller obtains first verification information from the baseboard controller and obtains second verification information from the updated seed file in the first memory; The access controller determines whether the update of the seed file is successful according to the first verification information and the second verification information; After determining that the update of the seed file is successful, the access controller controls the expander to reset so that the expander reads the updated seed file; After determining that the update of the seed file fails, the access controller sends a failure message to the baseboard controller to return to the step of the baseboard controller updating the seed file.

22. A server, characterized in that, It includes the hard disk management system according to any one of claims 1 to 7.

Images