Memory, acceleration unit, data read-write method, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a memory, an acceleration unit, a data reading and writing method, electronic equipment and a storage medium. The memory comprises a logic chip and a plurality of storage chips, the logic chip and the plurality of storage chips are vertically stacked, the plurality of storage chips are all located on the same side of the logic chip, and the plurality of storage chips are electrically connected with the logic chip respectively; the plurality of storage chips comprise a plurality of main storage chips and at least one standby storage chip, and the standby storage chip is used for replacing the failed main storage chip to store data; the logic chip is used for receiving a read-write request and performing read-write on the main storage chip and / or the standby storage chip according to the read-write request. According to the memory disclosed by the embodiment of the invention, the failure of part of the main storage chip in the memory does not influence the working performance of the memory, the yield of the memory in the production process can be improved, and the production efficiency is improved. And the production cost is low.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of chip technology, and in particular, to a memory, an acceleration unit, a data reading and writing method, an electronic device, and a storage medium. Background Art

[0002] With the rapid development of fields such as big data, artificial intelligence, and cloud computing, the demand for memory by hosts and servers is increasing day by day. Currently, by stacking multiple storage chips, a memory with a smaller occupied space and a larger capacity is formed to meet the memory requirements of hosts and servers.

[0003] However, due to the low yield rate of storage chips, the yield rate of a memory stacked with multiple storage chips is low, resulting in a high production cost of the memory. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a memory, an acceleration unit, a data reading and writing method, an electronic device, and a storage medium to at least solve or alleviate the above problems.

[0005] According to a first aspect of the embodiments of the present disclosure, there is provided a memory, including: a logic chip and a plurality of storage chips; the logic chip and the plurality of storage chips are vertically stacked, and the plurality of storage chips are all located on the same side of the logic chip, and the plurality of storage chips are respectively electrically connected to the logic chip; the plurality of storage chips include a plurality of primary storage chips and at least one spare storage chip, and the spare storage chip is used to replace a failed primary storage chip to store data; the logic chip is configured to receive a read / write request and perform reading and writing on the primary storage chip and / or the spare storage chip according to the read / write request.

[0006] According to a second aspect of the embodiments of the present disclosure, there is provided an acceleration unit, including: a substrate, a processing unit, and at least one memory as described in the first aspect above; the processing unit is electrically connected to the substrate, the logic chip in the memory is electrically connected to the substrate, and the processing unit and the memory are located on the same side of the substrate; the processing unit is configured to send a read / write request to the logic chip, so that the logic chip performs reading and writing on the primary storage chip and / or the spare storage chip in the memory according to the read / write request.

[0007] According to a third aspect of the embodiments of the present disclosure, a data reading and writing method is provided, which is applied to a logic chip. The logic chip and the multiple memory chips are vertically stacked, and all of the multiple memory chips are located on the same side of the logic chip. The multiple memory chips are electrically connected to the logic chip respectively. The multiple memory chips include multiple primary memory chips and at least one spare memory chip. The spare memory chip is used to replace a failed primary memory chip to store data. The method includes: receiving a reading and writing request; performing reading and writing on the primary memory chip and / or the spare memory chip according to the reading and writing request.

[0008] According to a fourth aspect of the embodiments of the present disclosure, an electronic device is provided, including: the acceleration unit as described in the second aspect above.

[0009] According to a fifth aspect of the embodiments of the present disclosure, a computer storage medium is provided, on which a computer program is stored. When the program is executed by a processor, the method as described in the third aspect above is implemented.

[0010] According to a sixth aspect of the embodiments of the present disclosure, a computer program product is provided, including computer instructions, and the computer instructions instruct a computing device to execute the method as described in the third aspect above.

[0011] It can be seen from the above technical solutions that the memory includes a logic chip and multiple memory chips. The multiple memory chips include multiple primary memory chips and at least one spare memory chip. When a primary memory chip fails, the failed primary memory chip can be replaced by a spare memory chip to ensure the working performance of the memory. Compared with the prior art, the failure of some primary memory chips in the memory will not affect the working performance of the memory, which can improve the yield rate of the memory in the production process and reduce the production cost. Description of the Drawings

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in the embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings.

[0013] Figure 1 is a schematic diagram of a memory according to an embodiment of the present disclosure;

[0014] Figure 2 is a schematic diagram of a memory according to another embodiment of the present disclosure;

[0015] Figure 3 is a schematic diagram of a memory including N memory chips according to an embodiment of the present disclosure;

[0016] Figure 4 Schematic diagram of a memory including m spare memory chips according to an embodiment of the present disclosure;

[0017] Figure 5 Schematic diagram of an acceleration unit according to an example of the present disclosure;

[0018] Figure 6 Flowchart of a data reading and writing method according to an example of the present disclosure;

[0019] Figure 7 Flowchart of a data reading and writing method according to another example of the present disclosure;

[0020] Figure 8 Schematic diagram of an electronic device according to an embodiment of the present disclosure. Detailed implementation manners

[0021] The following describes the present disclosure based on embodiments, but the present disclosure is not limited to these embodiments. In the following detailed description of the present disclosure, some specific details are described in detail. Those skilled in the art can fully understand the present disclosure without the description of these details. In order to avoid obscuring the essence of the present disclosure, well-known methods, processes, and flows are not described in detail. Additionally, the drawings are not necessarily drawn to scale.

[0022] First, some nouns or terms that appear during the description of the embodiments of the present disclosure are applicable to the following explanations.

[0023] Acceleration unit: In view of the low efficiency of traditional processors in some specialized fields (such as data reading, etc.), a processing unit designed to improve the data processing speed in these specialized fields. In the embodiments of the present disclosure, it is mainly a specialized processing unit designed to improve the speed of accessing DDR.

[0024] Memory: Memory is a hardware device in a computer system used for temporarily storing data and instructions, and is an important part of the computer's operation. The main function of memory is to provide a fast-access data storage space for the Central Processing Unit (CPU), Graphics Processing Unit (GPU), Artificial Intelligence (AI) processor, etc., in order to efficiently execute programs and process tasks.

[0025] Dynamic Random Access Memory: Dynamic Random Access Memory (DRAM) is a commonly used computer memory. Usually, a transistor and a capacitor are used to represent a bit, and the stored data will be lost after the power is cut off.

[0026] Memory

[0027] Figure 1 A schematic diagram of a memory according to an embodiment of the present disclosure is shown. As Figure 1 shown, the memory 100 includes a logic chip 101 and a plurality of memory chips 102. The logic chip 101 and the plurality of memory chips 102 are vertically stacked, and the plurality of memory chips 102 are all located on the same side of the logic chip 101. The plurality of memory chips 102 are electrically connected to the logic chip 101 respectively. The plurality of memory chips 102 include a plurality of primary memory chips 1021 and at least one spare memory chip 1022. The spare memory chip 1022 is used to replace a failed primary memory chip 1021 to store data. The logic chip 101 can receive read / write requests and perform read / write operations on the primary memory chip 1021 and / or the spare memory chip 1022 according to the read / write requests.

[0028] The memory 100 includes a logic chip 101 and a plurality of memory chips 102. As an example, Figure 1 a memory 100 including 5 memory chips 102 and 1 logic chip 101 is shown. The plurality of memory chips 102 are stacked on one side of the logic chip 101. The plurality of memory chips 102 include primary memory chips 1021 and spare memory chips 1022. When all the primary memory chips 1021 are valid, for example: all the primary memory chips 1021 are good products when the memory 100 is produced, the spare memory chips 1022 are redundantly arranged and do not participate in storing data. When there are failed primary memory chips 1021 among the plurality of primary memory chips 1021, for example: during the production process, there are defective primary memory chips 1021 in the memory 100, the spare memory chips 1022 can replace the failed primary memory chips 1021 to store data. The spare memory chips 1022 can be arranged at any position of the primary memory chips 1021. In one example, as Figure 1 shown, two spare memory chips 1022 are stacked. In another example, Figure 2 a schematic diagram of a memory according to another embodiment of the present disclosure is shown. As Figure 2 shown, the spare memory chips 1022 can be dispersedly arranged among the primary memory chips 1021. Optionally, the spare memory chips 1022 and the primary memory chips 1021 have the same size and specifications.

[0029] The logic chip 101 is electrically connected to each memory chip 102 respectively. After receiving a read / write request, the logic chip 101 parses the read / write request, determines the read / write address of the memory chip 102 requested to be read / written in the read / write request, and reads / writes the memory chip 102 corresponding to the read / write address according to the read / write request. It should be understood that since the backup memory chip 1022 can replace the failed main memory chip 1021, when the logic chip 101 reads and writes the memory chip 102 according to the read / write request, it can read and write the main memory chip 1021 and / or the backup memory chip 1022.

[0030] The following example illustrates the specific reading and writing process:

[0031] When the logic chip 101 receives a read / write request, the logic chip 101 parses the request and determines that the primary memory chip A needs to be read / written. The primary memory chip A is the normally operating primary memory chip 1021. At this time, the logic chip 101 reads / writes the primary memory chip A according to the read / write request. When the logic chip 101 receives a read / write request, the logic chip 101 parses the request and determines that the primary memory chip B needs to be read / written. The primary memory chip B is the failed primary memory chip 1021, and the backup memory chip C replaces the primary memory chip B to store data. At this time, the logic chip 101 reads / writes the backup memory chip C according to the read / write request. When the logic chip 101 receives a read / write request, the logic chip 101 parses the request and determines that the primary memory chip A and the primary memory chip B need to be read / written. At this time, the logic chip 101 reads / writes the primary memory chip A and the backup memory chip C according to the read / write request.

[0032] In the present disclosure, the provision of the spare memory chip 1022 can improve the yield rate of the memory 100. Specifically, assuming that the processing error rate of the main memory chip 1021 is 1-P g , then the processing yield of the main memory chip 1021 is P g If the memory 100 only includes k active memory chips 1021 and does not include spare memory chips 1022, the overall yield rate of the memory 100 is P g k Taking the memory 100 including 8 main memory chips 1021 as an example, when P g =90%, the yield rate of the memory 100 is 0.9 8 *100%=43.05%, when P g =95%, the yield rate of the memory 100 is 0.95 8 *100%=66.34%, when P g =98%, the yield rate of the memory 100 is 0.98 8*100% = 85.08%.

[0033] When j spare memory chips 1022 are set in the memory 100, since the spare memory chips 1022 can replace the primary memory chips 1021, among the k + j memory chips 102 of the memory 100, i primary memory chips 1021 are allowed to fail, where i is greater than 0 and less than or equal to j, that is, at most j primary memory chips 1021 are allowed to fail. Therefore, the overall yield of the memory 100 Taking the memory 100 including 8 primary memory chips 1021 and 1 spare memory chip 1022 as an example, when P g = 90%, the yield of the memory 100 is When P g = 95%, the yield of the memory 100 is When P g = 98%, the yield of the memory 100 is Taking the memory 100 including 8 primary memory chips 1021 and 2 spare memory chips 1022 as an example, when P g = 90%, the yield of the memory 100 is When P g = 95%, the yield of the memory 100 is When P g = 98%, the yield of the memory 100 is It can be seen from the above data that the yield of the memory 100 in the present disclosure is higher than that of the memory 100 in the prior art.

[0034] In the embodiment of the present disclosure, the memory 100 includes a logic chip 101 and a plurality of memory chips 102. The plurality of memory chips 102 include a plurality of primary memory chips 1021 and at least one spare memory chip 1022. When a primary memory chip 1021 fails, the spare memory chip 1022 can replace the failed primary memory chip 1021 to ensure the working performance of the memory 100. Compared with the prior art, the failure of some primary memory chips 1021 in the memory 100 does not affect the working performance of the memory 100, which can improve the yield of the memory 100 in the production process and reduce the production cost.

[0035] In a possible implementation, the logic chip 101 can determine the target primary storage chip 1021 and the target secondary storage chip 1022 according to the received configuration instruction. The target primary storage chip 1021 is the failed primary storage chip 1021, and the target secondary storage chip 1022 is the secondary storage chip 1022 that replaces the target primary storage chip 1021 to store data. The logic chip 101 determines the mapping relationship between the read / write addresses of the target primary storage chip 1021 and the read / write addresses of the target secondary storage chip 1022. After receiving a read / write request for the target primary storage chip 1021, the logic chip 101 reads and writes the target secondary storage chip 1022 according to the read / write request and the mapping relationship.

[0036] The logic chip 101 can receive a configuration instruction, which can indicate the failed active storage chip 102 and the secondary storage chip 1022 that replaces the failed primary storage chip 1021. After receiving the configuration instruction, the logic chip 101 parses the configuration instruction to determine the read / write addresses of the target primary storage chip 1021 and the read / write addresses of the target secondary storage chip 1022, maps the read / write addresses of the target primary storage chip 1021 to the read / write addresses of the target secondary storage chip 1022 to determine the mapping relationship, and stores the mapping relationship. After receiving a read / write request, the logic chip 101 parses the read / write request. If the read / write request indicates reading and writing to the target primary storage chip 1021, the logic chip 101 determines the target secondary storage chip 1022 that replaces the target primary storage chip 1021 according to the mapping relationship, and reads and writes the target secondary storage chip 1022 according to the read / write request.

[0037] The following uses an example to illustrate the specific process:

[0038] After receiving the configuration instruction, the logic chip 101 parses the configuration instruction. The configuration instruction indicates that the primary storage chip 3 has failed and indicates that the secondary storage chip 2 replaces the primary storage chip 3 to store data. The logic chip 101 maps the read / write addresses of the primary storage chip 3 included in the configuration instruction to the read / write addresses of the secondary storage chip 2 and stores the mapping relationship. When the logic chip 101 receives a read / write request, the logic chip 101 parses the read / write request to determine that it is necessary to read and write to the primary storage chip 3. At this time, the logic chip 101 converts the read / write addresses of the primary storage chip 3 in the read / write request to the read / write addresses of the secondary storage chip 2 according to the mapping relationship, and reads and writes the secondary storage chip 2 according to the read / write request.

[0039] In an embodiment of the present disclosure, the logic chip 101 may determine the mapping relationship between the read / write addresses of the target primary storage chip 1021 and the read / write addresses of the target backup storage chip 1022 according to the received configuration instruction. When the logic chip 101 receives a read / write request for the target primary storage chip 1021, it may perform read / write operations on the target backup storage chip 1022 according to the read / write request and the mapping relationship, so as to realize replacing the failed primary storage chip 1021 with the backup storage chip 1022, and the failure of some primary storage chips 1021 in the memory 100 will not affect the working performance of the memory 100, which can improve the yield rate of the memory 100 during the production process and reduce the production cost.

[0040] Figure 3 FIG. shows a schematic diagram of a memory including N storage chips according to an embodiment of the present disclosure. As Figure 3 shown, the memory 100 includes N storage chips 102, where N is an integer greater than 2; the first surface of the first storage chip 102 among the N storage chips 102 is attached to the first surface of the logic chip 101, the first surface of the nth storage chip 102 among the N storage chips 102 is attached to the second surface of the (n - 1)th storage chip 102, and the nth storage chip 102 is electrically connected to the logic chip 101 through the first to (n - 1)th storage chips 102, where n is an integer greater than or equal to 2 and less than or equal to N.

[0041] The memory 100 includes N storage chips 102, and among the N storage chips 102, there are multiple primary storage chips 1021 and at least one backup storage chip 1022, so N is an integer greater than 2. The N storage chips 102 are stacked in sequence on one side of the logic chip 101 and are respectively electrically connected to the logic chip 101.

[0042] Hereinafter, N = 5 will be used for illustration. When N = 5, n can be 2, 3, 4, and 5.

[0043] The first surface of the first storage chip 102 among the 5 storage chips 102 is attached to the first surface of the logic chip 101, the first surface of the second storage chip 102 is attached to the second surface of the first storage chip 102, the first surface of the third storage chip 102 is attached to the second surface of the second storage chip 102, the first surface of the fourth storage chip 102 is attached to the second surface of the third storage chip 102, and the first surface of the fifth storage chip 102 is attached to the second surface of the fourth storage chip 102.

[0044] Optionally, adjacent memory chips 102 can be electrically connected through micro-bumps. In one example, the memory chips 102 can adopt through-silicon via technology, and the nth memory chip 102 is electrically connected to the logic chip 101 through the 1st to n-1th memory chips 102 by means of a metal layer formed in the through-hole. For example, the 4th memory chip 102 is electrically connected to the logic chip 101 through the 1st to 3rd memory chips 102, the 5th memory chip 102 is electrically connected to the logic chip 101 through the 1st to 4th memory chips 102, and the 1st memory chip 102 is electrically connected to the logic chip 101 through micro-bumps.

[0045] In the embodiments of the present disclosure, multiple memory chips 102 are sequentially stacked on one side of the logic chip 101, realizing the stacked arrangement of the memory chips 102, and the multiple memory chips 102 are respectively electrically connected to the logic chip 101, enabling the logic chip 101 to read and write any memory chip 102 electrically connected to the logic chip 101 according to read and write requests, thus meeting the read and write requirements.

[0046] Figure 4 The figure shows a schematic diagram of a memory including m spare memory chips according to an embodiment of the present disclosure. As Figure 4 shown, the number of spare memory chips 1022 is m, where m is a positive integer less than or equal to N-2, and the (N-m+1)th to Nth memory chips 102 among the N memory chips 102 are spare memory chips 1022.

[0047] Since the memory chips 102 include multiple primary memory chips 1021, that is, at least two primary memory chips 1021, when there are m spare memory chips 1022 among the N memory chips 102, m is a positive integer less than or equal to N-2. For example, when N = 5, the memory 100 includes 5 memory chips 102, and the memory chips 102 can only include 1-3 spare memory chips 1022.

[0048] It should be understood that when none of the primary storage chips 1021 fails, the redundant standby storage chips 1022 do not store data. Due to line loss, external interference, etc., the integrity of the signals received by the storage chips 102 farther away from the logic chip 101 is worse. In order to enable the primary storage chips 1021 to have higher read / write performance, m standby storage chips 1022 are set at the position farthest from the logic chip 101, that is, the (N - m + 1)-th to N-th storage chips 102 among the N storage chips 102 are standby storage chips 1022. For example: The memory 100 includes 5 storage chips 102, and 2 of the 5 storage chips 102 are standby storage chips 1022. Then, in the order from the nearest to the logic chip 101, the 1st to 3rd storage chips 102 are primary storage chips 1021, and the 4th to 5th storage chips 102 are standby storage chips 1022. The memory 100 includes 9 storage chips 102, and 1 of the 9 storage chips 102 is a standby storage chip 1022. Then, in the order from the nearest to the logic chip 101, the 1st to 8th storage chips 102 are primary storage chips 1021, and the 9th storage chip 102 is a standby storage chip 1022.

[0049] In the embodiment of the present disclosure, the memory 100 is stacked in the order of the standby storage chip 1022, the primary storage chip 1021, and the logic chip 101, so that the distance between the primary storage chip 1021 and the logic chip 101 is relatively close, which can prevent the integrity of the signals sent by the logic chip 101 to the primary storage chip 1021 from being poor due to line loss, external interference, etc., and can ensure the read / write performance of the primary storage chip 1021.

[0050] In a possible implementation manner, the primary storage chip 1021 includes a dynamic random access memory, and / or the standby storage chip 1022 includes a dynamic random access memory.

[0051] In the embodiment of the present disclosure, the primary storage chip 1021 includes a DRAM, and / or the standby storage chip 1022 includes a DRAM, so that the storage chip 102 has higher read / write performance, and the memory 100 can be used as the memory of a host or a server.

[0052] Acceleration Unit

[0053] Figure 5 The schematic diagram of an acceleration unit according to an example of the present disclosure is shown. As Figure 5As shown, the acceleration unit 200 includes a substrate 201, a processing unit 202, and at least one memory 100. The processing unit 202 is electrically connected to the substrate 201. The logic chip 101 in the memory 100 is electrically connected to the substrate 201. The processing unit 202 and the memory 100 are located on the same side of the substrate 201. The processing unit 202 is configured to send read / write requests to the logic chip 101, so that the logic chip 101 reads from and writes to the primary storage chip 1021 and / or the spare storage chip 1022 in the memory 100 according to the read / write requests.

[0054] The acceleration unit 200 may be provided with multiple memories 100. The multiple memories 100 and the processing unit 202 are both located on the same side of the substrate 201. For example, the acceleration unit 200 includes 3 memories 100, and each memory 100 includes 9 storage chips 102, so that the acceleration unit 200 includes 27 storage chips 102. The processing unit 202 in the acceleration unit 200 may be a chip with processing capabilities such as a CPU or a GPU. When a program running on the processing unit 202 needs to read from and write to the memory 100, the processing unit 202 may send read / write requests to the logic chip 101 in the memory 100, so that the logic chip 101 in the memory 100 executes read / write tasks based on the read / write requests. The memory 100 in the present disclosure may be the memory 100 in any of the above embodiments. The structure of the memory 100 and the interaction logic between the chips can be seen in the description of any of the above embodiments.

[0055] In one example, the substrate 201 and the processing unit 202, as well as the substrate 201 and the logic chip 101, may be electrically connected through microbumps. In some other examples, the substrate 201 and the processing unit 202, as well as the substrate 201 and the logic chip 101, may also be electrically connected in other ways. The processing unit 202 and the logic chip 101 may transmit signals through the substrate 201. For example, the processing unit 202 may transmit read / write requests to the logic chip 101 through the substrate 201, and the logic chip 101 may transmit the read data to the processing unit 202 through the substrate 201.

[0056] In an embodiment of the present disclosure, the acceleration unit 200 includes a substrate 201, a processing unit 202, and at least one memory 100. The processing unit 202 can send read / write requests to the logic chip 101 in the memory 100. The logic chip 101 can perform read / write operations on the primary storage chip 1021 and / or the backup storage chip 1022 according to the read / write requests. Since the primary storage chip 1021 and the backup storage chip 1022 are provided in the memory 100, when the primary storage chip 1021 fails, the backup storage chip 1022 can replace the failed primary storage chip 1021 to ensure the working performance of the memory 100, thereby ensuring the working performance of the acceleration unit 200. Compared with the prior art, the failure of some primary storage chips 1021 in the memory 100 does not affect the working performance of the memory 100, and thus does not affect the working performance of the acceleration unit 200. The yield rate of the memory 100 in the production process can be improved, and the production cost can be reduced.

[0057] In a possible implementation manner, the processing unit 202 can send a configuration instruction to the logic chip 101, so that the logic chip 101 determines a target primary storage chip 1021 and a target backup storage chip 1022 according to the received configuration instruction. The target primary storage chip 1021 is the failed primary storage chip 1021, and the target backup storage chip 1022 is the backup storage chip 1022 that replaces the target primary storage chip 1021 to store data. The mapping relationship between the read / write address of the target primary storage chip 1021 and the read / write address of the target backup storage chip 1022 is determined, and after receiving a read / write request for reading / writing the target primary storage chip 1021, the target backup storage chip 1022 is read / written according to the read / write request and the mapping relationship.

[0058] During the production process and / or the usage process, if it is determined that the primary storage chip 1021 fails, an instruction can be input to the processing unit 202. The processing unit 202 can generate a configuration instruction based on the input instruction. The configuration instruction can indicate the failed primary storage chip 102 and the backup storage chip 1022 that replaces the failed primary storage chip 1021. The processing unit 202 sends the configuration instruction to the logic chip 101 in the memory 100. The logic chip 101 can receive the configuration instruction. After receiving the configuration instruction, the logic chip 101 parses the configuration instruction, determines the read / write addresses of the target primary storage chip 1021 and the read / write addresses of the target backup storage chip 1022, maps the read / write addresses of the target primary storage chip 1021 with the read / write addresses of the target backup storage chip 1022 to determine the mapping relationship, and stores the mapping relationship. After receiving a read / write request, the logic chip 101 parses the read / write request. If the read / write request indicates to read / write the target primary storage chip 1021, then according to the mapping relationship, it determines the target backup storage chip 1022 that replaces the target primary storage chip 1021, and reads / writes the target backup storage chip 1022 according to the read / write request.

[0059] In the embodiment of the present disclosure, the processing unit 202 can send a configuration instruction to the logic chip 101. The logic chip 101 can determine the mapping relationship between the read / write addresses of the target primary storage chip 1021 and the read / write addresses of the target backup storage chip 1022 according to the received configuration instruction. When the logic chip 101 receives a read / write request sent by the processing unit 202 to read / write the target primary storage chip 1021, it can read / write the target backup storage chip 1022 according to the read / write request and the mapping relationship, realizing the replacement of the failed primary storage chip 1021 by the backup storage chip 1022, so that the failure of some primary storage chips 1021 during the production process of the memory 100 will not affect the working performance of the memory 100, and thus will not affect the working performance of the acceleration unit 200, which can improve the yield rate of the memory 100 during the production process and reduce the production cost.

[0060] Data Reading and Writing Method

[0061] The memory in the foregoing embodiment can be applied to a host or a server to implement the memory read / write function of the host or the server. The working process of the memory will be described below through an embodiment of a data read / write method.

[0062] Figure 6The flowchart of a data reading and writing method according to an example of the present disclosure is shown. This data reading and writing method is applied to a logic chip. The logic chip and multiple memory chips are vertically stacked, and all the multiple memory chips are located on the same side of the logic chip. The multiple memory chips are electrically connected to the logic chip respectively. The multiple memory chips include multiple primary memory chips and at least one spare memory chip. The spare memory chip is used to replace a failed primary memory chip to store data. The logic chip can be the logic chip in any of the foregoing embodiments. As Figure 6 shown, the data reading and writing method includes the following steps 601 to step 602:

[0063] Step 601: Receive a read / write request.

[0064] Receive the read / write request sent by the processing unit. The processing unit can be a chip with processing capabilities such as a CPU or a GPU.

[0065] Step 602: Read and write the primary memory chip and / or the spare memory chip according to the read / write request.

[0066] In the embodiments of the present disclosure, a read / write request is received, and the primary memory chip and / or the spare memory chip are read and written according to the read / write request, thereby realizing the data reading and writing function. When the primary memory chip fails, the spare memory chip can replace the failed primary memory chip to ensure the working performance of the memory. Compared with the prior art, the failure of some primary memory chips in the memory will not affect the working performance of the memory, and relatively high data reading and writing performance can be achieved.

[0067] Figure 7 The flowchart of a data reading and writing method according to another example of the present disclosure is shown. As Figure 7 shown, the data reading and writing method further includes steps 701 to step 704:

[0068] Step 701: Receive a configuration instruction.

[0069] Step 702: Determine a target primary memory chip and a target spare memory chip according to the configuration instruction.

[0070] The target primary memory chip is the failed primary memory chip, and the target spare memory chip is the spare memory chip that replaces the target primary memory chip to store data.

[0071] Step 703: Determine the mapping relationship between the read / write address of the target primary memory chip and the read / write address of the target spare memory chip.

[0072] Step 704: If a read / write request for reading and writing the target primary memory chip is received, then read and write the target spare memory chip according to the read / write request and the mapping relationship.

[0073] In the embodiments of the present disclosure, a mapping relationship between the read / write addresses of the target primary storage chip and the read / write addresses of the target spare storage chip is determined according to the received configuration instruction. After a read / write request for the target primary storage chip is received, the target spare storage chip can be read / written according to the read / write request and the mapping relationship, so as to realize replacing the failed primary storage chip with the spare storage chip, so that the failure of some primary storage chips in the memory does not affect the working performance of the memory, and relatively high data read / write performance can be achieved.

[0074] It should be noted that the data read / write method in the embodiments of the present disclosure is a specific application of the memory in the foregoing embodiments. For the specific data read / write method, reference can be made to the description in the foregoing memory embodiments, and details will not be elaborated herein.

[0075] Electronic Device

[0076] Figure 8 The schematic diagram of an electronic device showing an example of the present disclosure is as Figure 8 shown. The electronic device 300 includes the acceleration unit 200 in any of the foregoing embodiments.

[0077] It should be noted that the electronic device 300 in this embodiment and the embodiment of the foregoing acceleration unit 200 are based on the same inventive concept and have the same beneficial effects as the embodiment of the foregoing acceleration unit 200, and details will not be elaborated herein.

[0078] Computer Program Product

[0079] The embodiments of the present disclosure further provide a computer program product, including computer instructions, and the computer instructions direct a computing device to perform operations corresponding to any of the foregoing method embodiments.

[0080] It should be pointed out that according to the needs of implementation, each component / step described in the embodiments of the present disclosure can be split into more components / steps, or two or more components / steps or part of the operations of the components / steps can be combined into new components / steps to achieve the purpose of the embodiments of the present disclosure.

[0081] Computer Storage Medium

[0082] The method according to the embodiments of the present disclosure can be implemented in hardware, firmware, or as software or computer code that can be stored in a recording medium (such as a CD ROM, RAM, floppy disk, hard disk, or magneto-optical disk), or as computer code originally stored in a remote recording medium or a non-transitory machine-readable medium and downloaded via a network and to be stored in a local recording medium, so that the method described herein can be stored as such software processing on a recording medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware (such as an ASIC or FPGA). It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component (such as RAM, ROM, flash memory, etc.) that can store or receive software or computer code, and when the software or computer code is accessed and executed by the computer, the processor, or the hardware, the data reading and writing method described herein is implemented. In addition, when a general-purpose computer accesses the code for implementing the data reading and writing method shown herein, the execution of the code converts the general-purpose computer into a dedicated computer for executing the data reading and writing method shown herein.

[0083] It should be noted that the information related to users (including but not limited to user device information, user personal information, etc.) and data (including but not limited to sample data for training a model, data for analysis, stored data, displayed data, etc.) involved in the embodiments of the present disclosure are all information and data that have been authorized by the users or fully authorized by all parties, and the collection, use, and processing of the relevant data need to comply with the relevant laws, regulations, and standards of the relevant countries and regions, and corresponding operation entrances are provided for users to select to authorize or reject.

[0084] It should be understood that the embodiments in this specification are all described in a progressive manner. The same or similar parts between the embodiments can be referred to each other, and the key points of each embodiment are the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the methods described in the device and system embodiments, the description is relatively simple, and the relevant parts can be referred to the partial descriptions of other embodiments.

[0085] It should be understood that the specific embodiments of this specification have been described. Other embodiments are within the scope of the claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and still achieve the desired result. Additionally, the processes depicted in the drawings do not necessarily require the specific order or sequential order shown to achieve the desired result. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0086] It should be understood that an element described in the singular herein or shown as only one in the drawings does not represent limiting the number of such elements to one. In addition, modules or elements described or shown herein as separate may be combined into a single module or element, and modules or elements described or shown herein as a single one may be split into multiple modules or elements.

[0087] It should also be understood that the terms and expressions used herein are for descriptive purposes only, and one or more embodiments of the present specification should not be limited to these terms and expressions. The use of these terms and expressions does not mean excluding any equivalent features of the illustration and description (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be regarded as covering all such equivalents.

Claims

1. A memory comprising: Logic chip and multiple memory chips; The logic chip and the multiple memory chips are vertically stacked, and the multiple memory chips are all located on the same side of the logic chip. The multiple memory chips are electrically connected to the logic chip respectively; The multiple memory chips include multiple primary memory chips and at least one spare memory chip, and the spare memory chip is used to replace the failed primary memory chip to store data; The logic chip is configured to receive read / write requests and perform read / write operations on the primary memory chip and / or the spare memory chip according to the read / write requests.

2. The memory according to claim 1, wherein, The logic chip is configured to determine a target primary memory chip and a target spare memory chip according to a received configuration instruction. The target primary memory chip is the failed primary memory chip, and the target spare memory chip is the spare memory chip that replaces the target primary memory chip to store data. Determine the mapping relationship between the read / write address of the target primary memory chip and the read / write address of the target spare memory chip, and after receiving a read / write request for reading / writing the target primary memory chip, perform read / write operations on the target spare memory chip according to the read / write request and the mapping relationship.

3. The memory according to claim 1, wherein, The memory includes N memory chips, where N is an integer greater than 2. The first surface of the first memory chip among the N memory chips is attached to the first surface of the logic chip. The first surface of the nth memory chip among the N memory chips is attached to the second surface of the (n - 1)th memory chip. The nth memory chip is electrically connected to the logic chip through the first to (n - 1)th memory chips, where n is an integer greater than or equal to 2 and less than or equal to N.

4. The memory according to claim 3, wherein, The number of the spare memory chips is m, where m is a positive integer less than or equal to N - 2. The (N - m + 1)th to Nth memory chips among the N memory chips are the spare memory chips.

5. The memory according to any one of claims 1-4, wherein, The primary memory chip includes a dynamic random access memory, and / or the spare memory chip includes a dynamic random access memory.

6. An acceleration unit, comprising: A substrate, a processing unit, and at least one memory according to any one of claims 1-5; The processing unit is electrically connected to the substrate, the logic chip in the memory is electrically connected to the substrate, and the processing unit and the memory are located on the same side of the substrate; The processing unit is configured to send read / write requests to the logic chip, so that the logic chip performs read / write operations on the primary memory chip and / or the spare memory chip in the memory according to the read / write requests.

7. The acceleration unit according to claim 6, wherein, The processing unit is configured to send a configuration instruction to the logic chip, so that the logic chip determines a target primary storage chip and a target backup storage chip according to the received configuration instruction, wherein the target primary storage chip is the failed primary storage chip, and the target backup storage chip is the backup storage chip that replaces the target primary storage chip to store data, determines a mapping relationship between the read and write addresses of the target primary storage chip and the read and write addresses of the target backup storage chip, and after receiving a read and write request for reading and writing the target primary storage chip, reads and writes the target backup storage chip according to the read and write request and the mapping relationship.

8. A data reading and writing method, applied to a logic chip, wherein the logic chip and multiple memory chips are vertically stacked, and the multiple memory chips are all located on the same side of the logic chip. The multiple memory chips are electrically connected to the logic chip, and the multiple memory chips include multiple primary memory chips and at least one backup memory chip, wherein the backup memory chip is used to replace the failed primary memory chip to store data. The method comprises: Receive read and write requests; Read and write the active storage chip and / or the standby storage chip according to the read and write request.

9. The method according to claim 8, further comprising: Receive configuration instructions; Determining a target primary storage chip and a target backup storage chip according to the configuration instruction, wherein the target primary storage chip is the failed primary storage chip, and the target backup storage chip is the backup storage chip that replaces the target primary storage chip to store data; Determining a mapping relationship between the read and write addresses of the target primary storage chip and the read and write addresses of the target backup storage chip; If a read / write request for reading or writing the target primary storage chip is received, the target backup storage chip is read / written according to the read / write request and the mapping relationship.

10. An electronic device, comprising: An acceleration unit as claimed in claim 6 or 7.

11. A computer storage medium having a computer program stored thereon, wherein when the program is executed by a processor, the data reading and writing method according to claim 8 or 9 is implemented.

12. A computer program product comprising computer instructions, wherein the computer instructions instruct a computing device to execute the data reading and writing method according to claim 8 or 9.

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