Memory management method and storage device

Abstract

The invention provides a memory management method and a storage device. The method comprises the following steps: receiving a first operation instruction from a host system, wherein the first operation instruction indicates to store first data; in response to the first operation instruction, storing the first data into the memory module based on the first operation mode; and in response to the trigger condition being satisfied, communicating management information to the host system, where the management information reflects whether the first data is still stored in the memory module based on the first mode of operation. Therefore, the working efficiency of the storage device can be improved.

Description

Technical Field

[0001] The present invention relates to the field of storage technologies, and more particularly to a memory management method and a storage device. Background Art

[0002] Flash memory is a non-volatile memory and is widely used in electronic devices such as memory cards, solid state drives, and portable multimedia players. In Universal Flash Storage (UFS) 4.0, data can be stored in a memory module at a relatively high access speed and with relatively high reliability through a specified mode, which is beneficial for frequent reading of this data in the future.

[0003] However, a problem that may be encountered in practice is that even if the data is preset to be stored based on the aforementioned specified mode, after a period of time, this data may be moved and / or its storage method may be changed in the memory module due to various factors. When this data needs to be read subsequently, the reading speed of this data will not be able to reach the expected speed, resulting in the working efficiency of the storage device not meeting expectations. Summary of the Invention

[0004] The present invention provides a memory management method and a storage device, which can improve the above problems and thus improve the working efficiency of the storage device.

[0005] An embodiment of the present invention provides a memory management method for a storage device, where the storage device includes a memory module, and the memory management method includes: receiving a first operation instruction from a host system, where the first operation instruction instructs to store first data; in response to the first operation instruction, storing the first data into the memory module based on a first operation mode; and in response to a trigger condition being satisfied, transmitting management information to the host system, where the management information reflects whether the first data is still stored in the memory module based on the first operation mode.

[0006] An embodiment of the present invention further provides a storage device, which includes a connection interface, a memory module, and a memory controller. The connection interface is used to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory controller is configured to: receive a first operation instruction from the host system, where the first operation instruction instructs to store first data; in response to the first operation instruction, store the first data into the memory module based on a first operation mode; and in response to a trigger condition being satisfied, transmit management information to the host system, where the management information reflects whether the first data is still stored in the memory module based on the first operation mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic diagram of a data storage system shown according to an embodiment of the present invention;

[0008] Figure 2 is a schematic diagram of a memory controller shown according to an embodiment of the present invention;

[0009] Figure 3 is a schematic diagram of a managed memory module shown according to an embodiment of the present invention;

[0010] Figure 4 is a schematic diagram of a management entity unit shown according to an embodiment of the present invention;

[0011] Figure 5 is a schematic diagram of management information shown according to an embodiment of the present invention;

[0012] Figure 6 is a flowchart of a memory management method shown according to an embodiment of the present invention;

[0013] Figure 7 is a flowchart of a memory management method shown according to an embodiment of the present invention. DETAILED DESCRIPTION

[0014] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals will be used in the drawings and the description to refer to the same or like parts.

[0015] Figure 1 is a schematic diagram of a data storage system shown according to an embodiment of the present invention. Please refer to Figure 1, the data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and is used to store data from the host system 11. For example, the host system 11 can be a smart phone, a tablet computer, a notebook computer, a desktop computer, an industrial computer, a game console, a server, or a computer system installed in a specific carrier (such as a vehicle, an aircraft, or a ship), and the type of the host system 11 is not limited thereto. In addition, the storage device 12 can include a solid state drive, a USB flash drive, a memory card, or other types of non-volatile storage devices.

[0016] The storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to the host system 11. For example, the connection interface 121 can support an embedded Multi-Media Card (eMMC), a Universal Flash Storage (UFS), a Peripheral Component Interconnect Express (PCIExpress), a Non-Volatile Memory Express (NVM express), a Serial Advanced Technology Attachment (SATA), a Universal Serial Bus (USB), or other types of connection interface standards. Therefore, the storage device 12 can communicate with the host system 11 (such as exchanging signals, instructions, and / or data) via the connection interface 121.

[0017] The memory module 122 is used to store data. For example, the memory module 122 can include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module can include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also called the threshold voltage). For example, the memory module 122 can include a Single Level Cell (SLC) NAND flash memory module, a Multi Level Cell (MLC) NAND flash memory module, a Triple Level Cell (TLC) NAND flash memory module, a Quad Level Cell (QLC) NAND flash memory module, and / or other memory modules with the same or similar characteristics.

[0018] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be regarded as the control core of the storage device 12 and is used to control the storage device 12. For example, the memory controller 123 can be used to control or manage the overall or partial operation of the storage device 12. For example, the memory controller 123 may include a Central Processing Unit (CPU), or other programmable general-purpose or special-purpose microprocessors, Digital Signal Processors (DSPs), programmable controllers, Application-Specific Integrated Circuits (ASICs), Programmable Logic Devices (PLDs), or other similar devices, or a combination of these devices. In one embodiment, the memory controller 123 may include a flash memory controller.

[0019] The memory controller 123 can send an instruction sequence to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a write instruction sequence to the memory module 122 to instruct the memory module 122 to store data in a specific storage unit. For example, the memory controller 123 can send a read instruction sequence to the memory module 122 to instruct the memory module 122 to read data from a specific storage unit. For example, the memory controller 123 can send an erase instruction sequence to the memory module 122 to instruct the memory module 122 to erase the data stored in a specific storage unit. In addition, the memory controller 123 can also send other types of instruction sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, which are not limited in the present invention. The memory module 122 can receive the instruction sequence from the memory controller 123 and access the storage unit inside the memory module 122 according to this instruction sequence.

[0020] Figure 2 is a schematic diagram of a memory controller shown according to an embodiment of the present invention. Please refer to Figure 1 and Figure 2 , the memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 through the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0021] The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 can be used to control or manage the overall or partial operation of the memory controller 123. For example, the memory control circuit 23 can communicate with the host system 11 through the host interface 21 and access the memory module 122 through the memory interface 22. For example, the memory control circuit 23 can include a control circuit such as an embedded controller or a microcontroller. In the following embodiments, the description of the memory control circuit 23 is the same as the description of the memory controller 123.

[0022] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuit 23 and is used to cache data. For example, the buffer memory 24 can be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122.

[0023] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to perform encoding and decoding on data to ensure the correctness of the data. For example, the decoding circuit 25 can support various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), Exclusive OR (XOR) code, etc. In one embodiment, the memory controller 123 may further include various other types of circuit modules (such as a power management circuit, etc.), which are not limited in the present invention.

[0024] Figure 3 is a schematic diagram of managing a memory module shown in an embodiment of the present invention. Please refer to Figures 1 to 3 , the memory module 122 includes a plurality of physical units 301(1) to 301(B). Each physical unit includes a plurality of memory cells and is used to store data non-volatilely.

[0025] In one embodiment, a physical unit may include one or more physical erasure units. In addition, a physical unit may include a plurality of sub-physical units. For example, a sub-physical unit may include one or more physical programming units.

[0026] In one embodiment, an entity programming unit may include multiple entity sectors. For example, the data capacity of an entity sector may be 512 bytes (B), and an entity programming unit may include 32 entity sectors. However, both the data capacity of an entity sector and / or the total number of entity sectors included in an entity programming unit may be adjusted according to practical requirements, and the present invention is not limited thereto. In one embodiment, an entity programming unit may be regarded as an entity page. For example, the storage capacity of an entity programming unit may be 16 kilobytes, and the present invention is not limited to this.

[0027] In one embodiment, an entity programming unit is the minimum unit for synchronously writing data in the memory module 122. For example, when performing a programming operation (also referred to as a write operation) on an entity programming unit to write data into this entity programming unit, multiple storage units in this entity programming unit may be programmed synchronously to store the corresponding data. For example, when programming an entity programming unit, a write voltage may be applied to this entity programming unit to change the threshold voltage of at least some of the storage units in this entity programming unit. For example, the threshold voltage of a storage unit may reflect the bit data stored in this storage unit.

[0028] In one embodiment, an entity erasure unit may contain multiple entity programming units. Multiple entity programming units in an entity erasure unit may be erased synchronously. For example, when performing an erase operation on an entity erasure unit, an erase voltage may be applied to multiple entity programming units in this entity erasure unit to change the threshold voltage of at least some of the storage units in these entity programming units. By performing an erase operation on an entity erasure unit, the data stored in this entity erasure unit can be cleared. In one embodiment, an entity erasure unit may be regarded as an entity block.

[0029] In one embodiment, the memory control circuit 23 may logically associate the entity units 301(1) to 301(A) and 301(A + 1) to 301(B) with the data area 31 and the idle area 32 respectively. The entity units 301(1) to 301(A) in the data area 31 all store data (also referred to as user data) from the host system 11. For example, any entity unit in the data area 31 may store valid data and / or invalid data. In addition, the entity units 301(A + 1) - 301(B) in the idle area 32 do not store data (such as valid data).

[0030] In one embodiment, if a certain physical unit does not store valid data, this physical unit can be associated with the idle area 32. In addition, the physical units in the idle area 32 can be erased to clear the data in this physical unit. In one embodiment, the physical units in the idle area 32 are also referred to as idle physical units. In one embodiment, the idle area 32 is also referred to as the free pool.

[0031] In one embodiment, when data is to be stored, the memory control circuit 23 can select one or more physical units from the idle area 32 and instruct the memory module 122 to store the data into the selected physical units. After the data is stored in this physical unit, this physical unit can be associated with the data area 31. In other words, one or more physical units can be alternately used between the data area 31 and the idle area 32.

[0032] In one embodiment, the memory control circuit 23 can configure a plurality of logical units 302(1)~302(C) to map the physical units in the data area 31 (i.e., physical units 301(1)~301(A)). For example, one logical unit can correspond to one logical block address (Logical Block Address, LBA) or other logical management units. One logical unit can be mapped to one or more physical units.

[0033] In one embodiment, if a certain physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in this physical unit includes valid data. On the contrary, if a certain physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that this physical unit does not currently store any valid data.

[0034] In one embodiment, the memory control circuit 23 can record the mapping relationship between the logical units and the physical units in at least one management table (also referred to as the logical-to-physical mapping table). In one embodiment, the memory control circuit 23 can instruct the memory module 122 to perform operations such as data reading, writing, or erasing according to the information in this management table (i.e., the logical-to-physical mapping table).

[0035] In one embodiment, the memory module 122 supports multiple operation modes for storing data. For example, the multiple operation modes include a first operation mode and a second operation mode. The first operation mode is different from the second operation mode. In one embodiment, the access performance of the data stored in the memory module 122 based on the first operation mode can be higher than that of the data stored in the memory module 122 based on the second operation mode. In one embodiment, the reliability of the data stored in the memory module 122 based on the first operation mode can be higher than that of the data stored in the memory module 122 based on the second operation mode.

[0036] In one embodiment, the memory control circuit 23 may instruct the memory module 122 to program a certain physical unit (also referred to as the first physical unit) in the memory module 122 based on a first operation mode, so as to store data into the first physical unit based on the first operation mode. In one embodiment, the memory control circuit 23 may instruct the memory module 122 to program another physical unit (also referred to as the second physical unit) in the memory module 122 based on a second operation mode, so as to store data into the second physical unit based on the second operation mode.

[0037] In one embodiment, after storing data into the first physical unit based on the first operation mode, each memory cell in the first physical unit can be used to store p bits. In one embodiment, after storing data into the second physical unit based on the second operation mode, each memory cell in the second physical unit can be used to store q bits. It should be noted that p is less than q, and both p and q are positive integers. For example, p can be 1, and q can be 2, 3, 4 or other positive integers. However, the values of p and q can be adjusted according to practical requirements as long as the above specifications are met.

[0038] In one embodiment, the first operation mode may include a single-level cell (SLC) mode or a pseudo single-level cell (pseudo SLC) mode. In one embodiment, the second operation mode may include at least one of a multi-level cell (MLC) mode, a triple-level cell (TLC) mode, and a quad-level cell (QLC) mode. In addition, the first operation mode and the second operation mode may also include other operation modes as long as they meet the above specifications.

[0039] In one embodiment, the memory control circuit 23 may configure a buffer (also referred to as a write buffer) in the memory module 122. The write buffer may include at least one physical unit. In particular, the write buffer may be dedicated to storing data stored based on the first operation mode. In other words, the physical unit belonging to the write buffer (such as the first physical unit) can be programmed based on the first operation mode to store data into this physical unit (or the write buffer) based on the first operation mode.

[0040] In one embodiment, the memory control circuit 23 may configure a storage area in the memory module 122. The storage area may include multiple physical units. In particular, compared with the write buffer, the storage area can be used to store data stored based on the second operation mode. In other words, the physical unit belonging to the storage area (such as the second physical unit) can be programmed based on the second operation mode to store data into this physical unit (or the storage area) based on the second operation mode.

[0041] In one embodiment, the physical units belonging to the storage area can also be used to store data stored based on the first operation mode. However, the physical units belonging to the write buffer cannot be used to store data stored based on the second operation mode.

[0042] Figure 4 is a schematic diagram of managing physical units shown according to an embodiment of the present invention. Please refer to Figure 4 , in one embodiment, the memory control circuit 23 can further divide the write buffer 41 and the storage area 42 in the Figure 3 data area 31. The write buffer 41 includes physical units 401(1) to 401(D). The storage area 42 includes physical units 401(D + 1) to 401(F). In one embodiment, the total number of physical units 401(1) to 401(D) is less than the total number of physical units 401(D + 1) to 401(F). In addition, both the physical units 401(1) to 401(D) and 401(D + 1) to 401(F) are included in the Figure 3 physical units 301(1) to 301(B).

[0043] In one embodiment, the memory control circuit 23 can configure the physical units 401(1) to 401(D) in the write buffer 41 to be dedicated to storing data stored based on the first operation mode. On the other hand, the memory control circuit 23 can configure the physical units 401(D + 1) to 401(F) in the storage area 42 to be used for storing data stored based on the second operation mode. In one embodiment, the memory control circuit 23 can also configure at least one physical unit in the storage area 42 to be used for storing data stored based on the first operation mode.

[0044] In one embodiment, the memory control circuit 23 can control the memory module 122 in the pin mode. For example, the memory control circuit 23 can control the memory module 122 in the pin mode by controlling the voltage of specific pins between the memory controller 123 and the memory module 122. In one embodiment, the memory control circuit 23 can control the memory module 122 in other modes different from the pin mode (such as the normal operation mode).

[0045] In one embodiment, in the pin mode, the memory control circuit 23 can force the memory module 122 to store data based on the first operation mode. For example, in the pin mode, all newly stored data in the memory module 122 will be forced to be stored in the Figure 4 write buffer 41 based on the first operation mode. However, if the memory module 122 is not controlled in the pin mode, the newly stored data in the memory module 122 can be stored in the Figure 4 write buffer 41 or the storage area 42 as required.

[0046] In one embodiment, in some cases (such as when the write buffer 41 is full or a data consolidation operation is performed), the data originally stored in the write buffer 41 may be moved or copied to the storage area 42 for storage. Once the data belonging to a certain logical unit is moved or copied from the write buffer 41 to the storage area 42, the data belonging to this logical unit in the write buffer 41 will be marked as invalid (i.e., become invalid data), while the data belonging to this logical unit in the storage area 42 will be marked as valid (i.e., become valid data). In one embodiment, the data consolidation operation may include a garbage collection (GC) operation or other operations that support data movement or copying within the memory module 122.

[0047] In one embodiment, the memory control circuit 23 may receive an operation instruction (also referred to as a first operation instruction) from the host system 11. The first operation instruction instructs to store data (also referred to as first data). For example, the first operation instruction may include at least one write instruction. The first data may belong to at least one logical unit (also referred to as a first logical unit).

[0048] In one embodiment, in response to the first operation instruction, the memory control circuit 23 may store the first data into the memory module 122 based on the first operation mode. For example, in the pin mode, the memory control circuit 23 may instruct the memory module 122 to program the first physical unit based on the first operation mode to store the first data. For example, according to the first operation instruction, the first data may be stored into the write buffer (such as Figure 4 the write buffer 41). In one embodiment, if the first data is stored in the write buffer, the first logical unit may be mapped to the write buffer.

[0049] In one embodiment, after storing the first data, the memory control circuit 23 may detect whether a trigger condition is satisfied. For example, the trigger condition includes that the write buffer (such as Figure 4 the write buffer 41) is full. In one embodiment, the trigger condition can also be adjusted according to practical requirements, such as adjusted to the used capacity of the write buffer reaching a preset capacity, etc., which is not limited in the present invention.

[0050] In one embodiment, in response to the triggering condition being satisfied (e.g., the write buffer being full), the memory control circuit 23 may transmit management information to the host system 11. In particular, the management information may reflect whether the foregoing first data is still stored in the memory module 122 based on the first operation mode. However, if the triggering condition is not satisfied (e.g., the write buffer is not full), the memory control circuit 23 may not transmit the management information to the host system 11.

[0051] In one embodiment, it is assumed that after the first data is stored in Figure 4 the write buffer 41, the first data continues to be stored in the write buffer 41 (i.e., the first data is not moved or copied to Figure 4 the storage area 42), then the management information may reflect that the first data is still stored in the memory module 122 based on the first operation mode.

[0052] In another embodiment, it is assumed that after the first data is stored in Figure 4 the write buffer 41, the first data is moved or copied to Figure 4 the storage area 42, then the management information may reflect that the first data is not stored in the memory module 122 based on the first operation mode. For example, the management information may reflect that the first data has been changed to be stored in the memory module 122 based on the second operation mode.

[0053] In one embodiment, after storing the first data in the memory module 122 based on the first operation mode, the memory control circuit 23 may change to store the first data in the memory module 122 based on the second operation mode. For example, the memory control circuit 23 may move or copy the first data from Figure 4 the write buffer 41 to the storage area 42.

[0054] In response to the first data being changed to be stored based on the second operation mode (i.e., the first data is moved or copied from the write buffer 41 to the storage area 42), the memory control circuit 23 may update the management information. For example, the updated management information may reflect that the first data is not stored in the memory module 122 based on the first operation mode.

[0055] Or, more specifically, the updated management information may reflect that the first data has been changed to be stored in the memory module 122 based on the second operation mode. In one embodiment, if the first data is moved or copied to the storage area, the first logical unit may be modified to map to the storage area.

[0056] Figure 5 is a schematic diagram of the management information shown in the embodiments of the present invention. Please refer to Figure 5, in one embodiment, the management information includes bitmap information 51. For example, the bitmap information 51 can be implemented as one or more bitmap tables. The bitmap information 51 can include a plurality of bits B(1) to B(n). The bits B(1) to B(n) respectively correspond to a plurality of logical units LBA(1) to LBA(n). For example, the logical units LBA(1) to LBA(n) can be included in Figure 3 the logical units 302(1) to 302(C). In the bitmap information 51, the bit B(i) (also referred to as the first bit) can correspond to the logical unit LBA(i) (also referred to as the first logical unit). It should be noted that the information content or format of the bitmap information 51 can also be adjusted according to practical needs, and the present invention does not limit it.

[0057] In one embodiment, assuming that the first data belongs to the logical unit LBA(i), the bit value of the bit B(i) can reflect whether the first data is still stored in the memory module 122 based on the first operation mode.

[0058] For example, if the bit value of the bit B(i) is "0", it can indicate or reflect that the first data is still stored in the memory module 122 based on the first operation mode. However, if the bit value of the bit B(i) is "1", it can indicate or reflect that the first data is not stored in the memory module 122 based on the first operation mode (or the first data is stored in the memory module 122 based on the second operation mode). By analogy, the bit values of the bits B(1) to B(n) can sequentially reflect whether the data belonging to the logical units LBA(1) to LBA(n) is still stored in the memory module 122 based on the first operation mode. Or, in one embodiment, the bit values of the bits B(1) to B(n) can sequentially reflect that the data belonging to the logical units LBA(1) to LBA(n) is currently stored in the memory module 122 based on a specific operation mode (such as the first operation mode or the second operation mode).

[0059] In one embodiment, assuming that the first data was originally stored in the memory module 122 based on the first operation mode (i.e., the bit value of the bit B(i) is "0"). In response to the first data being changed to be stored in the memory module 122 based on the second operation mode, the memory control circuit 23 can update the bit value of the bit B(i) from "0" to "1". Thus, the updated bit B(i) (or the bitmap information 51) can reflect that the first data has been changed to be stored in the memory module 122 based on the second operation mode. In addition, the update method for the bit B(i) can be applied to update the bits B(1) to B(n), and will not be elaborated one by one here.

[0060] In one embodiment, after storing the first data in the memory module 122 based on the first operation mode, the memory control circuit 23 may receive another operation instruction (also referred to as the second operation instruction) from the host system 11. The second operation instruction instructs to access the memory module 122. For example, the second operation instruction may include a write instruction, a read instruction, a delete instruction, or other types of operation instructions. According to the second operation instruction, the memory control circuit 23 may instruct the memory module 122 to perform a corresponding operation (also referred to as the target operation), such as a write operation, a read operation, or an erase operation, etc.

[0061] In one embodiment, in response to the triggering condition being satisfied (e.g., the write buffer being full), the memory control circuit 23 may transmit notification information together with response information corresponding to the second operation instruction to the host system 11 in response to the second operation instruction.

[0062] In particular, the notification information may reflect that the triggering condition has been satisfied. For example, the notification information may be used to notify the host system 11 that the triggering condition has been satisfied (e.g., the write buffer has been full). For example, the notification information may be included in the response information or transmitted to the host system 11 following the response information. In addition, the response information may be used to notify the host system 11 that the second operation instruction has been completed or the execution result of the target operation.

[0063] [[ID= 9]]Specifically, when, before, or after executing the target operation, if the memory control circuit 23 detects that the current write buffer is full, while sending the response information corresponding to the second operation instruction to the host system 11, the memory control circuit 23 may also send this notification information to the host system 11. Among them, this response information may be used to indicate the execution result of the target operation, while the notification information is used to indicate that the current write buffer has been full.

[0064] In one embodiment, after transmitting the notification information to the host system 11, the memory control circuit 23 may receive a query instruction from the host system 11. This query instruction may be used to request the management information.

[0065] In one embodiment, the memory control circuit 23 may receive a query instruction generated by the host system according to the notification information. The information included in the query instruction includes, but is not limited to: logical unit information and data length information. The logical unit information is used to define the starting logical unit corresponding to the management information. The data length information is used to define the logical unit range corresponding to the management information.

[0066] In one embodiment, the memory control circuit 23 may transmit the management information to the host system 11 according to the query instruction. The management information includes, but is not limited to, corresponding logical unit information, data length information, data storage mode, etc. (For example, the write status of at least part of the data currently stored in the memory module 122 is represented by 0 and 1. For example, 0 indicates that a certain data is currently stored in the first operation mode, and 1 indicates that a certain data is currently stored in the second operation mode or other non-first operation modes).

[0067] In this way, it can be realized that while the storage device 12 executes the relevant instructions of the host system 11, it monitors the usage of the memory module 122, and synchronizes the information to the host system 11 when the usage reaches the trigger condition, so that the host system 11 can timely obtain the management information of the memory module 122 to decide whether to adjust the storage mode and storage location of at least part of the data, which is beneficial to the management of the memory module 122 and data storage planning.

[0068] In one embodiment, the memory control circuit 23 may also actively transmit the management information to the host system 11 periodically or in response to the satisfaction of the trigger condition, without receiving the query instruction from the host system 11.

[0069] In one embodiment, taking Figure 5 as an example, the starting logical unit defined by the logical unit information may be logical unit LBA(1), and the logical unit range defined by the data length information may be n consecutive logical units (i.e., logical units LBA(1) to LBA(n)).

[0070] In one embodiment, after providing the management information to the host system 11, the host system 11 may decide whether to adjust the storage method of the first data based on the management information. For example, according to the management information, the host system 11 may determine whether the previously stored first data is still stored in the memory module 122 based on the first operation mode (or whether the first data is switched to be stored in the memory module 122 based on the second operation mode). According to whether the first data is still stored in the memory module 122 based on the first operation mode, the host system 11 may decide whether to instruct the storage device 12 to adjust the storage method of the first data to improve the working efficiency of the storage device 12.

[0071] In one embodiment, if the management information reflects that the first data is not stored in the memory module 122 based on the first operation mode (for example, the first data has been switched to be stored in the memory module 122 based on the second operation mode), after transmitting the management information to the host system 11, the memory control circuit 23 may receive an operation instruction (also referred to as the third operation instruction) from the host system 11. The third operation instruction can be used to indicate re-storing the first data. For example, the third operation instruction may include a write instruction. In one embodiment, the third operation instruction can be used to indicate re-storing the first data based on the first operation mode.

[0072] In one embodiment, in response to the third operation instruction, the memory control circuit 23 may re-store the first data in the memory module 122 based on the first operation mode. For example, in the pin mode, the memory control circuit 23 may instruct the memory module 122 to program a certain physical unit (also referred to as the third physical unit) based on the first operation mode to re-store the first data. For example, according to the third operation instruction, the first data may be re-stored to the write buffer (for example Figure 4 the write buffer 41). In one embodiment, by re-storing the data (such as the first data) that has been moved or copied to the storage area (for example Figure 4 the storage area 42) in the write buffer (for example Figure 4 the write buffer 41), the access (such as reading) performance of the host system 11 and / or the storage device 12 for the first data can be accelerated.

[0073] Figure 6 is a flowchart of a memory management method shown according to an embodiment of the present invention. Specifically, please refer to Figure 6 the steps shown:

[0074] In step S601, receive a first operation instruction from the host system, where the first operation instruction indicates storing the first data.

[0075] In step S602, in response to the first operation instruction, store the first data in the memory module based on the first operation mode.

[0076] In step S603, determine or detect whether the trigger condition is satisfied.

[0077] In response to the trigger condition being satisfied, in step S604, transmit the management information to the host system.

[0078] In particular, the management information may reflect whether the first data is still stored in the memory module based on the first operation mode. However, if the trigger condition is not satisfied, step S604 may not be executed and, for example, the process may return to step S601.

[0079] Figure 7 is a flowchart of a memory management method shown according to an embodiment of the present invention. Please refer to Figure 7 , in step S701, a second operation instruction is received from a host system, where the second operation instruction indicates accessing a memory module. In step S702, notification information is transmitted to the host system together with response information corresponding to the second operation instruction to respond to the second operation instruction, where the notification information reflects that the trigger condition is satisfied. In step S703, a query instruction is received from the host system, where the query instruction is used to request the management information. In step S704, according to the query instruction, the management information is transmitted to the host system.

[0080] However, Figure 6 as Figure 7 each step in has been described in detail above and will not be elaborated here. It should be noted that Figure 6 as Figure 7 each step in can be implemented as multiple pieces of program code or circuits, and the present invention does not limit this. In addition, Figure 6 as Figure 7 the method of can be used in combination with the above exemplary embodiments or used alone, and the present invention does not limit this.

[0081] In summary, the memory management method and storage device proposed by the embodiments of the present invention can continuously monitor whether the storage mode of specific data in the memory module has changed (for example, whether the operation mode for storing data has changed and / or whether it is continuously stored in a write buffer with relatively high access performance in the memory module) and can report the monitoring result to the host system. For example, the monitoring result can be reported to the host system through the aforementioned management information. The host system can decide whether to adjust the storage mode of the specific data according to the monitoring result. Thus, the working efficiency of the storage device can be effectively improved.

[0082] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method, characterized in that, For a storage device, wherein the storage device includes a memory module, and the memory management method includes: Receiving a first operation instruction from a host system, wherein the first operation instruction instructs to store first data; In response to the first operation instruction, storing the first data into the memory module based on a first operation mode; and In response to a trigger condition being satisfied, transmitting management information to the host system, wherein the management information reflects whether the first data is still stored in the memory module based on the first operation mode.

2. The memory management method according to claim 1, further comprising: After storing the first data into the memory module based on the first operation mode, changing to store the first data into the memory module based on a second operation mode, wherein the second operation mode is different from the first operation mode; And In response to the first data being changed to be stored based on the second operation mode, updating the management information.

3. The memory management method according to claim 1, wherein the trigger condition includes that a write buffer is full, and the write buffer is dedicated to storing data stored based on the first operation mode.

4. The memory management method according to claim 1, wherein the step of transmitting the management information to the host system includes: Receiving a second operation instruction from the host system, wherein the second operation instruction instructs to access the memory module; And Transmitting notification information together with response information corresponding to the second operation instruction to the host system to respond to the second operation instruction, wherein the notification information reflects that the trigger condition is satisfied.

5. The memory management method according to claim 4, wherein the step of transmitting the management information to the host system further includes: After transmitting the notification information to the host system, receiving a query instruction from the host system, wherein the query instruction is used to request the management information; And According to the query instruction, transmitting the management information to the host system.

6. The memory management method according to claim 5, wherein the query instruction includes logical unit information and data length information, the logical unit information is used to define a starting logical unit corresponding to the management information, and the data length information is used to define a logical unit range corresponding to the management information.

7. The memory management method according to claim 1, further comprising: If the management information reflects that the first data is not stored in the memory module based on the first operation mode, then after transmitting the management information to the host system, receiving a third operation instruction from the host system; And In response to the third operation instruction, re-storing the first data into the memory module based on the first operation mode.

8. The memory management method according to claim 1, wherein the management information includes bit mapping information, the bit mapping information includes a plurality of bits, the plurality of bits respectively correspond to a plurality of logical units, the first bit among the plurality of bits corresponds to the first logical unit among the plurality of logical units, the first data belongs to the first logical unit, and the bit value of the first bit reflects whether the first data is still stored in the memory module based on the first operation mode.

9. The memory management method according to claim 1, further comprising: Controlling the memory module in a pin mode; And In the pin mode, forcibly specifying that the memory module stores data based on the first operation mode.

10. The memory management method according to claim 1, wherein the memory module supports the first operation mode and the second operation mode, the first operation mode includes a single-level cell mode, and the second operation mode is different from the first operation mode.

11. A storage device, characterized in that, Comprising: A connection interface for connecting to a host system; A memory module; And A memory controller connected to the connection interface and the memory module, wherein the memory controller is configured to: Receive a first operation instruction from the host system, wherein the first operation instruction instructs to store first data; In response to the first operation instruction, store the first data in the memory module based on the first operation mode; And In response to the trigger condition being satisfied, transmit management information to the host system, wherein the management information reflects whether the first data is still stored in the memory module based on the first operation mode.

12. The storage device according to claim 11, wherein the memory controller is further configured to: After storing the first data in the memory module based on the first operation mode, change to store the first data in the memory module based on the second operation mode, wherein the second operation mode is different from the first operation mode; and In response to the first data being changed to be stored based on the second operation mode, update the management information.

13. The storage device according to claim 11, wherein the trigger condition includes that the write buffer is full, and the write buffer is dedicated to storing data stored based on the first operation mode.

14. The storage device according to claim 11, wherein the operation of the memory controller transmitting the management information to the host system includes: Receiving a second operation instruction from the host system, wherein the second operation instruction instructs to access the memory module; And Transmitting notification information together with response information corresponding to the second operation instruction to the host system to respond to the second operation instruction, wherein the notification information reflects that the trigger condition is satisfied.

15. The storage device according to claim 14, wherein the operation of the memory controller transmitting the management information to the host system further includes: After transmitting the notification information to the host system, a query instruction is received from the host system, where the query instruction is used to request the management information; and According to the query instruction, the management information is transmitted to the host system.

16. The storage device according to claim 15, wherein the query instruction includes logical unit information and data length information, the logical unit information is used to define the starting logical unit corresponding to the management information, and the data length information is used to define the logical unit range corresponding to the management information.

17. The storage device according to claim 11, wherein the memory controller is further configured to: If the management information indicates that the first data is not stored in the memory module based on the first operation mode, after transmitting the management information to the host system, a third operation instruction is received from the host system; and In response to the third operation instruction, the first data is re-stored in the memory module based on the first operation mode.

18. The storage device according to claim 11, wherein the management information includes bit mapping information, the bit mapping information includes a plurality of bits, the plurality of bits respectively correspond to a plurality of logical units, the first bit among the plurality of bits corresponds to the first logical unit among the plurality of logical units, the first data belongs to the first logical unit, and the bit value of the first bit reflects whether the first data is still stored in the memory module based on the first operation mode.

19. The storage device according to claim 11, wherein the memory controller is further configured to: Control the memory module in a pin mode; and In the pin mode, force the memory module to store data based on the first operation mode.

20. The storage device according to claim 11, wherein the memory module supports the first operation mode and the second operation mode, the first operation mode includes a single-level cell mode, and the second operation mode is different from the first operation mode.

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