Reliability optimization method for adaptive Flash with variable replacement area

Abstract

The invention provides a reliability optimization method for a self-adaptive Flash with a variable replacement area, and relates to the technical field of Flash design, the method comprises the following steps: setting a related register for realizing unavailable address management in a Flash controller; dividing an on-chip Flash address space into a normal storage address field and a storage replacement address field; the Flash controller performs self-inspection, and when a bad block is detected to appear in a normal storage area, address access of the bad block in the normal storage area is remapped to a corresponding address of a storage replacement area by configuring an address remapping register group; and when detecting that a bad block appears in the storage replacement area, automatically marking the address as a failure state through the replacement area bad block register group, so that the Flash controller can avoid the bad block address of the storage replacement area during address remapping. According to the method, the address field is replaced by the divided storage and the dynamic address mapping mode is adopted, so that the bit error rate caused by the unavailable area of the Flash is greatly reduced, and the reliability of Flash data storage is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of Flash (flash memory) design, and particularly to an adaptive Flash reliability optimization method with a variable replacement area. Background Art

[0002] Flash memory has been widely used in embedded chips due to its advantages such as non-volatile data storage, high speed, and high storage density. With the continuous increase in integration density, Flash defects caused by process manufacturing are inevitable; taking Flash using the floating gate process as an example, the writing and erasing of data are realized by hot electron injection and tunneling effect. Repeated reading and writing will cause oxide layer breakdown and traps, resulting in high leakage current, causing Flash failure and affecting the reliability of storage. At present, the real-time requirements of embedded applications are increasing, and the increase in the number of bad blocks and the software processing method of bad blocks lead to a serious decline in performance, making it difficult to meet the real-time processing requirements of the system. Therefore, developing a hardware-based reliability optimization method for on-chip Flash can significantly improve storage reliability and meet the real-time processing requirements of the system. Summary of the Invention

[0003] Aiming at the problems existing in the above background art, the present invention proposes an adaptive Flash reliability optimization method with a variable replacement area, which is designed and optimized from the hardware level to effectively improve the storage reliability of on-chip Flash and meet the real-time processing requirements of the system.

[0004] Specifically, the present invention provides an adaptive Flash reliability optimization method with a variable replacement area, including: Setting relevant registers in the Flash controller for unavailable address management; Dividing the on-chip Flash address space into a normal storage address segment and a storage replacement address segment; The Flash controller performs self-check. When a bad block appears in the normal storage area, through configuring the address remapping register group, the access to the bad block address in the normal storage area is remapped to the corresponding address in the storage replacement area; when a bad block appears in the storage replacement area, the address is automatically marked as an invalid state through the bad block register group in the replacement area, so that the Flash controller can avoid the bad block address in the storage replacement area during address remapping.

[0005] As a further description of the present invention, the process of dividing the on-chip Flash address space into a normal storage address segment and a storage replacement address segment specifically includes the following steps: Setting an address range configuration register in the Flash controller; The Flash controller loads the address division parameters from a preset Flash sector into the address range configuration register to define the base address of the normal storage area and the initial capacity of the storage replacement area.

[0006] As a further description of the present invention, a bad block register group is set in the Flash controller, and the bad block register group is used to store the bad block addresses of the normal storage area; When a bad block is detected in the normal storage area, the bad block address is written into the bad block register group.

[0007] As a further description of the present invention, when a bad block is detected in the storage replacement area, the address is automatically marked as an invalid state through the replacement area bad block register group, which specifically includes the following process: A replacement area bad block register group is set in the Flash controller, and the replacement area bad block register group is used to save the bad block addresses of the storage replacement area; When a bad block is detected in the storage replacement area, the bad block address is written into the replacement area bad block register group and marked as permanently invalid.

[0008] As a further description of the present invention, the method further includes: According to the number of bad blocks in the normal storage area obtained after self-checking, the capacity of the storage replacement area is dynamically adjusted, and the end address of the normal storage area and the base address of the storage replacement area are synchronously updated to make the physical addresses of the normal storage address segment and the storage replacement address segment continuous.

[0009] As a further description of the present invention, the dynamic adjustment of the capacity of the storage replacement area and the synchronous update of the end address of the normal storage area and the base address of the storage replacement area specifically include the following process: A dynamic capacity adjustment register is set in the Flash controller, and the dynamic capacity adjustment register is used to store the current number of bad blocks and the storage redundancy coefficient; After the Flash controller completes self-checking, the capacity of the storage replacement area is adjusted to N + preset storage redundancy, where N is the number of bad blocks in the normal storage area, and the preset storage redundancy is calculated according to the storage redundancy coefficient; The end address of the normal storage area and the base address of the storage replacement area are recalculated according to the adjusted capacity of the storage replacement area to ensure the physical continuity of the normal storage address segment and the storage replacement address segment.

[0010] As a further description of the present invention, the access to the bad block address in the normal storage area is remapped to the corresponding address in the storage replacement area by configuring the address remapping register group, which specifically includes the following process: An address remapping register group is set in the Flash controller, and the address remapping register group is used to store the original bad block address and the replacement address; The Flash controller traverses all the bad blocks in the normal storage area in the order of the bad block table, and according to the bad block address information, allocates the available addresses in the storage replacement area to each bad block in the normal storage area in sequence, generates the mapping relationship between the original bad block address and the replacement address, and writes it into the address remapping register group; Enable the address remapping function. If the accessed address matches a certain original bad block address in the address remapping register group, the access is redirected to the corresponding replacement address in the storage replacement area.

[0011] As a further description of the present invention, when performing replacement address allocation, if the bad block address in the storage replacement area is encountered, skip this address and point the replacement address to the next available address.

[0012] As a further description of the present invention, the method further includes: During the operation of the system, when the Flash controller detects a newly added bad block in the storage replacement area, update the register by configuring the remapping table, and update the entry in the address remapping register group that points to the invalid address to the next available replacement address in the storage replacement area.

[0013] As a further description of the present invention, the process of updating the register by configuring the remapping table and updating the entry in the address remapping register group that points to the invalid address to the next available replacement address in the storage replacement area specifically includes the following process: Set a remapping table update register in the Flash controller, and the remapping table update register is used to store the original address to be updated and the new replacement address; When detecting a newly added bad block in the storage replacement area, the Flash controller writes the newly added bad block address into the replacement area bad block register group, queries the entries in the address remapping register group whose replacement addresses are equal to the newly added bad block address, and then writes the original address to be updated representing the newly added bad block address and the new replacement address representing the next available replacement address in the storage replacement area into the remapping table update register; The Flash controller automatically scans the address remapping register group and replaces the saved newly added bad block address with the new replacement address.

[0014] Compared with the prior art, the present invention has the following beneficial technical effects: The present invention adopts an optimized method of dynamic storage area partitioning and address remapping for the high-density integrated application of on-chip Flash, greatly improving the reliability of data storage, realizing the management of unavailable addresses of Flash at the hardware structure level, fully solving the system performance degradation caused by software processing, and the size of the storage replacement area is configurable and the full address range of the flash is measurable.

[0015] Other features and advantages of this technical solution will be described in the subsequent description, and in part will become apparent from the description, or will be understood by practicing this technical solution. The objectives and other advantages of this technical solution can be achieved and obtained through the structures specifically pointed out in the written description and the accompanying drawings.

[0016] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings are used to provide a further understanding of the present technical solution and constitute a part of the specification. Together with the embodiments of the present technical solution, they are used to explain the present technical solution and do not constitute a limitation of the present technical solution. In the accompanying drawings: Figure 1 This is a schematic diagram of the principle of the adaptive Flash reliability optimization method with a variable replacement area provided by the present invention.

[0018] Figure 2 This is a flow chart of the adaptive Flash reliability optimization method with variable replacement area provided by the present invention. DETAILED DESCRIPTION

[0019] The preferred embodiments of the present technical solution are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present technical solution and are not used to limit the present technical solution.

[0020] The present invention provides an adaptive Flash reliability optimization method with a variable replacement region. Its core is to achieve transparent replacement of unusable addresses and full physical address domain testability through a hardware-level dynamic address remapping mechanism and on-chip storage replacement region partitioning. The technical solution of the present invention is described in detail below with reference to specific embodiments.

[0021] like Figure 1 - Figure 2 As shown, an embodiment of the present invention provides an adaptive Flash reliability optimization method with a variable replacement area, comprising the following steps: S1: Set the relevant registers for implementing unusable address management in the Flash controller.

[0022] Specifically, such as Figure 1As shown in the figure, the Flash controller in the present invention includes a global control register (FLASH_CTRL_REG), an address range configuration register (ADDR_RANGE_CFG_REG), a bad block register group (BAD_BLOCK_REGS), a status register (FLASH_STATUS_REG), a dynamic capacity adjustment register (DYNAMIC_REMAP_SIZE_REG), a remapped area bad block register group (REMAP_BAD_BLOCK_REGS), a remap table update register (REMAP_UPDATE_REG), an address remap register group (REMAP_REGS), a test control register (TEST_CTRL_REG), and other related registers.

[0023] More specifically, the global control register is used to store global control instructions. In the address range configuration register, bits [23:0] are NORMAL_BASE_ADDR, which is used to participate in defining the address range of the normal storage area, and bits [31:24] are REMAP_SIZE, which is used to define the capacity of the storage replacement area. If the initial value of REMAP_SIZE is 0, the storage replacement area is disabled, and the normal storage area occupies all the Flash space. The bad block register group is used to store the bad block addresses in the normal storage area. It is composed of multiple 32-bit registers, and each register can store a bad block address (such as the end address 0x000FFF of the first 4KB sector). The status register is used to store status flags. The dynamic capacity adjustment register (REMAP_ADJUST_REG) is used to store the current number of bad blocks and the storage redundancy coefficient. Among them, bits [15:0] represent the current number of bad blocks (BAD_BLOCK_CNT), and bits [23:16] store the redundancy coefficient (REDUNDANCY_RATIO, the default value is 0x000A, which means 10%), and the remaining bits are reserved. The remapped area bad block register group is used to save the bad block addresses in the storage replacement area (bits [23:0]). The address remap register group is used to store the original bad block addresses and replacement addresses. Specifically, this register group is composed of multiple groups of 64-bit registers, and each group contains two fields: the original bad block address (ORIG_ADDR, bits [23:0]) and the replacement address (REMAPPED_ADDR, bits [63:40]), and the remaining bits are reserved bits. The remap table update register is used to store the original address to be updated and the new replacement address. This register is a 64-bit register, where bits [23:0] store the original address to be updated (OLD_ADDR), and bits [63:40] store the new replacement address (NEW_ADDR), and the remaining bits are reserved bits. The test control register is used to store test control instructions. The SELF_TEST_EN bit in it can enable the self-test mode, and when the test mode selection bit (TEST_MODE_SEL) is configured to 0xF, a full address traversal test can be realized.

[0024] The bad block register group, the dynamic capacity adjustment register, the replacement area bad block register group, the remapping table update register, and the address remapping register group jointly complete the mapping of the unavailable address area in the normal storage area and the control of the storage replacement area.

[0025] S2: Divide the on-chip Flash address space into a normal storage address segment and a storage replacement address segment.

[0026] Specifically, after the chip is powered on and reset, the Flash controller first initializes the global control register through the reset logic, and then loads the address division parameters from the preset Flash sector to the address range configuration register to define the base address of the normal storage area (NORMAL_BASE_ADDR) and the initial capacity of the storage replacement area (REMAP_SIZE).

[0027] S3: The Flash controller performs self-check. When a bad block appears in the normal storage area, by configuring the address remapping register group, the access to the bad block address in the normal storage area is remapped to the corresponding address in the storage replacement area; when a bad block appears in the storage replacement area, the address is automatically marked as an invalid state through the replacement area bad block register group, so that the Flash controller can avoid the bad block address in the storage replacement area during address remapping.

[0028] Specifically, during the self-check of the normal storage area, traverse the addresses in the normal storage area and write 0xFF, 0x00, 0xAA, 0x00, 0x55, 0x00, 0xFF in sequence. The addresses where the check fails (bad blocks) are recorded in the bad block register group. According to the number of bad blocks in the normal storage area obtained after the self-check, dynamically adjust the capacity of the storage replacement area, and synchronously update the end address of the normal storage area (NORMAL_END_ADDR) and the base address of the storage replacement area (REMAP_BASE_ADDR) to make the physical addresses of the normal storage address segment and the storage replacement address segment continuous. After completing the self-check of the normal storage area, the Flash controller performs the same self-check on the storage replacement area, and writes the detected bad block addresses into the replacement area bad block register group and marks them as permanently invalid.

[0029] More specifically, the specific implementation process of the above-mentioned dynamic adjustment of the storage replacement area capacity and synchronous update of the end address of the normal storage area and the base address of the storage replacement area is as follows: After the Flash controller completes self-check, adjust the capacity of the storage replacement area to N + the preset storage redundancy, where N is the number of bad blocks in the normal storage area, and the preset storage redundancy is calculated based on the storage redundancy coefficient. Recalculate the end address of the normal storage area and the base address of the storage replacement area according to the adjusted capacity of the storage replacement area to ensure that the physical addresses of the normal storage address segment and the storage replacement address segment are continuous. Dynamically adjust the capacity of the storage replacement area according to the number of bad blocks, and synchronously update the end address of the normal storage area (NORMAL_END_ADDR) and the base address of the storage replacement area (REMAP_BASE_ADDR) to ensure physical address continuity. For example, if the number of bad blocks in the normal storage area after self-check is N, the capacity of the storage replacement area (REMAP_SIZE) is set to N × (1 + storage redundancy margin coefficient (REDUNDANCY_RATIO) / 10)) to ensure that the capacity of the storage replacement area covers the current bad blocks and reserves expansion space. During this process, the end address of the normal storage area (NORMAL_END_ADDR) is recalculated as NORMAL_BASE_ADDR+(ORIGINAL_SIZE-REMAP_SIZE-1), where NORMAL_BASE_ADDR is the base address of the normal storage area, ORIGINAL_SIZE is the original total capacity, and REMAP_SIZE is the adjusted capacity of the storage replacement area; the base address of the storage replacement area (REMAP_BASE_ADDR) is equal to NORMAL_END_ADDR + 1, thus ensuring the physical address continuity of the two areas. The new REMAP_SIZE is automatically updated to the address range configuration register. After all address parameters are updated, the Flash controller sets bit [1] of the status register (ADJUST_DONE flag) to indicate the completion of the adjustment.

[0030] By configuring the address remapping register group as described above, the access to the bad block address in the normal storage area is remapped to the corresponding address in the storage replacement area. The specific implementation process is as follows: The Flash controller traverses all the bad blocks in the normal storage area in the order of the bad block table, and based on the bad block address information, assigns available addresses in the storage replacement area to each bad block in the normal storage area in sequence, generates the mapping relationship between the original bad block address and the replacement address, and writes it into the address remapping register group; Enable the address remapping function (FLASH_CTRL_REG.REMAP_EN = 1). If the access address matches a certain original bad block address in the address remapping register group, the access is redirected to the corresponding replacement address in the storage replacement area, realizing real-time redirection to the replacement address when accessing a bad block. For example, if the bad block address in the normal storage area is 0x001000, and the starting address of the storage replacement area is 0x008000 and its first address 0x008000 is valid, a group of registers in the address remapping register group is configured such that ORIG_ADDR (original bad block address) = 0x001000 and REMAPPED_ADDR (replacement address) = 0x008000. The replacement address is allocated in an incremental manner. If an address in the storage replacement area is marked as a bad block in the replacement area bad block register group, that address is skipped, and REMAPPED_ADDR is pointed to the next available address (such as 0x008001). Thereafter, all processor access requests to the Flash will pass through the address conversion logic: If the access address falls within the normal storage area and does not appear in the ORIG_ADDR field of the address remapping register group, the original address is directly accessed; If the access address matches a certain ORIG_ADDR, the access is redirected to the corresponding REMAPPED_ADDR. The address conversion logic adopts a three-stage pipeline comparator architecture: The first stage compares the access address with the range of NORMAL_BASE_ADDR (normal storage area base address) / NORMAL_END_ADDR (normal storage area end address), the second stage parallelly compares all ORIG_ADDR fields, and the third stage selects and outputs the physical address.

[0031] During system operation, when the Flash controller detects a newly added bad block in the storage replacement area, by configuring the remapping table update register, the entry in the address remapping register group pointing to the invalid address is updated to the next available replacement address in the storage replacement area.

[0032] Specifically, when a new bad block is detected in the storage replacement area, the Flash controller writes the address of the new bad block into the bad block register group of the replacement area, queries the entries in the address remapping register group where all replacement addresses are equal to the address of the new bad block, and then writes the original address to be updated representing the address of the new bad block and the new replacement address representing the next available replacement address in the storage replacement area into the remapping table update register; the Flash controller automatically scans the address remapping register group and replaces the saved address of the new bad block with the new replacement address. For example, when it is detected that the address 0x008001 in the storage replacement area fails and the next available address is 0x008002, writing OLD_ADDR = 0x008001 and NEW_ADDR = 0x008002 into the remapping table update register can complete the update of the relevant entries. This mechanism indicates the update status through bit [0] (UPDATE_BUSY) of the status register.

[0033] Obviously, those skilled in the art can make various changes and modifications to this technical solution without departing from the spirit and scope of this technical solution. Thus, if these modifications and variations of this technical solution fall within the scope of the claims of this technical solution and its equivalent technologies, then this technical solution is also intended to include these changes and modifications.

Claims

1. An adaptive Flash reliability optimization method with a variable replacement area, characterized in that, Including: Setting relevant registers for implementing unavailable address management in the Flash controller; Dividing the on-chip Flash address space into a normal storage address segment and a storage replacement address segment; The Flash controller performs self-check. When a bad block appears in the normal storage area, by configuring the address remapping register group, the access to the bad block address in the normal storage area is remapped to the corresponding address in the storage replacement area; when a bad block appears in the storage replacement area, the address is automatically marked as an invalid state through the bad block register group in the replacement area, so that the Flash controller can avoid the bad block address in the storage replacement area during address remapping.

2. The adaptive Flash reliability optimization method with variable replacement area as claimed in claim 1, wherein The process of dividing the on-chip Flash address space into a normal storage address segment and a storage replacement address segment specifically includes the following steps: Setting an address range configuration register in the Flash controller; The Flash controller loads address division parameters from a preset Flash sector into the address range configuration register to define the base address of the normal storage area and the initial capacity of the storage replacement area.

3. The adaptive Flash reliability optimization method with variable replacement area according to claim 1, characterized in that Setting a bad block register group in the Flash controller, where the bad block register group is used to store the bad block addresses in the normal storage area; When a bad block is detected in the normal storage area, the bad block address is written into the bad block register group.

4. The adaptive Flash reliability optimization method with a variable replacement area as claimed in claim 1, wherein The process of automatically marking the address as an invalid state through the bad block register group in the replacement area when a bad block is detected in the storage replacement area specifically includes the following steps: Setting a bad block register group in the replacement area in the Flash controller, where the bad block register group in the replacement area is used to save the bad block addresses in the storage replacement area; When a bad block is detected in the storage replacement area, the bad block address is written into the bad block register group in the replacement area and marked as permanently invalid.

5. The adaptive Flash reliability optimization method with a variable replacement area according to claim 1, characterized in that, The method further includes: Dynamically adjusting the capacity of the storage replacement area according to the number of bad blocks in the normal storage area obtained after self-check, and synchronously updating the end address of the normal storage area and the base address of the storage replacement area to make the physical addresses of the normal storage address segment and the storage replacement address segment continuous.

6. The adaptive Flash reliability optimization method with a variable replacement area as claimed in claim 5, wherein The process of dynamically adjusting the capacity of the storage replacement area and synchronously updating the end address of the normal storage area and the base address of the storage replacement area specifically includes the following steps: Setting a dynamic capacity adjustment register in the Flash controller, where the dynamic capacity adjustment register is used to store the current number of bad blocks and the storage redundancy coefficient; After the Flash controller completes self-check, adjusting the capacity of the storage replacement area to N + preset storage redundancy, where N is the number of bad blocks in the normal storage area, and the preset storage redundancy is calculated according to the storage redundancy coefficient; Recalculating the end address of the normal storage area and the base address of the storage replacement area according to the adjusted capacity of the storage replacement area to ensure the continuity of the physical addresses of the normal storage address segment and the storage replacement address segment.

7. The adaptive Flash reliability optimization method with a variable replacement area as described in claim 1, wherein, The process of remapping the access to the bad block address in the normal storage area to the corresponding address in the storage replacement area by configuring the address remapping register group specifically includes the following steps: Setting an address remapping register group in the Flash controller, where the address remapping register group is used to store the original bad block address and the replacement address; The Flash controller traverses all the bad blocks in the normal storage area in the order of the bad block table, and according to the bad block address information, allocates the available addresses in the storage replacement area to each bad block in the normal storage area in sequence, generates the mapping relationship between the original bad block address and the replacement address, and writes it into the address remapping register group; Enable the address remapping function. If the accessed address matches a certain original bad block address in the address remapping register group, the access is redirected to the corresponding replacement address in the storage replacement area.

8. The adaptive Flash reliability optimization method with a variable replacement area as described in claim 7, characterized in that, When allocating the replacement address, if the bad block address in the storage replacement area is encountered, skip this address and point the replacement address to the next available address.

9. The adaptive Flash reliability optimization method with a variable replacement area according to claim 7, characterized in that, The method further includes: During the operation of the system, when the Flash controller detects a newly added bad block in the storage replacement area, update the register by configuring the remapping table, and update the entry in the address remapping register group that points to the invalid address to the next available replacement address in the storage replacement area.

10. The adaptive Flash reliability optimization method with a variable replacement area according to claim 9, characterized in that The process of updating the register by configuring the remapping table and updating the entry in the address remapping register group that points to the invalid address to the next available replacement address in the storage replacement area specifically includes the following process: Set a remapping table update register in the Flash controller, and the remapping table update register is used to store the original address to be updated and the new replacement address; When detecting a newly added bad block in the storage replacement area, the Flash controller writes the newly added bad block address into the replacement area bad block register group, queries the entries in the address remapping register group whose replacement addresses are equal to the newly added bad block address, and then writes the original address to be updated representing the newly added bad block address and the new replacement address representing the next available replacement address in the storage replacement area into the remapping table update register; The Flash controller automatically scans the address remapping register group and replaces the saved newly added bad block address with the new replacement address.

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