An adaptive Flash reliability optimization method with variable replacement area

Abstract

The present invention provides an adaptive Flash reliability optimization method with a variable replacement area, relating to the field of Flash design technology. The method comprises: providing relevant registers for implementing unavailable address management in a Flash controller; dividing the on-chip Flash address space into a normal storage address segment and a storage replacement address segment; the Flash controller performing a self-check, and when a bad block is detected in the normal storage area, configuring an address remapping register group so that access to the bad block address in the normal storage area is remapped to the corresponding address in the storage replacement area; and when a bad block is detected in the storage replacement area, automatically marking the address as invalid using the replacement area bad block register group, so that the Flash controller can avoid the bad block address in the storage replacement area during address remapping. The present invention utilizes the division of the storage replacement address segment and dynamic address mapping to significantly reduce the bit error rate caused by the Flash unavailable area and improve the reliability of Flash data storage.

Description

Technical Field

[0001] The present invention relates to the technical field of Flash (flash memory) design, and in particular to an adaptive Flash reliability optimization method with a variable replacement area. Background Art

[0002] Flash memory is widely used in embedded chips due to its advantages such as non-volatility, high speed, and high storage density. As integration density continues to increase, Flash defects caused by manufacturing processes are inevitable. For example, in Flash memory using a floating gate process, data is written and erased using hot electron injection and the tunneling effect. Repeated reading and writing can cause oxide breakdown and traps, resulting in high leakage current, causing Flash failure and compromising storage reliability. Currently, embedded applications are facing increasingly stringent real-time requirements. The increasing number of bad blocks and the software-based handling of bad blocks lead to significant performance degradation, making it difficult to meet the real-time processing requirements of the system. Therefore, developing a hardware-based on-chip Flash reliability optimization method can significantly improve storage reliability and meet the real-time processing requirements of the system. Summary of the Invention

[0003] In response to the problems existing in the above background technology, the present invention proposes an adaptive Flash reliability optimization method with a variable replacement area, which performs design optimization at the hardware level, effectively improves the storage reliability of on-chip Flash, and meets the real-time processing requirements of the system.

[0004] Specifically, the present invention provides an adaptive Flash reliability optimization method with a variable replacement area, comprising:

[0005] Setting relevant registers for implementing unavailable address management in the Flash controller;

[0006] Divide the on-chip Flash address space into a normal storage address segment and a storage replacement address segment;

[0007] The Flash controller performs self-checks. When a bad block is detected in the normal storage area, the address remapping register group is configured to remap the bad block address access in the normal storage area to the corresponding address in the storage replacement area. When a bad block is detected in the storage replacement area, the replacement area bad block register group automatically marks the address as invalid, allowing the Flash controller to avoid the bad block address in the storage replacement area during address remapping.

[0008] As a further explanation of the present invention, the division of the on-chip Flash address space into a normal storage address segment and a storage replacement address segment specifically includes the following process:

[0009] Set the address range configuration register in the Flash controller;

[0010] The Flash controller loads address partition parameters from a preset Flash sector into the address range configuration register to define a base address of a normal storage area and an initial capacity of a storage replacement area.

[0011] As a further illustration of the present invention, a bad block register group is set in the Flash controller, and the bad block register group is used to store the bad block addresses of the normal storage area;

[0012] When a bad block is detected in a normal storage area, the bad block address is written into the bad block register group.

[0013] As a further explanation of the present invention, when a bad block is detected in the storage replacement area, the address is automatically marked as failed through the replacement area bad block register group, which specifically includes the following process:

[0014] A replacement area bad block register group is set in the Flash controller, wherein the replacement area bad block register group is used to store and store the replacement area bad block address;

[0015] When a bad block is detected in the storage replacement area, the bad block address is written into the replacement area bad block register group and marked as permanently failed.

[0016] As a further illustration of the present invention, the method further comprises:

[0017] According to the number of bad blocks in the normal storage area obtained after self-test, the capacity of the storage replacement area is dynamically adjusted, and the end address of the normal storage area and the base address of the storage replacement area are synchronously updated to make the physical addresses of the normal storage address segment and the storage replacement address segment continuous.

[0018] As a further explanation of the present invention, the dynamic adjustment of the storage replacement area capacity and the synchronous update of the normal storage area end address and the storage replacement area base address specifically include the following process:

[0019] A dynamic capacity adjustment register is set in the Flash controller, wherein the dynamic capacity adjustment register is used to store the current number of bad blocks and a storage redundancy coefficient;

[0020] After the Flash controller completes the self-test, the storage replacement area capacity is adjusted to N+preset storage redundancy, where N is the number of bad blocks in the normal storage area and the preset storage redundancy is calculated according to the storage redundancy coefficient;

[0021] The end address of the normal storage area and the base address of the storage replacement area are recalculated according to the adjusted storage replacement area capacity to ensure that the physical addresses of the normal storage address segment and the storage replacement address segment are continuous.

[0022] As a further explanation of the present invention, the configuration of the address remapping register group so that the bad block address access in the normal storage area is remapped to the corresponding address in the storage replacement area specifically includes the following process:

[0023] An address remapping register group is set in the Flash controller, wherein the address remapping register group is used to store the original bad block address and the replacement address;

[0024] The Flash controller traverses all bad blocks in the normal storage area according to the bad block table. Based on the bad block address information, it sequentially allocates available addresses in the storage replacement area to each bad block in the normal storage area. It generates a mapping between the original bad block address and the replacement address and writes it into the address remapping register group.

[0025] Enable the address remapping function. If the access address matches an original bad block address in the address remapping register group, the access is redirected to the corresponding replacement address in the storage replacement area.

[0026] As a further illustration of the present invention, when allocating a replacement address, if a bad block address of a storage replacement area is encountered, the address is skipped and the replacement address is directed to the next available address.

[0027] As a further illustration of the present invention, the method further comprises:

[0028] During system operation, when the Flash controller detects a new bad block in the storage replacement area, it updates the entry pointing to the failed address in the address remapping register group to the next available replacement address in the storage replacement area by configuring the remapping table update register.

[0029] As a further illustration of the present invention, the updating of the entry pointing to the failed address in the address remapping register group to the next available replacement address in the storage replacement area by configuring the remapping table update register specifically includes the following process:

[0030] A remapping table update register is set in the Flash controller, wherein the remapping table update register is used to store the original address to be updated and the new replacement address;

[0031] When a new bad block is detected in the storage replacement area, the Flash controller writes the address of the new bad block into the replacement area bad block register group, queries the address remapping register group for entries equal to the new bad block address among all replacement addresses, and then writes the original address to be updated representing the new bad block address and the new replacement address representing the next available replacement address in the storage replacement area into the remapping table update register;

[0032] The Flash controller automatically scans the address remapping register group and replaces the newly added bad block addresses stored therein with the new replacement addresses.

[0033] Compared with the prior art, the present invention has the following beneficial technical effects:

[0034] Aiming at high-density integrated applications of on-chip Flash, the present invention adopts an optimization method of dynamic storage area partitioning and address remapping, greatly improving the reliability of data storage, realizing Flash unavailable address management at the hardware structure level, fully solving the system performance degradation caused by software processing, and the storage replacement area size is configurable and the full Flash address range is measurable.

[0035] Other features and advantages of this technical solution will be described in the subsequent description, and in part will become apparent from the description, or understood by practicing this technical solution. The objectives and other advantages of this technical solution can be achieved and obtained through the structures specifically pointed out in the written description and the accompanying drawings.

[0036] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The accompanying drawings are used to provide a further understanding of the present technical solution and constitute a part of the specification. Together with the embodiments of the present technical solution, they are used to explain the present technical solution and do not constitute a limitation of the present technical solution. In the accompanying drawings:

[0038] Figure 1 This is a schematic diagram of the principle of the adaptive Flash reliability optimization method with a variable replacement area provided by the present invention.

[0039] Figure 2 This is a flow chart of the adaptive Flash reliability optimization method with variable replacement area provided by the present invention. DETAILED DESCRIPTION

[0040] The preferred embodiments of the present technical solution are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present technical solution and are not used to limit the present technical solution.

[0041] The present invention provides an adaptive Flash reliability optimization method with a variable replacement region. Its core is to achieve transparent replacement of unusable addresses and full physical address domain testability through a hardware-level dynamic address remapping mechanism and on-chip storage replacement region partitioning. The technical solution of the present invention is described in detail below with reference to specific embodiments.

[0042] like Figure 1-Figure 2 As shown, an embodiment of the present invention provides an adaptive Flash reliability optimization method with a variable replacement area, comprising the following steps:

[0043] S1: Set the relevant registers for implementing unusable address management in the Flash controller.

[0044] Specifically, such as Figure 1 As shown, the Flash controller in the present invention includes a global control register (FLASH_CTRL_REG), an address range configuration register (ADDR_RANGE_CFG_REG), a bad block register group (BAD_BLOCK_REGS), a status register (FLASH_STATUS_REG), a dynamic capacity adjustment register (DYNAMIC_REMAP_SIZE_REG), a replacement area bad block register group (REMAP_BAD_BLOCK_REGS), a remapping table update register (REMAP_UPDATE_REG), an address remapping register group (REMAP_REGS), a test control register (TEST_CTRL_REG) and other related registers.

[0045] More specifically, the global control register stores global control instructions. In the address range configuration register, bits [23:0] are NORMAL_BASE_ADDR, which defines the address range of the normal storage area. Bits [31:24] are REMAP_SIZE, which defines the capacity of the replacement area. If the initial value of REMAP_SIZE is 0, the replacement area is disabled, and the normal storage area occupies all Flash memory space. The bad block register group stores bad block addresses in the normal storage area. It consists of multiple 32-bit registers, each of which can store a bad block address (for example, the end address of the first 4KB sector, 0x000FFF). The status register stores status flags. The dynamic capacity adjustment register (REMAP_ADJUST_REG) stores the current number of bad blocks and the redundancy factor. Bits [15:0] represent the current number of bad blocks (BAD_BLOCK_CNT), and bits [23:16] store the redundancy factor (REDUNDANCY_RATIO, with a default value of 0x000A, representing 10%). The remaining bits are reserved. The replacement area bad block register group stores the bad block addresses of the replacement area (bits [23:0]). The address remapping register group stores the original bad block addresses and replacement addresses. Specifically, this register group consists of multiple 64-bit registers, each containing two fields: the original bad block address (ORIG_ADDR, bits [23:0]) and the replacement address (REMAPPED_ADDR, bits [63:40]). The remaining bits are reserved. The remapping table update register stores the original address to be updated and the new replacement address. This 64-bit register stores the original address to be updated (OLD_ADDR) in bits [23:0] and the new replacement address (NEW_ADDR) in bits [63:40]. The remaining bits are reserved. The test control register stores test control instructions. The SELF_TEST_EN bit enables self-test mode. Setting the test mode select bit (TEST_MODE_SEL) to 0xF enables full address traversal testing.

[0046] The bad block register group, dynamic capacity adjustment register, replacement area bad block register group, remapping table update register and address remapping register group jointly complete the mapping of unavailable address areas in the normal storage area and the control of the storage replacement area.

[0047] S2: Divide the on-chip Flash address space into a normal storage address segment and a storage replacement address segment.

[0048] Specifically, after the chip is powered on and reset, the Flash controller first initializes the global control register through the reset logic, and then loads the address partition parameters from the preset Flash sector to the address range configuration register to define the normal storage area base address (NORMAL_BASE_ADDR) and the initial capacity of the storage replacement area (REMAP_SIZE).

[0049] S3: The Flash controller performs a self-check. When a bad block is detected in the normal storage area, the address remapping register group is configured to remap the bad block address access in the normal storage area to the corresponding address in the storage replacement area. When a bad block is detected in the storage replacement area, the replacement area bad block register group is used to automatically mark the address as invalid, so that the Flash controller can avoid the bad block address in the storage replacement area during address remapping.

[0050] Specifically, during a self-test of the normal storage area, the normal storage area address is traversed and 0xFF, 0x00, 0xAA, 0x00, 0x55, 0x00, and 0xFF are written in sequence. Addresses that fail verification (bad blocks) are recorded in the bad block register group. Based on the number of bad blocks in the normal storage area determined after the self-test, the capacity of the replacement storage area is dynamically adjusted, and the normal storage area end address (NORMAL_END_ADDR) and replacement storage area base address (REMAP_BASE_ADDR) are synchronously updated to ensure that the physical addresses of the normal storage address segment and replacement storage address segment are continuous. After completing the normal storage area self-test, the flash controller performs the same self-test on the replacement storage area. The detected bad block addresses are written to the replacement area bad block register group and marked as permanently failed.

[0051] More specifically, the specific implementation process of dynamically adjusting the storage replacement area capacity and synchronously updating the normal storage area end address and the storage replacement area base address is as follows:

[0052] After the flash controller completes its self-test, it adjusts the replacement area capacity to N + the preset redundancy factor, where N is the number of bad blocks in the normal storage area and the preset redundancy factor is calculated based on the redundancy factor. The normal storage area end address and replacement area base address are recalculated based on the adjusted replacement area capacity to ensure physical address continuity between the normal storage address segment and the replacement area address segment. The replacement area capacity is dynamically adjusted based on the number of bad blocks, and the normal storage area end address (NORMAL_END_ADDR) and replacement area base address (REMAP_BASE_ADDR) are updated simultaneously to ensure physical address continuity. For example, if the number of bad blocks in the normal storage area is N after the self-test completes, the replacement area capacity (REMAP_SIZE) is set to N × (1 + redundancy margin factor (REDUNDANCY_RATIO) / 10) to ensure that the replacement area capacity covers the current bad blocks and reserves space for expansion. During this process, the end address of the normal storage area (NORMAL_END_ADDR) is recalculated as NORMAL_BASE_ADDR + (ORIGINAL_SIZE - REMAP_SIZE - 1), where NORMAL_BASE_ADDR is the base address of the normal storage area, ORIGINAL_SIZE is the original total capacity, and REMAP_SIZE is the adjusted capacity of the storage replacement area. The storage replacement area base address (REMAP_BASE_ADDR) is equal to NORMAL_END_ADDR + 1, ensuring that the physical addresses of the two areas are continuous. The new REMAP_SIZE is automatically updated in the address range configuration register. After all address parameters are updated, the flash controller sets the [1] bit (ADJUST_DONE flag) in the status register to indicate that the adjustment is complete.

[0053] The above configuration of the address remapping register group allows the bad block address access in the normal storage area to be remapped to the corresponding address in the storage replacement area. The specific implementation process is as follows: the Flash controller traverses the bad blocks in all normal storage areas in order according to the bad block table, and allocates the available address of the storage replacement area in order for each bad block in the normal storage area based on the bad block address information, generates the mapping relationship between the original bad block address and the replacement address, and writes it to the address remapping register group; enables the address remapping function (FLASH_CTRL_REG.REMAP_EN=1), and if the access address matches an original bad block address in the address remapping register group, the access is redirected to the corresponding replacement address in the storage replacement area, realizing real-time redirection to the replacement address when accessing the bad block. For example, if the bad block address in the normal storage area is 0x001000, and the starting address of the replacement area is 0x008000, and its first address 0x008000 is valid, then a set of registers in the address remapping register set is configured with ORIG_ADDR (original bad block address) = 0x001000 and REMAPPED_ADDR (replacement address) = 0x008000. The replacement address is assigned incrementally. If an address in the replacement area is marked as bad in the replacement area bad block register set, that address is skipped and REMAPPED_ADDR is set to point to the next available address (such as 0x008001). All subsequent processor access requests to the Flash memory will undergo address translation logic: if the access address falls within the normal storage area and does not appear in the ORIG_ADDR field of the address remapping register set, the original address is accessed directly; if the access address matches a specific ORIG_ADDR, the access is redirected to the corresponding REMAPPED_ADDR. The address translation logic uses a three-stage pipeline comparator architecture: the first stage compares the access address with the NORMAL_BASE_ADDR (normal storage area base address) / NORMAL_END_ADDR (normal storage area end address) range, the second stage compares all ORIG_ADDR fields in parallel, and the third stage selects the output physical address.

[0054] During system operation, when the Flash controller detects a new bad block in the storage replacement area, it updates the entry pointing to the failed address in the address remapping register group to the next available replacement address in the storage replacement area by configuring the remapping table update register.

[0055] Specifically, when a new bad block is detected in the storage replacement area, the Flash controller writes the address of the new bad block to the replacement area bad block register group and queries the address remapping register group for an entry that is equal to the new bad block address among all replacement addresses. It then writes the original address to be updated, representing the new bad block address, and the new replacement address, representing the next available replacement address in the storage replacement area, to the remapping table update register. The Flash controller automatically scans the address remapping register group and replaces the new bad block address stored therein with the new replacement address. For example, if it detects that storage replacement area address 0x008001 is invalid and the next available address is 0x008002, the relevant entries are updated by writing OLD_ADDR = 0x008001 and NEW_ADDR = 0x008002 to the remapping table update register. This mechanism indicates the update status via bit [0] (UPDATE_BUSY) of the status register.

[0056] Obviously, those skilled in the art may make various changes and modifications to this technical solution without departing from the spirit and scope of this technical solution. Thus, if these modifications and variations of this technical solution fall within the scope of the claims of this technical solution and their equivalents, this technical solution is intended to include these modifications and variations.

Claims

1. An adaptive Flash reliability optimization method with a variable replacement area, characterized in that: include: Setting relevant registers for implementing unavailable address management in the Flash controller; Divide the on-chip Flash address space into a normal storage address segment and a storage replacement address segment; The Flash controller performs self-tests. When a bad block is detected in the normal storage area, it configures the address remapping register group to remap the bad block address in the normal storage area to the corresponding address in the storage replacement area. When a bad block is detected in the storage replacement area, the replacement area bad block register group automatically marks the address as invalid, allowing the Flash controller to avoid the bad block address in the storage replacement area during address remapping. According to the number of bad blocks in the normal storage area obtained after self-test, the capacity of the storage replacement area is dynamically adjusted, and the end address of the normal storage area and the base address of the storage replacement area are synchronously updated to make the physical addresses of the normal storage address segment and the storage replacement address segment continuous.

2. The adaptive Flash reliability optimization method with a variable replacement area according to claim 1, characterized in that: The on-chip Flash address space is divided into a normal storage address segment and a storage replacement address segment, specifically including the following process: Set the address range configuration register in the Flash controller; The Flash controller loads address partition parameters from a preset Flash sector into the address range configuration register to define a base address of a normal storage area and an initial capacity of a storage replacement area.

3. The adaptive Flash reliability optimization method with a variable replacement area according to claim 1, characterized in that: A bad block register group is set in the Flash controller, wherein the bad block register group is used to store bad block addresses in the normal storage area; When a bad block is detected in a normal storage area, the bad block address is written into the bad block register group.

4. The adaptive Flash reliability optimization method with a variable replacement area according to claim 1, wherein: When a bad block is detected in the storage replacement area, the address is automatically marked as a failed state through the replacement area bad block register group, which specifically includes the following process: A replacement area bad block register group is set in the Flash controller, wherein the replacement area bad block register group is used to store and store the replacement area bad block address; When a bad block is detected in the storage replacement area, the bad block address is written into the replacement area bad block register group and marked as permanently failed.

5. The adaptive Flash reliability optimization method with a variable replacement area according to claim 1, wherein: The dynamic adjustment of the storage replacement area capacity and the synchronous update of the normal storage area end address and the storage replacement area base address specifically include the following processes: A dynamic capacity adjustment register is set in the Flash controller, wherein the dynamic capacity adjustment register is used to store the current number of bad blocks and a storage redundancy coefficient; After the Flash controller completes the self-test, the storage replacement area capacity is adjusted to N+preset storage redundancy, where N is the number of bad blocks in the normal storage area and the preset storage redundancy is calculated according to the storage redundancy coefficient; The end address of the normal storage area and the base address of the storage replacement area are recalculated according to the adjusted storage replacement area capacity to ensure that the physical addresses of the normal storage address segment and the storage replacement address segment are continuous.

6. The adaptive Flash reliability optimization method with a variable replacement area according to claim 1, characterized in that: The configuration of the address remapping register group enables the bad block address access in the normal storage area to be remapped to the corresponding address in the storage replacement area, which specifically includes the following process: An address remapping register group is set in the Flash controller, wherein the address remapping register group is used to store the original bad block address and the replacement address; The Flash controller traverses all bad blocks in the normal storage area according to the bad block table. Based on the bad block address information, it sequentially allocates available addresses in the storage replacement area to each bad block in the normal storage area. It generates a mapping between the original bad block address and the replacement address and writes it into the address remapping register group. Enable the address remapping function. If the access address matches an original bad block address in the address remapping register group, the access is redirected to the corresponding replacement address in the storage replacement area.

7. The adaptive Flash reliability optimization method with a variable replacement area according to claim 6, characterized in that: When allocating replacement addresses, if a bad block address of the storage replacement area is encountered, the address is skipped and the replacement address is pointed to the next available address.

8. The adaptive Flash reliability optimization method with a variable replacement area according to claim 6, characterized in that: The method further comprises: During system operation, when the Flash controller detects a new bad block in the storage replacement area, it updates the entry pointing to the failed address in the address remapping register group to the next available replacement address in the storage replacement area by configuring the remapping table update register.

9. The adaptive Flash reliability optimization method with a variable replacement area according to claim 8, characterized in that: The updating register of the remapping table is configured to update the entry pointing to the failed address in the address remapping register group to the next available replacement address in the storage replacement area, which specifically includes the following process: A remapping table update register is set in the Flash controller, wherein the remapping table update register is used to store the original address to be updated and the new replacement address; When a new bad block is detected in the storage replacement area, the Flash controller writes the address of the new bad block into the replacement area bad block register group, queries the address remapping register group for entries equal to the new bad block address among all replacement addresses, and then writes the original address to be updated representing the new bad block address and the new replacement address representing the next available replacement address in the storage replacement area into the remapping table update register; The Flash controller automatically scans the address remapping register group and replaces the newly added bad block addresses stored therein with the new replacement addresses.

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