True random number generator, integrated circuit board and electronic equipment

Abstract

The embodiment of the invention provides a true random number generator, an integrated circuit board and electronic equipment, and relates to the technical field of random numbers, the true random number generator comprises a selection output circuit and a plurality of random number generation circuits, each random number generation circuit comprises a ring oscillator and a sampling sub-circuit, and a plurality of first signals are output through the ring oscillator; the method comprises the following steps: acquiring a plurality of first signals through a sampling sub-circuit, generating second signals according to the plurality of first signals, determining a target signal through a selection output circuit according to all the second signals, and outputting a signal value of the currently acquired target signal as a random number, the target signal is a second signal of which the currently acquired signal value is different from the last acquired signal value, so that the random number is acquired, and the signal value of the second signal randomly generated based on the ring oscillator is captured by the selection output circuit as the random number to be output, so that the randomness of the random number is improved; the problem of poor randomness in related technologies is solved.

Description

Technical Field

[0001] The present application relates to the technical field of random numbers, and particularly to a true random number generator, an integrated circuit board, and an electronic device. Background Art

[0002] Random numbers play a key role in fields such as modern cryptography, communication, and security applications, such as data encryption, security authentication, simulation, etc. However, the randomness of random numbers obtained by software programs is poor and cannot meet the current application requirements.

[0003] Currently, there is an urgent need to provide a true random number generator to solve the above problems. Summary of the Invention

[0004] In view of the above problems, embodiments of the present application are proposed to provide a true random number generator, an integrated circuit board, and an electronic device that overcome the above problems or at least partially solve the above problems, so as to solve the problem of poor randomness of random numbers obtained by software programs in related technologies.

[0005] To solve the above problems, embodiments of the present application disclose a true random number generator, including: a selection output circuit and a plurality of random number generation circuits, the plurality of random number generation circuits are respectively electrically connected to the selection output circuit; wherein, the random number generation circuit includes a ring oscillator and a sampling sub-circuit connected electrically;

[0006] The ring oscillator is used to output a plurality of first signals;

[0007] The sampling sub-circuit is used to collect the plurality of first signals and generate a second signal according to the plurality of first signals;

[0008] The selection output circuit is used to determine a target signal according to all the second signals, and output the signal value of the currently collected target signal as a random number; the target signal is a second signal whose currently collected signal value is different from the previously collected signal value;

[0009] Wherein, the selection output circuit collects the signal value of each second signal once in each preset clock cycle.

[0010] Optionally, the ring oscillator includes n inverters, n is a positive odd number; the n inverters are connected in series; among the n inverters, the output end of the nth inverter is electrically connected to the input end of the 1st inverter;

[0011] The sampling sub - circuit includes a first exclusive - OR gate unit and (n - 1) / 2 sampling sub - circuits. The sampling sub - circuit includes a Muller C cell and a first flip - flop. The output terminal of the Muller C cell is electrically connected to the input terminal of the first flip - flop, and the output terminal of the first flip - flop is electrically connected to the j - th input terminal of the first exclusive - OR gate unit; the output terminal of the first exclusive - OR gate unit of the k - th sampling sub - circuit is electrically connected to the k - th input terminal of the selection output circuit, where j is a positive integer less than or equal to (n - 1) / 2, and k is a positive integer less than or equal to the number of sampling sub - circuits;

[0012] The first input terminal of the Muller C cell is electrically connected to the output terminal of the i - th inverter, and the second input terminal of the Muller C cell is electrically connected to the output terminal of the (i + 1) - th inverter, where i is a positive odd number less than n.

[0013] Optionally, the ring oscillator includes a first inverter, a second inverter, a third inverter, a fourth inverter, and a fifth inverter; the sampling sub - circuit includes the first exclusive - OR gate unit, a first sampling sub - circuit, and a second sampling sub - circuit; the first sampling sub - circuit includes a Muller C cell and a first flip - flop, and the second sampling sub - circuit includes a Muller C cell and a first flip - flop;

[0014] The output terminal of the first inverter is electrically connected to the input terminal of the second inverter and the first input terminal of the Muller C cell of the first sampling sub - circuit respectively. The output terminal of the second inverter is electrically connected to the input terminal of the third inverter and the second input terminal of the Muller C cell in the first sampling sub - circuit respectively. The output terminal of the third inverter is electrically connected to the input terminal of the fourth inverter and the first input terminal of the Muller C cell in the second sampling sub - circuit respectively. The output terminal of the fourth inverter is electrically connected to the input terminal of the fifth inverter and the second input terminal of the Muller C cell in the second sampling sub - circuit respectively. The output terminal of the fifth inverter is electrically connected to the input terminal of the first inverter;

[0015] The first input terminal of the first exclusive - OR gate unit is electrically connected to the output terminal of the first flip - flop in the first sampling sub - circuit, and the second input terminal of the first exclusive - OR gate unit is electrically connected to the output terminal of the first flip - flop in the second sampling sub - circuit.

[0016] Optionally, the inverter is used to invert the acquired signal and output the first signal;

[0017] The Muller C unit is used to obtain two of the first signals and output a third signal according to the two first signals. Among them, when the signal values of the two first signals are both the first value, a third signal with the signal value of the first value is output; when the signal values of the two first signals are both the second value, a third signal with the signal value of the second value is output; when the signal values of the two first signals are different, the signal value of the third signal remains unchanged.

[0018] The first flip-flop is used to sample the third signal once in each clock cycle, and is also used to store the third signal sampled in the current clock cycle and output the third signal sampled in the previous clock cycle.

[0019] The first exclusive-OR gate unit is used to obtain all the third signals and output the second signal according to all the third signals. Among them, when the signal values of all the third signals are the same, a second signal with the signal value of the first value is output; when there is a third signal among all the third signals whose signal value is different from that of other third signals, a second signal with the signal value of the second value is output.

[0020] Optionally, the number of the sampling sub-circuits is m, where m is a positive integer; the selection output circuit includes a selection unit and m selection sub-circuits, and the selection sub-circuit includes a second flip-flop and a second exclusive-OR gate unit.

[0021] The output end of the k-th sampling sub-circuit is respectively electrically connected to the input end of the second flip-flop in the k-th selection sub-circuit and the first input end of the second exclusive-OR gate unit in the k-th selection sub-circuit. The output end of the second flip-flop in the k-th selection sub-circuit is respectively electrically connected to the second input end of the second exclusive-OR gate unit in the k-th selection sub-circuit and the p-th input end of the selection unit. The output end of the second exclusive-OR gate unit in the k-th selection sub-circuit is electrically connected to the q-th input end of the selection unit, where k is a positive integer less than or equal to m, and p and q are both positive integers less than or equal to 2m.

[0022] Optionally, the second flip-flop is used to sample the second signal once in each clock cycle, and is also used to store the second signal sampled in the current clock cycle and output the second signal sampled in the previous clock cycle.

[0023] The second exclusive-OR gate unit is configured to obtain a second signal and output a fourth signal according to the second signal. Wherein, when the signal value of the second signal collected in the current clock cycle is the same as the signal value of the second signal collected in the previous clock cycle, a fourth signal with a signal value of a first value is output; when the signal value of the second signal collected in the current clock cycle is different from the signal value of the second signal collected in the previous clock cycle, a fourth signal with a signal value of a second value is output;

[0024] The selection unit is configured to obtain all the fourth signals, determine the target signal according to all the fourth signals, and output the signal value of the target signal collected in the current clock cycle as the random number;

[0025] Wherein, the selection unit is specifically configured to determine, among all the fourth signals, the fourth signal with a signal value of the first value as the target fourth signal, determine the second flip-flop electrically connected to the second exclusive-OR gate unit that outputs the target fourth signal as the target second flip-flop, and determine the second signal output by the target second flip-flop as the target signal.

[0026] Optionally, the number of the ring oscillators is m, where m is a positive integer;

[0027] The true random number generator further includes a third exclusive-OR gate unit, and the third exclusive-OR gate unit is electrically connected to each of the ring oscillators. Wherein, the k-th input terminal of the third exclusive-OR gate unit is electrically connected to the output terminal of the k-th ring oscillator, and k is a positive integer less than or equal to m;

[0028] The output terminal of the third exclusive-OR gate unit is electrically connected to the input terminal of the selection output circuit.

[0029] Optionally, the ring oscillator is further configured to output a fifth signal;

[0030] The third exclusive-OR gate unit is configured to obtain all the fifth signals and output a sixth signal according to all the fifth signals. Wherein, when the signal values of all the fifth signals are the same, a sixth signal with a signal value of a first value is output; when there is a fifth signal among all the fifth signals whose signal value is different from that of other fifth signals, a sixth signal with a signal value of a second value is output;

[0031] The selection output circuit is further configured to, when all the second signals meet a preset condition, output the signal value of the sixth signal as the random number; wherein, the preset condition is that the currently collected signal value of the second signal is the same as the signal value collected last time.

[0032] Optionally, the first value is binary 0 and the second value is binary 1.

[0033] To solve the above problems, an embodiment of the present application also discloses an integrated circuit board, which includes the true random number generator described above and also includes a target circuit, and an output end of the true random number generator is connected to the target circuit.

[0034] Optionally, the integrated circuit board further includes a mesh metal connection wire, and the true random number generator and the target circuit are connected through the mesh metal connection wire.

[0035] To solve the above problems, an embodiment of the present application also discloses an electronic device, which includes the integrated circuit board described above.

[0036] The embodiments of the present application have the following advantages:

[0037] By outputting a plurality of first signals through a ring oscillator, then collecting the plurality of first signals through a sampling sub-circuit, generating a second signal according to the plurality of first signals, then determining a target signal according to all the second signals through a selection output circuit, and outputting the signal value of the currently collected target signal as a random number, wherein the target signal is a second signal whose currently collected signal value is different from the previously collected signal value, and the selection output circuit collects the signal value of each second signal once in each preset clock cycle, thereby realizing the acquisition of a random number, and the selection output circuit uses the second signal whose currently collected signal value is different from the previously collected signal value as the target signal to capture the signal value of the second signal randomly generated based on the ring oscillator, and outputs the signal value of the currently collected target signal as a random number, improving the randomness of the output random number and solving the problem that the randomness of the random number obtained by using a software program is relatively poor.

[0038] In addition, the true random number generator provided by the embodiment of the present application includes a selection output circuit and a plurality of random number generation circuits, and the plurality of random number generation circuits are respectively electrically connected to the selection output circuit; wherein, the random number generation circuit includes a ring oscillator and a sampling sub-circuit that are electrically connected, and the structure is relatively simple, improving the generation efficiency and generation speed of the random number. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 Shows a schematic structural diagram of a true random number generator according to an embodiment of the present application;

[0040] Figure 2 Shows a schematic diagram of a random number generation circuit according to an embodiment of the present application;

[0041] Figure 3 Shows a schematic diagram of a selection output circuit according to an embodiment of the present application;

[0042] Figure 4 shows a specific structural schematic diagram of a true random number generator according to an embodiment of the present application;

[0043] Figure 5 shows a schematic diagram of a random number acquisition process according to an embodiment of the present application;

[0044] Figure 6 shows a waveform schematic diagram of an inverter and a Muller C cell according to an embodiment of the present application;

[0045] Figure 7 shows a waveform schematic diagram of a second signal according to an embodiment of the present application. Specific embodiments

[0046] To make the above objects, features, and advantages of the present application more obvious and understandable, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0047] Refer to Figure 1 , an embodiment of the present application discloses a true random number generator, including: a selection output circuit 10 and a plurality of random number generation circuits 20, and the plurality of random number generation circuits 20 are respectively electrically connected to the selection output circuit 10; wherein, the random number generation circuit 20 includes a ring oscillator 21 and a sampling sub-circuit 22 that are electrically connected;

[0048] The ring oscillator 21 is configured to output a plurality of first signals;

[0049] The sampling sub-circuit 22 is configured to collect a plurality of first signals and generate a second signal according to the plurality of first signals;

[0050] The selection output circuit 10 is configured to determine a target signal according to all the second signals, and output the signal value of the currently collected target signal as a random number; the target signal is a second signal whose currently collected signal value is different from the previously collected signal value;

[0051] Wherein, the selection output circuit 10 collects the signal value of each second signal once in each preset clock cycle.

[0052] It should be noted that the number of random number generation circuits 20 is greater than or equal to two; the ring oscillator 21 is formed by connecting an odd number of inverters 211 end to end. The reason why the number of inverters 211 in the ring oscillator 21 is odd is that an odd number of inverters 211 can make the input and output signal values of the inverters 211 different in two adjacent cycles (ignoring the transmission time of the signal on the transmission line, the sum of the delay times of all inverters 211 is one cycle, and the delay time of the inverter 211 is the time when the output signal of the inverter 211 is delayed compared to the signal input to the inverter 211) to generate oscillation (the output signal value changes). For example, if the signal input to the inverter 211 in the current cycle is high level and the signal output by the inverter 211 is low level, then the signal input to the inverter 211 in the next cycle is low level and the signal output by the inverter 211 is high level.

[0053] The first signal is output by the inverters in the ring oscillator 21, and different inverters output different first signals.

[0054] The signal value of the signal can be in binary form, including binary 1 and binary 0. The signal value of the low-level signal is binary 0, and the signal value of the high-level signal is binary 1. For example, the signal value of the low-level first signal is binary 0, and the signal value of the high-level first signal is binary 1.

[0055] The ring oscillator 21 has no steady state. Due to the influence of random factors such as temperature and noise, the waveform of the output signal of the ring oscillator 21 jitters, that is, due to the influence of random factors such as temperature and noise, the first signal changes. For example, the signal value of the first signal changes from low level to high level, or the signal value of the first signal changes from high level to low level.

[0056] Specifically, the second signal generated by the sampling sub-circuit 22 is used to characterize the jitter of the waveform of the output signal of the ring oscillator 21 due to the influence of random factors such as temperature and noise, that is, due to the influence of random factors such as temperature and noise, the first signal changes, and then the second signal changes. For example, the second signal changes from low level to high level, or the signal value of the second signal changes from high level to low level.

[0057] The selection output circuit 10 uses the second signal whose currently collected signal value is different from the previously collected signal value as the target signal to capture the signal value of the second signal randomly generated based on the ring oscillator 21, and uses the signal value of the currently collected target signal as a random number for output to improve the randomness of the output random number.

[0058] For example, a true random number generator includes a selection output circuit and two random number generation circuits, namely random number generation circuit a and random number generation circuit b. Random number generation circuit a includes a ring oscillator a1 and a sampling sub-circuit a2, and random number generation circuit b includes a ring oscillator b1 and a sampling sub-circuit b2. The sampling sub-circuit a2 generates a second signal a4 based on a plurality of first signals a3 output by the ring oscillator a1, and the sampling sub-circuit b2 generates a second signal b4 based on a plurality of first signals b3 output by the ring oscillator b1. Referring to the following table (Table 1), the signal value of the second signal a4 collected by the selection output circuit in the previous clock cycle is binary 1, the signal value of the second signal b4 collected by the selection output circuit in the previous clock cycle is binary 0, the signal value of the second signal a4 collected by the selection output circuit in the current clock cycle is binary 1, and the signal value of the second signal b4 collected by the selection output circuit in the current clock cycle is binary 1.

[0059] Table 1: Signal value table for collecting the second signal a4 and the second signal b4

[0060] Signal Previous cycle Current cycle Second signal a4 1 1 Second signal b4 0 1

[0061] Referring to Table 1, since the signal value (binary 1) of the second signal b4 collected in the current clock cycle is different from the signal value (binary 0) of the second signal b4 collected in the previous clock cycle, the selection output circuit determines the second signal b4 as the target signal and outputs the signal value (binary 1) of the currently collected target signal (the second signal b4) as a random number.

[0062] In the related art, a random number is output by electrically connecting a plurality of high-order (the number of ring oscillators is greater than or equal to 10) ring oscillators to an exclusive OR unit. The random number output by the exclusive OR unit is based on the judgment result of whether the signal values output by the ring oscillators are the same. The similarities and differences of the signal values output by the plurality of ring oscillators are periodic. Therefore, the randomness of the random number output by electrically connecting a plurality of high-order ring oscillators to the exclusive OR unit is poor, and the high-order (the number of ring oscillators is greater than or equal to 10) ring oscillator has a complex structure and consumes a large amount of energy.

[0063] The true random number generator provided by the embodiment of the present application uses the selection output circuit 10 to use the second signal whose currently collected signal value is different from the previously collected signal value as the target signal, so as to capture the signal value of the second signal randomly generated based on the ring oscillator 21, and output the signal value of the currently collected target signal as a random number, improving the randomness of the output random number.

[0064] In the related art, a ring oscillator with multiple self-timed loops is electrically connected to a processor under the von Neumann architecture (discarding the same signal values and retaining different signal values) to output random numbers. Since at least 16 ring oscillators of the self-timed loop are required to generate random numbers with better randomness, and using a processor under the von Neumann architecture will discard a large amount of data, the number of bits of the final random number becomes uncontrollable, and the generation efficiency and generation speed of the random numbers are also reduced, occupying a large amount of computing resources.

[0065] The true random number generator provided by the embodiment of the present application includes a selection output circuit 10 and multiple random number generation circuits 20, and the multiple random number generation circuits 20 are respectively electrically connected to the selection output circuit 10; wherein, the random number generation circuit 20 includes a ring oscillator 21 and a sampling sub-circuit 22 that are electrically connected, and the structure is relatively simple, improving the generation efficiency and generation speed of random numbers.

[0066] In summary, the true random number generator provided by the embodiment of the present application outputs multiple first signals through the ring oscillator 21, then collects the multiple first signals through the sampling sub-circuit 22, generates a second signal according to the multiple first signals, and then determines a target signal through the selection output circuit 10 according to all the second signals, and outputs the signal value of the currently collected target signal as a random number. Among them, the target signal is the second signal whose signal value is different from the signal value of the previously collected signal. The selection output circuit 10 collects the signal value of each second signal once in each preset clock cycle, so as to obtain a random number, and the selection output circuit 10 uses the second signal whose signal value is different from the signal value of the previously collected signal as the target signal to capture the signal value of the second signal randomly generated by the ring oscillator 21, and outputs the signal value of the currently collected target signal as a random number, improving the randomness of the output random number and solving the problem of poor randomness of the random numbers obtained by using software programs.

[0067] In addition, the true random number generator provided by the embodiment of the present application includes a selection output circuit 10 and multiple random number generation circuits 20, and the multiple random number generation circuits 20 are respectively electrically connected to the selection output circuit 10; wherein, the random number generation circuit 20 includes a ring oscillator 21 and a sampling sub-circuit 22 that are electrically connected, and the structure is relatively simple, improving the generation efficiency and generation speed of random numbers.

[0068] Optionally, referring to Figure 2 , the ring oscillator 21 includes n inverters 211, where n is a positive odd number; the n inverters 211 are connected in series; among the n inverters 211, the output terminal of the nth inverter 211 is electrically connected to the input terminal of the first inverter 211;

[0069] The sampling sub-circuit 22 includes a first exclusive-OR gate unit 221 and (n - 1) / 2 sampling sub-circuits 222. The sampling sub-circuit 222 includes a Muller C cell 222b and a first flip-flop 222a. The output terminal of the Muller C cell 222b is electrically connected to the input terminal of the first flip-flop 222a, and the output terminal of the first flip-flop 222a is electrically connected to the j-th input terminal of the first exclusive-OR gate unit 221. The output terminal of the first exclusive-OR gate unit 221 of the k-th sampling sub-circuit 22 is electrically connected to the k-th input terminal of the selection output circuit 10, where j is a positive integer less than or equal to (n - 1) / 2, and k is a positive integer less than or equal to the number of sampling sub-circuits 22.

[0070] The first input terminal of the Muller C cell 222b is electrically connected to the output terminal of the i-th inverter 211, and the second input terminal of the Muller C cell 222b is electrically connected to the output terminal of the (i + 1)-th inverter 211, where i is a positive odd number less than n.

[0071] Specifically, the ring oscillator 21 includes n inverters 211, and n is a positive odd number greater than or equal to 5.

[0072] It should be noted that the inverter 211 is used to invert and output the signal input to the inverter 211. That is, when the signal input to the inverter 211 is high level, the signal output by the inverter 211 is low level; when the signal input to the inverter 211 is low level, the signal output by the inverter 211 is high level. The first exclusive-OR gate unit 221 is an exclusive-OR gate component. Among them, when the signal values of all signals input to the exclusive-OR element are the same, the signal output by the exclusive-OR element is binary 0. When there is a signal among all signals input to the exclusive-OR element whose signal value is different from that of other signals, the signal output by the exclusive-OR element is binary 1.

[0073] The Muller C cell 222b is the Muller C cell. The Muller C cell 222b has two input terminals and one output terminal. The truth table of the two input terminals and one output terminal of the Muller C cell 222b is as follows (Table 2):

[0074] Table 2: Truth table of two input terminals and one output terminal of the Muller C cell 222b

[0075] First input terminal Second input terminal Output terminal 0 0 0 1 0 Remain unchanged 0 1 Remain unchanged 1 1 1

[0076] Among them, when the signal value of the signal input to the first input terminal of the Muller C unit 222b is binary 0 and the signal value of the signal input to the second input terminal of the Muller C unit 222b is binary 0, the signal value of the signal output from the output terminal of the Muller C unit 222b is binary 0; when the signal value of the signal input to the first input terminal of the Muller C unit 222b is binary 1 and the signal value of the signal input to the second input terminal of the Muller C unit 222b is binary 1, the signal value of the signal output from the output terminal of the Muller C unit 222b is binary 1; when the signal value of the signal input to the first input terminal of the Muller C unit 222b is binary 1 and the signal value of the signal input to the second input terminal of the Muller C unit 222b is binary 0, the signal value of the signal output from the output terminal of the Muller C unit 222b remains unchanged; when the signal value of the signal input to the first input terminal of the Muller C unit 222b is binary 0 and the signal value of the signal input to the second input terminal of the Muller C unit 222b is binary 1, the signal value of the signal output from the output terminal of the Muller C unit 222b remains unchanged.

[0077] For example, when the signal value of the signal input to the first input terminal of the Muller C unit 222b is binary 0 and the signal value of the signal input to the second input terminal of the Muller C unit 222b is binary 0, the signal value of the signal output from the output terminal of the Muller C unit 222b is binary 0. At this time, if the signal value of the signal input to the first input terminal of the Muller C unit 222b becomes binary 1, then when the signal value of the signal input to the first input terminal of the Muller C unit 222b is binary 1 and the signal value of the signal input to the second input terminal of the Muller C unit 222b is binary 0, the signal value of the signal output from the output terminal of the Muller C unit 222b remains unchanged, that is, the signal value of the signal output from the output terminal of the Muller C unit 222b is still binary 0.

[0078] Optionally, the inverter 211 is used to invert the acquired signal and output a first signal;

[0079] The Muller C unit 222b is used to acquire two first signals and output a third signal according to the two first signals. Among them, when the signal values of the two first signals are both the first value, a third signal with the signal value of the first value is output; when the signal values of the two first signals are both the second value, a third signal with the signal value of the second value is output; when the signal values of the two first signals are different, the signal value of the third signal remains unchanged;

[0080] The first flip-flop 222a is used to sample the third signal once in each clock cycle, and is also used to store the third signal sampled in the current clock cycle and output the third signal sampled in the previous clock cycle;

[0081] The first exclusive - OR gate unit 221 is used to obtain all the third signals and output a second signal according to all the third signals. Among them, when the signal values of all the third signals are the same, a second signal with a signal value of the first value is output; when there is a third signal among all the third signals whose signal value is different from that of other third signals, a second signal with a signal value of the second value is output.

[0082] Optionally, the first value is binary 0 and the second value is binary 1.

[0083] A signal is represented as a low level by binary 0 and a high level by binary 1.

[0084] It should be noted that through the Muller C cell 222b, the inverter 211 electrically connected to the Muller C cell 222b in the ring oscillator 21 can be captured, and due to the influence of random factors such as temperature and noise, the waveform of the output signal jitters (the change of the signal value of the first signal).

[0085] Refer to Figure 6 , waveform Q1 is the ideal waveform of the first signal output by the i - th inverter (i.e., the signal input to the (i + 1)-th inverter), waveform Q2 is the ideal waveform of the first signal output by the (i + 1)-th inverter, waveform Q3 is the actual waveform of the first signal output by the i - th inverter, and due to the influence of random factors such as temperature and noise, the waveform of the output signal of the i - th inverter jitters (i.e., the change of the signal value of the first signal, Figure 6 as shown at E in ), the first input terminal of the Muller C cell is electrically connected to the output terminal of the i - th inverter, the second input terminal of the Muller C cell is electrically connected to the output terminal of the (i + 1)-th inverter, and waveform Q4 is the actual waveform of the third signal output by the Muller C cell.

[0086] For example, in a ring oscillator, the output terminal of inverter 1 is connected to the input terminal of inverter 2, the first input terminal of the Muller C cell is electrically connected to the output terminal of the i - th inverter, and the second input terminal of the Muller C cell is electrically connected to the output terminal of the (i + 1)-th inverter.

[0087] The first signal output by inverter 1 is the signal input to inverter 2. When the ring oscillator is not affected by random factors such as temperature and noise and the waveform of the output signal jitters, the signal value of the first signal output by inverter 1 is different from the signal value of the first signal output by inverter 2.

[0088] Assume that the initial signal value of the third signal output by the Muller C cell is binary 1, the signal value of the first signal output by the inverter 1 is binary 1, and the signal value of the first signal output by the inverter 2 is binary 0. According to Table 2, the signal value of the third signal output by the Muller C cell remains unchanged, that is, the signal value of the third signal output by the Muller C cell is binary 1. At this time, due to the influence of random factors such as temperature and noise, the signal value of the first signal output by the inverter 1 becomes binary 0. Since the inverter 2 outputs the first signal that is the inverse of the first signal output by the inverter 1 after a fixed delay time, within the fixed delay time of the inverter 2, the signal value of the first signal output by the inverter 2 is still binary 0. Then, when the signal value of the first signal output by the inverter 1 is binary 0 and the signal value of the first signal output by the inverter 2 is binary 0, the signal value of the third signal output by the Muller C cell changes from binary 1 to binary 0.

[0089] Therefore, in the ring oscillator, when the inverter 1 electrically connected to the Muller C cell has jitter in the waveform of the output signal (change in the signal value of the first signal) due to the influence of random factors such as temperature and noise, the signal value of the third signal output by the Muller C cell changes. Then, through the Muller C cell, it can capture the jitter (change in the signal value of the first signal) in the waveform of the output signal of the inverter 1 electrically connected to the Muller C cell in the ring oscillator due to the influence of random factors such as temperature and noise.

[0090] Optionally, the ring oscillator includes a first inverter, a second inverter, a third inverter, a fourth inverter, and a fifth inverter; the sampling sub-circuit includes a first exclusive-OR gate unit, a first sampling sub-circuit, and a second sampling sub-circuit; the first sampling sub-circuit includes a Muller C cell and a first flip-flop, and the second sampling sub-circuit includes a Muller C cell and a first flip-flop;

[0091] The output terminal of the first inverter is electrically connected to the input terminal of the second inverter and the first input terminal of the Muller C cell of the first sampling sub-circuit respectively. The output terminal of the second inverter is electrically connected to the input terminal of the third inverter and the second input terminal of the Muller C cell in the first sampling sub-circuit respectively. The output terminal of the third inverter is electrically connected to the input terminal of the fourth inverter and the first input terminal of the Muller C cell in the second sampling sub-circuit respectively. The output terminal of the fourth inverter is electrically connected to the input terminal of the fifth inverter and the second input terminal of the Muller C cell in the second sampling sub-circuit respectively. The output terminal of the fifth inverter is electrically connected to the input terminal of the first inverter;

[0092] The first input terminal of the first exclusive-OR gate unit is electrically connected to the output terminal of the first flip-flop in the first sampling sub-circuit, and the second input terminal of the first exclusive-OR gate unit is electrically connected to the output terminal of the first flip-flop in the second sampling sub-circuit.

[0093] It should be noted that a ring oscillator including five inverters is a fifth-order ring oscillator, and the first signal output by the fifth-order ring oscillator can be collected by two sampling sub-circuits.

[0094] Specifically, the Muller C cell of the first sampling sub-circuit obtains the first signal output by the first inverter and the first signal output by the second inverter, and outputs a third signal according to the first signal output by the first inverter and the first signal output by the second inverter. Among them, when the first signal output by the first inverter and the first signal output by the second inverter are both the first value, a third signal with a signal value of the first value is output; when the first signal output by the first inverter and the first signal output by the second inverter are both the second value, a third signal with a signal value of the second value is output; when the signal values of the first signal output by the first inverter and the first signal output by the second inverter are different, the signal value of the third signal remains unchanged;

[0095] The first flip-flop of the first sampling sub-circuit samples the third signal output by the Muller C cell of the first sampling sub-circuit once per clock cycle, and is also used to store the third signal output by the Muller C cell of the first sampling sub-circuit collected in the current clock cycle, and outputs the third signal of the Muller C cell of the first sampling sub-circuit collected in the previous clock cycle;

[0096] The Muller C cell of the second sampling sub-circuit obtains the first signal output by the third inverter and the first signal output by the fourth inverter, and outputs a third signal according to the first signal output by the third inverter and the first signal output by the fourth inverter. Among them, when the first signal output by the third inverter and the first signal output by the fourth inverter are both the first value, a third signal with a signal value of the first value is output; when the first signal output by the third inverter and the first signal output by the fourth inverter are both the second value, a third signal with a signal value of the second value is output; when the signal values of the first signal output by the third inverter and the first signal output by the fourth inverter are different, the signal value of the third signal remains unchanged;

[0097] The first flip-flop of the second sampling sub-circuit samples the third signal output by the Muller C cell of the second sampling sub-circuit once per clock cycle, and is also used to store the third signal output by the Muller C cell of the second sampling sub-circuit collected in the current clock cycle, and outputs the third signal of the Muller C cell of the second sampling sub-circuit collected in the previous clock cycle;

[0098] The first exclusive-OR gate unit is used to obtain the third signal output by the Muller C unit of the first sampling molecular circuit and the third signal output by the Muller C unit of the second sampling molecular circuit, and output a second signal according to the third signal output by the Muller C unit of the first sampling molecular circuit and the third signal output by the Muller C unit of the second sampling molecular circuit. Among them, when the signal values of the third signals output by the Muller C units of the first sampling molecular circuit and the second sampling molecular circuit are the same, a second signal with a signal value of the first value is output; when the signal values of the third signals output by the Muller C units of the first sampling molecular circuit and the second sampling molecular circuit are different, a second signal with a signal value of the second value is output.

[0099] The change in the signal value of the third signal output by the Muller C unit can be captured by the first exclusive-OR gate unit.

[0100] For example, assume that the initial signal value of the third signal output by the Muller C unit is binary 1. Then, when the signal values of the third signals output by the Muller C units of the first sampling molecular circuit (binary 1) and the second sampling molecular circuit (binary 1) are the same, the first exclusive-OR gate unit outputs a second signal with a signal value of the first value (binary 0).

[0101] At this time, for the first inverter in the ring oscillator, due to the influence of random factors such as temperature and noise, the waveform of the output signal of the ring oscillator jitters (the signal value of the first signal changes). From the previous analysis, it can be seen that when the first inverter in the ring oscillator jitters (the signal value of the first signal changes) due to the influence of random factors such as temperature and noise, the signal value of the third signal output by the Muller C unit of the first sampling molecular circuit changes, that is, the signal value of the third signal output by the Muller C unit of the first sampling molecular circuit changes from binary 1 to binary 0. Since the signal value of the third signal output by the Muller C unit of the first sampling molecular circuit (binary 0) is different from the signal value of the third signal output by the Muller C unit of the second sampling molecular circuit (binary 1) at this time, the first exclusive-OR gate unit outputs a second signal with a signal value of the second value (binary 1), that is, the signal value of the second signal output by the first exclusive-OR gate unit changes (from binary 0 to binary 1).

[0102] Therefore, the change in the signal value of the third signal output by the Muller C unit can be captured by the first exclusive-OR gate unit.

[0103] From the above, it can be seen that when it is determined that the signal value of the second signal output by the first XOR gate unit has changed, that is, when the signal value of the currently collected second signal is different from the signal value of the second signal collected last time, the signal value of the currently collected second signal is generated based on random factors such as temperature and noise.

[0104] Optionally, the number of sampling subcircuits 22 is m, where m is a positive integer; Figure 3 , the selection output circuit 10 includes a selection unit 11 and m selection sub-circuits 12, and the selection sub-circuit 12 includes a second flip-flop 121 and a second XOR gate unit 122;

[0105] The output end of the kth sampling sub-circuit 22 is electrically connected to the input end of the second trigger 121 in the kth selection sub-circuit 12 and the first input end of the second XOR gate unit 122 in the kth selection sub-circuit 12, respectively. The output end of the second trigger 121 in the kth selection sub-circuit 12 is electrically connected to the second input end of the second XOR gate unit 122 in the kth selection sub-circuit 12 and the pth input end of the selection unit 11, respectively. The output end of the second XOR gate unit 122 in the kth selection sub-circuit 12 is electrically connected to the qth input end of the selection unit 11, where k is a positive integer less than or equal to m, and p and q are both positive integers less than or equal to 2m.

[0106] It should be noted that the second XOR gate unit 122 is an XOR gate component.

[0107] Specifically, the number of the sampling sub-circuits 22 is m, where m is a positive integer greater than or equal to 2.

[0108] As can be seen from the above, the sampling sub-circuit 22 includes a first XOR gate unit 221 and (n-1) / 2 sampling sub-circuits 222. Figure 4 The output end of the first XOR gate unit 221 of the kth sampling sub-circuit 22 is electrically connected to the input end of the second trigger 121 in the kth selection sub-circuit 12 and the first input end of the second XOR gate unit 122 in the kth selection sub-circuit 12 respectively.

[0109] In the embodiment of the present application, the selection sub-circuit 12 is used to determine whether the currently acquired signal value of the second signal output by the sampling sub-circuit 22 is the same as the previously acquired signal value, and output a judgment result, that is, when the signal value of the second signal acquired in the current clock cycle is the same as the signal value of the second signal acquired in the previous clock cycle, a fourth signal with a signal value of the first value is output; when the signal value of the second signal acquired in the current clock cycle is different from the signal value of the second signal acquired in the previous clock cycle, a fourth signal with a signal value of the second value is output. The selection unit 11 selects a target signal from all the second signals according to the judgment results output by each selection sub-circuit 12, that is, among all the fourth signals, the fourth signal with a signal value of the second value is determined as the target fourth signal, and the second flip-flop 121 electrically connected to the second exclusive-OR gate unit 122 that outputs the target fourth signal is determined as the target second flip-flop 121, and the second signal output by the target second flip-flop 121 is determined as the target signal, and the signal value of the target signal acquired in the current clock cycle is output as a random number.

[0110] Optionally, the second flip-flop 121 is used to acquire the second signal once per clock cycle, and is also used to store the second signal acquired in the current clock cycle and output the second signal acquired in the previous clock cycle;

[0111] The second exclusive-OR gate unit 122 is used to acquire the second signal and output a fourth signal according to the second signal, where when the signal value of the second signal acquired in the current clock cycle is the same as the signal value of the second signal acquired in the previous clock cycle, a fourth signal with a signal value of the first value is output; when the signal value of the second signal acquired in the current clock cycle is different from the signal value of the second signal acquired in the previous clock cycle, a fourth signal with a signal value of the second value is output;

[0112] The selection unit 11 is used to acquire all the fourth signals, determine a target signal according to all the fourth signals, and output the signal value of the target signal acquired in the current clock cycle as a random number;

[0113] Among them, the selection unit 11 is specifically used to determine the fourth signal with a signal value of the first value among all the fourth signals as the target fourth signal, determine the second flip-flop 121 electrically connected to the second exclusive-OR gate unit 122 that outputs the target fourth signal as the target second flip-flop 121, and determine the second signal output by the target second flip-flop 121 as the target signal.

[0114] Refer to Figure 7, waveform P1 is the waveform of the second signal received by the first input terminal of the second XOR gate unit 122 (the waveform of the second signal output by the sampling sub-circuit 22), and waveform P2 is the waveform of the second signal received by the second input terminal of the second XOR gate unit 122 (the waveform of the second signal output by the second flip-flop 121).

[0115] As can be seen from the foregoing, when the signal value of the currently sampled second signal is different from the signal value of the previously sampled second signal, the signal value of the currently sampled second signal is generated based on random factors such as temperature and noise. Therefore, the signal value of the second signal generated based on random factors such as temperature and noise can be output as a random number. To obtain the signal value of the second signal generated based on random factors such as temperature and noise, it is necessary to determine whether the signal value of the currently sampled second signal is the same as the signal value of the previously sampled second signal.

[0116] Then, the second flip-flop 121 samples the second signal once per clock cycle, stores the second signal sampled in the current clock cycle through the second flip-flop 121, and outputs the second signal sampled in the previous clock cycle. Then, the second XOR gate unit 122 obtains the second signal, and when the signal value of the second signal sampled in the current clock cycle is the same as the signal value of the second signal sampled in the previous clock cycle, a fourth signal with a signal value of the first value is output; when the signal value of the second signal sampled in the current clock cycle is different from the signal value of the second signal sampled in the previous clock cycle, a fourth signal with a signal value of the second value is output. Then, all the fourth signals are obtained through the selection unit 11, the fourth signal with a signal value of the second value among all the fourth signals is determined as the target fourth signal, the second flip-flop 121 electrically connected to the second XOR gate unit 122 that outputs the target fourth signal is determined as the target second flip-flop 121, and then the second signal output by the target second flip-flop 121 is determined as the target signal. The signal value of the target signal sampled in the current clock cycle is the signal value of the second signal generated based on random factors such as temperature and noise, so the signal value of the target signal sampled in the current clock cycle is output as a random number.

[0117] Optionally, referring to Figure 4 , the number of ring oscillators 21 is m, where m is a positive integer;

[0118] The true random number generator further includes a third XOR gate unit 30, and the third XOR gate unit 30 is electrically connected to each ring oscillator 21. Among them, the k-th input terminal of the third XOR gate unit 30 is electrically connected to the output terminal of the k-th ring oscillator 21, and k is a positive integer less than or equal to m;

[0119] The output terminal of the third exclusive-OR gate unit 30 is electrically connected to the input terminal of the selection output circuit 10.

[0120] The random number generation circuit 20 includes a ring oscillator 21 and a sampling sub-circuit 22. The number of random number generation circuits 20 is m, the number of sampling sub-circuits 22 is m, and the number of ring oscillators 21 is m. The selection output circuit 10 includes a selection unit 11 and m selection sub-circuits 12. The output terminal of the third exclusive-OR gate unit 30 is electrically connected to the (2m + 1)-th input terminal of the selection unit 11.

[0121] Each ring oscillator 21 includes n inverters 211. The k-th input terminal of the third exclusive-OR gate unit 30 is electrically connected to the output terminal of the n-th inverter 211 in the k-th ring oscillator 21, where n is a positive odd number.

[0122] Specifically, the ring oscillator includes a first inverter, a second inverter, a third inverter, a fourth inverter, and a fifth inverter; the sampling sub-circuit includes a first exclusive-OR gate unit, a first sampling sub-circuit, and a second sampling sub-circuit; the first sampling sub-circuit includes a Muller C cell and a first flip-flop, and the second sampling sub-circuit includes a Muller C cell and a first flip-flop;

[0123] The output terminal of the first inverter is electrically connected to the input terminal of the second inverter and the first input terminal of the Muller C cell of the first sampling sub-circuit respectively. The output terminal of the second inverter is electrically connected to the input terminal of the third inverter and the second input terminal of the Muller C cell in the first sampling sub-circuit respectively. The output terminal of the third inverter is electrically connected to the input terminal of the fourth inverter and the first input terminal of the Muller C cell in the second sampling sub-circuit respectively. The output terminal of the fourth inverter is electrically connected to the input terminal of the fifth inverter and the second input terminal of the Muller C cell in the second sampling sub-circuit respectively. The output terminal of the fifth inverter is electrically connected to the input terminal of the first inverter;

[0124] The first input terminal of the first exclusive-OR gate unit is electrically connected to the output terminal of the first flip-flop in the first sampling sub-circuit, and the second input terminal of the first exclusive-OR gate unit is electrically connected to the output terminal of the first flip-flop in the second sampling sub-circuit;

[0125] The output terminal of the k-th fifth inverter is electrically connected to the k-th input terminal of the third exclusive-OR gate unit, where k is a positive integer less than or equal to m.

[0126] Optionally, the ring oscillator is further configured to output a fifth signal;

[0127] The third exclusive-OR gate unit is used to obtain all the fifth signals and output a sixth signal according to all the fifth signals. Among them, when the signal values of all the fifth signals are the same, a sixth signal with a signal value of the first value is output; when there is a fifth signal among all the fifth signals whose signal value is different from that of other fifth signals, a sixth signal with a signal value of the second value is output.

[0128] The selection output circuit is further used to output the signal value of the sixth signal as a random number when all the second signals meet the preset conditions; where the preset condition is that the currently collected signal value of the second signal is the same as the previously collected signal value.

[0129] Specifically, the ring oscillator includes n inverters, the fifth signal is the signal output by the nth inverter, and n is a positive odd number. As can be seen from the foregoing, the selection circuit includes a selection unit and m selection sub-circuits. The selection unit is specifically further used to output the signal value of the sixth signal as a random number when the signal values of all the fourth signals are the first value.

[0130] It should be noted that the signal values of all the fourth signals being the first value indicates that the currently collected signal value of each second signal is the same as the previously collected signal value. Then, the currently collected signal value of each second signal is not generated based on random factors such as temperature and noise, and the currently collected signal value of each second signal cannot be output as a random number.

[0131] Due to the influence of random factors such as temperature and noise, the waveform of the output signal of the ring oscillator jitters (the signal value of the fifth signal changes). Therefore, whether the signal values of all the fifth signals generated by the ring oscillator are the same is random. Therefore, the signal value of the sixth signal is output as a random number.

[0132] Optionally, refer to Figure 5, the random number acquisition process provided by the embodiments of the present application includes: X1. The ring oscillator oscillates, that is, the ring oscillator oscillates to output a plurality of first signals; X2. The sampling sub-circuit samples, that is, the sampling sub-circuit samples a plurality of first signals and generates a second signal according to the plurality of first signals; X3. The selection sub-circuit judges, that is, the selection sub-circuit includes a second flip-flop and a second exclusive-OR gate unit. The second flip-flop samples the second signal once per clock cycle, stores the second signal collected in the current clock cycle, and outputs the second signal collected in the previous clock cycle. The second exclusive-OR gate unit obtains the second signal and outputs a fourth signal according to the second signal; X4. The selection unit outputs, that is, the selection unit obtains all the fourth signals, determines the target signal according to all the fourth signals, and uses the signal value of the target signal collected in the current clock cycle as a random number for output. The specific implementation process is similar to the foregoing and will not be elaborated here.

[0133] In summary, a plurality of first signals are output by the ring oscillator 21, and then a plurality of first signals are collected by the sampling sub-circuit 22, and a second signal is generated according to the plurality of first signals. Then, the selection output circuit 10 determines the target signal according to all the second signals, and uses the signal value of the target signal collected currently as a random number for output. Among them, the target signal is the second signal whose signal value collected currently is different from the signal value collected last time. The selection output circuit 10 samples the signal value of each second signal once per preset clock cycle, thereby realizing the acquisition of random numbers. And the selection output circuit 10 uses the second signal whose signal value collected currently is different from the signal value collected last time as the target signal to capture the signal value of the second signal randomly generated based on the ring oscillator 21, and uses the signal value of the target signal collected currently as a random number for output, improving the randomness of the output random number and solving the problem of poor randomness of the random numbers obtained by using software programs.

[0134] In addition, the true random number generator provided by the embodiments of the present application includes a selection output circuit 10 and a plurality of random number generation circuits 20. The plurality of random number generation circuits 20 are respectively electrically connected to the selection output circuit 10; wherein, the random number generation circuit 20 includes a ring oscillator 21 and a sampling sub-circuit 22 which are electrically connected, and the structure is relatively simple, improving the generation efficiency and generation speed of random numbers.

[0135] To solve the above problems, the embodiments of the present application also disclose an integrated circuit board, which includes the above true random number generator and also includes a target circuit. The output end of the true random number generator is connected to the target circuit.

[0136] The above integrated circuit board further includes a mesh metal connection wire, and the true random number generator and the target circuit are connected through the mesh metal connection wire.

[0137] In an embodiment of the present application, by arranging a mesh metal connection wire between the detection circuit and the target circuit, the signal crosstalk problem is avoided.

[0138] To solve the above problems, an embodiment of the present application also discloses an electronic device, including the integrated circuit board as above.

[0139] In summary, the true random number generator provided by the embodiment of the present application outputs multiple first signals through a ring oscillator, then collects the multiple first signals through a sampling sub-circuit, generates a second signal according to the multiple first signals, and then determines a target signal according to all the second signals through a selection output circuit, and outputs the signal value of the currently collected target signal as a random number. Among them, the target signal is a second signal whose currently collected signal value is different from the previously collected signal value. The selection output circuit collects the signal value of each second signal once every preset clock cycle, so as to obtain a random number. And the selection output circuit uses the second signal whose currently collected signal value is different from the previously collected signal value as the target signal to capture the signal value of the second signal randomly generated based on the ring oscillator, and outputs the signal value of the currently collected target signal as a random number, improving the randomness of the output random number and solving the problem of poor randomness of the random number obtained by using a software program.

[0140] In addition, the true random number generator provided by the embodiment of the present application includes a selection output circuit and multiple random number generation circuits, and the multiple random number generation circuits are respectively electrically connected to the selection output circuit; wherein, the random number generation circuit includes a ring oscillator and a sampling sub-circuit that are electrically connected, and the structure is relatively simple, improving the generation efficiency and generation speed of random numbers.

[0141] Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is the difference from other embodiments. The same and similar parts among the embodiments can be referred to each other.

[0142] The above has introduced in detail a detection circuit and an integrated circuit board provided by the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application; at the same time, for those of ordinary skill in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A true random number generator, characterized in that, Comprising: A selection output circuit and a plurality of random number generation circuits, wherein the plurality of random number generation circuits are electrically connected to the selection output circuit respectively; wherein, each random number generation circuit includes a ring oscillator and a sampling sub-circuit which are electrically connected; The ring oscillator is configured to output a plurality of first signals; The sampling sub-circuit is configured to sample the plurality of first signals and generate a second signal according to the plurality of first signals; The selection output circuit is configured to determine a target signal according to all the second signals, and output the signal value of the currently sampled target signal as a random number; the target signal is a second signal whose currently sampled signal value is different from the previously sampled signal value; Wherein, the selection output circuit samples the signal value of each second signal once in each preset clock cycle.

2. The true random number generator according to claim 1, characterized in that, The ring oscillator includes n inverters, where n is a positive odd number; the n inverters are connected in series; in the n inverters, the output terminal of the nth inverter is electrically connected to the input terminal of the 1st inverter; The sampling sub-circuit includes a first exclusive-OR gate unit and (n - 1) / 2 sampling sub-units, each sampling sub-unit includes a Muller C cell and a first flip-flop, the output terminal of the Muller C cell is electrically connected to the input terminal of the first flip-flop, and the output terminal of the first flip-flop is electrically connected to the jth input terminal of the first exclusive-OR gate unit; the output terminal of the first exclusive-OR gate unit of the kth sampling sub-circuit is electrically connected to the kth input terminal of the selection output circuit, where j is a positive integer less than or equal to (n - 1) / 2, and k is a positive integer less than or equal to the number of sampling sub-circuits; The first input terminal of the Muller C cell is electrically connected to the output terminal of the ith inverter, and the second input terminal of the Muller C cell is electrically connected to the output terminal of the (i + 1)th inverter, where i is a positive odd number less than n.

3. The true random number generator according to claim 2, characterized in that, The ring oscillator includes a first inverter, a second inverter, a third inverter, a fourth inverter, and a fifth inverter; the sampling sub-circuit includes the first exclusive-OR gate unit, a first sampling sub-unit, and a second sampling sub-unit; the first sampling sub-unit includes a Muller C cell and a first flip-flop, and the second sampling sub-unit includes a Muller C cell and a first flip-flop; The output terminal of the first inverter is electrically connected to the input terminal of the second inverter and the first input terminal of the Muller C cell of the first sampling sub-unit respectively, the output terminal of the second inverter is electrically connected to the input terminal of the third inverter and the second input terminal of the Muller C cell in the first sampling sub-unit respectively, the output terminal of the third inverter is electrically connected to the input terminal of the fourth inverter and the first input terminal of the Muller C cell in the second sampling sub-unit respectively, the output terminal of the fourth inverter is electrically connected to the input terminal of the fifth inverter and the second input terminal of the Muller C cell in the second sampling sub-unit respectively, and the output terminal of the fifth inverter is electrically connected to the input terminal of the first inverter; The first input terminal of the first exclusive-OR gate unit is electrically connected to the output terminal of the first flip-flop in the first sampling sub-circuit, and the second input terminal of the first exclusive-OR gate unit is electrically connected to the output terminal of the first flip-flop in the second sampling sub-circuit.

4. The true random number generator according to claim 2, characterized in that, The inverter is used to invert the acquired signal and output the first signal; The Muller C unit is used to acquire two of the first signals and output a third signal according to the two first signals. Wherein, when the signal values of the two first signals are both the first value, a third signal with the signal value of the first value is output; when the signal values of the two first signals are both the second value, a third signal with the signal value of the second value is output; when the signal values of the two first signals are different, the signal value of the third signal remains unchanged; The first flip-flop is used to sample the third signal once in each clock cycle, and is also used to store the third signal sampled in the current clock cycle and output the third signal sampled in the previous clock cycle; The first exclusive-OR gate unit is used to acquire all of the third signals and output the second signal according to all of the third signals. Wherein, when the signal values of all of the third signals are the same, a second signal with the signal value of the first value is output; when there is a third signal among all of the third signals whose signal value is different from that of other third signals, a second signal with the signal value of the second value is output.

5. The true random number generator according to claim 1, wherein The number of the sampling sub-circuits is m, where m is a positive integer; the selection output circuit includes a selection unit and m selection sub-circuits, and the selection sub-circuit includes a second flip-flop and a second exclusive-OR gate unit; The output terminal of the kth sampling sub-circuit is respectively electrically connected to the input terminal of the second flip-flop in the kth selection sub-circuit and the first input terminal of the second exclusive-OR gate unit in the kth selection sub-circuit. The output terminal of the second flip-flop in the kth selection sub-circuit is respectively electrically connected to the second input terminal of the second exclusive-OR gate unit in the kth selection sub-circuit and the pth input terminal of the selection unit; the output terminal of the second exclusive-OR gate unit in the kth selection sub-circuit is electrically connected to the qth input terminal of the selection unit, where k is a positive integer less than or equal to m, and p and q are both positive integers less than or equal to 2m.

6. The true random number generator according to claim 5, characterized in that, The second flip-flop is used to sample the second signal once in each clock cycle, and is also used to store the second signal sampled in the current clock cycle and output the second signal sampled in the previous clock cycle; The second exclusive-OR gate unit is used to acquire the second signal and output a fourth signal according to the second signal. Wherein, when the signal value of the second signal sampled in the current clock cycle is the same as the signal value of the second signal sampled in the previous clock cycle, a fourth signal with the signal value of the first value is output; when the signal value of the second signal sampled in the current clock cycle is different from the signal value of the second signal sampled in the previous clock cycle, a fourth signal with the signal value of the second value is output; The selection unit is configured to obtain all of the fourth signals, determine the target signal according to all of the fourth signals, and output the signal value of the target signal collected in the current clock cycle as the random number; Specifically, the selection unit is configured to determine, as the target fourth signal, the fourth signal with a signal value of the first value among all of the fourth signals, determine, as the target second flip-flop, the second flip-flop electrically connected to the second exclusive-OR gate unit that outputs the target fourth signal, and determine the second signal output by the target second flip-flop as the target signal.

7. The true random number generator according to any one of claims 1 to 6, characterized in that, The number of the ring oscillators is m, where m is a positive integer; The true random number generator further includes a third exclusive-OR gate unit, which is electrically connected to each of the ring oscillators. Specifically, the k-th input terminal of the third exclusive-OR gate unit is electrically connected to the output terminal of the k-th ring oscillator, where k is a positive integer less than or equal to m; The output terminal of the third exclusive-OR gate unit is electrically connected to the input terminal of the selection output circuit.

8. The true random number generator according to claim 7, wherein The ring oscillator is further configured to output a fifth signal; The third exclusive-OR gate unit is configured to obtain all of the fifth signals and output a sixth signal according to all of the fifth signals. Specifically, when the signal values of all of the fifth signals are the same, a sixth signal with a signal value of the first value is output; when there is a fifth signal with a signal value different from that of other fifth signals among all of the fifth signals, a sixth signal with a signal value of the second value is output; The selection output circuit is further configured to output the signal value of the sixth signal as the random number when all of the second signals meet a preset condition; where the preset condition is that the currently collected signal value of the second signal is the same as the signal value collected last time.

9. The true random number generator according to claim 4 or 6, characterized in that, The first value is binary 0, and the second value is binary 1.

10. An integrated circuit board, characterized in that, Comprising the true random number generator according to any one of claims 1-9, further comprising a target circuit, and the output terminal of the true random number generator is connected to the target circuit.

11. The integrated circuit board according to claim 10, characterized in that, The integrated circuit board further includes a mesh metal connection wire, and the true random number generator and the target circuit are connected through the mesh metal connection wire.

12. An electronic device, characterized in that, Comprising the integrated circuit board according to claim 10 or 11.

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