A branch target address optimization storage structure based on a target address pool

Abstract

The application provides a branch target address optimization storage structure based on a target address pool, belongs to the technical field of address optimization storage structure, and comprises a target address pool and a working process thereof, further comprises a branch record buffer modification, and the working process of the target address pool comprises the following steps: S1, an allocation stage step, S2, a running stage step, which comprises a target address access link and a processing pipeline refreshing link; S3, a branch resolution stage step, which comprises a receiving execution result link, a prediction correct processing link and a prediction error processing link; S4, a branch predictor updating and releasing step, which comprises a prediction correct link, a prediction error link and a branch record buffer entry releasing link, and the application stores the index of the address in the target address pool through the branch record buffer, so that the effect of reducing the storage space is achieved, in view of the problems of large storage overhead and long life cycle of the traditional address storage scheme.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of address optimization storage structure, and particularly relates to a branch target address optimization storage structure based on a target address pool. BACKGROUND

[0002] With the evolution of integrated circuit technology and the rapid growth of computing demand, modern processors (CPUs) are developing towards higher performance and stronger parallelism. In both server and embedded device fields, the clock frequency, instruction issue width and instruction level parallelism (ILP) of the processor are constantly improving. To adapt to diversified application scenarios (such as artificial intelligence, big data, cloud computing, etc.), the front-end instruction fetch bandwidth and branch prediction accuracy requirements of the CPU are also increasingly high. At the same time, the chip power and area (PPA) constraints are becoming increasingly stringent. How to maintain high performance while reducing power consumption and chip area as much as possible has become a core challenge in the design of modern processor microarchitecture.

[0003] In the processor front-end unit (IFU), in order to effectively track and update the branch instructions, a large amount of branch information in the execution process often needs to be stored in the branch record buffer (BRB) or similar modules. Among them, the "target address (Target PC)" usually occupies a considerable bit width (for example, 48 bits or 64 bits), and since modern CPUs often need to configure tens to hundreds of entries (Entries) in the BRB, this makes the storage of Target PC alone consume considerable chip area and register file resources. Especially in the high-end wide-issue CPU scenario, the number of in-flight branches may be more, and the storage overhead is further magnified. How to significantly compress the Target PC storage resources while ensuring high branch prediction performance and correctness, reduce power consumption and improve overall efficiency is one of the difficult problems to be solved in the current CPU front-end design.

[0004] In modern CPU design, in order to improve the performance of the processor, a large number of buffers are often set in the front-end instruction fetch unit to record various information of in-flight branches. Taking the branch record buffer (Branch Record Buffer, BRB) as an example, in order to completely cover the entire life cycle of the branch instruction from fetching to retiring, the BRB often needs a large number of Entries (for example, 128), and records the complete Target PC of the branch in each Entry. If the PC width is large (for example, RV48 supports 48-bit address), then only storing these Target PC requires 128*48bit=0.75KB.

[0005] However, there is a strong mutual restraint relationship among the performance, power consumption and area (PPA) of CPU. Under the premise of ensuring high performance, the optimization of power consumption and area is particularly important. If all the complete Target PC of the branch on the way is directly stored in the BRB, it will bring a large overhead. Therefore, the application (invention) proposes a Target PC Pool (TP) scheme, which only stores the index of the TP in the BRB, thereby significantly compressing the storage demand of the BRB for the target address, and ensuring the correctness and efficiency of branch prediction and update at the system level.

[0006] Disadvantages of the prior art:

[0007] 1. Large storage overhead: When each BRB Entry stores the complete Target PC, the overall storage size doubles, resulting in increased chip area and power consumption.

[0008] 2. Long life cycle: The entire process of branch instruction from identification to retirement may be long, and the Target PC is always retained in the BRB during this period, and the cache space is not fully utilized.

[0009] 3. PPA optimization difficulty: IFU itself is a high-area / power-consumption hotspot, and the large-capacity Target PC storage further reduces the overall energy efficiency of the processor.

[0010] The application proposes a branch target address optimization storage structure based on a target address pool to solve the above problems. SUMMARY

[0011] The application places the complete Target PC information in the TPP when the branch instruction is written into the BRB. Only a Pool Index index needs to be recorded in the BRB. After branch resolution, if the prediction result is correct, the TPP can release the Target PC information of the entry earlier, without waiting for all branch prediction unit components to update before releasing. This scheme can design a smaller TP capacity (number of entries) (for example, only 16 entries) to meet the life cycle requirements from branch allocation entry to resolution, thereby significantly saving the storage resources that may need to be maintained in the BRB, thereby overcoming the problems in the above background technology.

[0012] Based on the above technical idea, the technical scheme adopted by the application is:

[0013] A branch target address optimization storage structure based on a target address pool, comprising a target address pool and its workflow.

[0014] The target address pool includes a 48-bit complete target address and a 1-bit status bit, and has a capacity much smaller than the branch record buffer;

[0015] The branch record buffer is also modified to only store an index pointing to the TP instead of a complete target address.

[0016] The workflow of the target address pool includes the following steps:

[0017] S1 allocation stage, including a branch instruction fetch stage, a target address pool writing stage, an index generating stage, and an update of the branch record buffer stage.

[0018] S2 running stage, including a target address accessing stage and a processing pipeline flush stage.

[0019] S3 branch resolution stage, including a receiving execution result stage, a correct prediction processing stage, and an incorrect prediction processing stage.

[0020] S4 branch predictor update and release stage, including a correct prediction stage, an incorrect prediction stage, and a branch record buffer entry release stage.

[0021] Further to the above technical solution, the branch instruction fetch stage in the S1 allocation stage includes a branch instruction entering a front-end fetch unit, being identified, and being allocated a branch record buffer entry, the target address pool writing stage includes writing a complete predicted target address of the branch into a free entry of the target address pool, and changing a status bit of the target address entry to 1.

[0022] Further to the above technical solution, the index generating stage includes the target address pool returning an index allocated to the entry, and the update of the branch record buffer stage includes only storing the index instead of a complete target address in a corresponding entry of the branch record buffer, and recording other branch information.

[0023] Further to the above technical solution, the target address accessing stage in the S2 running stage includes, when the pipeline needs to read a branch target address, the branch record buffer looking up the target address pool through the index to obtain a complete address.

[0024] Further to the above technical solution, the processing pipeline flush stage includes, if a pipeline flush occurs, changing a status bit of an entry of a branch and a subsequent branch in the target address pool to 0, and reserving but no longer using a corresponding index in the branch record buffer.

[0025] Further limiting the above technical solution, in the S3 branch resolution phase, receiving the execution result includes the execution unit completing the branch calculation and returning the actual target address and prediction correctness to the front end;

[0026] The predicted correct processing step includes locating the entry in the target address pool through the index in the branch record buffer, immediately releasing the TP entry, changing the status bit of the entry in the target address pool to 0 without waiting for subsequent operations, and retaining the branch record buffer entry until the branch is retired.

[0027] A further limitation of the above technical solution is that the prediction error processing link includes locating the entry in the target address pool through the index, overwriting the erroneous address, writing the correct target address calculated by the execution unit into the original entry position in the target address pool, keeping the status bit at 1, and the entry is still valid and will be released after the branch predictor is subsequently updated.

[0028] Further limitation of the above technical solution is the S4 branch predictor update and release step, in which the correct prediction link includes no need to update the branch predictor, the entry in the target address pool has been released in the branch resolution stage, and the status bit has been changed to 0. The wrong prediction link includes updating the branch predictor, reading the correct target address in the target address pool through the index of the branch record buffer, updating the branch predictor in combination with the branch information, releasing the entry in the target address pool, and changing the status bit of the entry in the target address pool to 0 after the branch predictor update is completed.

[0029] As a further limitation of the above technical solution, the branch record buffer entry release link includes releasing the branch record buffer entry after the branch instruction is retired, regardless of whether the prediction is correct or not.

[0030] Further limitation of the above technical solution is that the address width adapted by the target address pool includes 16 / 32 / 48 / 64 bits, and the address width bit is provided in the entry in the target address pool. The address width bit is composed of two Boolean characters. The content stored in the address width bit is 0 / 1 / 2 / 3 corresponding to the 16 / 32 / 48 / 64-bit address width, and the subsequent address content of different lengths is read by identifying the address width bit.

[0031] Compared with the prior art, the present invention has the following beneficial effects:

[0032] 1. Separate storage idea: The branch instruction only records the index pointing to the Target PC Pool in the BRB, rather than saving the complete Target PC.

[0033] 2. On-demand allocation and early release of the Target PC Pool (TPP): When a branch is resolved, if the branch prediction is correct, the entry can be released immediately without waiting for all subsequent update operations to complete.

[0034] 3. Flexible and scalable: The size of TPP can be set according to statistical analysis, usually much smaller than the number of entries of BRB, maximizing the saving of area and power consumption.

[0035] 4. Compatibility with existing branch prediction process: No fundamental change is needed for branch resolution, BPU update, pipeline flush, etc., only the index operation is added when allocating and releasing.

[0036] 5. Significant saving of storage area: By splitting the storage period and space requirements of Target PC, TPP only needs to cover the time window of branch allocation to resolution, and does not need to cover the retirement period of branch redundantly.

[0037] 6. Higher energy efficiency: The read / write access amount of Target PC in IFU is reduced, the power consumption of the memory is improved, and the overall PPA of CPU is improved.

[0038] 7. Little impact on other structures in the front end: It ensures the normal logic of branch prediction, and does not damage the branch identifier, direction and other fields originally recorded by BRB.

[0039] 8. Flexible adaptation to various processors: Whether the address width is 32 bits, 48 bits or 64 bits, similar saving effects can be achieved by adjusting the size of TP and the index bit width. BRIEF DESCRIPTION OF DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0041] Figure 1 A schematic diagram of a branch target address optimization storage structure based on a target address pool. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings Figure 1 The present application will be further described in detail.

[0043] Embodiment 1: The present embodiment provides a branch target address optimization storage structure based on a target address pool, as shown in Figure 1 , including a target address pool and its working process;

[0044] The target address pool includes storage of complete 48-bit target addresses and 1-bit status bits, and the capacity is much smaller than that of the branch record buffer;

[0045] It also includes branch record buffer modification, which includes storing only the index pointing to the TP instead of the full target address;

[0046] The workflow of the target address pool includes the following steps:

[0047] S1 allocation phase step, which includes branch instruction fetching, writing into the target address pool, generating indexes, and updating the branch record buffer;

[0048] S2 operation phase step, which includes the target address access link and the processing pipeline refresh link;

[0049] S3 branch parsing phase, which includes receiving execution results, correct prediction processing, and incorrect prediction processing;

[0050] S4 is a branch predictor update and release step, which includes a correct prediction phase, an incorrect prediction phase, and a branch record buffer entry release phase.

[0051] The S1 allocation phase step, in which the branch instruction fetch link includes the branch instruction entering the front-end instruction fetch unit, being identified and allocated a branch record buffer entry, and the writing target address pool link includes writing the complete predicted target address of the branch into a free entry in the target address pool, and changing the status bit of the target address entry to 1.

[0052] The index generation link includes the target address pool returning the index assigned to the entry, and the branch record buffer update link includes storing only the index, rather than the complete target address, in the corresponding entry of the branch record buffer and recording other branch information.

[0053] The S2 operation phase step includes the target address access link including when the pipeline needs to read the branch target address, the branch record buffer searches the target address pool through the index to obtain the complete address.

[0054] The pipeline refresh process includes: if a pipeline refresh occurs, changing the entry status bits of the refreshed branch and subsequent branches in the target address pool to 0, and retaining the corresponding index in the branch record buffer but no longer using it.

[0055] The S3 branch parsing phase step, in which the execution result is received, includes the execution unit completing the branch calculation and returning the actual target address and prediction correctness to the front end;

[0056] The predicted correct processing step includes locating the entry in the target address pool through the index in the branch record buffer, immediately releasing the TP entry, changing the status bit of the entry in the target address pool to 0 without waiting for subsequent operations, and retaining the branch record buffer entry until the branch is retired.

[0057] The prediction error processing link includes locating the entry in the target address pool by indexing, covering the error address, writing the correct target address calculated by the execution unit into the original entry position in the target address pool, keeping the state bit as 1, and the entry is still valid, and waiting for subsequent update of the branch predictor to release.

[0058] The branch predictor updating and releasing step includes that the prediction correct link does not need to update the branch predictor, the entry in the target address pool has been released in the branch resolution stage, and the state bit has been changed to 0; the prediction error link includes updating the branch predictor, the branch record buffer entry reads the correct target address in the target address pool by indexing, updates the branch predictor in combination with the branch information, releases the entry in the target address pool, and changes the state bit of the entry in the target address pool to 0 after the branch predictor is updated.

[0059] The branch record buffer entry release link includes that the branch record buffer entry is released after the branch instruction retires, regardless of whether the prediction is correct or not.

[0060] The address width of the target address pool adaptation includes 16 / 32 / 48 / 64 bits, and the entry in the target address pool is provided with an address width bit, the address width bit is composed of two Boolean characters, and the address width bit stores 0 / 1 / 2 / 3 corresponding to 16 / 32 / 48 / 64 bit address width, and the subsequent address content of different lengths is read by identifying the address width bit.

[0061] Embodiment 2: The embodiment provides a branch target address optimization storage structure based on a target address pool, as shown in Figure 1 , which also includes a TPP structure.

[0062] Target address pool Target PC Pool (TPP) structure:

[0063] Each target address Target PC (TP) entry includes a 48-bit complete target PC and a 1-bit state bit to mark whether the entry is valid.

[0064] It can be designed to be much less than the number of BRB entries (for example, TP has only 16 entries, while BRB has 128 entries).

[0065] Target PC Pool (TPP) workflow:

[0066] Allocation:

[0067] 1. After the branch instruction is fetched, the complete predicted target address corresponding to the branch instruction is written into the TP while the branch record buffer is written.

[0068] 2. After writing the entry, set the valid bit to 1 and return the tp_idx corresponding to the entry. Assuming the TP has 16 entries, the idx needs 4-bit.

[0069] 3. Write the tp_idx into the Branch Record Buffer (BRB) entry corresponding to the branch instruction.

[0070] In-Flight:

[0071] 1. The BRB only stores the tp_idx, the target address is always stored in the TPP, and does not occupy the register area of the BRB.

[0072] 2. If the pipeline is flushed, the target address stored in the TPP corresponding to the branch and subsequent branch instructions will be invalidated together, and the valid bit will be set to 0.

[0073] Resolve:

[0074] When the branch instruction is resolved, the instruction execution unit will return the prediction result to the IFU.

[0075] 1. If the prediction is correct, the corresponding entry storing the target address can be immediately indexed through the tp_idx stored in the BRB, and the valid bit is cleared to 0, indicating that the current entry has been deallocated.

[0076] 2. If the prediction is incorrect, the correct target address of the execution unit is written to the entry corresponding to the TPP, overwriting the previously stored incorrect address.

[0077] BP Update:

[0078] After the branch instruction is completed, the BRB needs to update the branch prediction unit by storing the contents.

[0079] 1. Correct prediction: the target branch stored in the branch prediction unit does not need to be updated.

[0080] 2. Incorrect prediction: the BRB reads the branch instruction information stored in itself, and also reads the TP through the tp_idx to obtain the correct branch target address to finally complete the BP update.

[0081] Deallocation:

[0082] 1. When the branch prediction is correct during branch resolution, the TP entry will be immediately deallocated.

[0083] 2. When branch resolution, the entry in TPP will be released after branch predictor is updated.

[0084] Significant area saving:

[0085] Only TP index is stored in BRB, greatly reducing the width of BRB entry.

[0086] TPP capacity can also be much smaller than the number of BRB entries, because not all branches are in the resolve state at the same time;

[0087] Take 128 Entry BRB, 48-bit address as an example: if not distinguished, it needs 128x48 bits = 0.75KB. If TP has only 16 entries, and Pool Index + prediction information (e.g. Pool Index needs 4 bits) is saved in BRB, nearly 0.6KB of storage can be saved, the specific calculation method is as follows:

[0088] Original scheme: 128x48 bits = 6144 bits (≈0.75KB)

[0089] New scheme TPP: 16x49 bits = 784 bits (≈0.1KB)

[0090] New scheme BRB: 128x4 bits (Pool Index) = 512 bits (≈0.06KB)

[0091] Total ≈0.16KB, compared with 0.75KB, nearly 80% storage area is saved.

[0092] Embodiment 3: The embodiment provides a target address pool-based branch target address optimization storage structure, as shown in Figure 1 Also includes a shared TP structure:

[0093] Shared Target PC Pool: If multiple branch instructions may share the same target PC, redundant storage can be further reduced. But need additional logic to distinguish reference count.

[0094] Variable word length: If part of the branch PC only needs 32-bit address space, the storage bit width can be adaptively shortened, but an additional flag bit is needed to indicate the address mode (32 / 64 bits, etc.).

[0095] The above is a further detailed description of the present application in combination with a specific preferred embodiment, which is convenient for the technical personnel in the technical field to understand and apply the present application, and cannot be regarded as the specific implementation of the present application.

Claims

1. A branch target address optimization storage structure based on a target address pool, characterized in that: Including target address pool and its workflow; The target address pool includes storage of the complete 48-bit target address and 1 status bit, and its capacity is smaller than the branch record buffer; It also includes branch record buffer modification, which includes storing only the index pointing to the TP instead of the full target address; The workflow of the target address pool includes the following steps: S1 allocation phase step, which includes branch instruction fetching, writing into the target address pool, generating indexes, and updating the branch record buffer; S2 operation phase step, which includes the target address access link and the processing pipeline refresh link; S3 branch parsing phase, which includes receiving execution results, correct prediction processing, and incorrect prediction processing; S4 branch predictor update and release step, which includes a correct prediction phase, an incorrect prediction phase, and a branch record buffer entry release phase; The S1 allocation phase includes the following steps: the branch instruction fetching step includes the branch instruction entering the front-end instruction fetch unit, being identified and allocated a branch record buffer entry; the writing step includes writing the complete predicted target address of the branch into a free entry in the target address pool, and changing the status bit of the target address entry to 1; The step of the S2 operation phase, in which the target address access link includes when the pipeline needs to read the branch target address, the branch record buffer searches the target address pool through the index to obtain the complete address; The S3 branch parsing phase step, in which the execution result receiving link includes the execution unit completing the branch calculation and returning the actual target address and prediction correctness to the front end; The predicted correct processing step includes locating the entry in the target address pool through the index in the branch record buffer, immediately releasing the TP entry, changing the status bit of the entry in the target address pool to 0 without waiting for subsequent operations, and retaining the branch record buffer entry until the branch is retired.

2. The branch target address optimization storage structure based on the target address pool according to claim 1, characterized in that: The index generation link includes the target address pool returning the index assigned to the entry, and the branch record buffer update link includes storing only the index, rather than the complete target address, in the corresponding entry of the branch record buffer and recording other branch information.

3. The branch target address optimization storage structure based on the target address pool according to claim 2, characterized in that: The pipeline refresh process includes: if a pipeline refresh occurs, changing the entry status bits of the refreshed branch and subsequent branches in the target address pool to 0, and retaining the corresponding index in the branch record buffer but no longer using it.

4. The branch target address optimization storage structure based on the target address pool according to claim 3, characterized in that: The prediction error processing link includes locating the entry in the target address pool through the index, overwriting the wrong address, writing the correct target address calculated by the execution unit into the original entry position in the target address pool, keeping the status bit at 1, and the entry is still valid and will be released after the branch predictor is subsequently updated.

5. The branch target address optimization storage structure based on the target address pool according to claim 4, characterized in that: S4 branch predictor update and release step. In this step, the correct prediction link includes no need to update the branch predictor, the entry in the target address pool has been released in the branch resolution stage, and the status bit has been changed to 0. The wrong prediction link includes updating the branch predictor, reading the correct target address in the target address pool through the index of the branch record buffer, updating the branch predictor in combination with the branch information, releasing the entry in the target address pool, and changing the status bit of the entry in the target address pool to 0 after the branch predictor update is completed.

6. The branch target address optimization storage structure based on the target address pool according to claim 5, characterized in that: The branch record buffer entry release phase includes releasing the branch record buffer entry after the branch instruction is retired, regardless of whether the prediction is correct or not.

7. The branch target address optimization storage structure based on the target address pool according to claim 6, characterized in that: The target address pool adapts to address widths of 16 / 32 / 48 / 64 bits. Entries in the target address pool are provided with address width bits, which consist of two Boolean characters. The address width bits store contents of 0 / 1 / 2 / 3 corresponding to 16 / 32 / 48 / 64-bit address widths. Subsequent address contents of different lengths are read by identifying the address width bits.

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