Method, device, medium and program product for executing hybrid heterogeneous computing tasks

Abstract

The present invention provides a method, device, medium, and program product for executing hybrid heterogeneous computing tasks, which can be applied in the field of computer technology. The method includes: in response to receiving a subtask from a target processor connected to a first controller in a controller array, the first controller divides the subtask into at least one task step; assigns the at least one execution step to at least one second controller in the controller array; uses the at least one second controller to process the at least one task step to obtain a subtask result for the subtask; and sends the subtask result to the target processor, so that multiple processors determine the execution result of the task to be executed based on their respective subtask results.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a method, device, medium and program product for executing hybrid heterogeneous computing tasks. Background Art

[0002] Traditional methods for training deep learning models typically rely on a single type of hardware accelerator to perform computational tasks. These hardware accelerators are optimized for specific computations and can achieve high efficiency under matching workloads.

[0003] However, a single hardware accelerator cannot efficiently cope with the diverse computing needs of model training. For example, although the processor can complete computationally intensive tasks relatively well, it is less efficient when processing logic-intensive tasks. In addition, the high power consumption of the processor limits its application in edge scenarios. Programmable hardware can customize its logical structure due to its programmability, but its programming complexity is high and its adaptability to irregular computing patterns is insufficient. In addition, the computing characteristics of different stages in the model training process vary significantly. It is difficult for existing hardware to dynamically adjust the architecture to match the real-time workload, resulting in limited overall training efficiency and increased hardware resource waste and system costs. Summary of the Invention

[0004] In view of the above problems, the present invention provides a method, device, medium and program product for executing hybrid heterogeneous computing tasks.

[0005] According to a first aspect of the present invention, a method for executing a hybrid heterogeneous computing task is provided, comprising: in response to receiving a subtask from a target processor connected to a first controller in a controller array, the first controller dividing the subtask into at least one task step, wherein the subtask is obtained by dividing the task to be executed, and when the task type of the subtask assigned to the target processor is a preset type, the target processor sends the subtask to the first controller; assigning at least one execution step to at least one second controller in the controller array, wherein the controller array includes a plurality of controllers connected in a ring topology; using the at least one second controller, processing the at least one task step respectively to obtain a subtask result of the subtask; and sending the subtask result to the target processor, so that the plurality of processors determine the execution result of the task to be executed based on their respective subtask results.

[0006] The second aspect of the present invention provides an execution device for hybrid heterogeneous computing tasks, including: a task division module, for responding to receiving a subtask from a target processor connected to a first controller in a controller array, the first controller dividing the subtask into at least one task step, wherein the subtask is obtained by dividing the task to be executed, and when the task type of the subtask assigned to the target processor is a preset type, the target processor sends the subtask to the first controller; a task allocation module, for respectively assigning at least one execution step to at least one second controller in the controller array, wherein the controller array includes multiple controllers connected in a ring topology; a task processing module, for using at least one second controller to process at least one task step respectively to obtain a subtask result of the subtask; a result sending module, for sending the subtask result to the target processor, so that multiple processors determine the execution result of the task to be executed based on their respective subtask results.

[0007] The third aspect of the present invention provides a device for executing hybrid heterogeneous computing tasks, comprising: a processor array, wherein the processor array includes multiple processors, and the multiple processors include a target processor, wherein the target processor is used to process subtasks obtained by dividing the task to be executed to obtain subtask results; a controller array, wherein the controller array includes multiple controllers connected in a ring topology, and the multiple controllers in the controller array are respectively connected to and only to one processor in the processor array; a first controller among the multiple controllers is used to divide the subtask into at least one task step in response to receiving a subtask from the target processor connected to the first controller in the controller array, and assign at least one execution step to at least one second controller in the controller array; multiple second controllers are used to process at least one task step respectively to obtain subtask results of the subtask; wherein, when the task type of the subtask assigned to the target processor is a preset type, the target processor sends the subtask to the first controller.

[0008] The fourth aspect of the present invention also provides an electronic device, comprising: one or more processors; a memory for storing one or more computer programs, wherein the one or more processors execute the one or more computer programs to implement the steps of the above method.

[0009] The fifth aspect of the present invention further provides a computer-readable storage medium having a computer program or instructions stored thereon, which implements the steps of the above method when the computer program or instructions are executed by a processor.

[0010] The sixth aspect of the present invention further provides a computer program product, comprising a computer program or instructions, which implement the steps of the above method when executed by a processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above contents and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings.

[0012] Figure 1 An application scenario diagram of a method, device, medium, and program product for executing a hybrid heterogeneous computing task according to an embodiment of the present invention is shown.

[0013] Figure 2 A flow chart of a method for executing a hybrid heterogeneous computing task according to an embodiment of the present invention is shown.

[0014] Figure 3 A schematic diagram showing a method for executing a hybrid heterogeneous computing task according to an embodiment of the present invention, wherein subtasks are processed in a pipeline form.

[0015] Figure 4 A flowchart of a method for executing a hybrid heterogeneous computing task for model training according to an embodiment of the present invention is shown.

[0016] Figure 5 A topology diagram of a device for executing hybrid heterogeneous computing tasks according to an embodiment of the present invention is shown.

[0017] Figure 6 A partial structural diagram of a controller array according to an embodiment of the present invention is shown.

[0018] Figure 7 A structural block diagram of a device for executing hybrid heterogeneous computing tasks according to an embodiment of the present invention is shown.

[0019] Figure 8 A block diagram of an electronic device suitable for implementing a method for executing hybrid heterogeneous computing tasks according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0020] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present invention. In the following detailed description, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of embodiments of the present invention. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concept of the present invention.

[0021] The terms used herein are only for describing specific embodiments and are not intended to limit the present invention. The terms "comprise", "include", etc. used herein indicate the presence of the features, steps, operations and / or components, but do not exclude the presence or addition of one or more other features, steps, operations or components.

[0022] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0023] When expressions such as "a plurality of A, B, and C, etc." are used, they should generally be interpreted in accordance with the meaning commonly understood by those skilled in the art (for example, "a system having a plurality of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0024] An embodiment of the present invention provides a method for executing a hybrid heterogeneous computing task, comprising: in response to receiving a subtask from a target processor connected to a first controller in a controller array, the first controller divides the subtask into at least one task step, wherein the subtask is obtained by dividing the task to be executed, and when the task type of the subtask assigned to the target processor is a preset type, the target processor sends the subtask to the first controller; assigning at least one execution step to at least one second controller in the controller array, wherein the controller array includes multiple controllers connected in a ring topology; using the at least one second controller, processing the at least one task step separately to obtain a subtask result of the subtask; and sending the subtask result to the target processor, so that the multiple processors determine the execution result of the task to be executed based on their respective subtask results.

[0025] Figure 1 An application scenario diagram of a method, device, medium, and program product for executing a hybrid heterogeneous computing task according to an embodiment of the present invention is shown.

[0026] like Figure 1As shown, an application scenario 100 of the method, device, medium, and program product for executing hybrid heterogeneous computing tasks according to an embodiment of the present invention includes an external device 110, a processor 120, a controller 130, and a memory 140. The external device 110 and the processor 120, the processor 120 and the controller 130, the processor 120 and the memory 140, and the controller 130 and the memory 140 are connected via electrical signals. The processor 120 and the controller 130 are connected via the Compute ExpressLink (CXL) protocol, enabling high-performance, low-latency communication between the processor 120 and the controller 130, thereby enabling tasks assigned to the processor 120 to be dispatched to the controller 130 for processing. Furthermore, the CXL protocol supports memory consistency and resource sharing.

[0027] The external device 110 may be a terminal device used by a user to initiate a hybrid heterogeneous computing task. After initiating the hybrid heterogeneous computing task, the external device 110 sends the hybrid heterogeneous computing task to the processor 120 .

[0028] Processor 120 can be any processor with powerful computing capabilities, such as a central processing unit (CPU) or a graphics processing unit (GPU). Processor 120 includes a computing array 121, an internal interconnect module 122, and high-bandwidth memory (HBM) 123. Computing array 121 is used to process tasks assigned to processor 120, internal interconnect module 122 is used for communication between multiple processors, and high-bandwidth memory 123 is used to store frequently used data during the processing of tasks assigned to processor 120.

[0029] The controller 130 includes a programmable logic area 131, a control module 132, and a flash memory module 133. The programmable logic area 131 can be programmed by the user to enable the controller 130 to implement various functions. The control module 132 is used to control a controller array consisting of multiple controllers using the controller 130, so that the multiple controllers can process tasks issued by the processor 120. The flash memory module 133 is used to reduce access latency and improve processing efficiency through high-speed caching.

[0030] The memory 140 is used to provide data support to the processor 120 and / or the controller 130 when the processor 120 and / or the controller 130 processes tasks, and to store the data processed by the processor 120 and / or the controller 130 so that the user can query and verify it through the external device 110.

[0031] It should be understood that Figure 1 The number of external devices, processors, controllers and memories in the embodiment is merely illustrative. Any number of external devices, processors, controllers and memories may be provided as required.

[0032] The following will be based on Figure 1 The scene described by Figures 2 to 4 The method for executing hybrid heterogeneous computing tasks according to an embodiment of the invention is described in detail.

[0033] Figure 2 A flow chart of a method for executing a hybrid heterogeneous computing task according to an embodiment of the present invention is shown.

[0034] like Figure 2 As shown, the method for executing a hybrid heterogeneous computing task in this embodiment includes operations S210 to S240.

[0035] In operation S210 , in response to receiving a subtask from a target processor connected to a first controller in a controller array, the first controller divides the subtask into at least one task step.

[0036] According to an embodiment of the present invention, a controller array includes multiple controllers. During the execution of a hybrid heterogeneous computing task, for each subtask, the controller that receives the subtask is the first controller, and the controller that processes the subtask is the second controller. If a first controller receives a subtask and subsequently processes the subtask, the controller is both the first controller and the second controller.

[0037] Among them, the controller may include a programmable device, which is an integrated circuit that can be programmed through a hardware description language. Therefore, the controller has strong parallel computing capabilities and logic configuration capabilities, and the controller's parallel computing capabilities are mainly reflected in the flexible parallel computing of heterogeneous tasks.

[0038] According to an embodiment of the present invention, subtasks are obtained by dividing the task to be executed, that is, the task to be executed is divided to obtain at least one subtask, and the at least one subtask is allocated so that at least one processor processes one subtask respectively.

[0039] According to an embodiment of the present invention, for each subtask, the target processor for processing the subtask is used to determine its task type. If the task type of the subtask assigned to the target processor is a preset type, the target processor sends the subtask to the first controller.

[0040] The preset types can be customized. Generally, the parallel computing capability of the processor is relatively strong, and the parallel computing capability of the processor is mainly reflected in the parallel computing of large-scale homogeneous tasks.

[0041] Preferably, the preset type can be determined based on the programming logic of the controller and the processor. Specifically, by programming the controller, the controller's processing capabilities for various types of tasks can be determined. After comparing the processing capabilities of the controller with the processing capabilities of the processor, the preset type can be set based on the task type corresponding to the task that the controller is better at.

[0042] For example, by comparing the capabilities of the processor and the controller, the preset type can preferably be set to a logic-intensive task, that is, when the target processor receives a subtask and determines that the subtask is a logic-intensive task, the subtask can be sent to the first controller connected to the target processor, and the first controller can be used to parse the subtask and control the controller array in which it is located to process the subtask.

[0043] In operation S220 , at least one execution step is respectively distributed to at least one second controller in the controller array.

[0044] According to an embodiment of the present invention, the controller array includes a plurality of controllers connected in a ring topology, wherein the plurality of controllers connected in a ring topology are connected end to end in a point-to-point manner to form a closed ring topology, and there are no redundant links or branch connections in the topology structure.

[0045] According to an embodiment of the present invention, the execution steps are respectively assigned to the second controllers, so that each second controller is assigned to execute one execution step, so as to fully utilize the parallel computing capability of the controllers and perform parallel computing on at least one execution step.

[0046] In operation S230 , at least one second controller is used to process at least one task step respectively to obtain a subtask result of the subtask.

[0047] According to an embodiment of the present invention, after the assignment is completed, the second controller is used to process the assigned task steps respectively, and the task results of the subtasks can be obtained based on the results of the multiple task steps.

[0048] In operation S240 , the subtask results are sent to the target processor, so that the multiple processors determine the execution results of the to-be-executed tasks according to their respective subtask results.

[0049] According to an embodiment of the present invention, the subtask results of at least one subtask included in the task to be executed can be determined based on the subtask results of the multiple processors, and the execution result can be determined based on the at least one subtask result.

[0050] According to an embodiment of the present invention, by sending subtasks of preset types from the target processor to the first controller for division, and using a controller array connected in a ring topology to process task steps in parallel, it is possible to optimize the configuration for different computing types and achieve collaborative scheduling of heterogeneous computing resources. The ring topology ensures the determinism and low latency of the communication path between controllers, avoids single point failures, and improves system reliability. In addition, the distributed processing of task steps utilizes the parallel computing capabilities of the controller array, reduces the load on the target processor, and can achieve efficient decomposition and execution of complex tasks. Therefore, through heterogeneous collaborative computing, it is possible to dynamically adapt to the different computing characteristics of different tasks, achieve intelligent allocation and efficient utilization of hardware resources, and improve the speed of task processing and reduce system power consumption and cost.

[0051] According to an embodiment of the present invention, dividing a subtask into at least one task step includes: parsing the subtask to obtain a parsing result, wherein the parsing result includes the task steps and the execution order between the task steps. Using the at least one second controller, processing the at least one task step separately to obtain a subtask result of the subtask includes: assigning the at least one task step to the at least one second controller based on the execution order and a preset function of the at least one second controller; and using the at least one second controller, sequentially executing the at least one task step in accordance with the execution order to obtain the subtask result.

[0052] According to an embodiment of the present invention, at least one preset function may be predefined for each second controller in the controller array, wherein the specific type of the preset function may be implemented by programming or other means according to actual needs and is not limited here.

[0053] According to an embodiment of the present invention, based on the execution order, task steps and the preset functions of multiple second controllers, the second controller for processing each task step can be determined, and at least one task step can be respectively assigned to the second controller for processing the task step.

[0054] According to an embodiment of the present invention, the second controller for executing each task step is determined in sequence according to the execution order, and the second controller is controlled in sequence to execute the assigned task steps in the above order to obtain the subtask result.

[0055] According to an embodiment of the present invention, task steps and execution order are obtained by parsing subtasks, providing a clear execution process for the subsequent scheduling of the controller array. This parsing process converts high-level subtasks into task steps that can be executed in parallel, enabling the system to optimize allocation based on the intrinsic logic of the task, ensuring orderliness when multiple controllers collaborate, and reducing execution conflicts and resource waste. In addition, task steps are allocated based on the execution order and the preset functions of the controller, thereby achieving heterogeneous adaptation of computing resources. Different controllers can be optimized for specific task types, combined with the efficient communication of the ring topology to ensure that task steps are executed in sequence, which not only gives full play to the parallel processing capabilities of the controller array, but also ensures the serial correctness of dependent tasks, thereby improving overall processing efficiency.

[0056] According to an embodiment of the present invention, at least one task step includes N steps, where N is an integer greater than 1; using at least one second controller, at least one task step is executed in sequence according to the execution order to obtain a subtask result, including: using the second controller corresponding to the first task step to execute the first task step to obtain the first step result; using the second controller corresponding to the nth task step in the execution order, based on the n-1th step result, execute the nth task step to obtain the nth step result, n=2,...N; wherein the Nth step result is used as the subtask result.

[0057] According to an embodiment of the present invention, when a subtask includes N task steps, the first task step, the second task step, ..., the nth task step, ..., the Nth task step among the N task steps are determined in order of execution.

[0058] According to an embodiment of the present invention, a subsequent task step requires the step result of the previous task step to execute. Therefore, according to the execution order, the second controller corresponding to the nth task step executes the nth task step based on the result of the n-1th step, thereby obtaining the nth task step. In particular, when n is N, it indicates that all N task steps included in the subtask have been executed, and therefore the result of the Nth task step is used as the subtask result.

[0059] In particular, when N task steps need to be processed multiple times in a subtask, at least one second controller can be controlled to repeatedly complete the N task steps multiple times in the form of a pipeline, thereby improving the utilization rate of the second controller and improving the processing efficiency of the subtask.

[0060] When N task steps need to be processed multiple times in a subtask, the subtask result can be obtained based on multiple N-th task step results obtained by processing the above N task steps multiple times.

[0061] Figure 3A schematic diagram showing a method for executing a hybrid heterogeneous computing task according to an embodiment of the present invention, wherein subtasks are processed in a pipeline form.

[0062] like Figure 3 As shown, the subtask that the current controller array needs to process includes four task steps, and the subtask needs to repeat the four task steps three times.

[0063] At time t0, the second controller corresponding to the first task step processes the first task step of the first subtask, obtaining a result for the first step of the first subtask. This result is then sent to the second controller corresponding to the second task step. At time t1, the second controller corresponding to the second task step processes the first task step of the second subtask based on the result for the first step of the first subtask, obtaining a result for the second step of the first subtask. Simultaneously, the second controller corresponding to the first task step processes the first step of the second subtask, obtaining a result for the first step of the second subtask. Similarly, at time t2, in addition to sequentially processing the third step of the first subtask and the second step of the second subtask, the second controller corresponding to the first task step also processes the first step of the third subtask, obtaining a result for the first step of the third subtask.

[0064] At times t3, t4 and t5, the first subtask, the second subtask and the third subtask are processed sequentially, and the result of the fourth task step of the first subtask is obtained at time t3, the result of the fourth task step of the second subtask is obtained at time t4, and the result of the fourth task step of the third subtask is obtained at time t5.

[0065] According to the fourth task step result of the first subtask, the fourth task step result of the second subtask and the fourth task step result of the third subtask, the subtask result of the subtask that the current control array needs to process can be obtained.

[0066] According to an embodiment of the present invention, for multi-step tasks, a pipelined, serial-parallel hybrid execution is achieved by transferring results between adjacent steps and combining them with the collaboration of ring-topology controllers. This execution approach ensures the logical correctness of the task while leveraging the parallel resources of the controller array, shortening overall execution time and improving task processing efficiency.

[0067] According to an embodiment of the present invention, at least one task step includes 1; using at least one second controller, at least one task step is processed separately to obtain a subtask result of the subtask, including: based on the preset function of at least one second controller, the task step is assigned to the second controller for executing the task step; and using the second controller for executing the task step to execute the task step to obtain the subtask result.

[0068] According to an embodiment of the present invention, when a subtask includes only one task step, a second controller for processing the task step is determined from multiple controllers based on respective preset functions of multiple second controllers, and the task step is allocated to the second controller.

[0069] According to an embodiment of the present invention, since the subtask only includes one task step, that is, the subtask is completed after the task step is completed, the subtask result can be obtained by executing the task step using the second controller for executing the task step.

[0070] According to an embodiment of the present invention, single-step tasks are directly assigned to the appropriate controller for execution, avoiding complex scheduling overhead. The ring topology ensures rapid routing of tasks to the target controller. Combined with the controller's optimized pre-set functionality, this enables efficient processing of single-step tasks, demonstrating the system's flexibility and low latency in simple task scenarios.

[0071] According to an embodiment of the present invention, sending the subtask result to the target processor includes: sending the subtask result to the first controller; and sending the subtask result to the target processor by using the first controller.

[0072] According to an embodiment of the present invention, since multiple controllers are connected in a ring topology, after obtaining the subtask result, the second controller that obtains the subtask result can send the subtask result to the first controller through the topology structure.

[0073] In the case that the subtask requires processing at least one task step multiple times, the first controller obtains multiple N-th task step results and determines the subtask result based on the multiple N-th task step results.

[0074] According to an embodiment of the present invention, after obtaining the subtask result, the first controller sends the subtask result to the target processor, so that the target processor and other processors determine the execution result of the task to be executed based on their respective subtask results.

[0075] According to an embodiment of the present invention, the first controller relays subtask results, utilizing a ring-shaped communication path to ensure that the result data is returned to the target processor via the shortest path. This centralized feedback mechanism simplifies the result aggregation process and reduces data transmission latency. Furthermore, it leverages the coordination capabilities of the first controller to avoid conflicts that might arise from direct communication between multiple controllers, thereby improving system stability.

[0076] According to an embodiment of the present invention, at least one subtask includes parallel subtasks that can be processed in parallel and dependent subtasks that need to rely on the execution results of other subtasks for execution; after the task to be executed is divided to obtain at least one subtask, the at least one subtask is respectively assigned to a processor for processing in the following manner: according to the task logic between multiple subtasks in the task to be executed, the dependent subtasks and the upstream subtasks of the dependent subtasks are divided into a subtask group, wherein the task logic represents the dependency relationship and task order between multiple subtasks; and the parallel subtasks and subtask groups are assigned to multiple processors for processing.

[0077] According to an embodiment of the present invention, among multiple subtasks, there are subtasks that can be executed directly without relying on the subtask results of other subtasks. Such subtasks can be executed in parallel with other subtasks and are therefore treated as parallel subtasks. Subtasks that require the subtask results of other subtasks to complete subsequent execution are treated as dependent subtasks.

[0078] According to an embodiment of the present invention, after a task to be processed is divided into multiple subtasks, the task logic between the multiple subtasks can be determined, and the parallel subtasks and dependent subtasks therein can be determined. The dependent subtasks and their upstream subtasks are grouped into a subtask group so that after the subtask group is assigned to a processor, the processor can obtain the subtask results of the upstream subtasks and execute the dependent subtasks based on the subtask results.

[0079] According to an embodiment of the present invention, since parallel subtasks do not need to depend on other subtasks, and the dependent subtasks have been divided into the same subtask group with their upstream subtasks, after the division of the subtask groups is completed, the subtask groups and parallel subtasks can be executed in parallel, and the parallel subtasks and subtasks can be assigned to multiple processors for processing, so that each processor is used to process one parallel subtask or one subtask group.

[0080] According to an embodiment of the present invention, by dividing dependent subtasks and their upstream tasks into subtask groups and assigning them to the same processor, cross-processor communication overhead is reduced. Combined with the independent allocation of parallel subtasks, the system achieves localized processing of dependencies and maximizes the concurrency of parallel tasks, ensuring the correctness of task logic while fully utilizing the parallel computing resources of multiple processors, thereby optimizing overall task execution efficiency.

[0081] According to an embodiment of the present invention, the method for executing a hybrid heterogeneous computing task further includes: when it is determined that the task type of the subtask is not a preset type, processing the subtask using a target processor to obtain a subtask result.

[0082] According to an embodiment of the present invention, since the controller is relatively better at processing subtasks of the preset type, its processing capability for subtasks of non-preset types is generally weaker than that of the processor. If it is determined that the subtask type is not the preset type, the target processor has higher processing efficiency and accuracy for the subtask. Therefore, the target processor can directly process the subtask and obtain the subtask result.

[0083] According to an embodiment of the present invention, by determining the task type, non-preset subtasks are retained for local execution on the target processor, avoiding unnecessary task migration overhead. This adaptive allocation mechanism enables the system to intelligently select execution paths based on task characteristics, while maintaining flexibility while reducing the communication and scheduling costs associated with heterogeneous collaboration and improving the overall energy efficiency of the system.

[0084] According to an embodiment of the present invention, multiple processors determine the execution results of the task to be executed based on their respective subtask results, including: synchronously sending the subtask results of the multiple processors to the master control processor used to determine the execution results, so that the master control processor can splice the multiple subtask results according to the task logic to obtain the execution results.

[0085] According to an embodiment of the present invention, after receiving multiple subtask results, the master control processor synchronizes and splices the multiple subtask results according to the task logic to obtain the execution result of the task to be executed.

[0086] Taking matrix multiplication as an example, the task to be executed is to calculate the multiplication result of two high-dimensional matrices. Through matrix partitioning, the two high-dimensional matrices are divided into multiple sub-matrices with the same partitioning granularity. Each sub-task represents the multiplication of a sub-matrix in the first high-dimensional matrix with a sub-matrix in the same position in the second high-order matrix. The sub-task result is the product of the two sub-matrices. After obtaining multiple sub-results representing the product of the sub-matrices, the original position of each sub-result in the high-dimensional matrix is ​​determined according to the task logic. The multiple sub-results are then spliced ​​together according to their original positions to obtain the execution result.

[0087] According to the embodiments of the present invention, a master control processor collects all subtask results and combines them according to task logic, achieving unified results integration for distributed computing. This ensures the correct reorganization of complex tasks after decomposition, and leverages the master control processor's coordination capabilities to ensure the integrity and accuracy of the final results.

[0088] Figure 4 A flowchart of a method for executing a hybrid heterogeneous computing task for model training according to an embodiment of the present invention is shown.

[0089] like Figure 4 As shown in Figure 1, the model training process includes steps T0 to T3. During the preprocessing phase, T0, operations such as tensor slicing, mask construction, position encoding, data loading, and normalization are required. During the forward propagation phase, T1, operations such as multi-head attention calculation, residual connection, activation function calculation, attention weight pruning, sparsification, mask decoding, and dynamic clipping judgment are required. During the backward propagation phase, T2, operations such as reverse error calculation, backbone gradient calculation, gradient calculation acceleration, gradient clipping, and parameter sparsification are required. During the gradient aggregation phase, T3, gradient synchronization is required across multiple processors.

[0090] By programming the controller array and setting the preset task type to logic-intensive, when a target processor receives a logic-intensive subtask, the subtask is sent to the first controller, which processes it and obtains a subtask result for the subtask and returns it to the target processor. If the target processor receives a non-logic-intensive task, such as a computationally intensive subtask, the subtask is directly processed by the target processor to obtain a subtask result for the subtask.

[0091] Specifically, Figure 4 As shown in the figure, in the T0 stage, the target processor sends tensor slicing, mask construction, and position encoding operations to the first controller, which is processed by the controller array. In the T1 stage, the target processor sends attention weight pruning, sparsification, mask decoding, and dynamic clipping judgment operations to the first controller, which is processed by the controller array. In the T2 stage, the target processor sends gradient calculation acceleration, gradient clipping, and parameter sparse processing operations to the first controller, which are processed by the controller array. Other operations in each stage can be completed by the target processor itself.

[0092] After the T0~T2 stages, each target processor can obtain the subtask results. In the T3 stage, the gradient synchronization is performed based on the subtask results of multiple processors to obtain the processing results of the tasks to be processed, and the model parameters are further adjusted.

[0093] Another aspect of the present invention provides a device for performing hybrid heterogeneous computing tasks, which will be described below in conjunction with Figure 5 Describe the device.

[0094] Figure 5 A topology diagram of a device for executing hybrid heterogeneous computing tasks according to an embodiment of the present invention is shown.

[0095] like Figure 5 As shown, the device 500 for executing hybrid heterogeneous computing tasks includes a processor array 510 and a controller array 520.

[0096] According to an embodiment of the present invention, the processor array 510 includes multiple processors. Figure 5 Shown in the figure are a first processor 511, a second processor 512, a third processor 513 and a fourth processor 514.

[0097] According to an embodiment of the present invention, the controller array 520 includes multiple controllers, and the multiple controllers are connected in an environment topology form. Figure 5 , controller 521, controller 522, controller 523, and controller 524 are shown. The multiple controllers in the controller array are respectively connected to, and only to, one processor in the processor array, i.e., controller 521 is connected to the first processor 511, controller 522 is connected to the second processor 512, controller 523 is connected to the third processor 513, and controller 524 is connected to the fourth processor 514.

[0098] The multiple processors include a target processor, and the multiple controllers include a first controller. In the process of executing a hybrid heterogeneous computing task, it is necessary to divide the task to be executed into at least one subtask, and assign at least one subtask to the processor for execution. During the execution of each subtask, the processor used to process the subtask is the target processor, and the controller connected to the target processor is the first controller.

[0099] The target processor is used to process subtasks obtained by dividing the tasks to be executed and obtain subtask results. When the task type of the subtask assigned to the target processor is a preset type, the target processor sends the subtask to the first controller.

[0100] The first controller is configured to, in response to receiving a subtask from a target processor connected to the first controller in the controller array, divide the subtask into at least one task step and assign at least one execution step to at least one second controller in the controller array. The plurality of second controllers are configured to process the at least one task step and obtain subtask results for the subtask. The second controller is the controller in the controller array that processes the task step of the subtask. If the first controller is also configured to process the task step, the first controller also serves as the second controller.

[0101] In this embodiment, the fourth processor 514 is a target processor, the controller 524 is a first controller, and the controllers 521 , 522 , and 523 are second controllers.

[0102] Because the first controller receives the subtask, the subtask can be parsed directly using the first controller without additional transmission, thereby reducing communication overhead. The controller array is further configured to control the first controller to parse the subtask and obtain a parsing result, wherein the parsing result includes the task steps and the execution order of the task steps.

[0103] According to an embodiment of the present invention, Figure 5 The topology shown is a minimum device unit for performing hybrid heterogeneous computing tasks. According to the actual task requirements, multiple devices such as Figure 5 The device units shown in the figure divide the processors of each unit into the same processor array for management, and the controller arrays of each device unit are retained separately, so that multiple controller arrays can be used to process multiple tasks in the form of pipelines in parallel.

[0104] According to an embodiment of the present invention, a heterogeneous collaborative architecture combining a processor array and a controller array in a ring topology enables hierarchical management of computing resources. Each controller connects only to one processor, which, combined with the low-latency communication of the ring topology, reduces resource contention and improves data transmission efficiency. A mechanism for offloading predefined subtasks allows the processors to focus on core computing while the controller array handles specific tasks, optimizing overall system performance.

[0105] According to another embodiment of the present invention, the processor array 510 further includes a processor switching unit 515. The processor switching unit is configured to communicate with each of the plurality of processors included in the processor array. Figure 5The figure shows that the processor switching unit 515 is connected to the first processor 511, the second processor 512, the third processor 513, and the fourth processor 514, respectively, and can communicate with the first processor 511, the second processor 512, the third processor 513, and the fourth processor 514, respectively. When communication is required between multiple processors, the processor switching unit 515 can be used as a relay to achieve communication between the multiple processors.

[0106] The processor array is also used to: utilize the task processor for task division in the processor array to divide the dependent subtasks and the upstream subtasks of the dependent subtasks into a subtask group according to the task logic between at least one subtask in the task to be executed, wherein the task logic represents the dependency relationship and task order between multiple subtasks; utilize the task processor to send the division results of parallel subtasks and subtask groups to the processor switching unit; and utilize the processor switching unit to distribute the parallel subtasks and subtask groups to multiple processors for processing.

[0107] The task processor can be any one of the first processor 511, the second processor 512, the third processor 513 and the fourth processor 514. The task processor can be used to divide at least one subtask obtained by dividing the task to be executed, and divide it according to the task logic, so that the dependent subtasks and the upstream subtasks of the dependent subtasks are divided into a subtask group. Since the task processor is also connected to the processor switching unit, the divided subtask group and the undivided parallel subtasks can be sent to the processor switching unit, and the processor switching unit will distribute the parallel subtasks and subtask groups one by one to multiple processors for parallel processing.

[0108] According to an embodiment of the present invention, the processor switching unit centrally manages subtask allocation and combines it with task logic analysis to achieve localized processing of dependent subtasks and the rational distribution of parallel subtasks. This intelligent allocation mechanism reduces cross-processor communication overhead, leverages the parallel processing capabilities of the ring-topology controller array, optimizes load balancing across multiple processors, and improves overall system throughput.

[0109] According to an embodiment of the present invention, the processor array is further configured to: when it is determined that the task type of the subtask is not a preset type, process the subtask using the target processor to obtain a subtask result.

[0110] According to an embodiment of the present invention, the processor array includes a master control processor for determining the execution result; the processor array is also used to: synchronously send the subtask results of multiple processors to the master control processor, so that the master control processor can splice the multiple subtask results according to the task logic to obtain the execution result.

[0111] According to an embodiment of the present invention, the master control processor may be any one of the first processor 511, the second processor 512, the third processor 513 and the fourth processor 514. After the processors corresponding to multiple subtasks obtain the subtask results, the multiple processors may synchronously send their respective subtask results to the master control processor through the processor switching unit 515. The processor switching unit 515 sends the task logic to the master control processor so that the master control processor can splice the multiple subtask results according to the task logic to obtain the execution result.

[0112] According to an embodiment of the present invention, the master control processor achieves unified integration of distributed computing by collecting the results of all subtasks and combining them according to task logic. This centralized result processing model leverages the master control processor's global perspective to ensure the correct reorganization of complex tasks after decomposition. It is particularly suitable for scenarios requiring holistic data analysis and improves the accuracy and reliability of the system in processing large tasks.

[0113] Figure 6 A partial structural diagram of a controller array according to an embodiment of the present invention is shown.

[0114] According to an embodiment of the present invention, the controller array includes four controllers. Figure 6 Only the first controller 610 and the second controller 620 are shown in the figure, and the internal structures of other controllers are the same as those of the first controller 610 and the second controller 620.

[0115] like Figure 6 As shown, each controller includes a scheduling unit and a logic unit. The first controller 610 includes a first scheduling unit 611 and a first logic unit 612, while the second controller 620 includes a second scheduling unit 621 and a second logic unit 622. The first logic unit 612 and the second logic unit 622 are programmed to implement the preset functions of the first and second controllers, respectively. The first scheduling unit 611 can allocate multiple task steps based on the multiple task steps and the preset functions of the multiple second scheduling units.

[0116] Each controller also includes a communication unit. The first controller 610 includes a first communication unit 613, and the second controller 620 includes a second communication unit 623. The communication units include a processor communication component and a controller communication component. The processor communication component enables communication between the controller and its connected processor, while the controller communication component enables communication between the controller and other controllers in the controller array. The controller communication component can be implemented using the Advanced eXtensible Interface (AXI).

[0117] The controller array is also used to: control the first controller, based on the execution order between at least one task step and the preset functions of multiple controllers, use the scheduling unit of the first controller to distribute multiple task steps to multiple second controllers respectively; and use the respective logic units of the multiple second controllers to execute at least one task step in sequence according to the execution order to obtain subtask results.

[0118] According to an embodiment of the present invention, at least one task step includes N steps, where N is an integer greater than 1; the controller array is further used to: use the second controller corresponding to the first task step to execute the first task step to obtain the first step result; in accordance with the execution order, use the second controller corresponding to the nth task step, based on the n-1th step result, execute the nth task step to obtain the nth step result, n=2,…N; wherein the Nth step result is used as the subtask result.

[0119] Before executing the nth task step, the controller communication component of the second controller corresponding to the n-1th task step is used to send the n-1th step result to the second controller corresponding to the nth task step, so that the second controller corresponding to the nth task step uses the n-1th step result to execute the nth task step.

[0120] According to another embodiment of the present invention, at least one task step includes 1; the controller array is also used to: assign the task step to a second controller for executing the task step based on the preset functions of multiple second controllers; and use the second controller for executing the task step to execute the task step to obtain a subtask result.

[0121] According to an embodiment of the present invention, after determining the second controller for executing the task step, the controller communication component of the first controller can be used to distribute the task step to the second controller so that the second controller executes the task step and obtains the subtask result.

[0122] Therefore, the first controller is further configured to: send the subtask result to the first controller using the communication unit of the second controller that obtains the subtask result; and send the subtask result to the target processor using the communication unit of the first controller.

[0123] The first controller 610 can use the scheduling unit 611 to control the second controller 620 that obtains the subtask result, so that after the second controller 620 completes the task steps and obtains the subtask result, it uses the controller communication component in the second communication unit 623 to send the subtask result to the first controller 610. After receiving the subtask result using the controller communication component in the first communication unit 613, the first controller 610 uses the processor communication component in the first communication unit 613 to send the subtask result to the target processor.

[0124] According to an embodiment of the present invention, the controller's communication unit utilizes a ring topology to implement bidirectional transmission of subtask results. Result data is returned from the execution controller to the first controller via the shortest path, and then fed back from the first controller to the target processor. This two-stage transmission mechanism reduces data transmission distance and, combined with the parallel communication capabilities of the ring topology, reduces result feedback latency and improves system response speed.

[0125] Based on the above-mentioned method for executing hybrid heterogeneous computing tasks, the present invention also provides a device for executing hybrid heterogeneous computing tasks. Figure 7 The device is described in detail.

[0126] Figure 7 A structural block diagram of a device for executing hybrid heterogeneous computing tasks according to an embodiment of the present invention is shown.

[0127] like Figure 7 As shown, the execution device 700 of the hybrid heterogeneous computing task of this embodiment includes a task division module 710, a task allocation module 720, a task processing module 730 and a result sending module 740.

[0128] The task division module 710 is configured to, in response to receiving a subtask from a target processor connected to a first controller in the controller array, divide the subtask into at least one task step, wherein the subtask is obtained by dividing the task to be executed. If the task type of the subtask assigned to the target processor is a preset type, the target processor sends the subtask to the first controller. In one embodiment, the task division module 710 can be configured to perform operation S210 described above, and will not be further described here.

[0129] The task assignment module 720 is configured to assign at least one execution step to at least one second controller in the controller array, wherein the controller array includes a plurality of controllers connected in a ring topology. In one embodiment, the task assignment module 720 may be configured to perform operation S220 described above, which will not be further described herein.

[0130] The task processing module 730 is used to use at least one second controller to process at least one task step respectively to obtain a subtask result of the subtask. In one embodiment, the task processing module 730 can be used to perform the operation S230 described above, which will not be repeated here.

[0131] The result sending module 740 is used to send the subtask result to the target processor so that multiple processors can determine the execution result of the task to be executed based on their respective subtask results. In one embodiment, the result sending module 740 can be used to perform the operation S240 described above, which will not be repeated here.

[0132] According to an embodiment of the present invention, the task processing module 730 includes a step allocation submodule and a step execution submodule.

[0133] The step allocation submodule is used to allocate at least one task step to at least one second controller based on the execution order and the preset functions of the plurality of second controllers.

[0134] The step execution submodule is used to use at least one second controller to execute at least one task step in sequence according to the execution order to obtain a subtask result.

[0135] According to an embodiment of the present invention, the step execution submodule includes a first execution unit and a second execution unit.

[0136] The first execution unit is configured to execute the first task step using the second controller corresponding to the first task step to obtain a first step result.

[0137] The second execution unit is used to execute the nth task step in accordance with the execution order, using the second controller corresponding to the nth task step, based on the result of the n-1th step, to obtain the nth step result, n=2,...N; wherein the Nth step result is used as the subtask result.

[0138] According to an embodiment of the present invention, the step execution submodule further includes a step allocation unit and a third execution unit.

[0139] The step allocating unit is used to allocate the task steps to the second controllers for executing the task steps based on the preset functions of the plurality of second controllers.

[0140] The third execution unit is configured to execute the task step using the second controller for executing the task step to obtain a subtask result.

[0141] According to an embodiment of the present invention, the result sending module 740 includes a first sending submodule and a second sending submodule.

[0142] The first sending submodule is used to send the subtask result to the first controller.

[0143] The second sending submodule is used to send the subtask result to the target processor using the first controller.

[0144] According to an embodiment of the present invention, the apparatus 700 for executing hybrid heterogeneous computing tasks further includes a task grouping module and a task group allocating module.

[0145] The task grouping module is used to group dependent subtasks and their upstream subtasks into a subtask group according to the task logic between multiple subtasks in the task to be executed, wherein the task logic represents the dependency relationship and task order between multiple subtasks.

[0146] The task group allocation module is used to allocate parallel subtasks and subtask groups to multiple processors for processing.

[0147] According to an embodiment of the present invention, the apparatus 700 for executing hybrid heterogeneous computing tasks further includes a local processing module.

[0148] The local processing module is used to process the subtask using the target processor to obtain a subtask result when it is determined that the task type of the subtask is not a preset type.

[0149] According to an embodiment of the present invention, any multiple modules among the task division module 710, the task allocation module 720, the task processing module 730, and the result sending module 740 can be combined into a single module, or any one of these modules can be split into multiple modules. Alternatively, at least part of the functionality of one or more of these modules can be combined with at least part of the functionality of other modules and implemented in a single module. According to an embodiment of the present invention, multiple modules among the task division module 710, the task allocation module 720, the task processing module 730, and the result sending module 740 can be at least partially implemented as hardware circuits, such as a field programmable gate array (FPGA), a programmable logic array (PLA), a system on a chip, a system on a substrate, a system on a package, an application specific integrated circuit (ASIC), or can be implemented in hardware or firmware by any other reasonable method of integrating or packaging circuits, or can be implemented in any one of the three implementation methods of software, hardware, and firmware, or in any appropriate combination of any of these. Alternatively, multiple of the task division module 710 , the task allocation module 720 , the task processing module 730 and the result sending module 740 may be at least partially implemented as computer program modules, which may perform corresponding functions when executed.

[0150] Figure 8 A block diagram of an electronic device suitable for implementing a method for executing hybrid heterogeneous computing tasks according to an embodiment of the present invention is shown.

[0151] like Figure 8As shown, an electronic device 800 according to an embodiment of the present invention includes a processor 801, which can perform various appropriate actions and processes based on programs stored in a read-only memory (ROM) 802 or programs loaded from a storage unit 808 into a random access memory (RAM) 803. The processor 801 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor and / or related chipsets and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 801 may also include onboard memory for caching purposes. The processor 801 may include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of the present invention.

[0152] Various programs and data required for the operation of the electronic device 800 are stored in the RAM 803. The processor 801, ROM 802, and RAM 803 are connected to each other via a bus 804. The processor 801 executes the programs in the ROM 802 and / or RAM 803 to perform various operations according to the method flow of the embodiment of the present invention. It should be noted that the programs may also be stored in one or more memories other than the ROM 802 and RAM 803. The processor 801 may also execute the programs stored in the one or more memories to perform various operations according to the method flow of the embodiment of the present invention.

[0153] According to an embodiment of the present invention, electronic device 800 may further include an input / output (I / O) interface 805, which is also connected to bus 804. Electronic device 800 may also include one or more of the following components connected to I / O interface 805: an input section 806 including a keyboard, mouse, etc.; an output section 807 including devices such as a cathode ray tube (CRT), liquid crystal display (LCD), and speakers; a storage section 808 including a hard disk; and a communication section 809 including a network interface card such as a LAN card or modem. Communication section 809 performs communication processing via a network such as the Internet. A drive 810 is also connected to I / O interface 805 as needed. Removable media 811, such as a magnetic disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed in drive 810 as needed, so that computer programs read from the removable media can be installed into storage section 808 as needed.

[0154] The present invention also provides a computer-readable storage medium, which may be included in the device / apparatus / system described in the above embodiments, or may exist independently and not incorporated into the device / apparatus / system. The computer-readable storage medium carries one or more programs, which, when executed, implement the method according to the embodiments of the present invention.

[0155] According to an embodiment of the present invention, a computer-readable storage medium may be a non-volatile computer-readable storage medium, and may include, for example, but not limited to: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In the present invention, a computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. For example, according to an embodiment of the present invention, a computer-readable storage medium may include the ROM 802 and / or RAM 803 described above, and / or one or more memories other than ROM 802 and RAM 803.

[0156] The embodiments of the present invention further include a computer program product, which includes a computer program containing program code for executing the method shown in the flowchart. When the computer program product is run in a computer system, the program code is used to cause the computer system to implement the method provided by the embodiments of the present invention.

[0157] The computer program executes the above functions defined in the system / device of the embodiment of the present invention when executed by the processor 801. According to the embodiment of the present invention, the system, device, module, unit, etc. described above can be implemented by a computer program module.

[0158] In one embodiment, the computer program may be stored on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may be transmitted and distributed in the form of a signal on a network medium, downloaded and installed via the communication portion 809, and / or installed from a removable medium 811. The program code contained in the computer program may be transmitted using any appropriate network medium, including but not limited to wireless, wired, or any suitable combination thereof.

[0159] In such an embodiment, the computer program can be downloaded and installed from a network via the communication section 809 and / or installed from a removable medium 811. When the computer program is executed by the processor 801, the above-described functions defined in the system of the embodiment of the present invention are performed. According to the embodiment of the present invention, the systems, devices, means, modules, units, etc. described above can be implemented by computer program modules.

[0160] According to an embodiment of the present invention, the program code for executing the computer program provided by the embodiment of the present invention can be written in any combination of one or more programming languages. Specifically, these computer programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages ​​include, but are not limited to, languages ​​such as Java, C++, Python, "C" or similar programming languages. The program code can be executed entirely on the user computing device, partially on the user device, partially on a remote computing device, or entirely on a remote computing device or server. In the case of a remote computing device, the remote computing device can be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computing device (for example, using an Internet service provider to connect via the Internet).

[0161] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or a part of code, and the above-mentioned module, program segment, or a part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0162] It will be understood by those skilled in the art that the features described in the various embodiments of the present invention may be combined and / or coupled in various ways, even if such combinations or couplings are not explicitly described in the present invention. In particular, the features described in the various embodiments of the present invention may be combined and / or coupled in various ways without departing from the spirit and teachings of the present invention. All such combinations and / or couplings fall within the scope of the present invention.

[0163] The above describes embodiments of the present invention. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present invention. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be advantageously used in combination. Without departing from the scope of the present invention, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. A method for executing a hybrid heterogeneous computing task, characterized in that: The method comprises: In response to receiving a subtask from a target processor connected to a first controller in a controller array, the first controller divides the subtask into at least one task step, wherein the subtask is obtained by dividing the task to be executed, and if the task type of the subtask assigned to the target processor is a preset type, the target processor sends the subtask to the first controller; Assigning the at least one task step to at least one second controller in the controller array so that the task step corresponds to the second controller in a one-to-one manner, wherein the correspondence between the task step and the second controller is determined according to the task step and a preset function of the second controller, wherein the preset function is implemented by programming the second controller, wherein the controller array includes a plurality of controllers connected in a ring topology, and each of the plurality of controllers is connected to only one processor; Using the at least one second controller, processing the at least one task step separately in a pipeline form to obtain a subtask result of the subtask; Sending the subtask results to the target processor, so as to synchronously send the subtask results of the multiple processors to the master control processor for determining the execution result, so that the master control processor can splice the multiple subtask results according to the task logic to obtain the execution result; The step of dividing the subtask into at least one task step includes: The subtask is parsed to obtain a parsing result, wherein the parsing result includes task steps and an execution order between the task steps.

2. The method according to claim 1, characterized in that The utilizing the at least one second controller to process the at least one task step separately to obtain a subtask result of the subtask includes: Based on the execution order and the preset function of the at least one second controller, respectively allocating the at least one task step to the at least one second controller; and Utilizing the at least one second controller, the at least one task step is sequentially executed in the execution order to obtain the subtask result.

3. The method according to claim 2, characterized in that The at least one task step includes N steps, where N is an integer greater than 1; The using the at least one second controller to sequentially execute the at least one task step in the execution order to obtain the subtask result includes: Utilizing the second controller corresponding to the first task step to execute the first task step, and obtaining a result of the first step; According to the execution order, using the second controller corresponding to the nth task step, based on the result of the n-1th step, execute the nth task step to obtain the result of the nth step, where n=2, ...N; The result of step N is used as the subtask result.

4. The method according to claim 1, wherein The at least one task step includes 1; The utilizing the at least one second controller to process the at least one task step separately to obtain a subtask result of the subtask includes: Allocating the task step to a second controller for executing the task step based on a preset function of at least one second controller; and The second controller for executing the task step is used to execute the task step to obtain the subtask result.

5. The method according to claim 1, wherein The sending of the subtask result to the target processor includes: sending the subtask result to the first controller; and The subtask result is sent to the target processor using the first controller.

6. The method according to claim 1, wherein At least one subtask includes a parallel subtask that can be processed in parallel and a dependent subtask that needs to be executed based on the execution results of other subtasks; After the task to be executed is divided into the at least one subtask, the at least one subtask is respectively assigned to a processor for processing in the following manner: According to the task logic between the multiple subtasks in the task to be executed, the dependent subtask and the upstream subtask of the dependent subtask are divided into a subtask group, wherein the task logic represents the dependency relationship and task order between the multiple subtasks; and The parallel subtasks and the subtask groups are distributed to a plurality of the processors for processing.

7. The method according to claim 6, characterized in that The method further comprises: When it is determined that the task type of the subtask is not the preset type, the subtask is processed by the target processor to obtain a subtask result.

8. The method according to claim 7, characterized in that The multiple processors determine the execution results of the to-be-executed tasks according to the results of their respective subtasks, including: The subtask results of each of the multiple processors are synchronously sent to a master control processor for determining the execution result, so that the master control processor splices the multiple subtask results according to the task logic to obtain the execution result.

9. A device for performing hybrid heterogeneous computing tasks, characterized in that: The device comprises: A processor array, wherein the processor array includes a plurality of processors, wherein the plurality of processors includes a target processor, wherein the target processor is used to process subtasks obtained by dividing the task to be executed and obtain subtask results, so that the master control processor can splice the plurality of subtask results according to the task logic to obtain an execution result; A controller array, wherein the controller array comprises a plurality of controllers connected in a ring topology, and the plurality of controllers in the controller array are respectively connected to and only to one processor in the processor array; a first controller among the plurality of controllers, configured to, in response to receiving a subtask from a target processor connected to the first controller in the controller array, divide the subtask into at least one task step, and assign the at least one task step to at least one second controller in the controller array, so that the task step corresponds to the second controller in a one-to-one manner, wherein the correspondence between the task step and the second controller is determined based on the task step and a preset function of the second controller, wherein the preset function is implemented by programming the second controller; The plurality of second controllers are used to process the at least one task step respectively in a pipeline form to obtain subtask results of the subtask; Wherein, when the task type of the subtask assigned to the target processor is a preset type, the target processor sends the subtask to the first controller; Wherein, the controller array is further used for: The first controller is controlled to parse the subtask to obtain a parsing result, wherein the parsing result includes task steps and an execution order of the task steps.

10. The device according to claim 9, characterized in that The controller includes a scheduling unit and a logic unit, wherein the logic unit is programmed to implement the preset functions of the controller; The controller array is further configured to: controlling the first controller to allocate the plurality of task steps to the plurality of second controllers respectively using a scheduling unit of the first controller based on an execution order of at least one task step and preset functions of the plurality of controllers; and Utilizing the respective logic units of the plurality of second controllers, the at least one task step is sequentially executed in the execution order to obtain the subtask result.

11. The device according to claim 10, characterized in that The at least one task step includes N steps, where N is an integer greater than 1; The controller array is further configured to: Utilizing the second controller corresponding to the first task step to execute the first task step, and obtaining a result of the first step; According to the execution order, using the second controller corresponding to the nth task step, based on the result of the n-1th step, execute the nth task step to obtain the result of the nth step, where n=2, ...N; The result of step N is used as the subtask result.

12. The device according to claim 9, characterized in that The at least one task step includes 1; The controller array is further configured to: Allocating the task steps to the second controllers for executing the task steps based on the preset functions of the plurality of second controllers; and The second controller for executing the task step is used to execute the task step to obtain the subtask result.

13. The device according to claim 9, characterized in that The controller further includes a communication unit; The first controller is further configured to: using a communication unit of the second controller that obtains the subtask result to send the subtask result to the first controller; and The subtask result is sent to the target processor using the communication unit of the first controller.

14. The device according to claim 9, characterized in that The processor array further includes a processor switching unit, wherein the processor switching unit is configured to communicate with each of the plurality of processors included in the processor array; At least one subtask includes a parallel subtask that can be processed in parallel and a dependent subtask that needs to be executed based on the execution results of other subtasks; The processor array is further configured to: Using a task processor for task division in the processor array, the dependent subtask and its upstream subtask are divided into a subtask group according to a task logic between at least one subtask in the task to be executed, wherein the task logic represents the dependency relationship and task order between the plurality of subtasks; Using the task processor, sending the division results of the parallel subtasks and the subtask groups to the processor switching unit; and The processor switching unit is used to distribute the parallel subtasks and the subtask groups to the multiple processors for processing.

15. The device according to claim 14, characterized in that The processor array is further configured to: When it is determined that the task type of the subtask is not the preset type, the subtask is processed by the target processor to obtain the subtask result.

16. The device according to claim 15, characterized in that The processor array includes a master control processor for determining the execution result; The processor array is further configured to: The subtask results of each of the multiple processors are synchronously sent to the master control processor, so that the master control processor can splice the multiple subtask results according to the task logic to obtain the execution result.

17. An electronic device comprising: one or more processors; a memory for storing one or more computer programs, It is characterized in that the one or more processors execute the one or more computer programs to implement the steps of the method according to any one of claims 1 to 8.

18. A computer-readable storage medium having a computer program or instruction stored thereon, characterized in that: When the computer program or instruction is executed by a processor, the steps of the method according to any one of claims 1 to 8 are implemented.

19. A computer program product comprising a computer program or instructions, characterized in that When the computer program or instruction is executed by a processor, the steps of the method according to any one of claims 1 to 8 are implemented.

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