FPGA prototype verification method of supercomputing ASIC chip and related equipment

Abstract

The invention discloses a field programmable gate array (FPGA) prototype verification method for super-computing application specific integrated circuit (ASIC) chips and related equipment. The method comprises the following steps of: configuring position parameters and corresponding computing parameters for each super-computing ASIC chip in a super-computing system through a master control personal computer (PC); the main control PC issues corresponding data of the current simulation chip to at least one FPGA based on the position parameters, so that the FPGA simulates the calculation function of the corresponding super-calculation ASIC chip, and a calculation result is transmitted back to the main control PC; the simulation steps are repeated, and the position parameters are iteratively updated each time to switch the simulated chip instances until all the super-computing ASIC chips in the super-computing system are covered, so that system-level function verification is completed, the working process of the multiple super-computing ASIC chips can be simulated by multiplexing the same FPGA and adopting a multi-time iterative computation mode, and the system-level function verification is completed. The verification work amount is reduced, and the hardware cost input is reduced.

Description

Technical Field

[0001] The present invention relates to the field of chip verification technology, and in particular to an FPGA prototype verification method for a supercomputing ASIC chip and related equipment. Background Art

[0002] To meet computing power requirements, in actual product applications, multiple ASIC chips are often used for parallel computing to jointly complete the computing tasks required by the system. Array-type supercomputing ASIC chips are a typical application model. Its working principle is that each ASIC chip in the system completes part of the system's algorithm calculation by setting internal registers or parameters; after each ASIC chip completes its own calculation, the system's main controller merges the calculation results to achieve the calculation required by the system.

[0003] However, array-type supercomputing ASIC chip systems usually require multiple identical ASIC chips as computing units. In a supercomputing system, dozens or even hundreds of them are often required. Such a large number of ASIC chip systems face many problems in verification before chip tape-out. Before mass production of traditional supercomputing ASIC chips, a single ASIC chip is generally functionally verified first, and then MPW small-batch tape-out is used multiple times. MPW small-batch tape-out can truly verify the functionality of supercomputing ASIC chips in the system, but this method has obvious disadvantages. It is not only time-consuming but also costly.

[0004] Therefore, how to efficiently and cost-effectively perform system-level functional verification on array-type supercomputing ASIC chips before tape-out has become an urgent problem to be solved. Traditional methods cannot meet current needs due to cost and time constraints. Summary of the Invention

[0005] The embodiments of the present invention provide an FPGA prototype verification method and related equipment for a supercomputing ASIC chip. By reusing the same FPGA and adopting multiple iterative calculations, the working processes of multiple supercomputing ASIC chips can be simulated, thereby reducing the verification engineering workload and lowering the hardware cost investment.

[0006] In a first aspect, an FPGA prototype verification method for a supercomputer ASIC chip provided by an embodiment of the present invention includes: configuring position parameters and corresponding calculation parameters for each supercomputer ASIC chip in a supercomputer system through a master control PC; the master control PC based on the position parameters, sending the serial number of the currently simulated chip, calculation parameters, and original data to at least one FPGA, where the serial number is bound to the position parameter; the FPGA simulates the calculation function of the corresponding supercomputer ASIC chip according to the received serial number, calculation parameters, and original data, and sends the calculation result back to the master control PC; repeating the above simulation steps, and each time iteratively updating the position parameter to switch the simulated chip instance until all supercomputer ASIC chips in the supercomputer system are covered; the master control PC sorts and splices the calculation results of multiple iterations according to the position parameters to generate a target calculation result of the supercomputer system, so as to complete the system-level function verification.

[0007] In some embodiments, the number of FPGAs is one or two, and the chip function is simulated in the following manner: when using one FPGA, the calculation processes of all supercomputer ASIC chips are serially simulated by updating the position parameters; when using two FPGAs, the collaborative calculation process of two chips is simulated by parallelly configuring different position parameters.

[0008] In some embodiments, when using two FPGAs, it further includes: the master control PC randomly sets the position parameters of the two FPGAs to simulate a data loss or disconnection scenario, and during the parallel calculation process, the data transmission timing of the two FPGAs is monitored in real time to obtain the calculation results for verifying the data synchronization and fault tolerance mechanism between chips.

[0009] In some embodiments, the supercomputer system is composed of multiple subsystems, each subsystem includes a main controller, a secondary main controller, and multiple supercomputer ASIC chips, and the position parameters include: the identifier of the subsystem to which the chip belongs; the logical serial number of the chip within the subsystem.

[0010] In some embodiments, the master control PC sorts and splices the calculation results of multiple iterations according to the position parameters to generate a target calculation result of the supercomputer system, including: the master control PC hierarchically sorts the calculation results of multiple iterations according to the subsystem identifier and logical serial number in the position parameters; the sorted multiple calculation results are spliced according to a preset splicing rule to generate a target calculation result.

[0011] Second aspect, an FPGA prototype verification system for a supercomputer ASIC chip is provided in an embodiment of the present invention. The FPGA prototype verification system is used to execute the FPGA prototype verification method described in any one of the first aspects. The FPGA prototype verification system includes: a master control PC, configured to configure position parameters, issue calculation tasks, and merge calculation results according to the position parameters; at least one FPGA, connected to the master control PC, configured to simulate the functions of the supercomputer ASIC chip.

[0012] In some embodiments, when two FPGAs are included, the FPGA prototype verification system further includes: a data synchronization module, configured to verify the data transmission consistency between the two FPGA simulation chips; an exception injection module, triggering data exceptions by modifying the position parameters to test the fault tolerance of the system.

[0013] In some embodiments, the FPGA is a general-purpose FPGA, supporting switching the simulated chip instances by reconfiguring the position parameters.

[0014] In some embodiments, the merging rules of the master control PC include: grouping data according to the subsystem levels in the position parameters; splicing the data within the group according to the logical sequence numbers.

[0015] Third aspect, a computer-readable storage medium is provided in an embodiment of the present invention, storing a computer program, which when executed by a processor, implements the FPGA prototype verification method for a supercomputer ASIC chip described in any one of the first aspects.

[0016] An embodiment of the present invention includes an FPGA prototype verification method and related devices for a supercomputer ASIC chip. The method includes: configuring position parameters and corresponding calculation parameters for each supercomputer ASIC chip in the supercomputer system through a master control PC; the master control PC, based on the position parameters, sends the serial number, calculation parameters, and original data of the currently simulated chip to at least one FPGA, where the serial number is bound to the position parameter; the FPGA simulates the calculation function of the corresponding supercomputer ASIC chip according to the received serial number, calculation parameters, and original data, and sends the calculation result back to the master control PC; repeating the above simulation steps, and updating the position parameters iteratively each time to switch the simulated chip instance until all supercomputer ASIC chips in the supercomputer system are covered; the master control PC sorts and splices the calculation results of multiple iterations according to the position parameters to generate the target calculation result of the supercomputer system, so as to complete the system-level function verification. It can be understood that the present invention uses a general FPGA to simulate the functions implemented by a supercomputer ASIC chip. Compared with the traditional prototype verification method, such as using 1536 FPGAs to establish a supercomputer system for verification, the hardware cost is effectively reduced. Only a very small amount of FPGA hardware resources are required to achieve the function verification of a system composed of a large number of supercomputer ASIC chips, which can save a large amount of hardware procurement and development costs for enterprises. In addition, by reusing the same FPGA and adopting the method of multiple iterative calculations to simulate the working processes of multiple supercomputer ASIC chips, the amount of hardware construction and configuration work can be effectively reduced, and before the supercomputer ASIC chip is taped out, the functions and performance of the system implemented by the supercomputer ASIC chip can be fully verified. Furthermore, potential problems in the system can be discovered in advance, the chip functions and performance can be improved, so as to increase the probability of successful first-time tape-out of the supercomputer ASIC chip, avoid tape-out failures caused by functional design defects, save time and a large amount of tape-out costs, and effectively improve the R & D efficiency.

[0017] Other features and advantages of the present invention will be described in the following specification. Moreover, the objectives and other advantages of the present invention can be realized and obtained through the structures specifically pointed out in the specification, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings are used to provide a further understanding of the technical solutions of the present invention, and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the technical solutions of the present invention, and do not constitute a limitation to the technical solutions of the present invention.

[0019] Figure 1 is a flowchart of the steps of the FPGA prototype verification method for a supercomputer ASIC chip provided by an embodiment of the present invention;

[0020] Figure 2It is a schematic diagram of the system structure of a supercomputer ASIC chip in the FPGA prototype verification method of a supercomputer ASIC chip provided by an embodiment of the present invention;

[0021] Figure 3 It is a schematic diagram of the subsystem structure of a supercomputer ASIC chip in the FPGA prototype verification method of a supercomputer ASIC chip provided by an embodiment of the present invention;

[0022] Figure 4 It is a schematic diagram of single FPGA prototype verification in the FPGA prototype verification system of a supercomputer ASIC chip provided by an embodiment of the present invention;

[0023] Figure 5 It is a schematic diagram of dual FPGA prototype verification in the FPGA prototype verification system of a supercomputer ASIC chip provided by an embodiment of the present invention;

[0024] Figure 6 It is a schematic diagram of an example process in the FPGA prototype verification method of a supercomputer ASIC chip provided by an embodiment of the present invention. Detailed implementation manners

[0025] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0026] It should be noted that although functional module division is performed in the system schematic diagram and the logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order from the module division in the system or the order in the flowchart. Terms such as "first", "second", etc. in the specification, claims and the above-mentioned drawings are used to distinguish similar objects and do not necessarily need to describe a specific order or sequence.

[0027] Currently, to meet the computing power requirements, in actual product applications, multiple ASIC chips are often used for parallel computing to jointly complete the computing tasks required by the system. The array-type supercomputer ASIC chip is a typical application mode among them. Its working principle is that each ASIC chip in the system completes a part of the algorithm calculation of the system by setting internal registers or parameters. After each ASIC chip completes its respective calculation, the main controller of the system merges the calculation results to achieve the required operation of the system. However, the array-type supercomputer ASIC chip system usually requires multiple identical ASIC chips as computing units. In a supercomputer system, dozens or even hundreds are often needed. For such a large number of ASIC chip systems, there are many problems in the verification before chip tape-out. Before mass production tape-out of traditional supercomputer ASIC chips, generally, the function of a single ASIC chip is verified first, and then MPW small-batch tape-out is carried out multiple times. Through MPW small-batch tape-out, the function of the supercomputer ASIC chip in the system can be verified truly, but this method has obvious disadvantages. It not only has a long time cycle but also is costly.

[0028] Therefore, how to efficiently and low-costly perform system-level function verification on array-type supercomputer ASIC chips before tape-out has become an urgent problem to be solved. Due to cost and time limitations, traditional methods cannot meet the current requirements.

[0029] Based on this, the embodiments of the present invention provide an FPGA prototype verification method for supercomputer ASIC chips and related devices, which can simulate the working process of multiple supercomputer ASIC chips by reusing the same FPGA and adopting the method of multiple iterative calculations, so as to reduce the verification workload and reduce the investment in hardware costs.

[0030] Next, the embodiments of the present invention will be further described with reference to the accompanying drawings of the specification.

[0031] Refer to Figure 1 , Figure 1 which is a flowchart of the steps of an FPGA prototype verification method for supercomputer ASIC chips provided by an embodiment of the present invention. In a first aspect, the embodiments of the present invention provide an FPGA prototype verification method for supercomputer ASIC chips, which at least includes the following steps:

[0032] Step S110, configure position parameters and corresponding calculation parameters for each supercomputer ASIC chip in the supercomputer system through the master control PC;

[0033] Step S120, based on the position parameters, the master control PC sends the serial number, calculation parameters, and original data of the currently simulated chip to at least one FPGA, where the serial number is bound to the position parameters;

[0034] Step S130: The FPGA simulates the computing function of the corresponding supercomputer ASIC chip according to the received serial number, calculation parameters, and original data, and transmits the calculation result back to the main control PC.

[0035] Step S140: Repeat the above simulation steps, and update the position parameters iteratively each time to switch the simulated chip instance until all the supercomputer ASIC chips in the supercomputer system are covered.

[0036] Step S150: The main control PC sorts and splices the calculation results of multiple iterations according to the position parameters to generate the target calculation result of the supercomputer system, so as to complete the system-level function verification.

[0037] It can be understood that the present invention uses a general FPGA to simulate the functions implemented by supercomputer ASIC chips. Compared with the traditional prototype verification method, such as using 1536 FPGAs to build a supercomputer system for verification, it effectively reduces the hardware cost. Only a very small amount of FPGA hardware resources are required to achieve the function verification of a system composed of a large number of supercomputer ASIC chips, which can save a large amount of hardware procurement and development costs for enterprises. In addition, by reusing the same FPGA and adopting the method of multiple iterative calculations to simulate the working processes of multiple supercomputer ASIC chips, the amount of work for hardware construction and configuration can be effectively reduced, and before the supercomputer ASIC chip is taped out, the functions and performances of the system implemented by the supercomputer ASIC chip can be fully verified, so that possible problems in the system can be discovered in advance, the chip functions and performances can be improved, the probability of successful first-time tape-out of the supercomputer ASIC chip can be increased, the tape-out failure caused by functional design defects can be avoided, time and a large amount of tape-out costs can be saved, and the R & D efficiency can be effectively improved.

[0038] In some embodiments, the position parameter is used to uniquely identify the physical or logical position of the chip in the system; the chip serial number, as the unique identifier of each supercomputer ASIC chip in the entire verification system, can accurately locate the specific supercomputer ASIC chip to be simulated, enabling the main control PC and the FPGA to clearly identify the current simulation object; the calculation parameters specify in detail the behavior patterns and rules that the supercomputer ASIC chip should follow during the simulation calculation process, including but not limited to numerous operation setting information, such as determining what specific operation the chip performs, whether it is a simple addition, multiplication, or complex convolution operation, matrix operation, etc. The selection of these operation types directly determines the nature and purpose of the chip calculation; the original data is the initial material and source for the supercomputer ASIC chip to perform calculation processing. In an actual supercomputer system, this data may come from different sources such as the measurement results of scientific experiments, samples in big data analysis, and pixel information in image and video processing.

[0039] In some embodiments, the supercomputer system targeted by this embodiment consists of multiple subsystems. Each subsystem includes a main controller, a secondary main controller, and multiple supercomputer ASIC chips. Each supercomputer ASIC chip has specific functions and computing capabilities, and they cooperate together to meet the overall computing power requirements of the supercomputer system. Among them, the main control PC is connected to the supercomputer system through a high-speed network to ensure fast and stable data transmission. At least one FPGA is connected to the main control PC. The FPGA used in this embodiment is a general-purpose FPGA, which can meet the needs of simulating the functions of different supercomputer ASIC chips. At the same time, the system is equipped with necessary storage devices to store information such as raw data, calculation parameters, and intermediate calculation results.

[0040] In some embodiments, corresponding to step S110, the main control PC assigns the subsystem number to which each supercomputer ASIC chip belongs and its logical serial number within the subsystem as position parameters according to the topology of the supercomputer system and the layout of each ASIC chip. For example, if the supercomputer system has 8 subsystems numbered from 0 to 7, and there are 16 supercomputer ASIC chips in each subsystem with logical serial numbers from 0 to 15. Then, the position parameters of a chip may be expressed as (3, 7), indicating that the chip is located at the 7th position in the 3rd subsystem.

[0041] It can be understood that according to the specific calculation tasks to be completed by the supercomputer system and the division of labor of each supercomputer ASIC chip, the main control PC configures corresponding calculation parameters for each ASIC chip. The calculation parameters may include settings such as data operation types (such as addition, multiplication, convolution operations, etc.), data precision requirements, and the number of operation iterations. These parameters are precisely configured to ensure that each supercomputer ASIC chip performs correct operation processing in subsequent simulation calculations.

[0042] In some embodiments, corresponding to step S120: The main control PC decides to send data to one or two FPGAs according to the system settings or current verification requirements. When only one FPGA is needed for verification, all simulation data is sent to this FPGA. When using two FPGAs, the main control PC reasonably distributes the data to the two FPGAs according to the chip serial numbers. For example, the data related to the chips with odd serial numbers is sent to FPGA1, and the data of the chips with even serial numbers is sent to FPGA2.

[0043] It can be understood that the master PC assigns a unique serial number to each supercomputer ASIC chip to be simulated and binds this serial number to the previously configured position parameters. For example, the chip with the position parameter (3, 7) may be assigned the serial number 55. Then, the serial number, the corresponding calculation parameters, and the original data for calculation are packed in a specific data format and sent to the corresponding FPGA through a high-speed network interface. The data format design ensures integrity and accuracy during transmission. For example, byte alignment and verification means are used to ensure the data is correct.

[0044] In some embodiments, corresponding to step S130: After receiving the data, the FPGA first parses the data, determines the supercomputer ASIC chip to be simulated according to the serial number, and then calls the built-in algorithm module according to the calculation parameters to simulate the calculation function of the supercomputer ASIC chip. For example, if the calculation parameters indicate that the chip is to perform a matrix multiplication operation, the FPGA uses its own logic units to construct a corresponding matrix multiplication operation circuit to perform calculation processing on the received original data.

[0045] Furthermore, after completing the corresponding calculation task, the FPGA can format and organize the calculation results. The formatted calculation results include the serial number, the calculation result value, and some auxiliary information, such as whether there is an abnormal flag bit in the calculation, etc. Then, through the interface connected to the master PC, these calculation results are sent back to the master PC to ensure the accuracy and integrity of the data during the entire transmission process.

[0046] In some embodiments, corresponding to step S140: The master PC is internally provided with a counter and a logic control module. Each time the simulation process from step S110 to step S130 is completed, the counter is incremented by 1, and the logic control module checks the comparison between the value of the counter and the total number of supercomputer ASIC chips in the supercomputer system.

[0047] It can be understood that at the beginning of each iteration, the master PC updates the position parameters according to a pre-set update rule. For example, the subsystem number and the logical serial number can be incremented or decremented in sequence to switch the simulated chip instance. If the previously simulated chip is at the position (3, 7), the next time it may switch to the chip at the position (3, 8). If the number of chips in the subsystem exceeds the limit, it switches to the starting numbered chip of the next subsystem, and so on in a loop until all supercomputer ASIC chips are covered.

[0048] In some embodiments, when using two FPGAs, when the master PC updates the position parameters in each iteration, it synchronously coordinates the work of the two FPGAs, updates the allocation rules, and accurately sends the new serial number, calculation parameters, and original data to their respective corresponding FPGAs to ensure that the chip instances simulated by the two FPGAs perform calculations in parallel and accurately according to the updated parameters.

[0049] In some embodiments, corresponding to step S150: after the master PC receives the calculation results returned from the FPGA, it sorts them according to the position parameters carried in each calculation result according to a preset sorting rule. The sorting rule can be sorting from the smallest subsystem number to the largest, and then sorting from the smallest logical sequence number within the same subsystem; it can also be sorting according to the physical position of the chip corresponding to the calculation result in the supercomputer system, which depends on the requirements of the supercomputer system design for the final result processing.

[0050] It can be understood that the master PC splices the sorted calculation results according to a specific splicing rule. The splicing method is determined according to the data format and length of the output result of the supercomputer system. For example, for numerical data, the calculation results of each chip may be concatenated in sequence; for image or matrix data, they may be merged and reconstructed according to the corresponding positions, etc. After splicing, the target calculation result of the supercomputer system is obtained. Further, the master PC can compare the generated target calculation result with the preset standard result to determine whether they are consistent. If they are consistent, it means that the supercomputer ASIC chip has passed the system-level function verification in this FPGA prototype verification environment; if they are not consistent, further analyze and troubleshoot the problem to ensure the correctness and feasibility of the supercomputer system design.

[0051] Reference Figure 2 , Figure 2 FIG. is a schematic diagram of the system structure of the supercomputer ASIC chip in the FPGA prototype verification method of the supercomputer ASIC chip provided by an embodiment of the present invention; in some embodiments, the supercomputer system is composed of multiple subsystems, and each subsystem includes a main controller, a secondary main controller, and multiple supercomputer ASIC chips. The position parameters include: the identifier of the subsystem to which the chip belongs; the logical sequence number of the chip within the subsystem; wherein, in Figure 2 FIG. shows a typical application system architecture of the supercomputer ASIC chip to be verified in the present invention in actual application. The system is composed of 0 to 32 subsystems, and the specific composition structure of each subsystem is as shown in Figure 3 shown.

[0052] Reference Figure 3 , Figure 3 FIG. is a schematic diagram of the subsystem structure of the supercomputer ASIC chip in the FPGA prototype verification method of the supercomputer ASIC chip provided by an embodiment of the present invention; from Figure 3It can be clearly seen that a subsystem consists of a main controller, four secondary main controllers, and multiple supercomputer ASIC chips. Specifically, each secondary main controller mounts 12 supercomputer ASIC chips. During the actual operation of the system, each supercomputer ASIC chip is responsible for completing a part of the system's computing functions, and then the computing results of all supercomputer ASIC chips are summarized and integrated via the secondary main controllers and the main controller.

[0053] From this, it can be known that the number of supercomputer ASIC chips required for each computing subsystem is: 4 × 12 = 48 (pieces). And a typical supercomputer system consists of 32 such subsystems. Therefore, the total number of supercomputer ASIC chips required for a typical supercomputer system is: 48 × 32 = 1536 (pieces).

[0054] It can be understood that if the prototype verification method of traditional chips is adopted, a supercomputer system built with 1536 FPGAs needs to be built for verification, which will bring huge cost investment and extremely large engineering volume. To effectively solve this problem and achieve the goal of verifying the system function at the same time, the present invention simulates and realizes the supercomputer system originally built with 1536 FPGAs by means of a serial prototype of one FPGA or two FPGAs, and then verifies the functions of the supercomputer ASIC chips. Among them, the system block diagrams of the serial prototype of one FPGA or two FPGAs are respectively as Figure 4 and Figure 5 shown.

[0055] Refer to Figure 4 and Figure 5 , Figure 4 is a schematic diagram of single-FPGA prototype verification in the FPGA prototype verification system of the supercomputer ASIC chip provided by an embodiment of the present invention; Figure 5 is a schematic diagram of dual-FPGA prototype verification in the FPGA prototype verification system of the supercomputer ASIC chip provided by an embodiment of the present invention; In some embodiments, the number of FPGAs is one or two, and the chip functions are simulated in the following manner: when using one FPGA, the computing processes of all supercomputer ASIC chips are serially simulated by updating the position parameters; when using two FPGAs, the collaborative computing processes of two chips are simulated by parallelly configuring different position parameters.

[0056] In some embodiments, when using two FPGAs, it further includes: the main control PC randomly sets the position parameters of the two FPGAs to simulate data loss or disconnection scenarios, and during the parallel computing process, the data transmission timings of the two FPGAs are monitored in real time to obtain the calculation results for verifying the data synchronization and fault tolerance mechanism between the chips.

[0057] In some embodiments, as Figure 4As shown in the figure, when the number of FPGAs is one, the supercomputer system simulated by this single FPGA mainly consists of a PC, a main controller, and a supercomputer ASIC chip simulated by the FPGA; it can be understood that when conducting system-level prototype verification, the PC will first send the serial number of the supercomputer ASIC chip to be simulated by the current FPGA in the system, and at the same time provide the calculation parameters corresponding to this serial number; subsequently, the PC will send the raw data to be calculated corresponding to this serial number; based on this, the ASIC chip currently simulated by the FPGA completes the calculation task corresponding to the serial number, and uploads the calculation result of the supercomputer ASIC chip with this serial number to the PC through the main controller, and the PC is responsible for caching the data of the current serial number.

[0058] Furthermore, after completing the calculation of one supercomputer ASIC chip, the PC will set a new serial number, the corresponding calculation parameters, and the corresponding raw calculation data again. After the supercomputer ASIC chip corresponding to the new serial number completes the calculation, it will upload the calculation result to the PC again, and the PC continues to cache the data of the current serial number. In this way, in a typical supercomputer system, if a single FPGA prototype verification platform is used, the above process needs to be repeated 1536 times to complete the complete calculation of a system;

[0059] It can be understood that after completing the calculations of all 1536 supercomputer ASIC chips in a system, the PC comprehensively merges the intermediate results generated by these 1536 calculations to obtain the final calculation result of the supercomputer system, thereby realizing the functional verification of the supercomputer system.

[0060] It is worth noting that Figure 4 the single FPGA simulated supercomputer system shown can only verify the calculation function of the supercomputer ASIC chip, but cannot verify the collaborative working function between the supercomputer ASIC chips. To solve this limitation and realize the verification of the multi-chip collaborative working process of the supercomputer ASIC chip, the present invention also designs a dual FPGA prototype verification platform as shown in Figure 5 In this prototype verification platform, the present invention can not only simulate the parallel calculation process of two supercomputer ASIC chips, but also only needs to repeat the calculation process 768 times for a typical supercomputer system.

[0061] It can be understood that by verifying the logic of calculation synchronization and transmission synchronization of two supercomputer ASIC chips, the FPGA prototype verification platform jointly composed of Figure 4 and Figure 5 can comprehensively and fully realize the verification of the calculation and working timing of the supercomputer ASIC chip.

[0062] In some embodiments, the master PC sorts and splices the calculation results of multiple iterations according to the position parameters to generate the target calculation result of the supercomputer system, including: the master PC hierarchically sorts the calculation results of multiple iterations according to the subsystem identifier and logical sequence number in the position parameters; and splices the sorted multiple calculation results according to a preset splicing rule to generate the target calculation result.

[0063] Reference Figure 6 , Figure 6 FIG. Figure 6 is a schematic diagram of an example process in the FPGA prototype verification method of the supercomputer ASIC chip provided by an embodiment of the present invention; it can be understood that, in the actual execution process of the present invention, the following specific work processes may further be included: after the system is successfully powered on and initialized, the supercomputer ASIC chip simulated by the FPGA is first initialized, and at this time, the serial number is set to start from 0; after the initialization of the supercomputer ASIC chip is completed, the system issues the original calculation data corresponding to the serial number; the supercomputer ASIC chip of the current serial number completes the calculation task corresponding to its own serial number according to the parameters corresponding to the serial number, and uploads the calculation result to the PC, and the PC is responsible for caching the current calculation result; after the calculation of the current serial number is completed, the serial number of the supercomputer ASIC chip is automatically incremented by 1, and then the calculation of the supercomputer ASIC chip of the next serial number is started; this continues until the operations of all the supercomputer ASIC chips with all serial numbers in the system are completed, and thus the prototype verification calculation of a supercomputer system is declared to end.

[0064] In a second aspect, an embodiment of the present invention provides an FPGA prototype verification system for a supercomputer ASIC chip. The FPGA prototype verification system is used to execute the FPGA prototype verification method in any one of the first aspects. The FPGA prototype verification system includes: a master PC, configured to configure position parameters, issue calculation tasks, and merge calculation results according to the position parameters; and at least one FPGA, connected to the master PC, configured to simulate the functions of the supercomputer ASIC chip.

[0065] It can be understood that the master PC in the entire verification system needs to plan a unique position parameter identifier for each supercomputer ASIC chip according to the architecture of the supercomputer system and the calculation task requirements of each supercomputer ASIC chip, and analyze the system topology structure and the functional division of each chip during the configuration process, accurate to the subsystem number and the logical sequence number within the subsystem, as the basis for subsequent data flow and result integration.

[0066] In some embodiments, when there are two FPGAs, the FPGA prototype verification system further includes: a data synchronization module, configured to verify the data transmission consistency between the two FPGA simulation chips; and an exception injection module, which triggers data exceptions by modifying the position parameters to test the fault tolerance of the system.

[0067] In some embodiments, the data synchronization module is responsible for verifying the data transmission consistency between two FPGA simulation chips. The phase-locked loop technology and timestamp comparison mechanism can be adopted to verify the time accuracy, data integrity, and transmission sequence consistency of the two FPGA-simulated supercomputer ASIC chips during the data transmission process. For example, at the data sending end, timestamps are marked for each data packet; at the receiving end, through timestamp comparison, it is ensured that the received data completely matches the sent data in terms of sequence and time. Through real-time monitoring and feedback mechanisms, if minor deviations in data transmission are found, dynamic adjustment and error correction are performed in a timely manner to ensure that the data transmission consistency error between the two FPGA simulation chips is controlled within an extremely small range.

[0068] In some embodiments, the anomaly injection module can modify the position parameters to trigger various data anomaly situations, such as data loss, misalignment, checksum errors, etc. For example, during the testing process, the anomaly injection module can precisely modify the position parameters according to the preset anomaly scenarios and injection frequencies, thereby interfering with the normal data transmission and calculation processes between the FPGA simulation chips. At this time, by detecting multi-dimensional indicators such as the processing method of the main controller for the error data, whether the system can automatically correct errors and resume normal operations, and the impact of the errors on the final calculation results, the fault tolerance of the system is evaluated. Based on the test results, the robustness and stability of the system in the face of various complex actual operating environments are improved.

[0069] In some embodiments, the FPGA is a general-purpose FPGA, which supports switching the simulated chip instances by reconfiguring the position parameters.

[0070] In some embodiments, the merging rules of the main control PC include: grouping data according to the subsystem levels in the position parameters; splicing the data within the group according to the logical sequence numbers.

[0071] In some embodiments, all the functions of the supercomputer ASIC chip can be simulated by using one FPGA in the present invention. However, in the system, since multiple supercomputer ASIC chips need to transmit data to the main controller, two FPGAs are used to simulate two supercomputer ASIC chips to verify whether unexpected problems will occur to other supercomputer ASIC chips in the system when data retransmission, data disconnection, data loss, etc. occur to one supercomputer ASIC chip, and whether other supercomputer ASIC chips in the system can work according to the pre-design. It can be understood that because the supercomputer ASIC chips are simulated by two FPGAs, the positions of the supercomputer ASIC chips in the system can be arbitrarily set by the PC. To achieve the purpose of verifying whether another supercomputer ASIC chip works properly when there are problems with the interface data, such a requirement can be achieved only by using two FPGA simulations, so no more FPGA simulations are needed.

[0072] It should be noted that, for example, when using more than two FPGAs, such as 3 or 4, the quantity of this synchronous verification is mainly affected by cost factors. Since the logic units of the supercomputer ASIC chips are numerous, FPGAs with very good performance are required. Using more FPGAs for simulation will increase the cost of product R & D. Moreover, according to the requirements analysis, only two are needed to achieve the purpose of FPGA prototype verification.

[0073] In some embodiments, when the present invention verifies the computing synchronization, it will not pair and group the ASIC chips. When verifying the computing function, the serial numbers of the ASICs are incremented, such as calculating together for 1 and 2; calculating together for 3 and 4; while when verifying the interface data synchronization, the position serial numbers of two ASIC chips in the system are randomly set for verifying the data synchronization.

[0074] In a third aspect, an embodiment of the present invention provides a computer-readable storage medium storing a computer program, which when executed by a processor implements the FPGA prototype verification method for a supercomputer ASI C chip as described in any one of the first aspects; for example, executing the Figure 1 method steps S110 to S150 described above.

[0075] Those of ordinary skill in the art can understand that all or some of the steps and systems in the methods disclosed above can be implemented as software, firmware, hardware, and their appropriate combinations. Some physical components or all physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or can be implemented as hardware, or can be implemented as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include a computer storage medium (or a non-transitory medium) and a communication medium (or a transitory medium). As is well known to those of ordinary skill in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable instructions, data structures, program modules, or other data. The computer storage medium includes, but is not limited to, RAM, ROM, EEPROM, flash memory, or other memory technologies, CD-ROM, digital versatile disc (DVD), or other optical disc storage, magnetic cassette, tape, magnetic disk storage, or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, as is well known to those of ordinary skill in the art, the communication medium generally includes computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and can include any information delivery medium.

[0076] The above is a specific description of the preferred embodiments of the present invention. However, the present invention is not limited to the above-mentioned embodiments. Those skilled in the art can make various equivalent deformations or substitutions without departing from the spirit of the present invention, and these equivalent deformations or substitutions are all included within the scope defined by the claims of the present invention.

Claims

1. An FPGA prototype verification method for a supercomputer ASIC chip, characterized in that, Including: Configuring position parameters and corresponding calculation parameters for each supercomputer ASIC chip in the supercomputer system by the master control PC; Based on the position parameters, the master control PC sends the serial number, calculation parameters, and original data of the currently simulated chip to at least one FPGA, where the serial number is bound to the position parameters; The FPGA simulates the calculation function of the corresponding supercomputer ASIC chip according to the received serial number, calculation parameters, and original data, and sends the calculation result back to the master control PC; Repeat the above simulation steps, and update the position parameters iteratively each time to switch the simulated chip instance until all supercomputer ASIC chips in the supercomputer system are covered; The master control PC sorts and splices the calculation results of multiple iterations according to the position parameters to generate the target calculation result of the supercomputer system, so as to complete the system-level function verification.

2. The FPGA prototype verification method for the supercomputer ASIC chip according to claim 1, characterized in that The number of the FPGAs is one or two, and the chip functions are simulated in the following ways: When using one FPGA, the calculation processes of all supercomputer ASIC chips are serially simulated by updating the position parameters; When using two FPGAs, the collaborative calculation process of two chips is simulated by parallelly configuring different position parameters.

3. The FPGA prototype verification method of the supercomputer ASIC chip according to claim 2, characterized in that When using two FPGAs, it further includes: The master control PC randomly sets the position parameters of the two FPGAs to simulate data loss or disconnection scenarios, and in the parallel calculation process, the data transmission timing of the two FPGAs is monitored in real time to obtain the calculation results for verifying the data synchronization and fault tolerance mechanism between chips.

4. The FPGA prototype verification method for the supercomputer ASIC chip according to claim 1, characterized in that The supercomputer system is composed of multiple subsystems, each subsystem includes a main controller, a secondary main controller, and multiple supercomputer ASIC chips, and the position parameters include: the identifier of the subsystem to which the chip belongs; the logical serial number of the chip within the subsystem.

5. The FPGA prototype verification method for the supercomputer ASIC chip according to claim 1, wherein The master control PC sorts and splices the calculation results of multiple iterations according to the position parameters to generate the target calculation result of the supercomputer system, including: The master control PC hierarchically sorts the calculation results of multiple iterations according to the subsystem identifier and logical serial number in the position parameters; The sorted multiple calculation results are spliced according to the preset splicing rules to generate the target calculation result.

6. An FPGA prototype verification system for a supercomputer ASIC chip, characterized in that, The FPGA prototype verification system is used to execute the FPGA prototype verification method described in any one of claims 1 to 5, and the FPGA prototype verification system includes: A master control PC, which is used to configure position parameters, issue calculation tasks, and merge calculation results according to position parameters; At least one FPGA, connected to the master control PC, which is used to simulate the functions of supercomputer ASIC chips.

7. The FPGA prototype verification system of the supercomputer ASIC chip according to claim 6, wherein When two FPGAs are included, the FPGA prototype verification system further includes: A data synchronization module: which is used to verify the data transmission consistency between the two FPGA-simulated chips; An exception injection module: which triggers data exceptions by modifying position parameters to test the fault tolerance ability of the system.

8. The FPGA prototype verification system of the supercomputer ASIC chip according to claim 6, characterized in that, The FPGA is a general-purpose FPGA, which supports switching the simulated chip instance by reconfiguring the position parameters.

9. The FPGA prototype verification system for the supercomputer ASIC chip according to claim 6, characterized in that, The merging rules of the master control PC include: Grouping data according to the subsystem hierarchy in the position parameters; Splicing the data within the group according to the logical serial number.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the FPGA prototype verification method for the supercomputer ASIC chip according to any one of claims 1 to 5.

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