Instruction debugging method and device, equipment, medium and program product

Abstract

The invention provides an instruction debugging method and device, equipment, a medium and a program product. The method comprises the steps of obtaining a debugging instruction of a target engine, wherein the target engine is a stack-free processor; on the basis of a source code mapping file, code data corresponding to the debugging instruction are determined, the source code mapping file is used for describing the mapping relation between the instruction of the target engine and the stack code, and the code data are used for indicating the stack code corresponding to the debugging instruction; based on the encoded data, a location of the error source code is determined. Thus, mapping from the debugging instruction to the stack code can be established through the source code mapping file, on one hand, the source code can be checked in time, the position of the error source code can be positioned according to the debugging instruction, and debugging is simple; and on the other hand, the performance data corresponding to the source code can be obtained according to the source code mapping file, so that the analysis performance of the operator is optimized.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technologies, and in particular, to a method, apparatus, device, medium, and program product for debugging instructions. Background Art

[0002] With the development of artificial intelligence, many heterogeneous processors for accelerating deep neural networks have emerged. Such heterogeneous processors have parallel processing capabilities and low power consumption, and are widely used in fields such as autonomous driving, natural language processing, face recognition, speech recognition, and image processing. However, such heterogeneous processors usually cannot generate corresponding stacks when running files. Therefore, when debugging the generated instructions, it is necessary to locate the operator where the instruction is located and search line by line of code, resulting in time-consuming debugging and the problem of being unable to check the source code in a timely manner, which brings inconvenience to debugging. Summary of the Invention

[0003] To overcome the problems in the related art, the present disclosure provides a method, apparatus, device, medium, and program product for debugging instructions, which can check the source code in a timely manner, locate the position of the incorrect source code according to the debugging instruction, and the debugging is simple.

[0004] According to a first aspect of an embodiment of the present disclosure, a method for debugging instructions is provided, including: obtaining a debugging instruction of a target engine, where the target engine is a stackless processor; determining, based on a source code mapping file, encoded data corresponding to the debugging instruction, where the source code mapping file is used to describe the mapping relationship between the instructions of the target engine and stack encodings, and the encoded data is used to indicate the stack encoding corresponding to the debugging instruction; and determining the position of the incorrect source code based on the encoded data.

[0005] In some embodiments, the above method further includes: determining a first instruction included in the target engine; using each layer of the stack corresponding to the first instruction as a node of a call graph, and using the call relationship between the (i + 1)-th layer and the i-th layer of the stack corresponding to the first instruction as a directed edge of the call graph, to obtain a call graph of the stack corresponding to the first instruction, where i is a positive integer; determining the encoded data corresponding to the first instruction based on the call graph, and determining the source code mapping file corresponding to the target engine according to the call graph and the encoded data corresponding to the first instruction.

[0006] In some embodiments, each layer of the stack corresponding to the first instruction is used as a node of the call graph, and the call relationship between the (i + 1)-th layer and the i-th layer of the stack corresponding to the first instruction is used as a directed edge of the call graph, so as to obtain the call graph of the stack corresponding to the first instruction, including: representing the stack corresponding to the first instruction as a first addressing list; in the case that at least one element in the first addressing list is not included in the first node list, adding the at least one element to the first node list to obtain an updated first node list; in the case that the edge corresponding to two adjacent elements in the first addressing list is not included in the first directed edge list, adding the edge corresponding to the two adjacent elements to the first directed edge list to obtain an updated first directed edge list; and obtaining the call graph of the stack corresponding to the first instruction based on the updated first node list and the updated first directed edge list.

[0007] In some embodiments, the above method further includes: obtaining a second node list and a second directed edge list; performing an initialization operation on the second node list to obtain a first node list, and performing an initialization operation on the second directed edge list to obtain a first directed edge list.

[0008] In some embodiments, determining the encoded data corresponding to the first instruction based on the call graph includes: representing the first instruction as a directed path based on the call graph; representing the first instruction in a source code mapping encoding form based on the directed path to obtain the encoded data corresponding to the first instruction; wherein, the encoded data corresponding to the first instruction includes at least one of the following: the identification information of the first instruction, the total number of nodes included in the directed path corresponding to the first instruction, the index of the starting node of the directed path corresponding to the first instruction, and the indexes of the ending nodes of all the edges in the directed path corresponding to the first instruction.

[0009] In some embodiments, the above method further includes: when only one edge starting from the first node is included in the directed path corresponding to the second instruction, setting the indexes of the ending nodes of all the edges in the directed path corresponding to the second instruction as an empty set; wherein, the second instruction is one of the first instructions; and the first node is the starting node corresponding to the second instruction.

[0010] In some embodiments, the above method further includes: compiling the neural network structure through a compilation tool to obtain a model file corresponding to the neural network structure; and obtaining the stack corresponding to the first instruction from the model file based on the stack acquisition function and / or extraction code.

[0011] In some embodiments, compiling the neural network structure through a compilation tool to obtain a model file corresponding to the neural network structure includes: compiling the neural network structure through the compiler layer of the compilation tool to obtain at least one operator; and calling an implementation function and an instruction generation function through the multiplication operation operator in the at least one operator to generate a model file corresponding to the neural network structure.

[0012] According to a second aspect of the embodiments of the present disclosure, there is provided a debugging device for instructions, including: a first acquisition module configured to acquire debugging instructions of a target engine, where the target engine is a stackless processor; a first determination module configured to determine encoded data corresponding to the debugging instructions based on a source code mapping file, where the source code mapping file is used to describe the mapping relationship between the instructions of the target engine and stack encodings, and the encoded data is used to indicate the stack encoding corresponding to the debugging instructions; a second determination module configured to determine the location of the source code with errors based on the encoded data.

[0013] In some embodiments, the above device further includes: a third determination module configured to determine a first instruction included in the target engine; a fourth determination module configured to use each layer of the stack corresponding to the first instruction as a node of a call graph, and use the call relationship between the (i + 1)-th layer and the i-th layer of the stack corresponding to the first instruction as a directed edge of the call graph, to obtain a call graph of the stack corresponding to the first instruction, where i is a positive integer; a fifth determination module configured to determine the encoded data corresponding to the first instruction based on the call graph, and determine the source code mapping file corresponding to the target engine according to the call graph and the encoded data corresponding to the first instruction.

[0014] In some embodiments, the fourth determination module is further configured to perform the following steps: represent the stack corresponding to the first instruction as a first addressing list; in the case where at least one element in the first addressing list is not included in the first node list, add the at least one element to the first node list to obtain an updated first node list; in the case where the edge corresponding to two adjacent elements in the first addressing list is not included in the first directed edge list, add the edge corresponding to the two adjacent elements to the first directed edge list to obtain an updated first directed edge list; and obtain a call graph of the stack corresponding to the first instruction based on the updated first node list and the updated first directed edge list.

[0015] In some embodiments, the above device further includes: a second acquisition module configured to acquire a second node list and a second directed edge list; an initialization module configured to perform an initialization operation on the second node list to obtain a first node list, and perform an initialization operation on the second directed edge list to obtain a first directed edge list.

[0016] In some embodiments, the fifth determination module is further configured to perform the following steps: represent the first instruction as a directed path based on the call graph; represent the first instruction in the form of a source code mapping encoding based on the directed path to obtain the encoded data corresponding to the first instruction; wherein, the encoded data corresponding to the first instruction includes at least one of the following: the identification information of the first instruction, the total number of nodes included in the directed path corresponding to the first instruction, the index of the starting node of the directed path corresponding to the first instruction, and the indices of the terminating nodes of all edges in the directed path corresponding to the first instruction.

[0017] In some embodiments, the above device further includes: a setting module configured to set the indices of the terminating nodes of all edges in the directed path corresponding to the second instruction to an empty set when there is only one edge starting from the first node in the directed path corresponding to the second instruction; wherein, the second instruction is one of the first instructions; and the first node is the starting node corresponding to the second instruction.

[0018] In some embodiments, the above device further includes: a sixth determination module configured to compile the neural network structure through a compilation tool to obtain a model file corresponding to the neural network structure; and a third acquisition module configured to obtain the stack corresponding to the first instruction from the model file based on the stack acquisition function and / or extraction code.

[0019] In some embodiments, the sixth determination module is further configured to perform the following steps: compile the neural network structure through the compiler layer of the compilation tool to obtain at least one operator; and generate a model file corresponding to the neural network structure by invoking an implementation function and an instruction generation function through the multiplication operation operator in the at least one operator.

[0020] According to a third aspect of the embodiments of the present disclosure, there is provided an electronic device including: a processor; and a memory for storing a computer program or instruction; wherein, the processor executes the computer program or instruction to implement the steps in any one of the instruction debugging methods in the first aspect above.

[0021] According to a fourth aspect of the embodiments of the present disclosure, there is provided a non-transitory computer-readable storage medium storing a computer program or instruction, and when the computer program or instruction in the storage medium is executed by a processor, the steps in any one of the instruction debugging methods in the first aspect above are implemented.

[0022] According to a fifth aspect of the embodiments of the present disclosure, there is provided a computer program product including a computer program or instruction, and when the computer program or instruction is executed by a processor, the steps in any one of the instruction debugging methods in the first aspect above are implemented.

[0023] The technical solutions provided by the embodiments of the present disclosure may include the following beneficial effects:

[0024] By obtaining the debug instructions of the target engine, i.e., the stackless processor, and then based on the source code mapping file for describing the mapping relationship between the instructions of the target engine and the stack encoding, determining the encoded data corresponding to the debug instructions, where the encoded data is used to indicate the stack encoding corresponding to the debug instructions, and finally determining the location of the error source code according to the encoded data. In this way, through the source code mapping file, a mapping between the debug instructions and the stack encoding can be established. On the one hand, the source code can be checked in a timely manner, and the location of the error source code can be located according to the debug instructions, making the debugging simple; on the other hand, the performance data corresponding to the source code can be obtained according to the source code mapping file, so as to optimize the analysis performance of the operator.

[0025] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. Brief Description of the Drawings

[0026] The drawings herein are incorporated into the specification and form a part of this specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure.

[0027] Figure 1 is a flowchart of a method for debugging instructions shown according to an exemplary embodiment;

[0028] Figure 2 is a schematic diagram of the composition of an SCMP file shown according to an exemplary embodiment;

[0029] Figure 3 is a schematic diagram of the corresponding relationship between a directed graph, a call graph, and an SCMP encoding shown according to an exemplary embodiment;

[0030] Figure 4 is a schematic diagram of the structure of a compilation tool shown according to an exemplary embodiment;

[0031] Figure 5 is a block diagram of a device for debugging instructions shown according to an exemplary embodiment;

[0032] Figure 6 is a block diagram of the structure of an electronic device 600 shown according to an exemplary embodiment;

[0033] Figure 7 is a block diagram of a server 700 shown according to an exemplary embodiment. Detailed Embodiments

[0034] Exemplary embodiments will be described in detail herein, and examples thereof are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. On the contrary, they are merely examples of devices consistent with some aspects of the present disclosure as detailed in the appended claims.

[0035] In the related art, after a source code program is compiled on a computer with an x86 architecture, an executable file and a library file are generated, which store central processing unit (CPU) instructions and generate the code corresponding to the source program for the instructions. When the instructions run, the stack generated by the program corresponds to the source code, which makes the program debugging traceable, and debugging can be performed through debugging tools such as (GNU Debugger, gdb), etc. However, with the development of artificial intelligence, many heterogeneous processors (also known as stackless processors) for deep neural network acceleration have emerged. Many of the files obtained by such processors do not contain control instructions. Therefore, when running the file, the stack corresponding to the instructions cannot be generated. Furthermore, when debugging the generated instructions, since the mapping from the instructions to the source code cannot be successfully established, it is necessary to locate the operator where the instruction is located and search line by line for the code, resulting in problems such as time-consuming debugging and inability to check the source code in a timely manner, which brings inconvenience to debugging. In addition, a heterogeneous processor usually includes multiple independently running engines, and these engines usually have corresponding atomic instructions. All the instructions of each engine can form a channel. In actual debugging, the influence of these engines on the internal memory of the processor also needs to be considered simultaneously.

[0036] The hardware accelerator of a heterogeneous processor needs to generate instructions through a compiler and then accelerate the model by running the model file generated by the compiler. When compiling a deep neural network model, the compiler traverses and calls each operator in the deep neural network according to the topological order. During the call of the operator, a series of instructions are sequentially generated according to the operator logic and saved in the model file. Such a model file can complete the acceleration of the deep neural network model without the participation of a stack when running. The above design of the heterogeneous processor can reduce the hardware cost and runtime overhead. However, in the absence of stack participation, it is impossible to determine which source code each instruction corresponds to, which poses a challenge to debugging such a model file. Usually, the debugging of the above model file is based on instruction string disassembly, ignoring the possible parallel relationship between engines, executing instructions in sequence, and then extracting data at appropriate positions and comparing it with standard data to locate the error position. However, the error position is relatively vague and not accurate enough.

[0037] Based on this, in the embodiments of the present disclosure, by obtaining the debug instructions of the target engine, i.e., the stackless processor, and then based on the source code mapping file for describing the mapping relationship between the instructions of the target engine and the stack encoding, the encoding data corresponding to the debug instructions is determined. The encoding data is used to indicate the stack encoding corresponding to the debug instructions. Finally, based on the encoding data, the position of the error source code is determined. In this way, through the source code mapping file, the mapping between the debug instructions and the stack encoding can be established. On the one hand, the source code can be checked in a timely manner, and the position of the error source code can be located according to the debug instructions, making the debugging simple. On the other hand, the performance data corresponding to the source code can be obtained according to the source code mapping file, thereby optimizing the analysis performance of the operator.

[0038] Figure 1 is a flowchart of a method for debugging an instruction shown according to an exemplary embodiment. As Figure 1 shown, the method for debugging an instruction is used in a heterogeneous processor, and the method mainly includes the following steps:

[0039] In step S101, obtain the debug instructions of the target engine.

[0040] In step S102, based on the source code mapping file, determine the encoding data corresponding to the debug instructions.

[0041] In step S103, based on the encoding data, determine the position of the error source code.

[0042] Here, the target engine can be a stackless processor, and the stackless processor can be a heterogeneous processor. For example, open source instruction set architecture (RISC-V), neural processing unit (NPU), tensor processing unit (TPU), etc. The embodiments of the present disclosure do not make limitations in this regard. The source code mapping file (SCMP file) is used to describe the mapping relationship between the instructions of the target engine and the stack encoding. The encoding data is used to indicate the stack encoding corresponding to the debug instructions, and it can be in the form of source map code (SCMP encoding).

[0043] In some embodiments, for step S101, the processor may include one or more engines (also referred to as cores). The target engine is the engine during the debugging of the debug instructions. Usually, the target engine includes multiple instructions. Therefore, the error instruction that needs to be adjusted or modified, i.e., the debug instruction, is determined from the multiple instructions corresponding to the target engine.

[0044] In some embodiments, for the debugging instruction in step S101, it can be determined manually by the debugger or determined by the debugging tool. The embodiments of the present disclosure do not make specific limitations on this.

[0045] In some embodiments, for step S102, during the debugging process of the instruction, in order to locate the position of the error source code, it is necessary to determine the encoded data corresponding to the debugging instruction. Since the source code mapping file can describe the mapping relationship between the instructions of the target engine and the stack encoding, therefore, through this source code mapping file, the encoded data corresponding to the debugging instruction can be determined.

[0046] In some embodiments, for the source code mapping file in step S102, it can be a file formed by encoding and storing the mapping relationship between the instructions of the target engine and the stack encoding. This file can be determined in advance before step S101 or determined after step S101. The embodiments of the present disclosure do not make limitations on this.

[0047] In some embodiments, for step S103, after determining the encoded data corresponding to the debugging instruction, according to the addressing in the encoded data, the library file or the execution file name and the relative address of the library file or the execution file can be determined. Then, the line number where the error source code is located can be determined through the source code line acquisition command, and further the position of the error source code can be determined.

[0048] In some embodiments, for step S103, the source code line acquisition command can be the addr2line command of the linux system or other commands. The embodiments of the present disclosure do not make limitations on this.

[0049] In some embodiments, for step S103, since the encoded data corresponding to the debugging instruction contains the brief stack information obtained by concatenating the source code lines corresponding to each layer from top to bottom in the stack encoding, therefore, the position of the error source code can also be determined according to the number of times the source code line is currently hit in the encoded data, by running the program that generates the debugging instruction through a debugging tool such as gdb.

[0050] In some embodiments, by obtaining the debugging instruction of the target engine, that is, the stackless processor, and then based on the source code mapping file used to describe the mapping relationship between the instructions of the target engine and the stack encoding, determining the encoded data corresponding to the debugging instruction, where the encoded data is used to indicate the stack encoding corresponding to the debugging instruction, and finally determining the position of the error source code according to the encoded data. In this way, through the source code mapping file, a mapping between the debugging instruction and the stack encoding can be established. On the one hand, the source code can be checked in time, and the position of the error source code can be located according to the debugging instruction, which is simple to debug; on the other hand, the performance data corresponding to the source code can be obtained according to the source code mapping file, so as to optimize the analysis performance of the operator.

[0051] In some embodiments, for the source code mapping file in step S102, it can be determined through the following steps: step a, determine the first instruction included in the target engine; step b, use each layer of the stack corresponding to the first instruction as a node of the call graph, and use the call relationship between the (i + 1)-th layer and the i-th layer of the stack corresponding to the first instruction as the directed edge of the call graph to obtain the call graph of the stack corresponding to the first instruction; step c, determine the encoded data corresponding to the first instruction based on the call graph, and determine the source code mapping file corresponding to the target engine according to the call graph and the encoded data corresponding to the first instruction.

[0052] Here, i is a positive integer. A stack can be understood as a data structure for storing data, and a stack can contain at least one layer. A call graph can be understood as a file obtained after representing the stack in the form of nodes and directed edges.

[0053] It can be understood that since the engine of the processor contains one or more atomic instructions, and all the instructions included in each engine can form a channel, in order to distinguish the instructions in the channel, the source code mapping file corresponding to each channel can be determined in the form of a single channel, or the source code mapping file corresponding to each channel in multiple channels can be determined separately and these source code mapping files can be summarized to obtain the total source code mapping file corresponding to all channels. It is also possible to determine the source code mapping file by other means, and the embodiments of the present disclosure do not limit this.

[0054] In some embodiments, for the stack in step b, after obtaining the first instruction included in the target engine, since the first instruction corresponds to the stack, the compilation tool will also generate the stack corresponding to the first instruction while generating the first instruction. Therefore, after determining the first instruction, the stack corresponding to the first instruction can also be obtained. Generally, one instruction corresponds to one stack.

[0055] In some embodiments, for step b, after obtaining the stack corresponding to the first instruction (denoted as the first stack), based on the relationship between the layers included in the first stack, each layer of the first stack is regarded as a node of the call graph, and the call relationship between the (i + 1)-th layer and the i-th layer of the first stack is used as the directed edge of the call graph, and the first stack can be represented as a call graph, thereby obtaining the call graph corresponding to the first stack.

[0056] In some embodiments, when storing the nodes, the stored values can be uniformly addressed. In an example, for the i-th layer of a certain stack, its node can be represented as uaddrs[i].

[0057] In some embodiments, for step c, after obtaining the call graph corresponding to the first stack, the first instruction can be represented as a directed path in the call graph (i.e., the complete path from the starting node to the ending node). The directed path is arranged in sequence in the call graph according to the path represented by the first instruction. The directed path can be represented in the form of SCMP encoding, and the encoded data corresponding to the first instruction is obtained. Then, based on the call graph and the encoded data corresponding to the first instruction, the source code mapping file corresponding to the target engine can be obtained.

[0058] In this way, through the above steps a to c, the source code mapping file corresponding to the target engine can be determined. And since the SCMP encoding contains at least the stack top information of the first instruction and the information of the adjacent stack below the stack top, and its encoded memory occupancy is small, usually one or two bytes can be used to record each layer of the stack. Therefore, based on this design of SCMP encoding, the redundancy of the instruction string stack information can be reduced.

[0059] In some embodiments, for step b, after obtaining the first stack, the pointer array of each stack frame of the first stack from top to bottom (denoted as frame_ptrs) can also be obtained, and the positioning binary tuple corresponding to the first stack is determined according to the pointer array. In this way, by representing the first instruction in the form of a binary tuple, the instruction data can be represented concisely and clearly, simplifying the instruction data and facilitating the improvement of the execution efficiency of the processor.

[0060] In some embodiments, for the above positioning binary tuple, it can be represented as: (lib_names[i], lib_addrs[i]), (i = 1, 2,..., D), and the positioning binary tuple can be further represented by the unified addressing uaddrs[i].

[0061] Here, D represents the depth of the first stack, that is, the number of layers of the first stack, and D is a positive integer greater than 2; lib_names[i] represents the name of the library file or executable file referenced by each stack frame; lib_addrs[i] represents the relative address of the library file or executable file referenced by each stack frame; i represents the number of layers of the stack, i = 1 at the stack top, and i increases sequentially from the stack top to the stack bottom.

[0062] In some embodiments, in the above process, for the source code mapping file in step S102, it may further include a file header, and the file header may contain the metadata of the source code mapping file.

[0063] In some embodiments, the above file header may contain the meta information of the call graph and the meta information of each first instruction. In some embodiments, the above file header may further include a marker information, and the marker information can be used to determine whether the encoded data needs to be compressed.

[0064] Here, the meta - information can be understood as descriptive information used to describe information related to the content, coverage, owner of the call graph or encoded data, and the way the data is provided, etc.

[0065] Figure 2 is a schematic diagram showing the composition of an SCMP file according to an exemplary embodiment. As Figure 2 shown, the SCMP file includes the following parts: a file header, a call graph, and encoded data. Among them, the file header includes meta - information and marker information. The call graph includes a node list and a directed edge table (also called an adjacency list). The node list contains Nv nodes, where Nv is a positive integer, and each node stores the unified addressing corresponding to the layers of the stack. The directed edge table includes Ne linked lists with head nodes. The head node stores the starting node of the directed edge, and other nodes store the ending node of the directed edge. The encoded data may include, but is not limited to: in n engines (one engine can correspond to one channel), for each instruction included in each engine, the corresponding SCMP encoding, respectively: the SCMP encoding corresponding to L(1) instructions included in channel 1, the SCMP encoding corresponding to L(2) instructions included in channel 2, …, the SCMP encoding corresponding to L(n) instructions included in channel n. Among them, L(1) is a positive integer greater than 3, L(2) is a positive integer greater than 3, L(n) is a positive integer greater than 3. The L(1) instructions included in channel 1 are respectively: #1:1, #1:2, #1:3, …, #1:L(1). The L(2) instructions included in channel 2 are respectively: #2:1, #2:2, #2:3, …, #2:L(2). The L(n) instructions included in channel n are respectively: #n:1, #n:2, #n:3, …, #n:L(n).

[0066] In some embodiments, Figure 2 the instruction #1:1 in can be the name or identifier corresponding to the instruction, and the data stored therein can be: the encoded data corresponding to the first instruction of channel 1. The #1 is the index of the channel, indicating channel 1, and the second 1 indicates the index of the instruction.

[0067] In some embodiments, Figure 2 is an exemplary illustration of the composition of the SCMP file. The number of nodes, the number of directed edges, the number of instructions, etc. included therein are only for exemplary illustration and are not used to limit it.

[0068] In some embodiments, in the above process, for the source - code mapping file in step S102, its storage process may include the following steps:

[0069] (1) Write the file header, and this step may include but is not limited to recording the number of bytes used by the four components of the SCMP encoding, the number of bytes used for unified addressing, the meta-information of unified addressing, whether the SCMP encoding needs to be extremely compressed, etc.

[0070] (2) Save the call graph, specifically, the node list nodes and the adjacency list edges can be saved.

[0071] (3) Save the instruction data, specifically, the SCMP encoding of each first instruction can be saved.

[0072] In some embodiments, the above step b may include: step b1, representing the stack corresponding to the first instruction as a first addressing list; step b2, when at least one element in the first addressing list is not included in the first node list, adding the at least one element to the first node list to obtain an updated first node list; step b3, when the edge corresponding to two adjacent elements in the first addressing list is not included in the first directed edge list, adding the edge corresponding to the two adjacent elements to the first directed edge list to obtain an updated first directed edge list; step b4, obtaining the call graph of the stack corresponding to the first instruction based on the updated first node list and the updated first directed edge list.

[0073] It can be understood that by performing unified addressing on the first stack, a first addressing list corresponding to the first stack can be obtained. After obtaining the first addressing list, it is necessary to determine whether each element in the first addressing list is included in the first node list. If at least one element in the first addressing list is not included in the first node list, then add the at least one element to the first node list to obtain an updated first node list, and determine whether the edge corresponding to two adjacent elements in the first addressing list is included in the first directed edge list; if each element in the first addressing list is included in the first node list, then determine whether the edge corresponding to two adjacent elements in the first addressing list is included in the first directed edge list. If the edge corresponding to two adjacent elements in the first addressing list is not included in the first directed edge list, then add the edge corresponding to the two adjacent elements to the first directed edge list to obtain an updated first directed edge list; if the edges corresponding to two adjacent elements in the first addressing list are all included in the first directed edge list, it means that all the directed edges corresponding to the first stack are already included in the first directed edge list. Finally, based on the updated first node list and the updated first directed edge list, the call graph corresponding to the first stack is obtained. In this way, the call graph corresponding to the first instruction included in the target engine is obtained through the above method, which is simple, efficient, fast, and convenient to view.

[0074] In some embodiments, the execution order of step b2 and step b3 may be exchanged or they may be executed simultaneously, and the present disclosure embodiment does not limit the execution order of the two.

[0075] In some embodiments, during the above process, for the first addressing list in step b1, it can be expressed as uaddrs[j]. In some embodiments, the length of the first addressing list can be the depth of the first stack corresponding to the first addressing list, that is, the number of layers of the stack corresponding to the first addressing list, which can be represented by code_len[j].

[0076] It can be understood that j can represent the execution order of the first instruction. Since one instruction corresponds to one stack, the first instruction j can represent the j-th stack and can also represent the j-th first instruction, and j is a positive integer.

[0077] In some embodiments, during the above process, for each element uaddrs[j][i] (i = 1, 2,..., code_len[j]) in the first addressing list in step b2, it is judged whether uaddrs[j][i] is in the first node list. If it is not in the first node list, the element can be added to the end of the first node list.

[0078] Here, i can be the sorting of the elements in the first addressing list.

[0079] In some embodiments, during the above process, for each element uaddrs[j][i] (i = 1, 2,..., code_len[j] - 1) in the first addressing list in step b3, let c[i] be index(nodes, uaddrs[j][i]), and it is judged whether the edge (c[i + 1], c[i]) is in the first directed edge list edges1; if not, the edge (c[i + 1], c[i]) is added to edges1. At the same time, the index of the termination node of all edges in the directed path corresponding to the first instruction j (denoted as code_skips[j][i]) can be set to the index of the directed edge with the start node c[i + 1] and the termination node c[i] in the directed edges starting with c[i + 1] in edges1.

[0080] In some embodiments, during the above process, for the first node list in step b2 and the first directed edge list in step b3, they can be obtained through the following steps, specifically including: obtaining a second node list and a second directed edge list; performing an initialization operation on the second node list to obtain the first node list, and performing an initialization operation on the second directed edge list to obtain the first directed edge list.

[0081] Understandably, a second node list and a second directed edge list can be obtained, and these two lists can be pre-determined. Then, an initialization operation is performed on the second node list. For example, the values corresponding to the elements in the second node list are set to zero, and a first node list can be obtained. And an initialization operation is performed on the second directed edge list. For example, the values corresponding to the elements in the second directed edge list are set to zero, and a first directed edge list is obtained. In this way, a first node list and a first directed edge list can be obtained, which is convenient for subsequent updating of the two lists.

[0082] In some embodiments, in the above process, determining the encoded data corresponding to the first instruction in step c may include: based on the call graph, representing the first instruction as a directed path; based on the directed path, representing the first instruction in the form of source code mapping encoding to obtain the encoded data corresponding to the first instruction.

[0083] Here, the encoded data corresponding to the first instruction includes at least one of the following: the identification information of the first instruction (denoted as code_hit), the total number of nodes included in the directed path corresponding to the first instruction (denoted as code_len), the index of the starting node of the directed path corresponding to the first instruction (denoted as code_sta), and the indexes of the terminating nodes of all edges in the directed path corresponding to the first instruction (denoted as code_skip).

[0084] Understandably, after determining the call graph of the first stack, each instruction can be represented as a directed path in the call graph. Then, according to the relationship between the nodes and directed edges in the call graph, the first instruction is represented as a directed path. Then, by representing the first instruction in the SCMP encoding form, the encoded data corresponding to the first instruction can be obtained.

[0085] In some embodiments, for code_hit, it can represent the saving order of the current first instruction. For example, which instruction is the current first saved instruction, or it can also represent the number of times the code line corresponding to the top of the stack of the first instruction is currently hit. In some embodiments, let the value of the counter be HIT += 1, and then code_hit[j] can be set to HIT to achieve automatic update of code_hit.

[0086] In some embodiments, for code_len, it can represent the depth of the stack corresponding to the first instruction.

[0087] In some embodiments, for code_sta, it can represent the starting index corresponding to the first stack (denoted as uaddrs[D]), and code_sta[j] can be set to index(nodes,uaddrs[j][code_len[j]).

[0088] In some embodiments, for code_skip, it can be a list containing D - 1 elements, and the i-th element code_skip[i] is the index of the termination node of the edge corresponding to the call relationship between the (i + 1)-th layer stack and the i-th layer stack.

[0089] In some embodiments, for step S103, the debugging instruction can also be debugged by combining the source code mapping file with gdb. The specific debugging process can include: taking the depth D of the first stack as an adjustable parameter. When combining with gdb for debugging, set a breakpoint for the code behavior corresponding to uaddrs[D], and stop when it is hit code_hit times. At this time, the code line corresponding to uaddrs[D] represents a layer of the error stack. In this way, according to code_hit and the SCMP encoding, the line where the error source code is located can be located, that is, the location of the error source code.

[0090] Figure 3 It is a schematic diagram showing the corresponding relationship between a directed graph, a call graph, and SCMP encoding according to an exemplary embodiment. According to the index of the first instruction in the instruction string, the SCMP encoding corresponding to a certain first instruction can be found in the SCMP file, as Figure 3 shown in (a) of. This SCMP encoding can include four components: (code_hit, code_len, code_sta, code_skip), where the value of code_hit is 10, the value of code_len is 3, the value of code_sta is 3, and the values of code_skip are 1 and 2. As Figure 3 shown in (a) of, the nodes included in the call graph in the SCMP file are respectively: 0(0x15), 1(0x49), 2(0x93), 3(0x61), 4(0x32), 5(0x73), 6(0x58). Among them, the directed edges corresponding to node 1 are 0 and 5, the directed edges corresponding to node 2 are 1 and 4, the directed edges corresponding to node 3 are 1, 2, and 4, the directed edges corresponding to node 4 are 0 and 5, the directed edges corresponding to node 6 are 1, 4, and 5, and there are no corresponding directed edges between node 1 and node 5.

[0091] In some embodiments, according to Figure 3 the SCMP encoding shown in (a) of, through code_len, it can be determined that the total number of nodes corresponding to the first instruction is 3; through code_sta, it can be determined that the index of the starting node of the directed path corresponding to the first instruction is 3. In Figure 3Among the nodes of the call graph shown in (a), it can be determined that the node corresponding to index 3 is node 3. Through code_skip, it can be determined that the indices of the termination nodes of all edges in the directed path corresponding to the first instruction are 1 and 2. Based on indices 1 and 2, search for Figure 3 the directed edges of the call graph shown in (a). It can be determined that the one corresponding to index 1 is directed edge 1, the node corresponding to directed edge 1 is node 1, the one corresponding to index 2 is directed edge 5, and the node corresponding to directed edge 5 is node 5. Based on this, it can be determined that Figure 3 the directed path corresponding to the SCMP encoding shown in (a) is: from node 3 to node 1 to node 5, that is, Figure 3 the directed path from node 3 to node 1 to node 5 in the directed graph shown in (b).

[0092] In some embodiments, according to Figure 3 the nodes and directed edges shown in (a), a directed graph can be drawn, and the obtained directed graph is as shown in Figure 3 the directed graph shown in (b).

[0093] In some embodiments, the above Figure 3 is only for illustrative purposes and is not used to limit it.

[0094] In some embodiments, for the index of the termination node in the encoded data corresponding to the first instruction in step c, it may include: when there is only one edge starting from the first node in the directed path corresponding to the second instruction, setting the indices of the termination nodes of all edges in the directed path corresponding to the second instruction as an empty set; where the second instruction is one of the first instructions; and the first node is the starting node corresponding to the second instruction.

[0095] It can be understood that when there is only one edge starting from the first node in the directed path corresponding to the second instruction, it indicates that the second instruction can be compressed at this time. Therefore, setting the indices of the termination nodes of all edges in the directed path corresponding to the second instruction (i.e., code_skip) as an empty set, then this edge in the directed path corresponding to the second instruction can be omitted from code_skip. In this way, the encoded data can be managed more efficiently.

[0096] In some embodiments, in the above process, for the stack corresponding to the first instruction in step b, it can be obtained through the following steps: Step 1, compile the neural network structure through a compilation tool to obtain a model file corresponding to the neural network structure; Step 2, based on the stack acquisition function and / or extract code, obtain the stack corresponding to the first instruction from the model file.

[0097] Here, the model file can be understood as the file obtained after compiling the input neural network structure by a compilation tool. The compilation tool can be any tool chain related to the stackless processor for instruction generation, and the embodiments of the present disclosure do not make specific limitations thereto.

[0098] Understandably, for any neural network structure, by compiling it with a compilation tool, the model file corresponding to the neural network structure is obtained. After obtaining the model file, based on the stack acquisition function and / or extraction code, the stack corresponding to the first instruction can be obtained from the model file. In this way, the stack corresponding to the first instruction can be determined, which is convenient for subsequent determination of the source code mapping file.

[0099] In some embodiments, for step 1, the model file can be directly obtained after being compiled by the compilation tool, or can be pre-determined. The embodiments of the present disclosure do not make specific limitations thereto.

[0100] In some embodiments, for step 2, the stack acquisition function can be a backtrace-related function in C language, or can be other functions. The embodiments of the present disclosure do not make specific limitations thereto.

[0101] In some embodiments, for step 2, the extraction code can be pre-written code for obtaining instruction data. In one example, the extraction code can be inserted in the instruction layer to obtain the instruction data corresponding to the model file.

[0102] In some embodiments, in the above process, step 1 may include: compiling the neural network structure through the compiler layer of the compilation tool to obtain at least one operator; and generating the model file corresponding to the neural network structure by calling the implementation function and the instruction generation function through the multiplication operator in the at least one operator.

[0103] In some embodiments, for the compilation tool in the above step 1, its tool chain can be divided into three layers, from top to bottom: the compiler layer, the operator layer, and the instruction layer; or can be divided into two layers, namely: the compiler layer and the instruction layer. The method described in the embodiments of the present disclosure mainly acts on the instruction layer. Regardless of how many layers the tool chain of the compilation tool is divided into, in the case where the tool chain of the compilation tool includes the instruction layer, it does not affect the implementation of the method described in the embodiments of the present disclosure.

[0104] In one example, by compiling a neural network structure through the compiler layer of a compilation tool, at least one operator can be obtained. The at least one operator may include a multiplication operation operator (e.g., matmulOp); then, through the multiplication operation operator, an implementation function (e.g., impl_matmul) in the operator layer can be called, and according to the operator logic function (e.g., impl_matmul) of the multiplication operation operator, an instruction generation function (e.g., fma_gen_cmd) in the instruction layer can be called to generate an fma instruction, and thus a model file corresponding to the neural network structure can be obtained.

[0105] Figure 4 FIG. 4 is a schematic structural diagram of a compilation tool according to an exemplary embodiment. As Figure 4 shown, the compilation tool may include a compiler layer, an operator layer, and an instruction layer. Its input is a neural network structure, and its output is a model file.

[0106] In one example, Figure 4 the binary representation of a first instruction included in the model file output in 4 may be: 011001…01.

[0107] Based on the same inventive concept, an embodiment of the present disclosure provides a debugging device for instructions to execute the above-mentioned debugging method for instructions. Figure 5 FIG. 5 is a block diagram of a debugging device for instructions according to an exemplary embodiment. As Figure 5 shown, the device mainly includes: a first acquisition module 501 configured to acquire a debugging instruction of a target engine, where the target engine is a stackless processor; a first determination module 502 configured to determine encoded data corresponding to the debugging instruction based on a source code mapping file, where the source code mapping file is used to describe the mapping relationship between the instructions of the target engine and stack encodings, and the encoded data is used to indicate the stack encoding corresponding to the debugging instruction; a second determination module 503 configured to determine the position of the error source code based on the encoded data.

[0108] In some embodiments, the above-mentioned device further includes: a third determination module configured to determine a first instruction included in the target engine; a fourth determination module configured to use each layer of the stack corresponding to the first instruction as a node of a call graph, and use the call relationship between the (i + 1)-th layer and the i-th layer of the stack corresponding to the first instruction as a directed edge of the call graph to obtain a call graph of the stack corresponding to the first instruction, where i is a positive integer; a fifth determination module configured to determine the encoded data corresponding to the first instruction based on the call graph, and determine a source code mapping file corresponding to the target engine according to the call graph and the encoded data corresponding to the first instruction.

[0109] In some embodiments, the fourth determination module is further configured to perform the following steps: represent the stack corresponding to the first instruction as a first addressing list; in the case that at least one element in the first addressing list is not included in the first node list, add the at least one element to the first node list to obtain an updated first node list; in the case that the edge corresponding to two adjacent elements in the first addressing list is not included in the first directed edge list, add the edge corresponding to the two adjacent elements to the first directed edge list to obtain an updated first directed edge list; based on the updated first node list and the updated first directed edge list, obtain the call graph of the stack corresponding to the first instruction.

[0110] In some embodiments, the above apparatus further includes: a second acquisition module configured to acquire a second node list and a second directed edge list; an initialization module configured to perform an initialization operation on the second node list to obtain a first node list, and perform an initialization operation on the second directed edge list to obtain a first directed edge list.

[0111] In some embodiments, the fifth determination module is further configured to perform the following steps: represent the first instruction as a directed path based on the call graph; represent the first instruction in the form of a source code mapping encoding based on the directed path to obtain the encoded data corresponding to the first instruction; wherein the encoded data corresponding to the first instruction includes at least one of the following: the identification information of the first instruction, the total number of nodes included in the directed path corresponding to the first instruction, the index of the starting node of the directed path corresponding to the first instruction, and the indexes of the terminating nodes of all the edges in the directed path corresponding to the first instruction.

[0112] In some embodiments, the above apparatus further includes: a setting module configured to set the indexes of the terminating nodes of all the edges in the directed path corresponding to the second instruction as an empty set when only one edge starting from the first node is included in the directed path corresponding to the second instruction; wherein the second instruction is one of the first instructions; and the first node is the starting node corresponding to the second instruction.

[0113] In some embodiments, the above apparatus further includes: a sixth determination module configured to compile the neural network structure through a compilation tool to obtain a model file corresponding to the neural network structure; a third acquisition module configured to obtain the stack corresponding to the first instruction from the model file based on the stack acquisition function and / or the extracted code.

[0114] In some embodiments, the sixth determination module is further configured to perform the following steps: compile the neural network structure through the compiler layer of the compilation tool to obtain at least one operator; call an implementation function and an instruction generation function through the multiplication operation operator in the at least one operator to generate a model file corresponding to the neural network structure.

[0115] Regarding the device in the above embodiments, the specific manner in which each module performs operations has been described in detail in the embodiments related to the method, and will not be elaborated here.

[0116] Based on the same inventive concept, embodiments of the present disclosure provide an electronic device that can be used to implement the above-mentioned instruction debugging method. Figure 6 FIG. 600 is a block diagram of an electronic device 600 shown according to an exemplary embodiment. For example, the electronic device 600 can be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0117] Referring to Figure 6 , the electronic device 600 may include one or more of the following components: a processing component 602, a memory 604, a power component 606, a multimedia component 608, an audio component 610, an input / output (I / O) interface 612, a sensor component 614, and a communication component 616.

[0118] The processing component 602 generally controls the overall operation of the electronic device 600, such as operations associated with at least one of display, telephone call, data communication, camera operation, and recording operation. The processing component 602 may include one or more processors 620 to execute instructions to complete all or part of the steps of the above method. In addition, the processing component 602 may include one or more modules to facilitate the interaction between the processing component 602 and other components. For example, the processing component 602 may include a multimedia module to facilitate the interaction between the multimedia component 608 and the processing component 602.

[0119] The memory 604 is configured to store various types of data to support the operations on the electronic device 600. Examples of such data include at least one of the following: instructions for any application or method operating on the electronic device 600, contact data, phone book data, messages, pictures, and videos. The memory 604 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, a magnetic disk, or an optical disk.

[0120] The power supply component 606 provides power to various components of the electronic device 600. The power supply component 606 can include at least one of the following: a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 600.

[0121] The multimedia component 608 includes a screen that provides an output interface between the electronic device 600 and the user. In some embodiments, the screen can include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen can be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors can not only sense the boundaries of the touch or swipe actions, but also detect the duration and pressure associated with the touch or swipe operations. In some embodiments, the multimedia component 608 includes a front camera and / or a rear camera. When the electronic device 600 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera can receive external multimedia data. Each of the front camera and the rear camera can be a fixed optical lens system or have a focal length and optical zoom capabilities.

[0122] The audio component 610 is configured to output and / or input audio signals. For example, the audio component 610 includes a microphone (MIC). When the electronic device 600 is in an operation mode, such as a call mode, a recording mode, and a voice recognition mode, the microphone is configured to receive external audio signals. The received audio signals can be further stored in the memory 604 or sent via the communication component 616. In some embodiments, the audio component 610 further includes a speaker for outputting audio signals.

[0123] The I / O interface 612 provides an interface between the processing component 602 and a peripheral interface module, and the peripheral interface module may be a keyboard, a click wheel, buttons, etc. These buttons may include, but are not limited to: a home button, a volume button, a power button, and a lock button.

[0124] The sensor component 614 includes one or more sensors for providing an assessment of the status of various aspects of the electronic device 600. For example, the sensor component 614 can detect the on / off state of the electronic device 600, the relative positioning of components, such as the display and keypad of the electronic device 600. The sensor component 614 can also detect a change in the position of the electronic device 600 or a component in the electronic device 600, the presence or absence of user contact with the electronic device 600, the orientation or acceleration / deceleration of the electronic device 600, and the temperature change of the electronic device 600. The sensor component 614 can include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor component 614 can also include a light sensor, such as a complementary metal oxide semiconductor (CMOS) or a charge coupled device (CCD) image sensor, for use in imaging applications. In some embodiments, the sensor component 614 can further include at least one of the following, but is not limited to: an acceleration sensor, a gyro sensor, a magnetic sensor, a pressure sensor, and a temperature sensor.

[0125] The communication component 616 is configured to facilitate communication between the electronic device 600 and other devices in a wired or wireless manner. The electronic device 600 can access a communication standard-based wireless network, such as Wi-Fi, 4G, 5G, or a combination thereof. In an exemplary embodiment, the communication component 616 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 616 further includes a Near Field Communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on Radio Frequency Identification (RFID) technology, Infrared Data Association (IrDA) technology, Ultra Wide Band (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0126] In an exemplary embodiment, the electronic device 600 can be implemented by one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components.

[0127] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 604 including executable instructions or a computer program, and the above instructions or computer program can be executed by the processor 620 of the electronic device 600 to complete the above method. For example, the non-transitory computer-readable storage medium can be a ROM, a Random Access Memory (RAM), a Compact Disc Read-Only Memory (CD-ROM), magnetic tape, floppy disk, and optical data storage device, etc.

[0128] A non-transitory computer-readable storage medium, when the instructions in the storage medium are executed by the processor of the mobile terminal, enables the mobile terminal to execute any one of the debugging methods of the instructions in the embodiments of the present disclosure. For example, the method includes:

[0129] Obtain the debug instruction of the target engine, where the target engine is a stackless processor; based on the source code mapping file, determine the encoded data corresponding to the debug instruction, and the source code mapping file is used to describe the mapping relationship between the instructions of the target engine and the stack encoding, and the encoded data is used to indicate the stack encoding corresponding to the debug instruction; based on the encoded data, determine the location of the error source code.

[0130] An embodiment of the present disclosure provides a computer program product, which includes: a computer program or executable instructions, and the computer program or executable instructions are stored in a computer-readable storage medium. The processor of the computer device reads the computer program or executable instructions from the computer-readable storage medium, and the processor executes the computer program or executable instructions, so that the computer device executes the debug method of any one of the above instructions in the embodiment of the present disclosure.

[0131] Based on the same inventive concept, an embodiment of the present disclosure provides a server, which can be used to implement the debug method of the above instructions. Figure 7 is a block diagram of a server 700 shown according to an exemplary embodiment. Refer to Figure 7 , the server 700 includes a processing component 722, which further includes one or more processors, and memory resources represented by a memory 732 for storing instructions executable by the processing component 722, such as application programs. The application programs stored in the memory 732 may include one or more modules each corresponding to a set of instructions. In addition, the processing component 722 is configured to execute instructions to perform the debug method of any one of the above instructions. For example, the method includes:

[0132] Obtain the debug instruction of the target engine, where the target engine is a stackless processor; based on the source code mapping file, determine the encoded data corresponding to the debug instruction, and the source code mapping file is used to describe the mapping relationship between the instructions of the target engine and the stack encoding, and the encoded data is used to indicate the stack encoding corresponding to the debug instruction; based on the encoded data, determine the location of the error source code.

[0133] The server 700 may further include a power supply component 726 configured to perform power management of the server 700, a wired or wireless network interface 750 configured to connect the server 700 to a network, and an input / output (I / O) interface 758. The server 700 may operate an operating system stored in the memory 732, such as Windows ServerTM, Mac OSXTM, UnixTMLinuxTM, FreeBSDTM or the like.

[0134] Other embodiments of the present disclosure will be readily apparent to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include known or customary technical means in the art not disclosed herein. The specification and examples are only to be considered exemplary, and the true scope and spirit of the present disclosure are pointed out by the claims.

[0135] It should be understood that the present disclosure is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present disclosure is only limited by the appended claims.

Claims

1. A debugging method for instructions, characterized in that, Including: Obtaining a debug instruction of a target engine, where the target engine is a stackless processor; Based on a source code mapping file, determining encoded data corresponding to the debug instruction, where the source code mapping file is used to describe the mapping relationship between the instructions of the target engine and stack encodings, and the encoded data is used to indicate the stack encoding corresponding to the debug instruction; Based on the encoded data, determining the location of the error source code.

2. The method according to claim 1, characterized in that, The method further includes: Determining a first instruction included in the target engine; Taking each layer of the stack corresponding to the first instruction as a node of a call graph, and taking the call relationship between the (i + 1)-th layer and the i-th layer of the stack corresponding to the first instruction as a directed edge of the call graph, to obtain a call graph of the stack corresponding to the first instruction, where i is a positive integer; Based on the call graph, determining the encoded data corresponding to the first instruction, and according to the call graph and the encoded data corresponding to the first instruction, determining a source code mapping file corresponding to the target engine.

3. The method according to claim 2, wherein The taking each layer of the stack corresponding to the first instruction as a node of a call graph, and taking the call relationship between the (i + 1)-th layer and the i-th layer of the stack corresponding to the first instruction as a directed edge of the call graph, to obtain a call graph of the stack corresponding to the first instruction, includes: Representing the stack corresponding to the first instruction as a first addressing list; In the case that at least one element in the first addressing list is not included in a first node list, adding the at least one element to the first node list to obtain an updated first node list; In the case that an edge corresponding to two adjacent elements in the first addressing list is not included in a first directed edge list, adding the edge corresponding to the two adjacent elements to the first directed edge list to obtain an updated first directed edge list; Based on the updated first node list and the updated first directed edge list, obtaining a call graph of the stack corresponding to the first instruction.

4. The method according to claim 3, wherein The method further includes: Obtaining a second node list and a second directed edge list; Performing an initialization operation on the second node list to obtain a first node list, and performing an initialization operation on the second directed edge list to obtain a first directed edge list.

5. The method according to claim 2, characterized in that, The based on the call graph, determining the encoded data corresponding to the first instruction, includes: Based on the call graph, representing the first instruction as a directed path; Based on the directed path, representing the first instruction in a source code mapping encoding form to obtain the encoded data corresponding to the first instruction; Wherein, the encoded data corresponding to the first instruction includes at least one of the following: identification information of the first instruction, the total number of nodes included in the directed path corresponding to the first instruction, the index of the starting node of the directed path corresponding to the first instruction, and the indexes of the terminating nodes of all edges in the directed path corresponding to the first instruction.

6. The method according to claim 5, wherein The method further includes: When there is only one edge starting from a first node in the directed path corresponding to a second instruction, setting the indexes of the terminating nodes of all edges in the directed path corresponding to the second instruction as an empty set; Among them, the second instruction is one of the first instructions; the first node is the starting node corresponding to the second instruction.

7. The method according to claim 2, characterized in that The method further includes: compiling the neural network structure through a compilation tool to obtain a model file corresponding to the neural network structure; obtaining the stack corresponding to the first instruction from the model file based on a stack acquisition function and / or extraction code.

8. The method according to claim 7, wherein The compiling the neural network structure through a compilation tool to obtain a model file corresponding to the neural network structure includes: compiling the neural network structure through a compiler layer of the compilation tool to obtain at least one operator; generating a model file corresponding to the neural network structure by invoking an implementation function and an instruction generation function through a multiplication operation operator among the at least one operator.

9. A debugging device for instructions, characterized in that, including: a first acquisition module configured to acquire a debug instruction of a target engine, where the target engine is a stackless processor; a first determination module configured to determine encoded data corresponding to the debug instruction based on a source code mapping file, where the source code mapping file is used to describe a mapping relationship between instructions of the target engine and stack encodings, and the encoded data is used to indicate a stack encoding corresponding to the debug instruction; a second determination module configured to determine a location of an error source code based on the encoded data.

10. An electronic device, characterized in that, including: a processor; a memory for storing a computer program or instruction; Among them, the processor executes the computer program or instruction to implement the steps of the method according to any one of claims 1 to 8.

11. A non-transitory computer-readable storage medium storing a computer program or instructions, characterized in that, When the computer program or instruction in the storage medium is executed by the processor, the steps of the method according to any one of claims 1 to 8 are implemented.

12. A computer program product comprising a computer program or instructions, characterized in that, When the computer program or instruction is executed by the processor, the steps of the method according to any one of claims 1 to 8 are implemented.

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