Method for generating page table, method for verifying page table, electronic device and computer program product

Abstract

The invention discloses a page table generation method, a page table verification method, electronic equipment and a computer program product. The method for generating the page table comprises the following steps: receiving page table configuration information input by a user, wherein the page table configuration information comprises a first address, an address translation mode and translation granularity; determining an address mapping rule according to the address translation mode and the translation granularity; the multi-level page table is inquired according to an address mapping rule, the first address is translated into a second address, a page table descriptor and a page table descriptor address of each level of page table are generated in the process of translating the first address, and the page table descriptor comprises a page table base address of a next level of page table generated according to a preset rule or an output address of a current page table; and generating a target page table according to the page table descriptor and the page table descriptor address. According to the method provided by the embodiment of the invention, the page table capable of meeting the corresponding business requirements can be flexibly generated according to the page table configuration information input by the user, and the flexibility of constructing the page table is greatly improved.

Description

Technical Field

[0001] This specification relates to the technical field of memory management in computer systems. Specifically, it relates to address translation technology in the field of memory management, and more specifically, to a method for generating a page table, a method for verifying a page table, an electronic device, and a computer program product. Background Art

[0002] The System Memory Management Unit (SMMU) plays a crucial role in modern computing devices. Its main functions include address translation, memory access permission control, and cache management, etc. As a key data structure for the SMMU to implement the mapping from virtual memory to physical memory, the construction method of the page table has always been a research hotspot and technical difficulty in this field.

[0003] Currently, dedicated hardware tools can be used to construct the page table. These dedicated hardware tools can automatically complete complex address mapping calculations and page table entry initialization tasks. For example, some high-end systems use such dedicated hardware tools to construct the page table, which can improve the efficiency and accuracy of page table construction and management to a certain extent. In embedded systems, the page table can also be directly generated by firmware or system initialization code.

[0004] However, whether the page table is constructed through firmware or hardware tools, its flexibility is greatly limited and it is difficult to adapt to rapidly changing business requirements. Summary of the Invention

[0005] To solve the above technical problems, this application provides a method for generating a page table, a method for verifying a page table, an electronic device, and a computer program product, so as to achieve the purpose of improving the flexibility of page table construction and making the page table adapt to rapidly changing business requirements.

[0006] To achieve the above technical purpose, the embodiments of this application provide the following technical solutions:

[0007] In a first aspect, the embodiments of this application provide a method for generating a page table, and the method for generating a page table includes:

[0008] Receiving page table configuration information input by a user, where the page table configuration information includes: a first address, an address translation mode, and a translation granularity;

[0009] Determining an address mapping rule according to the address translation mode and the translation granularity, where the address mapping rule includes a mapping rule for translating the first address into a second address;

[0010] Query the multi-level page table according to the address mapping rule, translate the first address into the second address, and generate page table descriptors and page table descriptor addresses of each level of page table during the process of translating the first address, where the page table descriptor includes: the page table base address of the next-level page table generated according to a preset rule or the output address of the current page table;

[0011] Generate a target page table according to the page table descriptor and the page table descriptor address.

[0012] In a second aspect, an embodiment of the present application provides a method for verifying a page table. The method for verifying the page table includes:

[0013] Receive page table configuration information input by a user, where the page table configuration information includes: a first address, an address translation mode, and a translation granularity;

[0014] Determine an address mapping rule according to the address translation mode and the translation granularity, where the address mapping rule includes a mapping rule for translating the first address into a second address;

[0015] Query the multi-level page table according to the address mapping rule, translate the first address into the second address, and generate page table descriptors and page table descriptor addresses of each level of page table generated during the process of translating the first address, where the page table descriptor includes: the page table base address of the next-level page table generated according to a preset rule or the output address of the current page table;

[0016] Generate a target page table according to the page table descriptor and the page table descriptor address;

[0017] Store the target page table in a memory communicatively connected to the system memory management unit;

[0018] Send a translation request to the system memory management unit and obtain the result of the system memory management unit processing the translation request, where the translation request includes the first address.

[0019] In a third aspect, an embodiment of the present application provides an electronic device, including a processor configured to execute the method for generating a page table as described in the first aspect or the method for verifying a page table as described in the second aspect.

[0020] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is run by a processor, it implements the method for generating a page table as described in the first aspect or the method for verifying a page table as described in the second aspect.

[0021] Fifth aspect, an embodiment of the present application provides a computer program product, on which a computer program is stored. When the computer program is executed by a processor, it implements the method for generating a page table as described in the first aspect or the method for verifying a page table as described in the second aspect.

[0022] The method for generating a page table provided by the embodiment of the present application can meet rapidly changing business requirements. A user inputs page table configuration information based on business requirements, where the page table configuration information includes: a first address, an address translation mode, and a translation granularity. Then, according to the address translation mode and the translation granularity, an address mapping rule is determined, where the address mapping rule includes a mapping rule for translating the first address into a second address. By simulating the process of querying multi-level page tables during translation, the first address is translated into the second address, and page table descriptors and page table descriptor addresses of each level of page tables are generated during the process of translating the first address. Since the page table descriptors and page table descriptor addresses record key information of the page tables. Therefore, a target page table that meets business requirements can be generated according to the page table descriptors and the page table descriptor addresses. The method provided in this embodiment can flexibly generate a page table that meets corresponding business requirements according to the page table configuration information input by the user, greatly improving the flexibility of building a page table. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained according to the provided drawings without creative efforts.

[0024] Figure 1 It is a schematic flowchart of a method for generating a page table provided by an embodiment of the present application;

[0025] Figure 2 It is a schematic structural diagram of a tabledescriptor;

[0026] Figure 3 It is a schematic structural diagram of a block descriptor;

[0027] Figure 4 It is a schematic structural diagram of a page descriptor;

[0028] Figure 5 It is one of the schematic diagrams of the process of looking up a multi-level page table in an embodiment of the present application;

[0029] Figure 6 It is the second of the schematic diagrams of the process of looking up a multi-level page table in an embodiment of the present application;

[0030] Figure 7 It is the third schematic diagram of the page table lookup process in the embodiment of the present application;

[0031] Figure 8 It is the fourth schematic diagram of the page table lookup process in the embodiment of the present application;

[0032] Figure 9 It is the fifth schematic diagram of the page table lookup process in the embodiment of the present application;

[0033] Figure 10 It is the schematic flowchart of a page table verification method provided by the embodiment of the present application;

[0034] Figure 11 It is the schematic diagram of the verification environment of the target page table provided by the embodiment of the present application;

[0035] Figure 12 It is the schematic diagram of the process of verifying the target page table provided by the embodiment of the present application;

[0036] Figure 13 It is the structural block diagram of a page table generation device provided by the embodiment of the present application;

[0037] Figure 14 It is the structural block diagram of a page table verification device provided by the embodiment of the present application;

[0038] Figure 15 It is the schematic diagram of the structure of an electronic device provided by an embodiment of the present application. Detailed implementation manners

[0039] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of this specification should have the ordinary meanings understood by those of ordinary skill in the field to which this specification belongs. The "first", "second" and similar terms used in the embodiments of this specification do not represent any order, quantity or importance, but are only used to avoid confusion of components.

[0040] Unless otherwise required by the context, throughout this specification, "a plurality" means "at least two", and "including" is interpreted as an open and inclusive meaning, that is, "including, but not limited to". In the description of this specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "examples", "specific examples" or "some examples", etc. are intended to indicate that specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of this specification. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the embodiments described below can be understood as implementation manners.

[0041] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings in the embodiments of this specification. Obviously, the described embodiments are only a part of the embodiments of this specification, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in this specification without creative efforts shall fall within the scope of protection of this specification.

[0042] Overview

[0043] As described in the background art, the method of constructing a page table has always been a research hotspot and technical difficulty in the technical field of the system memory management unit. By using a dedicated hardware tool to construct a page table, the function of this hardware tool is usually relatively powerful. In addition to being difficult to adapt to the rapidly changing business requirements, the cost of this hardware tool is also very high. In an embedded system, by generating a page table through firmware or system initial code, its flexibility and scalability will be greatly limited, and it is also difficult to adapt to the rapidly changing business requirements.

[0044] It can be understood that in actual business or verification environments, it is usually necessary to construct a page table that can meet the specified business requirements according to the business requirements. In scenarios with variable and rapidly changing business requirements, whether using a hardware tool or firmware, it is difficult to meet the requirements. For this reason, in some solutions, a method of manual static configuration can be used to construct a page table, that is, the construction and management of the page table are usually flexibly configured based on business requirements through manual or static tools. However, this method involves complex configuration files or manual editing of page table entries, and its operation is cumbersome and error-prone. Therefore, there is currently no good solution that can automatically construct a page table while adapting to rapidly changing business requirements.

[0045] In view of the above technical status quo, the inventors of the present application propose that in order to adapt to rapidly changing business requirements, users can flexibly input page table configuration information according to current business requirements. Then, based on the page table configuration information, simulate the process of querying multi-level page tables during translation, and finally generate a page table according to the page table descriptors and page table descriptor addresses generated during the translation process. Furthermore, an embodiment of the present application proposes a method for generating a page table, which can cope with rapidly changing business requirements. The user inputs page table configuration information based on business requirements, where the page table configuration information includes: a first address, an address translation mode, and a translation granularity. Then, according to the address translation mode and the translation granularity, determine an address mapping rule, where the address mapping rule includes a mapping rule for translating the first address into a second address. By simulating the process of querying multi-level page tables during translation, translate the first address into the second address, and generate page table descriptors and page table descriptor addresses for each level of page table during the process of translating the first address. Since the page table descriptors and page table descriptor addresses record key information of the page table. Therefore, a target page table that meets business requirements can be generated according to the page table descriptors and the page table descriptor addresses. The method provided in this embodiment can flexibly generate a page table that meets corresponding business requirements according to the page table configuration information input by the user, greatly improving the flexibility of constructing the page table.

[0046] Exemplary method

[0047] An embodiment of the present application provides a method for generating a page table, which is applied to an electronic device. The electronic device has the ability to process data and can process data according to the method provided in this embodiment and finally generate a target page table. In some embodiments, the electronic device has the ability to run application programs or code. For example, a script (such as a Python script, but not limited to this) can be designed according to the steps of generating the target page table in the present application and run the script in the electronic device to generate the target page table. The electronic device includes but is not limited to: servers, computers, and smart phones. As Figure 1 shown, the method for generating a page table includes:

[0048] S101: Receive page table configuration information input by the user, where the page table configuration information includes: a first address, an address translation mode, and a translation granularity.

[0049] In this step, the translation granule (TG) can be understood as the size of the memory block processed in a single operation during the address translation process. For example, the translation granule can be 4KB, 16KB, 64KB, etc. The address translation mode defines the hierarchical logic of address conversion. For example, the address translation modes include: only stage1, only stage2, and nested. Among them, the only stage1 mode means only stage 1. In the address translation process of this mode, the virtual address (VA) is usually translated into the intermediate physical address (IPA). The only stage2 mode means only stage 2. In the address translation process of this mode, the IPA is usually translated into the physical address (PA). The nested mode means nested, and it is necessary to combine stage1 and stage2 for address translation. In the address translation process of this mode, the VA is usually first translated into IPA by using stage1, and then the IPA is translated into PA by using stage2. The first address represents the address before translation. For example, if the address translation mode is only stage1, then the first address is the virtual address; if the address translation mode is only stage2, then the first address is the intermediate physical address.

[0050] It can be understood that the specific contents of the first address, the address translation mode, and the translation granule are related to the actual business requirements. Users can determine the specific contents of the three based on the actual business requirements, and then input the page table configuration information. For example, the actual business requirements include: when using the page table to translate the address, it is necessary to be in the only stage2 mode, the translation granule is 64KB, and the IPA before translation is 0x2000_0000. Then, the page table configuration information will include: 0x2000_0000, only stage2, and 64KB.

[0051] In some embodiments, different fields can be used to represent the first address, address translation mode, and translation granularity respectively. For example, the STE.config field represents the address translation mode. When the field value is 3'b0xx, it is judged as an invalid value; when the field value is 3'b100, no page table needs to be generated; when the field value is 3'b101, it is judged as the only stage1 mode; when the field value is 3'b110, it is judged as the only stage2 mode; when the field value is 3'b111, it is judged as the nested mode. The STE.S2TG field represents the translation granularity in the stage2 mode. Among them, only when the field value of the STE.config field is 3'b101 or 3'b111, that is, in the only stage2 or nested mode, it is valid. When the field value is other values, this parameter does not need to be configured, and the default value of this parameter is 0. When the field value of the STE.S2TG field is 2'b00, the translation granularity is 4KB; when the field value is 2'b01, the translation granularity is 64KB; when the field value is 2'b10, the translation granularity is 16KB; when the field value is 2'b11, it is an illegal value and the program reports an error. The VA field represents the address. Then in the actual business requirements including: when translating the address using the page table, in the only stage2 mode, the translation granularity is 64KB, and the IPA before translation is 0x2000_0000, the page table configuration information can include: STE.config = 3'b110, STE.S2TG = 2'b01, VA = 0x2000_0000.

[0052] In some embodiments, the page table configuration information can also include other information that acts on the page table translation process in addition to the first address, address translation mode, and translation granularity, which will not be elaborated here. Similarly, the specific content of this other information is also related to the actual business requirements.

[0053] S102: Determine the address mapping rule according to the address translation mode and the translation granularity.

[0054] It should be noted that in the process of translating the address using the page table, the specific translation strategy is usually jointly determined by the address translation mode and the translation granularity. Therefore, here the address mapping rule is determined through the address translation mode and the translation granularity, and then the process of translating the address using the page table is simulated using the address mapping rule. Among them, the address mapping rule includes the mapping rule for translating the first address into the second address.

[0055] In some embodiments, different combinations of address translation modes and translation granularities are used as indexes, and then corresponding address mapping rules are set for each index. Thus, when executing S102, the corresponding address mapping rules can be determined based on the specific content of the page table configuration information. For example, index 1 consists of only stage1 and 4KB, and its corresponding address mapping rule is rule 1. Index 2 consists of only stage2 and 4KB, and its corresponding address mapping rule is rule 2. Index 3 consists of nested and 4KB, and its corresponding address mapping rule is rule 3. Index 4 consists of only stage1 and 16KB, and its corresponding address mapping rule is rule 4. Index 5 consists of only stage2 and 16KB, and its corresponding address mapping rule is rule 6. When the page table configuration information includes nested and 4KB, the address mapping rule can be determined as rule 3.

[0056] S103: Query the multi-level page table according to the address mapping rule, translate the first address into the second address, and generate page table descriptors and page table descriptor addresses of each level of the page table during the process of translating the first address.

[0057] S104: Generate a target page table according to the page table descriptor and the page table descriptor address.

[0058] It should be noted that the process of address translation using a page table generally includes querying the multi-level page table in a table lookup manner, so as to translate the first address into the second address. This embodiment will simulate this process, and in each table lookup process, key information of the corresponding page table, that is, page table descriptors and page table descriptor addresses, will be generated according to the requirements of the table lookup. Thus, the smoothness of the table lookup process can be ensured. After obtaining the second address at the end of the table lookup, the key information generated for each level of the page table will be used as the key information for generating the target page table, and finally the required target page table will be generated based on this. The target page table generated in this way can smoothly implement the address translation process under the indication of the page table configuration information. That is, the target page table can be regarded as a page table generated according to the actual business requirements.

[0059] It can be understood that the page table descriptor, which is the descriptor of the page table, can generally be divided into: table descriptor, block descriptor, and page descriptor. In some embodiments, in the page tables of level0, level1, and level2, the page table descriptors of the page tables can generally be divided into table descriptor and block descriptor. For example, when Descriptor bit[1] is 0, it indicates that the page table descriptor is a block descriptor, and when Descriptor bit[1] is 1, it indicates that the page table descriptor is a table descriptor. In the page table of level3, there is usually only a page descriptor, and Descriptor bit[1] is 1. For the data structures of table descriptor, block descriptor, and page descriptor, reference can be made to Figures 2 - 4 . Figure 2 Taking 64 bits as an example, the table descriptor represents the starting address of the next-level page table through bits m to 47. Figure 3 Similarly taking 64 bits as an example, the block descriptor represents the output address through bits n to 47. Figure 4 Continuing to take 64 bits as an example, the page descriptor can represent the output address through bits 12 to 47. Therefore, the page table descriptor generally contains the starting address of the next-level page table or the output address. In this embodiment, these addresses will be automatically generated according to certain rules and used as the key information of the page table descriptor. Therefore, the page table descriptor includes: the page table base address of the next-level page table or the output address of the current page table generated according to the preset rules. The page table descriptor address is the address of the page table descriptor. Through the page table descriptor address, the corresponding page table descriptor can be found.

[0060] In some embodiments, the generated target page table can be used only to process translation requests carrying a first address, so that only one page table entry will be found in each level of the page table. That is to say, only one page table entry will be involved in each level of the page table. Since no other page table entries are involved, the page table descriptor of each level of the page table can also be regarded as the descriptor of the corresponding page table entry in the page table. The page table descriptor address can be regarded as the address of the corresponding page table entry. For example, during the process of using the target page table to process a translation request carrying a first address, the second page table entry of the level 0 page table, the third page table entry of the level 1 page table, and the fourth page table entry of the level 2 page table are sequentially found. Then, the descriptor of the second page table entry of the level 0 page table can be used as the page table descriptor of the level 0 page table. The descriptor of the third page table entry of the level 1 page table can be used as the page table descriptor of the level 1 page table. The descriptor of the fourth page table entry of the level 2 page table can be used as the page table descriptor of the level 3 page table.

[0061] In some embodiments, in the case of involving multi-level table lookup, the page table descriptors and page table descriptor addresses at each level can be adjusted to a data structure with a one-to-one correspondence setting, and then used as the target page table. Of course, the page table descriptors and page table descriptor addresses can also be formatted according to the form of the existing page table data format to generate the target page table, which will not be elaborated here.

[0062] Embodiments of the present application can meet rapidly changing business requirements. The user inputs page table configuration information based on business requirements, where the page table configuration information includes: a first address, an address translation mode, and a translation granularity. Then, according to the address translation mode and the translation granularity, an address mapping rule is determined, where the address mapping rule includes a mapping rule for translating the first address into a second address. By simulating the process of querying multi-level page tables during translation, the first address is translated into the second address, and page table descriptors and page table descriptor addresses at each level are generated during the process of translating the first address. Since the page table descriptors and page table descriptor addresses record key information of the page table. Therefore, a target page table that meets business requirements can be generated according to the page table descriptors and page table descriptor addresses. The method provided in this embodiment can flexibly generate a page table that meets corresponding business requirements according to the page table configuration information input by the user, greatly improving the flexibility of constructing the page table.

[0063] In some embodiments of the present application, querying multi-level page tables according to the address mapping rule, translating the first address into the second address, and recording the page table descriptors and page table descriptor addresses generated during the translation process includes:

[0064] Determine each level of page table that needs to be queried during the translation process according to the address mapping rule;

[0065] For each level of page table to be queried, perform the query operation in sequence, and generate the page table descriptor and the page table descriptor address for each level of page table until the first address is translated into the second address.

[0066] It should be noted that when simulating the process of address translation using the page table through the address mapping rule, the page tables usually required to be queried are multi-level page tables, and the address translation is finally realized through table lookups at each level. For the sake of understanding, the table lookup process is described below. For example, in the case where the address translation mode is only stage1, the translation granularity is 4KB, and the levels of the page tables to be queried involve level0, level1, level2, and level3, the table lookup process is as Figure 5 shown, including:

[0067] After obtaining the translation table base address, use [47:39] of the first address to index to the page table descriptor of the level 0 page table or the descriptor of the corresponding page table entry in the level 0 page table. For unified description, the page table descriptor is used in the following description. Here, [47:39] represents the 39th bit to the 47th bit, and the same expression will not be explained below. The page table base address of the level 1 page table is stored in the page table descriptor of the level 0 page table, and then the level 1 page table is found based on this. Then use [38:30] of the first address to index to the page table descriptor of the level 1 page table. The page table base address of the level 2 page table is stored in the page table descriptor of the level 1 page table, and then the level 2 page table is found based on this. According to this rule, the page table descriptor of the level 3 page table is found, and [47:12] of the output address is obtained from it, and it is concatenated with [11:0] of the first address to get the second address.

[0068] It can be understood that during the simulation of the table lookup process, record the address of the found page table or page table entry and use it as the page table descriptor address. At the same time, the page table base address of the next-level page table is included in the page table descriptor generated for the found page table or page table entry. Thus, during the simulation of the table lookup process, the page table descriptor and the page table descriptor address required to generate the target page table can be obtained.

[0069] In the embodiments of the present application, the table lookup process of the multi-level page table is simulated, so that the page table descriptor and the page table descriptor address required to generate the target page table can be obtained during the process.

[0070] In order to further improve the flexibility of constructing the page table, in some embodiments of the present application, the page table configuration information further includes: the page table level; the method further includes: during the process of translating the first address, setting the type of the first page table to a block descriptor and setting the type of the second page table to a table descriptor;

[0071] Among them, the first - level page table includes: the page table with the same page - table level as that in the page - table configuration information during the translation of the first address; the second - level page table includes: the page tables other than the first - level page table during the translation of the first address.

[0072] It should be noted that each page - table entry of the page table will be mapped to different memory regions. In some actual business scenarios or page - table verification scenarios, it is necessary to limit the memory regions mapped by the page - table entries. Among them, the size of the memory region mapped by the page - table entry is usually determined by the translation granularity and the page - table level. The relationship among the three is shown in Table 1 below:

[0073]

[0074]

[0075] Table 1

[0076] For example, for the target page table to be constructed, the size of the memory region mapped by its page - table entry is 2MB. Then, the translation granularity in the page - table configuration information needs to be set to 4KB, and the page - table level needs to be set to 2.

[0077] It should be noted that the block descriptor is the block descriptor in the above - mentioned embodiment, and the table descriptor is the table descriptor in the above - mentioned embodiment. To avoid repetition, they will not be repeated here. In addition, during the process of looking up the multi - level page table, unless the page - table level of the last - level page table is level3, the type of the last - level page table is usually the block descriptor to ensure that the output address is stored through the page - table descriptor of the last - level page table, and further the final address translation is realized with the help of the output address. Taking the translation granularity of 4KB and the page - table level of 3 as an example, for the generated target page table, during the translation process / multi - level look - up process, four page tables will be found in sequence, namely the four page tables of level 0, level 1, level 2, and level3. Among them, the types of the three page tables of level 0, level 1, and level2 should be table descriptor, and the type of the level 3 page table should be page descriptor. Another example, taking the translation granularity of 16KB and the page - table level of 2 as an example, for the generated target page table, during the translation process / multi - level look - up process, three page tables will be found in sequence, namely the three page tables of level 0, level 1, and level2. Among them, the types of the two page tables of level 0 and level 1 should be table descriptor, and the type of the level2 page table should be block descriptor.

[0078] Therefore, during the process of querying the multi-level page table according to the address mapping rule, the type of each level of page table will be determined based on the page table level. That is, determine which one of the following the descriptor of the page table is: tabledescriptor, block descriptor, or pagedescriptor. Then select the determined type to construct the page table descriptor. For example, after querying the level 1 page table, first determine whether the page table level in the page table configuration information is level 1. If not, then determine that the type of the level 1 page table is tabledescriptor. Construct the page table descriptor of the level 1 page table according to the structure of tabledescriptor. If so, then determine that the type of the level 1 page table is block descriptor. Construct the page table descriptor of the level 1 page table according to the structure of block descriptor.

[0079] In the embodiments of the present application, the page table level can be specified during the process of constructing the target page table, so as to generate page table entries with a specified mapped memory area size according to the actual business requirements, thereby further improving the flexibility of constructing the page table.

[0080] In order to avoid the inability to correctly generate the target page table due to violating the multi-level page table query rule, in some embodiments of the present application, after receiving the page table configuration information input by the user, the method further includes:

[0081] Determine whether the page table level in the page table configuration information is legal based on the legal detection rule, and output a prompt message in the case of illegality;

[0082] Among them, the legal detection rule includes at least one of the following:

[0083] When the translation granularity is 4 kilobytes, the page table level shall not be 0;

[0084] When the translation granularity is 16 kilobytes, the page table level shall not be 0 or 1;

[0085] When the translation granularity is 64 kilobytes, the page table level shall not be 0 or 1.

[0086] It should be noted that during the subsequent use of the generated target page table, the first address will be translated according to the multi-level page table query rule. Therefore, it should follow the multi-level page table query rule. If the process of constructing the target page table does not follow the multi-level page table query rule, it is bound to be unable to correctly generate the target page table. It may be the case that the target page table cannot be generated, or it may be the case that the generated target page table cannot correctly translate the first address. Whichever case occurs, it has a negative impact on the entire process of verifying the target page table. For this reason, in this embodiment, a checking mechanism can be set when constructing the target page table to prevent problems caused by the target page table not conforming to the multi-level page table query rule.

[0087] It can be understood that in this embodiment, the legal detection rule is the multi-level page table query rule, that is, the constraint between the translation granularity and the page table level. Regarding the specific constraint content, it will not be elaborated here. For the prompt information, it can take the non-compliance between the translation granularity and the page table level as the reminder content and output it to the user in any way. For example, it can output the text content: The translation granularity and the page table level do not meet the constraint conditions. Please modify the translation granularity or the page table level again.

[0088] In the embodiment of the present application, by setting the legal detection rule to constrain the relationship between the translation granularity and the page table level, it is possible to avoid the inability to correctly generate the target page table due to violation of the multi-level page table query rule.

[0089] To further improve the flexibility of constructing the target page table, in some embodiments of the present application, the page table configuration information further includes: a plurality of page table attributes, and the page table descriptor of the third page table includes a plurality of page table attribute fields, and the third page table includes: the last-level page table in the process of translating the first address; the method further includes:

[0090] When generating the page table descriptor of the third page table, write the plurality of page table attributes in the page table configuration information into the plurality of page table attribute fields of the page table descriptor of the third page table.

[0091] It should be noted that as the last-level page table in a multi-level page table, its type is usually block descriptor or page descriptor. It usually contains fields such as Upper block attributes, Lower block attributes, and nT, which are used to store page table attribute values to represent the various page table attributes of the page table. These page table attributes are of great significance during the use of the page table. Therefore, corresponding page table attributes can be set based on actual business requirements or verification requirements to further enhance the flexibility of constructing the target page table. Regarding fields such as Upper block attributes, Lower block attributes, and nT, Upper block attributes define the attributes for the next-level translation table, such as access permission restrictions, etc., and Lower block attributes are used to control memory sharing attributes and access permissions, etc. nT can be used as a special function indicator or to control the behavior of the TLB (Translation Lookaside Buffer), which will not be elaborated here.

[0092] In the embodiments of the present application, corresponding page table attributes can be set based on actual business requirements or verification requirements, thereby further enhancing the flexibility of constructing the target page table.

[0093] To avoid page tables with address conflicts in the target page table, in some embodiments of the present application, the addresses in the page table descriptors of page tables at all levels are completely different.

[0094] It should be noted that the address in the page table descriptor of page tables at all levels is usually the page table start address or output address of the next-level page table. During the subsequent use of the target page table, the storage location of each level of page table will be determined according to the address in the page table descriptor of its upper-level page table. Only in this way can each level of page table be accurately found during the multi-level table lookup process. If there is an address conflict in the target page table, or in other words, there are duplicate addresses in the page table descriptors of page tables at all levels. Then, problems are bound to occur during the subsequent use of the target page table. Therefore, this problem should be considered and solved in advance during the process of constructing the target page table. That is, when generating the page table descriptors of page tables at all levels, it is necessary to ensure that their addresses do not duplicate. In some embodiments, a large number of non-duplicate addresses can be preset, and when generating the page table descriptor of each level of page table, an address is sequentially obtained from them as the address in the page table descriptor. In other embodiments, a set of rules for generating non-duplicate addresses can be pre-designed, and when generating the page table descriptor of each level of page table, an address is generated using this rule as the address in the page table descriptor.

[0095] In the embodiments of the present application, it is possible to avoid duplicate addresses in the page table descriptors of page tables at all levels, and solve problems such as memory management chaos and program exceptions caused by duplicate addresses.

[0096] For the convenience of quickly generating the addresses in the page table descriptors, in some embodiments of the present application, the addresses in the page table descriptors of page tables at all levels are randomly generated.

[0097] It should be noted that for the page table descriptors and the addresses they contain, reference can be made to the above embodiments, which will not be elaborated here. Similarly, if there are duplicate addresses in the page table descriptors of page tables at all levels, the problems caused are usually significant. To quickly generate addresses for the page table descriptors and take into account the problem of duplicate addresses, the addresses can be randomly generated in a random manner. It can not only quickly generate addresses, but also greatly reduce the probability of duplicate addresses. In some embodiments, to avoid duplicate addresses in the randomly generated addresses, after randomly generating an address, it can be checked whether there is the same address in the previous page table descriptors at all levels. If not, the currently randomly generated address is used as the address in the page table descriptor of the current-level page table. If there is the same address, a new address is randomly generated again until the generated address is completely different from the addresses in the previous page table descriptors at all levels.

[0098] It can be understood that the number of bits of the randomly generated address can be less than or equal to the number of bits required for the start address of the next-level page table or the output address in the page table descriptor. In some embodiments, when it is less than the number of bits required for the start address of the next-level page table or the output address in the page table descriptor, after randomly generating an address, the address is used as the high-order part of the address in the page table descriptor, and the low-order part can be filled with all zeros to complete the number of bits.

[0099] In the embodiments of the present application, the addresses in the page table descriptors can be randomly generated in a random manner, which can not only quickly generate addresses, but also greatly reduce the probability of duplicate addresses.

[0100] In some embodiments of the present application, when the address translation mode in the page table configuration information is the first address translation mode or the second address translation mode, the page table configuration information further includes: an initial page table base address;

[0101] In the process of querying a multi-level page table according to the address mapping rule and translating the first address into the second address, the initial page table base address in the page table configuration information is determined as the page table base address of the first-level page table;

[0102] The first address translation mode indicates translating a virtual address into an intermediate physical address, and the second address translation mode indicates translating the intermediate physical address into a physical address.

[0103] It should be noted that the first address translation mode can be only stage1 in the above embodiments, and the second address translation mode can be only stage2 in the above embodiments. For only stage1 and only stage2, refer to the relevant descriptions in the above embodiments and will not be repeated here. The first-level page table is the page table first queried in the multi-level table lookup process. For example, the first-level page table can usually be the level 0 page table, but it is not limited thereto. For another example, when the translation granularity is 16KB and the address translation mode is only stage2, the first-level page table is the level 1 page table. In this embodiment, the page table base address of the first-level page table can be specified. In some embodiments, when the page table configuration information represents the page table base address through a field, the STE.S2TTB field can be used to represent the translation table base address in the only stage2 mode (i.e., the page table base address of the first-level page table, and the same description will be used hereinafter without further explanation), which can be 48 bits. For example, it can be valid only when STE.config is 3’b101 or 3’b111, that is, in the only stage2 or nested mode, and this parameter does not need to be configured when STE.config is other values, and the default value of this parameter is 0. The CD.TTB field can be used to represent the translation table base address in the only stage1 mode, which can be 48 bits. For example, it can be valid only when STE.config is 3’b100 or 3’b111, that is, in the only stage1 or nested mode, and this parameter does not need to be configured when STE.config is other values, and the default value of this parameter is 0.

[0104] It can be understood that the translation table base address, translation granularity, address translation mode, page table level, etc. jointly affect the translation process of the target page table and also affect the process of constructing the target page table. In this embodiment, the process of constructing the target page table will be further described in combination with the multi-level page table lookup process. At the same time, the differences in the process of constructing the target page table will be described in combination with key factors such as the translation table base address, translation granularity, address translation mode, and page table level.

[0105] Continue to refer to Figure 5, when the address translation mode is only stage1, the translation granularity is 4KB, and the page table level is level3, the page table base address of the first-level page table in the page table configuration information is used as the translation table base address. For example, the translation table base address can be determined by CD.TTB. The corresponding tabledescriptor address is indexed by [47:39] of the first address, and the address is recorded in the page table address sequence. Build the tabledescriptor of the level 0 page table. For example, fill the Next-leveltable address[47:12] field with a randomly generated address and zero-extend the lower bits to form a 48-bit address. The address in the final field is the base address of the level 1 page table, and the tabledescriptor is recorded in the page table data sequence. And so on until the current page table is the level 3 page table, since its level 3 is the same as the level3 in the page table configuration information. Therefore, a page descriptor will be built. The corresponding page descriptor address is indexed by [20:12] of the first address, and the address is recorded in the page table address sequence. The page descriptor structure is as Figure 4 shown and will not be elaborated here. Build the page descriptor of the current page table based on the page descriptor structure. For example, the Output address field can be randomly generated by a python script, and the Upper attributes and Lowerattributes are filled according to the input page table attribute values, and together they form a page descriptor and are recorded in the page table data sequence. The page table address sequence records the page table descriptor address, and the page table data sequence records the page table descriptor. Thus, the final target page table can be generated based on the two sequences.

[0106] It should be noted that if the page table level in the page table configuration information is different, there will be certain differences from the above process. For example, only change the page table level in the page table configuration information, for example, change it to level 1. Then the above process can only proceed to the level 1 page table, as Figure 6 shown. When the current-level page table is the level 0 page table, the process is the same as Figure 5The corresponding process is the same as above and will not be elaborated here. When the current page table is a level 1 page table, since its level 1 is the same as that in the page table configuration information, a block descriptor will be constructed. Among them, the Output address[47:30] field is concatenated with the [29:0] of the first address to obtain the second address of the final translation result. For example, the Output address is randomly generated by a python script, and the Upper block attributes and Lower block attributes of the descriptor are filled according to the input page table attribute values, and together they form a block descriptor and are recorded in the page table data sequence. Of course, if the page table level in the page table configuration information is not level 1, then a table descriptor is constructed. For example, the Next-level table address[47:12] field is filled with a randomly generated address, and it is zero-extended to a 48-bit address with all low bits being zero. The address in the final field is the base address of the level 1 page table, and the table descriptor is recorded in the page table data sequence. In addition, if the address translation mode in the above scenario is changed to only stage2, the process is basically the same as the above process. The difference is that in the only stage2 mode, the first address is the intermediate physical address, and the second address is the physical address. While in the only stage2 mode, the first address is the virtual address, and the second address is the intermediate physical address.

[0107] See Figure 7 , in the case where the address translation mode is only stage1 and the translation granularity is 16KB, the process of constructing the target page table and performing multi-level table lookups using the target page table is similar to the above Figure 5 and Figure 6 shown process and will not be elaborated here. It should be noted that compared with the above Figure 5 and Figure 6 shown process, Figure 7 The difference in the processing method in the shown scenario is that the division method of the input first address is different, and 11 bits of the first address are parsed each time. In the case where the address translation mode is only stage2 and the translation granularity is 16KB, the process of constructing the target page table is similar to the process of constructing the target page table in the case where the address translation mode is only stage1 and the translation granularity is 16KB. The difference between the two is that when the first-level page table is a level 1 page table and indexing the page table entries of the level 1 page table, the [47:36] bits of the first address are used.

[0108] See Figure 8, when the address translation mode is only stage1 or only stage2 and the translation granularity is 64KB, the process of constructing the target page table and performing multi-level lookups using the target page table is similar to the process shown in the above Figure 5 and Figure 6 and will not be elaborated here. It should be noted that, compared with the process shown in the above Figure 5 and Figure 6 , the difference in the processing method in the scenario shown in Figure 8 is that the division method of the input first address is different. The first address of 13 bits is parsed each time, and when indexing the page table entries of the first-level page table, which is the level 1 page table, the bits [47:42] of the first address are used.

[0109] In the embodiments of the present application, the initial page table base address can be specified to further improve the flexibility of constructing the target page table and meet the service requirements of starting the lookup at a specified address.

[0110] In some embodiments of the present application, when the address translation mode in the page table configuration information is the third address translation mode, the page table descriptor addresses of each level of page table are generated during the translation of the first address, including:

[0111] For each page table queried during the translation of the first address, the address obtained by translating the page table base address of the currently queried page table according to the second address translation mode is concatenated with the corresponding bits in the first address to obtain the target address, and the target address is determined as the page table descriptor address of the currently queried page table;

[0112] Among them, the third address translation mode indicates that the virtual address is first translated into an intermediate physical address, and then the intermediate physical address is translated into a physical address; the second address translation mode indicates that the intermediate physical address is translated into a physical address.

[0113] It should be noted that the first address translation mode can be only stage1 in the above embodiments, the second address translation mode can be only stage2 in the above embodiments, and the third address translation mode can be nested in the above embodiments. For only stage1, only stage2, and nested, reference can be made to the relevant descriptions in the above embodiments and will not be repeated here.

[0114] It can be understood that the process of constructing the target page table under nested and performing multi-level table lookups using the target page table is similar to the process of constructing the target page table and performing multi-level table lookups under only stage1 and only stage2. To avoid repetition, it will not be elaborated here. Below, taking the address translation mode as nested and the translation granularity as 64KB as an example, the process of constructing the target page table will be exemplarily described. As Figure 9 shown, the intermediate physical address can be obtained based on STE.S1ContextPtr, and then the translation table base address is obtained through stage2 translation of the intermediate physical address.

[0115] Enable stage1 translation. The translation table base address is again translated through stage2 to obtain the corresponding physical address, thereby finding the level 1 page table. Then, the corresponding table descriptor address is indexed through the first address [47:42], and the address is recorded in the page table address sequence. Construct a table descriptor. The Next-leveltable address[47:16] field in this table descriptor is filled with an address randomly generated by a python script and zero-extended to a 48-bit address at the low bits, which is the base address (IPA) of the stage 1 level 2 page table. Record the table descriptor in the page table data sequence.

[0116] The base address (IPA) of the stage 1 level 2 page table is translated through stage 2 to obtain the base address (PA) of the stage 1 level 2 page table. If the page table level in the page table configuration information is not 2, then the page table at this level is a table descriptor, and the corresponding table descriptor address is indexed through the first address [41:29], and the address is recorded in the page table address sequence. The process of constructing the table descriptor is the same as the process of constructing the table descriptor for the above level 1 page table, which will not be elaborated here. If the page table level in the page table configuration information is 2, then the page table at this level is a block descriptor, and the block descriptor is constructed. The Output address [47:29] field is filled with a random address randomly generated by a python script, and the low bits are zero-extended to form a 48-bit address, that is, the final IPA output by stage 1 translation. The remaining fields of the block descriptor are filled according to the page table attributes in the page table configuration information, and the finally generated block descriptor is recorded in the page table data sequence. And so on until stage 1 translation is completed. The address output by stage 1 translation is the final intermediate physical address, and this final intermediate physical address is translated through stage 2 to obtain the final physical address. It should be noted that after constructing the target page table, when performing multi-level table lookups using the target page table, if a level 3 page table is queried, then the result of translating the physical address in its page table descriptor through stage 2 will be concatenated with the [15:0] bits in the first address to obtain the second address.

[0117] As Figure 10 shown, according to another aspect of the present application, a method for verifying a page table is provided, and the method includes:

[0118] S1001: Receive page table configuration information input by a user, where the page table configuration information includes: a first address, an address translation mode, and a translation granularity.

[0119] S1002: Determine an address mapping rule according to the address translation mode and the translation granularity, where the address mapping rule includes a mapping rule for translating the first address into a second address.

[0120] S1003: Query a multi-level page table according to the address mapping rule, translate the first address into a second address, and generate page table descriptors and page table descriptor addresses of each level of page table generated during the translation of the first address, where the page table descriptor includes: a page table base address of the next level of page table generated according to a preset rule or an output address of the current page table.

[0121] S1004: Generate a target page table according to the page table descriptor and the page table descriptor address.

[0122] S1005: Store the target page table in the memory communicatively connected to the system memory management unit.

[0123] S1006: Send a translation request to the system memory management unit and obtain the result of the system memory management unit processing the translation request, where the translation request includes a first address.

[0124] It should be noted that the processes of S1001 to S1004 are the same as those of S101 to S104 in the above embodiments and will not be elaborated here. Moreover, the process of generating the target page table in the embodiments of the present application can be the same as that of the methods for generating page tables in the above embodiments, and the specific content can refer to the relevant descriptions of the above embodiments.

[0125] Regarding the system memory management unit and the memory, they will not be elaborated here. In some embodiments, a verification environment can be built to verify the target page table, where the verification environment is as Figure 11 shown and includes:

[0126] TCU: Short for Translation Control Unit, i.e., the translation control unit. It is also an important part of the SMMU. APB master: Connects to the PROG (APB slave) interface of the TCU and accesses the internal registers through the PROG interface. ACE lite slave: Connects to the QTW (The Queue and Table Walk) of the TCU, receives two types of translation requests, namely translation table walk and command queue read, sent by the TCU, and returns response data. The target page table generated in this embodiment is stored in the memory therein. Of course, the verification environment can also include other hardware devices in the SMMU that implement the address translation process, which will not be elaborated here. It should be noted that the entire process of verifying the target page table can be as Figure 12 shown and includes: S1201, input parameters and parse them. This is equivalent to inputting the page table configuration information in the above embodiments and identifying the corresponding data in the page table configuration information. S1202, fill the page table according to the address mapping rule. This is equivalent to the process of generating the page table descriptor and the page table descriptor address in the above embodiments and will not be elaborated here. S1203, export the target page table and write the target page table into the memory. The generated page table descriptor and the page table descriptor can be used as the target page table, exported in an appropriate file format, and written into the Figure 11 memory therein. S1204, send a translation request to verify the correctness of the target page table. Using Figure 11The provided verification environment sends a translation request carrying a first address to the TCU. Based on the translation situation of processing the translation request in the verification environment, that is, whether the first address can be translated into a second address, the correctness of the target page table is verified. For example, if the first address is successfully translated into a second address, then the generated target page table is correct. If the first address cannot be successfully translated into a second address, then the generated target page table is incorrect.

[0127] The page table verification method provided by the embodiments of the present application can meet rapidly changing business requirements. The user inputs page table configuration information based on business requirements, where the page table configuration information includes: a first address, an address translation mode, and a translation granularity. Then, according to the address translation mode and the translation granularity, an address mapping rule is determined, where the address mapping rule includes a mapping rule for translating the first address into a second address. By simulating the process of querying multiple-level page tables during translation, the first address is translated into a second address, and page table descriptors and page table descriptor addresses of each level of page tables are generated during the translation of the first address. Since the page table descriptors and page table descriptor addresses record key information of the page table. Therefore, a target page table that meets business requirements can be generated according to the page table descriptors and page table descriptor addresses, and then the target page table is verified, especially SMMU module-level verification can be achieved. The method provided in this embodiment can flexibly generate a page table that meets corresponding business requirements according to the page table configuration information input by the user, greatly improving the flexibility of constructing the page table.

[0128] Exemplary Device

[0129] Some implementation manners of the present application also provide a device for generating a page table, as Figure 13 shown. The device for generating a page table includes:

[0130] A page table configuration module 1301, configured to receive page table configuration information input by a user, where the page table configuration information includes: a first address, an address translation mode, and a translation granularity;

[0131] An address mapping module 1302, configured to determine an address mapping rule according to the address translation mode and the translation granularity, where the address mapping rule includes a mapping rule for translating the first address into a second address;

[0132] A page table information generation module 1303, configured to query multiple-level page tables according to the address mapping rule, translate the first address into a second address, and generate page table descriptors and page table descriptor addresses of each level of page tables during the translation of the first address, where the page table descriptor includes: a page table base address of the next-level page table generated according to a preset rule or an output address of the current page table;

[0133] The page table generation module 1304 is configured to generate a target page table according to a page table descriptor and a page table descriptor address.

[0134] In some embodiments, the page table information generation module 1303 is specifically configured to determine each level of page table that needs to be queried during the translation process according to the address mapping rule; for each level of page table that needs to be queried, perform a query operation in sequence, and generate a page table descriptor and a page table descriptor address for each level of page table until the first address is translated into the second address.

[0135] In some embodiments, the page table configuration information further includes: the page table level; the apparatus further includes: a page table type module, configured to set the type of the first page table to a block descriptor and set the type of the second page table to a table descriptor during the process of translating the first address; wherein, the first page table includes: the page table with the same page table level as that in the page table configuration information during the process of translating the first address, and the second page table includes: the page table other than the first page table during the process of translating the first address.

[0136] In some embodiments, the apparatus further includes: a prompt module, configured to determine whether the page table level in the page table configuration information is legal based on a legal detection rule, and output a prompt message when it is illegal; wherein, the legal detection rule includes at least one of the following:

[0137] When the translation granularity is 4 kilobytes, the page table level shall not be 0;

[0138] When the translation granularity is 16 kilobytes, the page table level shall not be 0 or 1;

[0139] When the translation granularity is 64 kilobytes, the page table level shall not be 0 or 1.

[0140] In some embodiments, the page table configuration information further includes: a plurality of page table attributes, and the page table descriptor of the third page table includes a plurality of page table attribute fields, and the third page table includes: the last level of page table during the process of translating the first address; the apparatus further includes: a page table attribute module, configured to write the plurality of page table attributes in the page table configuration information into the plurality of page table attribute fields of the page table descriptor of the third page table when generating the page table descriptor of the third page table.

[0141] In some embodiments, the addresses in the page table descriptors of each level of page table are completely different.

[0142] In some embodiments, the addresses in the page table descriptors of each level of page table are randomly generated.

[0143] In some embodiments, when the address translation mode in the page table configuration information is the first address translation mode or the second address translation mode, the page table configuration information further includes: an initial page table base address; in the process of querying a multi-level page table according to the address mapping rule and translating the first address into the second address, the initial page table base address in the page table configuration information is determined as the page table base address of the first-level page table; the first address translation mode indicates translating a virtual address into an intermediate physical address, and the second address translation mode indicates translating the intermediate physical address into a physical address.

[0144] In some embodiments, the page table information generation module 1303 is specifically configured to, for each page table queried during the translation of the first address, splice the address obtained by translating the page table base address of the currently queried page table according to the second address translation mode with the corresponding bits in the first address to obtain a target address, and determine the target address as the page table descriptor address of the currently queried page table; wherein, the third address translation mode indicates first translating a virtual address into an intermediate physical address and then translating the intermediate physical address into a physical address; the second address translation mode indicates translating the intermediate physical address into a physical address.

[0145] The apparatus for generating a page table provided by the embodiment of the present application belongs to the same inventive concept as the method for generating a page table provided by the above embodiment of the present application. For technical details not described in detail in this embodiment, reference may be made to the specific processing content of the method for generating a page table provided by the above embodiment of the present application, which will not be elaborated here.

[0146] Some embodiments of the present application further provide a page table verification apparatus, as Figure 14 shown. The page table verification apparatus includes:

[0147] A page table configuration module 1401, configured to receive page table configuration information input by a user, where the page table configuration information includes: a first address, an address translation mode, and a translation granularity;

[0148] An address mapping module 1402, configured to determine an address mapping rule according to the address translation mode and the translation granularity, where the address mapping rule includes a mapping rule for translating the first address into a second address;

[0149] A page table information generation module 1403, configured to query a multi-level page table according to the address mapping rule, translate the first address into a second address, and generate page table descriptors and page table descriptor addresses of each level of page table during the translation of the first address, where the page table descriptor includes: a page table base address of a next-level page table generated according to a preset rule or an output address of the current page table;

[0150] A page table generation module 1404, configured to generate a target page table according to the page table descriptor and the page table descriptor address.

[0151] A storage module 1405, configured to store a target page table into a memory communicatively connected to a system memory management unit;

[0152] A verification request module 1406, configured to send a translation request to the system memory management unit and obtain a result of the system memory management unit processing the translation request, where the translation request includes a first address.

[0153] The page table verification device provided by the embodiment of the present application belongs to the same inventive concept as the page table verification method provided by the above embodiment of the present application. For technical details not described in detail in this embodiment, reference may be made to the specific processing content of the page table verification method provided by the above embodiment of the present application, which will not be elaborated here.

[0154] Exemplary electronic device

[0155] Another embodiment of the present application further proposes an electronic device, including a processor configured to execute the steps in the method for generating a page table or the method for verifying a page table according to various embodiments of the present application described in the above embodiment of the present application. Refer to Figure 15 As shown, an exemplary embodiment of the present application further provides an electronic device, including: a memory and a processor, where the memory stores a computer program, and when the processor executes the computer program, it executes the steps in the method for generating a page table or the method for verifying a page table according to various embodiments of the present application described in the above embodiment of the present application.

[0156] The internal structure of the electronic device may be as Figure 15 As shown, the electronic device includes a processor, a memory, a network interface, and an input device connected through a system bus. Among them, the processor of the electronic device is used to provide computing and control capabilities. The memory of the electronic device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the electronic device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, it performs the steps in the method for generating a page table or the method for verifying a page table according to various embodiments of the present application described in the above embodiment of the present application.

[0157] The processor may include a main processor, and may also include a baseband chip, a modem, etc.

[0158] The memory stores a program for implementing the technical solution of the present invention, and may also store an operating system and other key services. Specifically, the program may include program code, and the program code includes computer operation instructions. More specifically, the memory may include a read-only memory (ROM), other types of static storage devices that can store static information and instructions, a random access memory (RAM), other types of dynamic storage devices that can store information and instructions, a disk memory, a flash memory, and so on.

[0159] The processor may be a general-purpose processor, such as a general-purpose central processing unit (CPU), a microprocessor, etc., or may be an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the program of the present invention. It may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0160] The input device may include a device for receiving data and information input by a user, such as a keyboard, a mouse, a camera, a scanner, a light pen, a voice input device, a touch screen, a pedometer or a gravity sensor, etc.

[0161] The output device may include a device for allowing information to be output to a user, such as a display screen, a printer, a speaker, etc.

[0162] The communication interface may include a device of any transceiver type for communicating with other devices or communication networks, such as an Ethernet, a radio access network (RAN), a wireless local area network (WLAN), etc.

[0163] The processor executes the program stored in the memory and calls other devices, which can be used to implement each step of any method for generating a page table or a method for verifying a page table provided in the above embodiments of the present application.

[0164] The electronic device may further include a display component and a voice component. The display component may be a liquid crystal display screen or an electronic ink display screen. The input device of the electronic device may be a touch layer covering the display component, or may be a button, a trackball or a touchpad provided on the housing of the electronic device, or may also be an external keyboard, a touchpad or a mouse, etc.

[0165] Those skilled in the art can understand, Figure 15The structure shown is only a block diagram of some structures related to the solution of this application, and does not constitute a limitation on the electronic device to which the solution of this application is applied. The specific electronic device may include more or fewer components than those shown in the figure, or combine some components, or have a different component arrangement.

[0166] Exemplary Computer Program Product and Storage Medium

[0167] In addition to the above methods and devices, the method for generating a page table or the method for verifying a page table provided by the embodiments of this application may also be a computer program product, which includes computer program instructions. When the computer program instructions are run by a processor, the processor is caused to execute the steps in the method for generating a page table or the method for verifying a page table according to various embodiments of this application described in the "Exemplary Method" section above of this application.

[0168] The computer program product can be written in any combination of one or more programming languages for executing the program code for the operations of the embodiments of this application. The programming languages include object-oriented programming languages such as Java, C++, etc., and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computing device, partially on the user's device, executed as an independent software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0169] In addition, the embodiments of this application also provide a computer-readable storage medium, on which a computer program is stored. The computer program is executed by a processor to perform the steps in the method for generating a page table or the method for verifying a page table according to various embodiments of this application described in the "Exemplary Method" section above of this application.

[0170] Those of ordinary skill in the art can understand that all or part of the processes in the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the above method embodiments. Among them, any reference to a memory, storage, database, or other medium used in the embodiments provided in this application can include non-volatile and / or volatile memories. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM), etc.

[0171] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this application.

[0172] The above-described embodiments only represent several embodiments of this application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the solutions provided by the embodiments of this application. It should be noted that for those of ordinary skill in the art, without departing from the concept of this application, several modifications and improvements can still be made, and these all belong to the protection scope of this application. Therefore, the protection scope of the patent of this application should be subject to the appended claims.

Claims

1. A method for generating a page table, characterized in that, The method includes: Receiving page table configuration information input by a user, where the page table configuration information includes: a first address, an address translation mode, and a translation granularity; Determining an address mapping rule according to the address translation mode and the translation granularity, where the address mapping rule includes a mapping rule for translating the first address into a second address; Querying a multi-level page table according to the address mapping rule, translating the first address into the second address, and generating page table descriptors and page table descriptor addresses of each level of page table during the process of translating the first address, where the page table descriptor includes: a page table base address of a next-level page table generated according to a preset rule or an output address of the current page table; Generating a target page table according to the page table descriptor and the page table descriptor address.

2. The method according to claim 1, characterized in that Querying a multi-level page table according to the address mapping rule, translating the first address into the second address, and recording the page table descriptors and page table descriptor addresses generated during the translation process, including: Determining each level of page table to be queried during the translation process according to the address mapping rule; Performing a query operation on each level of page table to be queried in sequence, and generating page table descriptors and page table descriptor addresses of each level of page table until the first address is translated into the second address.

3. The method according to claim 1, characterized in that, The page table configuration information further includes: a page table level; the method further includes: during the process of translating the first address, setting the type of the first page table to a block descriptor, and setting the type of the second page table to a table descriptor; Wherein, the first page table includes: the page table with the same page table level as that in the page table configuration information during the process of translating the first address, and the second page table includes: the page tables other than the first page table during the process of translating the first address.

4. The method according to claim 3, characterized in that, After receiving the page table configuration information input by the user, the method further includes: Determining whether the page table level in the page table configuration information is legal based on a legal detection rule, and outputting a prompt message in the case of illegality; Wherein, the legal detection rule includes at least one of the following: When the translation granularity is 4 kilobytes, the page table level shall not be 0; When the translation granularity is 16 kilobytes, the page table level shall not be 0 or 1; When the translation granularity is 64 kilobytes, the page table level shall not be 0 or 1.

5. The method according to claim 1, wherein The page table configuration information further includes: a plurality of page table attributes, and the page table descriptor of the third page table includes a plurality of page table attribute fields, where the third page table includes: the last level of page table during the process of translating the first address; The method further includes: When generating the page table descriptor of the third page table, writing the plurality of page table attributes in the page table configuration information into the plurality of page table attribute fields of the page table descriptor of the third page table.

6. The method according to claim 2, wherein The addresses in the page table descriptors of each level of page table are completely different.

7. The method according to claim 2, wherein The addresses in the page table descriptors of each level of page table are randomly generated.

8. The method according to claim 1, wherein In the case where the address translation mode in the page table configuration information is the first address translation mode or the second address translation mode, the page table configuration information further includes: an initial page table base address; When querying the multi-level page table according to the address mapping rule and translating the first address into the second address, the initial page table base address in the page table configuration information is determined as the page table base address of the first-level page table; The first address translation mode indicates translating the virtual address into an intermediate physical address, and the second address translation mode indicates translating the intermediate physical address into a physical address.

9. The method according to claim 1, characterized in that, When the address translation mode in the page table configuration information is the third address translation mode, during the process of translating the first address, generating the page table descriptor addresses of each level of page table includes: For each page table queried during the process of translating the first address, concatenate the address obtained by translating the page table base address of the currently queried page table according to the second address translation mode with the corresponding bits in the first address to obtain a target address, and determine the target address as the page table descriptor address of the currently queried page table; Wherein, the third address translation mode indicates first translating the virtual address into an intermediate physical address, and then translating the intermediate physical address into a physical address; the second address translation mode indicates translating the intermediate physical address into a physical address.

10. A method for verifying a page table, characterized in that The method includes: Receiving page table configuration information input by a user, wherein the page table configuration information includes: a first address, an address translation mode, and a translation granularity; Determining an address mapping rule according to the address translation mode and the translation granularity, wherein the address mapping rule includes a mapping rule for translating the first address into a second address; Querying a multi-level page table according to the address mapping rule, translating the first address into the second address, and generating page table descriptors and page table descriptor addresses of each level of page table during the process of translating the first address, wherein the page table descriptor includes: a page table base address of the next-level page table generated according to a preset rule or an output address of the current page table; Generating a target page table according to the page table descriptor and the page table descriptor address; Storing the target page table in a memory communicatively connected to the system memory management unit; Sending a translation request to the system memory management unit and obtaining the result of the system memory management unit processing the translation request, wherein the translation request includes the first address.

11. An electronic device, characterized in that, Includes a processor configured to execute the method according to any one of claims 1 to 10.

12. A computer program product, characterized in that, A computer program is stored on the computer program product, and when the computer program is executed by a processor, the method according to any one of claims 1 to 10 is implemented.

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