A server and a two-wire serial bus anti-hanging device thereof

Abstract

The present application discloses a server and an anti-hanging device for its two-wire serial bus, which relates to the field of fault handling technology, including: a fault detection module for outputting an abnormal signal when detecting any one of the following situations: a serial clock line hanging, a serial data line hanging, and a bus conflict in I2C; an isolation module for disconnecting the clock connection between each slave device mounted on I2C and I2C after receiving the abnormal signal, and restoring the clock connection between each slave device and I2C after disconnection; an oscillation module for outputting a specified number of pulses to the serial clock line of I2C to reset I2C after receiving the abnormal signal and the isolation module has restored the clock connection between each slave device and I2C. The solution of the present application has high real-time performance, and can automatically detect and recover from abnormal situations such as serial clock line hanging, data line hanging, and bus conflict, thereby improving the comprehensiveness of abnormality handling.

Description

Technical Field

[0001] The present application relates to the technical field of fault handling, and in particular to a server and an anti-hang-up device for a two-wire serial bus thereof. Background Art

[0002] The I2C (Inter-Integrated Circuit) bus is a bidirectional, two-wire synchronous serial bus that requires only two wires to transmit information between connected devices. These wires require only one data line, SDA (Serial Data Line), and one clock line, SCL (Serial Clock Line). Both SDA and SCL are bidirectional I / O lines. The interface circuit uses open-drain outputs and requires a pull-up resistor to the power supply VCC. When the bus is idle, both lines are high.

[0003] Because the I2C bus uses an open-drain output structure, device deadlock can cause the SDA / SCL signal lines to remain at a persistent low level (i.e., a bus hang), leading to system-level failure. Some solutions rely on FPGAs (Field Programmable Gate Arrays) / MCUs (Micro Controller Units) to poll and monitor bus status. However, FPGAs / MCUs are expensive and lack real-time performance. In practical applications, they require processing resources and have response latencies exceeding 200ms, making them difficult to meet the real-time requirements of applications such as edge servers.

[0004] In summary, how to effectively resolve I2C bus anomalies, reduce hardware costs, and ensure real-time performance is a technical problem that those skilled in the art urgently need to solve. Summary of the Invention

[0005] The present application provides a server and a two-wire serial bus anti-hanging device thereof, so as to effectively solve I2C bus anomalies, reduce hardware costs and ensure real-time performance.

[0006] The present application provides a two-wire serial bus anti-hang-up device, comprising:

[0007] A fault detection module is used to output an abnormal signal when detecting any of the following situations: a serial clock line hang, a serial data line hang, or a bus conflict on a two-wire serial bus;

[0008] an isolation module, configured to disconnect the clock connection between each slave device mounted on the two-wire serial bus and the two-wire serial bus after receiving the abnormal signal, and restore the clock connection between each slave device and the two-wire serial bus after disconnection;

[0009] The oscillation module is configured to output a specified number of pulses to a serial clock line of the two-wire serial bus to reset the two-wire serial bus after receiving an abnormal signal and the isolation module restores the clock connection between each of the slave devices and the two-wire serial bus.

[0010] The present application also provides a server, comprising the above-mentioned anti-hang-up device for the two-wire serial bus.

[0011] In the solution of the present application, the fault detection module can output an abnormality signal when it detects any of the following situations: a serial clock line hang, a serial data line hang, or a bus conflict on the two-wire serial bus, thereby improving the comprehensiveness of the anti-hanging device of the present application in handling abnormalities. After the fault detection module outputs the abnormality signal, the isolation module disconnects the clock connection between each slave device mounted on the two-wire serial bus and the two-wire serial bus, and restores the clock connection between each slave device and the two-wire serial bus after disconnection, so that pulses can be sent to the serial clock line subsequently. After the oscillation module receives the abnormality signal and the isolation module restores the clock connection between each slave device and the two-wire serial bus, the oscillation module can output a specified number of pulses to the serial clock line of the two-wire serial bus, so that the two-wire serial bus can be reset according to the rules of the two-wire serial bus, thereby resolving the abnormality. It can also be seen that the above process can be automatically executed by the anti-hanging device, so that the solution of the present application can achieve automatic recovery of I2C bus hang without master control intervention. In addition, the present application solution implements abnormality detection and recovery of the I2C bus through full hardware, and does not rely on FPGA / MCU, so that the hardware cost of the anti-hanging device of the present application solution is low and can have high real-time performance.

[0012] In summary, the anti-hanging device of the present application has low hardware cost and high real-time performance. It can automatically detect and recover from abnormal situations such as serial clock line hanging, serial data line hanging, and bus conflict, thereby improving the comprehensiveness of abnormality handling. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0014] Figure 1 A schematic structural diagram of a two-wire serial bus anti-hang-up device provided in a specific embodiment of the present invention;

[0015] Figure 2 This is a structural diagram of a fault detection module in a specific embodiment of the present invention;

[0016] Figure 3 Schematic diagram of the structure of an oscillation module in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0017] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0018] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0019] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. Figure 1 , Figure 1 This is a schematic structural diagram of a two-wire serial bus anti-hang-up device provided in a specific embodiment of the present invention. The two-wire serial bus anti-hang-up device may include:

[0020] The fault detection module 10 is configured to output an abnormality signal when detecting any one of the following situations: a serial clock line hang, a serial data line hang, or a bus conflict in the two-wire serial bus;

[0021] The isolation module 20 is used to disconnect the clock connection between each slave device mounted on the two-wire serial bus and the two-wire serial bus after receiving the abnormal signal, and restore the clock connection between each slave device and the two-wire serial bus after disconnection;

[0022] The oscillation module 30 is configured to output a specified number of pulses to the serial clock line of the two-wire serial bus to reset the two-wire serial bus after receiving the abnormal signal and the isolation module 20 restores the clock connection between each slave device and the two-wire serial bus.

[0023] In the present application, the fault detection module 10 can not only effectively detect the I2C bus hang situation (serial clock line hang, serial data line hang), but also effectively detect the bus conflict situation of the I2C bus. When any of these situations occurs, it can output an abnormal signal to reset the I2C bus through the isolation module 20 and the oscillation module 30, thereby completing the handling of the abnormal situation.

[0024] The specific structure of the fault detection module 10 can be set and adjusted according to actual needs, as long as it can achieve the functional requirements of the fault detection module 10 of the present application. For example, in a specific embodiment of the present invention, the fault detection module 10 may include:

[0025] The first fault detection unit is configured to output an abnormal signal when detecting that a serial clock line of the two-wire serial bus is hung;

[0026] The second fault detection unit is configured to output an abnormality signal when detecting that a serial data line of the two-wire serial bus is hung;

[0027] a third fault detection unit, configured to output an abnormality signal when a bus conflict is detected on the two-wire serial bus;

[0028] The OR gate circuits connected to the first fault detection unit, the second fault detection unit and the third fault detection unit respectively are used to output abnormal signals to the isolation module 20 and the oscillation module 30 when receiving abnormal signals output by any fault detection unit among the first fault detection unit, the second fault detection unit and the third fault detection unit.

[0029] In this embodiment, considering that the fault detection module 10 needs to detect the serial clock line hanging, serial data line hanging, and bus conflict on the I2C bus, it can be specifically detected by three fault detection units respectively, and then input to the OR gate circuit, and then the output of the OR gate circuit is used as the output of the fault detection module 10. This design is easy to implement and can ensure that the structure of the fault detection module 10 is relatively simple. Figure 2 , is a structural diagram of the fault detection module 10 in a specific implementation manner, Figure 2 In the example, the fault detection module 10 is specifically composed of a first fault detection unit, a second fault detection unit and a third fault detection unit.

[0030] The first fault detection unit detects a hang condition of the serial clock line on the I2C bus, that is, a hang condition of the SCL line. The specific structure can be set according to actual needs. For example, in a specific embodiment of the present invention, the first fault detection unit includes:

[0031] The first counting circuit is used to count when it detects that the serial clock line of the two-wire serial bus is at a low level; each time a rising edge or a falling edge occurs on the serial clock line, the counting circuit resets its own counting value to zero; when its own counting value reaches a preset first value, the counting circuit outputs a high-level signal as an abnormality signal output by the first fault detection unit.

[0032] In this embodiment, the first fault detection unit is implemented by a counting circuit, namely a first counting circuit. The first counting circuit needs to be connected to the SCL line. For example, in one embodiment, the first counting circuit is implemented based on a CD4521. The SCL line of the I2C bus can be connected to the clock input of the CD4521. Whenever a rising edge or a falling edge appears on the SCL line, the first counting circuit can be reset, that is, its own count value is cleared to zero. If the SCL line is in a low-level stagnant state, that is, when the first counting circuit detects that the SCL line is at a low level, it will count. It is understandable that if the count value reaches a preset first value, it indicates that the SCL line is in a low-level stagnant state, and during this process, the SCL line does not have a rising edge or a falling edge. Therefore, it can be determined that the SCL line is hung, and the first counting circuit can output a high-level signal as the abnormality signal output by the first fault detection unit.

[0033] The preset first value acts as a threshold, and its specific value can be set based on actual needs. For example, in one specific scenario, each increment of the count value of the first counter circuit represents a unit time duration equal to nine pulse periods of the SCL line. That is, when the serial clock line of the two-wire serial bus is detected to be at a low level, the count value will increment by one after a period of "nine pulse periods." For example, if the first value is set to 10, the count value of the first counter circuit will reach 10 when the SCL line is at a low level for 90 consecutive pulse periods. At this point, the first counter circuit will output a high-level signal as the abnormality signal output by the first fault detection unit, indicating that the SCL line is hung.

[0034] The second fault detection unit detects whether the serial data line on the I2C bus is hung, that is, whether the SDA line is hung. The specific structure can be set according to actual needs. For example, in a specific embodiment of the present invention, the second fault detection unit may include:

[0035] The second counting circuit is used to monitor the level state of the serial data line whenever a rising edge appears on the serial clock line during each first detection period, and to increase its own count value by 1 when the level state of the serial data line is a low level; when its own count value reaches a preset second value, it outputs a high-level signal as an abnormality signal output by the second fault detection unit; and at the end of each round of the first detection period, it starts the next round of the first detection period and clears its own count value.

[0036] In this embodiment, the second fault detection unit is implemented by a counting circuit, namely a second counting circuit. The second counting circuit needs to be connected to the SCL line and the SDA line. For example, in one embodiment, a CD4521 is used to implement the first counting circuit, and another CD4521 is used to implement the second counting circuit.

[0037] The clock input of the second counting circuit needs to be jointly controlled by the SCL line and the SDA line of the I2C bus. Specifically. During each first detection time, whenever a rising edge appears on the SCL line, the level state of the SDA line can be monitored. If at this time, the level state of the monitored SDA line is a low level, the second counting circuit needs to add 1 to its own count value. It can be understood that during the first detection time, whenever a rising edge appears on the SCL line, under normal circumstances, the level state of the SDA line may be a high level or a low level, but it will not always be a low level. That is to say, under normal circumstances, the count value of the second counting circuit will not reach the preset second value. If the count value of the second counting circuit reaches the preset second value, it can be determined that the level state of the SDA line is a continuous low level during the first detection time, indicating that the SDA line is hung, so the second counting circuit will output a high level signal as the abnormal signal output by the second fault detection unit.

[0038] In addition, it can be understood that at the end of the first detection duration of each round, it is necessary to start the first detection duration of the next round and clear its own count value. That is to say, the count value of the second counting circuit will be automatically cleared periodically, so that at the beginning of the first detection duration of each round, the count value of the second counting circuit starts to increase from 0.

[0039] The preset second value also serves as a threshold value. The length of the first detection time and the specific value of the second value can be set according to actual needs.

[0040] The third fault detection unit detects bus conflicts on the I2C bus. The specific circuit structure can be set according to actual needs. For example, in a specific embodiment of the present invention, the third fault detection unit includes:

[0041] an edge detection circuit for monitoring whether a level state of the serial data line changes whenever a rising edge occurs on the serial clock line during each second detection time period, and if so, outputting a conflict signal to the third counting circuit;

[0042] The third counting circuit is used to increase its own count value by 1 whenever a conflict signal is received within each second detection period; when its own count value reaches a preset third value, output a high-level signal as an abnormal signal output by the third fault detection unit; and at the end of each round of the second detection period, start the next round of the second detection period and clear its own count value.

[0043] In this embodiment, the third fault detection unit is implemented by a counting circuit and an edge detection circuit. The third counting circuit can be implemented based on CD4521, for example, and the edge detection circuit can be implemented based on a D flip-flop, for example.

[0044] When transmitting data signals, according to the I2C specification, SDA can only change when SCL is low, and the SDA level needs to be maintained when SCL is high, that is, "sampling on the rising edge and changing on the falling edge." Therefore, under normal circumstances, whenever the SCL line has a rising edge, the level of the SDA line should remain unchanged. Correspondingly, if the level of the SDA line changes at the same time as the SCL line has a rising edge, a conflict signal needs to be output to the third counting circuit. In actual applications, this abnormal situation is usually caused by conflicts between slave devices on the I2C bus.

[0045] For example, when a D flip-flop is used to implement the edge detection circuit of this embodiment, the SCL line can be connected to the clock terminal of the D flip-flop, and the SDA line can be connected to the data input terminal of the D flip-flop. Whenever a rising edge appears on the SCL line, it can be determined whether the level of the data output terminal of the D flip-flop has jumped. If so, a conflict signal can be output to the third counting circuit.

[0046] During each second detection period, the third counting circuit will add 1 to its own count value each time it receives a conflict signal. When the count value of the third counting circuit itself reaches a preset third value, it means that the conflict situation occurs too much, and the third counting circuit will output a high-level signal as the abnormal signal output by the third fault detection unit.

[0047] In addition, it can be understood that at the end of the second detection duration of each round, the third counting circuit needs to start the second detection duration of the next round and clear its own count value. That is to say, the count value of the third counting circuit will be automatically cleared periodically, so that at the beginning of the second detection duration of each round, the count value of the third counting circuit starts to increase from 0.

[0048] See Figure 2The outputs of the first fault detection unit, the second fault detection unit and the third fault detection unit are all connected to the OR gate circuit, so that when any fault detection unit among the first fault detection unit, the second fault detection unit and the third fault detection unit outputs an abnormal signal, the OR gate circuit can output an abnormal signal to the isolation module 20 and the oscillation module 30.

[0049] In a specific embodiment of the present invention, the fault detection module 10 can also be connected to the fault recording module. When the fault recording module receives an abnormal signal, it can store the level status on the I2C bus when the fault occurs to support subsequent diagnosis. For example, in a specific embodiment, a preset non-volatile storage device, such as an EEPROM, can be used to continuously record the level status of the SCL line and the SDA line on the I2C bus, and a circular storage method can be used to ensure that the EEPROM will never be full. For example, the abnormal signal output by the fault detection module 10 can be specifically connected to the write protection pin of the EEPROM, so that if the write protection pin of the EEPROM receives a high-level signal, the write protection is triggered, specifically, the level status of the SCL line and the SDA line within a period of time recorded before the current moment is fixed, that is, as the level status on the I2C bus when the fault occurs, it is not allowed to be overwritten by newly written data, so as to assist the staff in subsequent diagnosis. Figure 2 In the example, EEPROM is used to store the level status on the I2C bus when a fault occurs.

[0050] After the fault detection module 10 outputs the abnormal signal, the isolation module 20 and the oscillation module 30 can be used to reset the I2C bus. Specifically, according to the provisions of I2C, by sending 9 clk signals, the slave device can be prompted to release the I2C bus, that is, the I2C bus is reset. In this regard, the present application scheme takes into account that if the SDA is hung, that is, when SDA is continuously pulled low by a slave device mounted on the I2C bus, by sending 9 consecutive clk signals, the slave device can release the I2C bus and reset the I2C bus. However, if the SCL line is pulled low, then sending 9 consecutive clk signals may fail. In this embodiment, the isolation module 20 disconnects the clock connection between each slave device mounted on the I2C bus and the I2C bus, so that each I2C bus can be restored to a high level, and then the clock connection between each slave device and the I2C bus is restored. In this way, the 9 consecutive clk signals can be successfully sent without the failure of sending 9 clk signals. In other words, the isolation module 20 of the present application is configured to ensure that the oscillation module 30 successfully resets the I2C bus.

[0051] Furthermore, it is understood that, upon receiving the abnormal signal and after the isolation module 20 has restored the clock connection between each slave device and the two-wire serial bus, the oscillation module 30 should output a specified number of pulses to the serial clock line of the two-wire serial bus to reset the two-wire serial bus. That is, after the fault detection module 10 outputs the abnormal signal, the isolation module 20 completes its work first, and then the oscillation module 30 completes its work. There are various ways to implement this order of operation. For example, in one scenario, due to the simple circuit structure and rapid execution of the isolation module 20, this order of operation can be achieved without additional operation. That is, the isolation module 20 will naturally complete its own work before the oscillation module 30. Of course, in some scenarios, a specific circuit structure can be specifically configured to ensure the order of operation of the isolation module 20 and the oscillation module 30. For example, a delay circuit can be provided between the fault detection module 10 and the oscillation module 30 so that the oscillation module 30 receives the abnormal signal slightly later than the isolation module 20, ensuring that the oscillation module 30 resumes its work after the isolation module 20 completes its work. In other words, the oscillation module 30 outputs a specified number of pulses to the serial clock line of the two-wire serial bus, thereby achieving a synchronous reset of each slave device, thereby resetting the two-wire serial bus. The specified number can typically be set to 9. Of course, in some embodiments, it can be set to a value greater than 9 to provide redundancy.

[0052] The isolation module 20 functions as an analog switch, disconnecting the clock connection between each slave device connected to the I2C bus and the I2C bus, and restoring the clock connection between each slave device and the I2C bus after disconnection. The specific structure of the isolation module 20 can be set according to actual needs. For example, in one embodiment of the present invention, the isolation module 20 may include N tri-state buffers corresponding to N slave devices, each of which is used to:

[0053] After receiving the abnormal signal, the clock connection between the corresponding slave device mounted on the two-wire serial bus and the two-wire serial bus is disconnected, and the clock connection between the slave device and the two-wire serial bus is restored after the disconnection.

[0054] In this embodiment, for each slave device mounted on the I2C bus, its clock pin is mounted on the SCL line of the I2C bus through a three-state buffer corresponding to itself. N is a positive integer representing the number of slave devices mounted on the I2C bus, which is also equal to the number of three-state buffers set in this embodiment of the present application.

[0055] Each tri-state buffer can be, for example, a 74HC126 tri-state buffer. For any 74HC126 tri-state buffer, after receiving the abnormal signal output by the fault detection module 10, the 74HC126 tri-state buffer can disconnect the clock connection of the corresponding slave device. After disconnecting the clock connection of the slave device, the clock connection between the slave device and the I2C bus can be restored.

[0056] After the isolation module 20 completes its work, the oscillation module 30 can output a specified number of pulses to the serial clock line of the two-wire serial bus to reset the two-wire serial bus. The specific structure of the oscillation module 30 can be set according to actual needs. For example, in one embodiment of the present invention, the oscillation module 30 includes:

[0057] A signal conditioning circuit is used to obtain the signal of the serial clock line and amplify and output it;

[0058] a phase-locked circuit, configured to receive an output signal from the signal conditioning circuit and perform phase locking, and output a specified number of pulses to a serial clock line of the two-wire serial bus to reset the two-wire serial bus after receiving an abnormal signal and the isolation module restores a clock connection between each slave device and the two-wire serial bus;

[0059] The frequency of the pulse output by the phase-locked circuit is equal to the frequency of the output signal of the signal conditioning circuit; and the frequency of the output signal of the signal conditioning circuit is equal to the clock frequency of the serial clock line.

[0060] This implementation takes into account that the clock frequency of the SCL line of the I2C bus has multiple selectable values, that is, the clock frequency of the SCL line may be different in different situations. However, the present application requires the oscillator module 30 to output a specified number of pulses to the SCL line. Therefore, one implementation scheme is to set parameters for the oscillator module 30 based on the specific situation at hand, so that the pulse frequency of the pulses output by the oscillator module 30 matches the clock frequency of the SCL line in that situation. For example, in some situations, appropriate parameters are selected for the resistors, capacitors, and other components of the voltage-controlled oscillator in the phase-locked circuit so that the pulse frequency of the pulses output by the oscillator module 30 matches the clock frequency of the SCL line in that situation. However, this implementation scheme extracts the required clock frequency based on the signal on the SCL line and outputs it. This allows this implementation scheme to be effectively applied in different situations, eliminating the need to set parameters for the oscillator module 30 based on the specific situation, thereby increasing the application flexibility of the present application scheme.

[0061] Specifically, in this embodiment, the signal conditioning circuit obtains the signal of the SCL line and amplifies and outputs it, and the phase-locked circuit can phase-lock it. Then, after receiving an abnormal signal and the isolation module 20 restores the clock connection between each slave device and the two-wire serial bus, it can output a specified number of pulses to the serial clock line of the two-wire serial bus to reset the two-wire serial bus.

[0062] In this embodiment, since the phase-locked circuit receives the output signal of the signal conditioning circuit and performs phase locking, the pulse frequency output by the phase-locked circuit will be equal to the frequency of the output signal of the signal conditioning circuit, that is, equal to the clock frequency of the SCL line.

[0063] Furthermore, it should be noted that even if the SCL line becomes hung, the signal conditioning circuit can obtain the signal of the SCL line before the SCL line becomes hung, so that the phase-locked circuit can still generate pulses of the same frequency and phase based on the remaining clock frequency of the SCL line (i.e., the clock frequency of the SCL line before the line becomes hung), and output a specified number of pulses to the serial clock line of the two-wire serial bus to reset the two-wire serial bus after the isolation module 20 completes its work.

[0064] In a specific embodiment of the present invention, please refer to Figure 3 , the signal conditioning circuit 31 may include:

[0065] an amplifier circuit, used for acquiring and amplifying the signal of the serial clock line;

[0066] A filter circuit, used for filtering the output of the amplifier circuit;

[0067] The trigger circuit is used to convert the output of the filter circuit into a square wave signal and output it to the phase-locked circuit.

[0068] This implementation takes into account the relatively small signal amplitude of the SCL line. To facilitate the operation of the phase-locked circuit, an amplifier circuit is required to capture and amplify the weak, noisy signal on the SCL line. For example, an LM358 is used for signal amplification. The output of the amplifier circuit can then be filtered using a filter circuit. This filter circuit can typically be a bandpass filter circuit, for example, with a center frequency covering 10kHz-400kHz, which can effectively filter out out-of-band noise. The trigger circuit can perform waveform shaping, converting the output of the filter circuit into a square wave signal and outputting it to the phase-locked circuit. For example, in one specific scenario, the trigger circuit is a Schmitt trigger (such as the CD40106), which can effectively convert a sine wave or pulse into a square wave, ensuring that the output signal meets the phase-locked circuit's input signal requirements.

[0069] In a specific embodiment of the present invention, please refer to Figure 3, the phase-locked circuit 32 may include:

[0070] a phase comparator, configured to perform phase comparison on an output signal of the signal conditioning circuit and an output signal of the voltage-controlled oscillator, and output a phase comparison result;

[0071] A voltage-controlled oscillator, configured to generate an output signal of a corresponding frequency based on the phase comparison result, so that the frequency of the output signal generated by the voltage-controlled oscillator follows the frequency of the output signal of the signal conditioning circuit;

[0072] a pulse output circuit, configured to obtain an output signal of the voltage-controlled oscillator and output a specified number of pulses to a serial clock line of the two-wire serial bus to reset the two-wire serial bus after receiving an abnormal signal and the isolation module restores a clock connection between each slave device and the two-wire serial bus;

[0073] The pulse frequency of the pulse output by the pulse output circuit is equal to the frequency of the output signal of the voltage-controlled oscillator.

[0074] In this embodiment, the phase comparator can perform phase comparison on the output signal of the signal conditioning circuit and the output signal of the voltage controlled oscillator, and output a phase comparison result. The phase comparison result is a pulse proportional to the phase difference. In practical applications, a filter can usually be used, such as Figure 3 In this example, a loop filter is used to convert the pulse into a smooth DC voltage to control the frequency of the output signal of the voltage-controlled oscillator.

[0075] The phase comparison result serves as the control voltage for the voltage-controlled oscillator. Based on the phase comparison result, the voltage-controlled oscillator can generate an output signal of a corresponding frequency. In other words, the frequency of the output signal of the voltage-controlled oscillator will change with the control voltage until the output signal of the voltage-controlled oscillator and the output signal of the signal conditioning circuit are at the same frequency and in the same phase, thus achieving lock. Of course, the present application does not require whether the phase is the same, and only requires that the frequency of the output signal generated by the voltage-controlled oscillator can effectively follow the frequency of the output signal of the signal conditioning circuit. In addition, it can be understood that when the clock on the SCL line is normal, the voltage-controlled oscillator has already achieved follow-up lock. Therefore, if the clock on the SCL line is abnormal, the pulse output circuit can immediately output a specified number of pulses to the SCL line upon receiving the abnormal signal by obtaining the output signal of the voltage-controlled oscillator to reset the I2C bus. In actual applications, the anti-deadlock device for a two-wire serial bus using the present application can detect the abnormality and complete the forced reset of the I2C bus in less than 1ms, which is approximately 50 times faster than the response time of traditional MCU solutions (average response time of 50ms).

[0076] Based on the above description, it can be seen that the pulse output circuit not only needs to receive an abnormal signal, but also needs to reset the I2C bus only after the isolation module 20 restores the clock connection between each slave device and the two-wire serial bus. Of course, as described above, in normal situations, the isolation module 20 will quickly complete its work. Therefore, in actual applications, when the pulse output circuit receives an abnormal signal, it can be regarded as the isolation module 20 has completed its work, that is, it can be regarded as the isolation module 20 has cut off and restored the clock connection between each slave device and the two-wire serial bus. At this time, the pulse output circuit can automatically obtain the output signal of the voltage-controlled oscillator and output a specified number of pulses to the SCL line according to the frequency of the output signal, which can realize the synchronous reset of the master and slave devices mounted on the I2C bus, and also reset the I2C bus. A counting device can be provided in the pulse output circuit to count the number of output pulses so that the number of output pulses meets the requirements.

[0077] In the solution of the present application, the fault detection module 10 can output an abnormality signal when it detects any of the following situations: a serial clock line hang, a serial data line hang, or a bus conflict on the two-wire serial bus. This improves the comprehensiveness of the anti-hanging device of the present application in handling abnormalities. After the fault detection module 10 outputs the abnormality signal, the isolation module 20 disconnects the clock connection between each slave device mounted on the two-wire serial bus and the two-wire serial bus, and restores the clock connection between each slave device and the two-wire serial bus after disconnection, so that pulses can be sent to the serial clock line. After the oscillation module 30 receives the abnormality signal and the isolation module restores the clock connection between each slave device and the two-wire serial bus, the oscillation module 30 can output a specified number of pulses to the serial clock line of the two-wire serial bus, so that the two-wire serial bus can be reset according to the rules of the two-wire serial bus, thereby resolving the abnormality. It can be seen that the above process can be automatically executed by the anti-hanging device, so that the solution of the present application can achieve automatic recovery of I2C bus hang without master intervention. In addition, the present application solution implements abnormality detection and recovery of the I2C bus through full hardware, and does not rely on FPGA / MCU, so that the hardware cost of the anti-hanging device of the present application solution is low and can have high real-time performance.

[0078] In summary, the anti-hanging device of the present application has low hardware cost and high real-time performance. It can automatically detect and recover from abnormal situations such as serial clock line hanging, serial data line hanging, and bus conflict, thereby improving the comprehensiveness of abnormality handling.

[0079] Corresponding to the above embodiments of the anti-hang-up device for a two-wire serial bus, an embodiment of the present invention further provides a server, which can be referred to in correspondence with the above. The server may include the anti-hang-up device for a two-wire serial bus as in any of the above embodiments.

[0080] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0081] The above describes in detail a server and a two-wire serial bus anti-deadlock device provided by this application. This document uses specific examples to illustrate the principles and implementation methods of this application. The description of the above examples is only intended to help understand the method and core concept of this application. It should be noted that for those skilled in the art, without departing from the principles of this application, various improvements and modifications can be made to this application, and these improvements and modifications also fall within the scope of protection of this application.

Claims

1. A two-wire serial bus anti-hang-up device, characterized in that: include: A fault detection module is used to output an abnormal signal when detecting any of the following situations: a serial clock line hang, a serial data line hang, or a bus conflict on a two-wire serial bus; an isolation module, configured to disconnect the clock connection between each slave device mounted on the two-wire serial bus and the two-wire serial bus after receiving the abnormal signal, and restore the clock connection between each slave device and the two-wire serial bus after disconnection; an oscillation module, configured to output a specified number of pulses to a serial clock line of the two-wire serial bus to reset the two-wire serial bus after receiving an abnormal signal and the isolation module restores a clock connection between each of the slave devices and the two-wire serial bus; The fault detection module includes: The first fault detection unit is configured to output an abnormal signal when detecting that a serial clock line of the two-wire serial bus is hung; The second fault detection unit is configured to output an abnormality signal when detecting that a serial data line of the two-wire serial bus is hung; a third fault detection unit, configured to output an abnormality signal when a bus conflict is detected on the two-wire serial bus; an OR gate circuit connected to the first fault detection unit, the second fault detection unit, and the third fault detection unit, respectively, for outputting an abnormality signal to the isolation module and the oscillation module upon receiving an abnormality signal output by any of the first fault detection unit, the second fault detection unit, and the third fault detection unit; The second fault detection unit includes: The second counting circuit is configured to monitor the level state of the serial data line whenever a rising edge appears on the serial clock line during each first detection period, and to increase its own count value by 1 when the level state of the serial data line is low; output a high-level signal as an abnormality signal output by the second fault detection unit when its own count value reaches a preset second value; and start the next round of first detection period at the end of each round of first detection period and clear its own count value to zero.

2. The anti-hang-up device for a two-wire serial bus according to claim 1, wherein: The first fault detection unit includes: The first counting circuit is used to count when it detects that the serial clock line of the two-wire serial bus is at a low level; each time a rising edge or a falling edge occurs on the serial clock line, the counting circuit resets its own counting value to zero; when its own counting value reaches a preset first value, the counting circuit outputs a high-level signal as the abnormality signal output by the first fault detection unit.

3. The anti-hang-up device for a two-wire serial bus according to claim 1, wherein: The third fault detection unit includes: an edge detection circuit, configured to monitor whether a level state of the serial data line changes whenever a rising edge occurs on the serial clock line within each second detection time period, and if so, output a conflict signal to a third counting circuit; The third counting circuit is used to increase its own count value by 1 whenever it receives the conflict signal within each second detection time period; when its own count value reaches a preset third value, output a high-level signal as the abnormal signal output by the third fault detection unit; and at the end of each round of the second detection time period, start the next round of the second detection time period and clear its own count value to zero.

4. The anti-hang-up device for a two-wire serial bus according to claim 1, wherein: The isolation module includes N tri-state buffers corresponding to the N slave devices respectively, and each tri-state buffer is used to: After receiving the abnormal signal, disconnecting the clock connection between the corresponding slave device mounted on the two-wire serial bus and the two-wire serial bus, and restoring the clock connection between the slave device and the two-wire serial bus after disconnection; N is a positive integer.

5. The anti-hang-up device for a two-wire serial bus according to any one of claims 1 to 4, characterized in that: The oscillation module includes: A signal conditioning circuit is used to obtain the signal of the serial clock line and amplify and output it; a phase-locked circuit, configured to receive the output signal of the signal conditioning circuit and perform phase locking, and output a specified number of pulses to a serial clock line of the two-wire serial bus to reset the two-wire serial bus after receiving an abnormal signal and the isolation module restores the clock connection between each of the slave devices and the two-wire serial bus; The frequency of the pulse output by the phase-locked circuit is equal to the frequency of the output signal of the signal conditioning circuit; and the frequency of the output signal of the signal conditioning circuit is equal to the clock frequency of the serial clock line.

6. The anti-hang-up device for a two-wire serial bus according to claim 5, characterized in that: The signal conditioning circuit comprises: an amplifier circuit, used for acquiring and amplifying the signal of the serial clock line; a filtering circuit, configured to filter the output of the amplifying circuit; A trigger circuit is used to convert the output of the filter circuit into a square wave signal and output the square wave signal to the phase-locked circuit.

7. The anti-hang-up device for a two-wire serial bus according to claim 5, characterized in that: The phase-locked circuit comprises: a phase comparator, configured to perform phase comparison on the output signal of the signal conditioning circuit and the output signal of the voltage-controlled oscillator, and output a phase comparison result; a voltage-controlled oscillator, configured to generate an output signal of a corresponding frequency based on the phase comparison result, so that the frequency of the output signal generated by the voltage-controlled oscillator follows the frequency of the output signal of the signal conditioning circuit; a pulse output circuit, configured to, after receiving an abnormal signal and the isolation module restoring a clock connection between each of the slave devices and the two-wire serial bus, obtain an output signal of the voltage-controlled oscillator and output a specified number of pulses to a serial clock line of the two-wire serial bus to reset the two-wire serial bus; The pulse frequency of the pulse output by the pulse output circuit is equal to the frequency of the output signal of the voltage-controlled oscillator.

8. A server, characterized in that: The invention comprises the anti-hang-up device of the two-wire serial bus according to any one of claims 1 to 7.

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