Performance evaluation method and device for hardware Trojan horse detection algorithm, equipment and medium

Abstract

The invention discloses a performance evaluation method and device for a hardware Trojan detection algorithm, equipment and a medium, and relates to the technical field of information security, and the method comprises the steps: controlling a hardware Trojan simulation circuit to generate a first pseudo-random sequence according to a random number seed issued by an upper computer; comparing the first pseudo-random sequence with a second pseudo-random sequence issued by an upper computer to obtain a sequence comparison result; if it is judged that the hardware Trojan simulation circuit meets the preset activation condition according to the sequence comparison result, an encryption protection removal circuit in the hardware Trojan simulation circuit is enabled to replace a side channel protection design circuit in the encryption circuit to operate; performing hardware Trojan detection on the to-be-detected circuit by using the hardware Trojan detection algorithm to obtain a detection result, and performing performance evaluation on the hardware Trojan detection algorithm based on the detection result; wherein the circuit to be detected is a coupling circuit of the encryption circuit and the hardware Trojan simulation circuit. And the performance of the hardware Trojan horse detection algorithm can be evaluated more reliably.

Description

Technical Field

[0001] The present invention relates to the field of information security technology, and particularly to a method, device, equipment and medium for evaluating the performance of a hardware Trojan detection algorithm. Background Art

[0002] For implanting a hardware Trojan in a cryptographic algorithm in an encrypted circuit, usually a combination of one or more gate circuit nodes with a low flip probability is utilized, and the hardware Trojan circuit is activated under specific circumstances. Generally, after activation, the hardware Trojan will use the communication module of the chip to send the algorithm key to the outside. After obtaining the key, the Trojan implantor decrypts the ciphertext encrypted by the chip's encryption algorithm to obtain the plaintext. Further, when the hardware Trojan circuit is activated and deactivated, since the communication module is invoked, there is an obvious difference in the circuit operation power consumption, that is, activating the hardware Trojan circuit enables the hardware Trojan detection algorithm to detect whether there is a hardware Trojan in the circuit to be detected. Therefore, the general process of the traditional hardware Trojan detection algorithm is to perform encryption and decryption of a large amount of data, collect the power consumption curve, use the statistical principle to find the vectors with large offsets, and then further analyze to find the triggering conditions of the hardware Trojan.

[0003] However, with the development of side-channel technology and cryptographic algorithm attack and defense technology, the current hardware Trojan implantation has become increasingly concealed. For example, when activated, the key is replaced with all zeros, and the normal encryption and decryption process is still followed, and the mathematical loopholes of the algorithm itself are used to recover the plaintext. The power consumption difference between the activation and deactivation of such a Trojan is much smaller than that of the traditional hardware Trojan, which poses higher requirements for the hardware Trojan detection algorithm.

[0004] In summary, the performance of the hardware Trojan detection algorithm is very important for users. However, the current performance evaluation of the hardware Trojan detection algorithm still simulates the traditional hardware Trojan as an incentive. There is an urgent need to establish a new method for evaluating the hardware Trojan detection algorithm to determine whether different detection algorithms have the ability to deal with new types of hardware Trojans.

[0005] In summary, how to more reliably evaluate the performance of the hardware Trojan detection algorithm is a problem to be solved in this field. Summary of the Invention

[0006] In view of this, the purpose of the present invention is to provide a method, device, equipment and medium for evaluating the performance of a hardware Trojan detection algorithm, which can more reliably evaluate the performance of the hardware Trojan detection algorithm. The specific scheme is as follows:

[0007] In a first aspect, the present application discloses a method for evaluating the performance of a hardware Trojan detection algorithm, including:

[0008] Controlling a hardware Trojan simulation circuit to generate a first pseudo-random sequence according to a random number seed issued by a host computer;

[0009] Compare the first pseudo-random sequence with the second pseudo-random sequence sent by the host computer to obtain a sequence comparison result;

[0010] If it is determined according to the sequence comparison result that the hardware Trojan simulation circuit meets the preset activation condition, enable the encryption protection removal circuit in the hardware Trojan simulation circuit to operate instead of the side-channel protection design circuit in the encryption circuit; wherein, the encryption protection removal circuit includes a clock division control circuit and a pseudo-operation control circuit;

[0011] Use a hardware Trojan detection algorithm to perform hardware Trojan detection on the circuit to be detected to obtain a detection result, and perform performance evaluation on the hardware Trojan detection algorithm based on the detection result; wherein, the circuit to be detected is a coupled circuit of the encryption circuit and the hardware Trojan simulation circuit.

[0012] Optionally, it further includes:

[0013] Pull up the random number input enable signal to trigger the transmission of the random number seed sent by the host computer and the second pseudo-random sequence to the random number register of the hardware Trojan simulation circuit through the advanced high-performance bus.

[0014] Optionally, the hardware Trojan detection algorithm is a hardware Trojan detection algorithm based on side-channel analysis;

[0015] Before controlling the hardware Trojan simulation circuit to generate the first pseudo-random sequence according to the random number seed sent by the host computer, it further includes:

[0016] Obtain the first power consumption curve of the current circuit to be detected;

[0017] Correspondingly, the use of the hardware Trojan detection algorithm to perform hardware Trojan detection on the circuit to be detected to obtain a detection result includes:

[0018] Obtain the second power consumption curve of the current circuit to be detected, and use the hardware Trojan detection algorithm based on side-channel analysis to perform hardware Trojan detection on the first power consumption curve and the second power consumption curve to obtain a detection result.

[0019] Optionally, after enabling the encryption protection removal circuit in the hardware Trojan simulation circuit, it further includes:

[0020] The clock division control circuit determines the clock division coefficient corresponding to each round of encryption algorithm in the encryption circuit from a preset number set according to a preset sequence cycle order;

[0021] The pseudo-operation control circuit moves the pseudo-operations of the target number of rounds to before the encryption algorithm of the first round; wherein, the target number corresponds to the preset anti-side-channel attack level.

[0022] Optionally, after obtaining the second power consumption curve of the circuit to be detected currently, the method further includes:

[0023] The hardware Trojan horse simulation circuit filters the power consumption curve corresponding to the pseudo-operations in the target number of rounds in the second power consumption curve to obtain a filtered power consumption curve, and performs side-channel analysis on the filtered power consumption curve to obtain the key information for implementing encrypted communication in the encryption circuit.

[0024] Optionally, the hardware Trojan horse simulation circuit further includes a random number register, a linear feedback shift register, a comparator, and a counter; wherein, the random number register is respectively connected to the linear feedback shift register and the comparator, the comparator is connected to the counter, and the counter is respectively connected to the clock frequency division control circuit and the pseudo-operation control circuit;

[0025] The controlling the hardware Trojan horse simulation circuit to generate a first pseudo-random sequence according to the random number seed issued by the host computer includes:

[0026] Controlling the linear feedback shift register of the hardware Trojan horse simulation circuit to generate a first pseudo-random sequence according to the random number seed issued by the host computer.

[0027] Optionally, comparing the first pseudo-random sequence with the second pseudo-random sequence issued by the host computer to obtain a sequence comparison result includes:

[0028] Using the comparator to compare a first value corresponding to the current clock in the first pseudo-random sequence with a second value corresponding to the current clock in the second pseudo-random sequence issued by the host computer to obtain a sequence comparison result at the current clock;

[0029] If the sequence comparison result at the current clock indicates that the first value is the same as the second value, increment the value of the counter by 1;

[0030] If the sequence comparison result at the current clock indicates that the first value is different from the second value, clear the value of the counter to zero;

[0031] Correspondingly, after obtaining the sequence comparison results at each clock, the method further includes:

[0032] Determining whether the current value of the counter is equal to a preset threshold;

[0033] If the value of the counter is greater than the preset threshold, it is determined that the hardware Trojan horse simulation circuit meets the preset activation condition.

[0034] In a second aspect, the present application discloses a performance evaluation device for a hardware Trojan horse detection algorithm, including:

[0035] A random sequence generation module, configured to control a hardware Trojan simulation circuit to generate a first pseudo-random sequence according to a random number seed sent by a host computer.

[0036] A comparison result generation module, configured to compare the first pseudo-random sequence with a second pseudo-random sequence sent by the host computer to obtain a sequence comparison result.

[0037] A Trojan operation simulation module, configured to, if it is determined according to the sequence comparison result that the hardware Trojan simulation circuit meets a preset activation condition, enable an encryption protection removal circuit in the hardware Trojan simulation circuit to operate instead of a side-channel protection design circuit in an encryption circuit; wherein, the encryption protection removal circuit includes a clock division control circuit and a pseudo-operation control circuit.

[0038] An algorithm performance evaluation module, configured to perform hardware Trojan detection on a circuit to be detected by using a hardware Trojan detection algorithm to obtain a detection result, and perform performance evaluation on the hardware Trojan detection algorithm based on the detection result; wherein, the circuit to be detected is a coupled circuit of the encryption circuit and the hardware Trojan simulation circuit.

[0039] In a third aspect, the present application discloses an electronic device, including:

[0040] A memory, configured to store a computer program;

[0041] A processor, configured to execute the computer program to implement the steps of the performance evaluation method of the hardware Trojan detection algorithm disclosed above.

[0042] In a fourth aspect, the present application discloses a computer-readable storage medium, configured to store a computer program; wherein, when the computer program is executed by a processor, the steps of the performance evaluation method of the hardware Trojan detection algorithm disclosed above are implemented.

[0043] The beneficial effects of this application are as follows: This application controls a hardware Trojan simulation circuit to generate a first pseudo-random sequence according to a random number seed sent by a host computer; compares the first pseudo-random sequence with a second pseudo-random sequence sent by the host computer to obtain a sequence comparison result; if it is determined according to the sequence comparison result that the hardware Trojan simulation circuit meets a preset activation condition, enables an encryption protection removal circuit in the hardware Trojan simulation circuit to operate instead of a side-channel protection design circuit in the encryption circuit; wherein, the encryption protection removal circuit includes a clock frequency division control circuit and a pseudo-operation control circuit; uses a hardware Trojan detection algorithm to detect a circuit to be detected to obtain a detection result, and performs performance evaluation on the hardware Trojan detection algorithm based on the detection result; wherein, the circuit to be detected is a coupled circuit of the encryption circuit and the hardware Trojan simulation circuit. It can be seen that in this application, the circuit to be detected is a coupled circuit of an encryption circuit and a hardware Trojan simulation circuit. The first pseudo-random sequence generated by the hardware Trojan simulation circuit is compared with the second pseudo-random sequence sent by the host computer. When it is determined according to the sequence comparison result that the hardware Trojan simulation circuit meets the preset activation condition, the encryption protection removal circuit in the hardware Trojan simulation circuit is pulled high, that is, the hardware Trojan simulation circuit is changed from a silent state to an active state to operate instead of the side-channel protection design circuit in the encryption circuit. Pulling high the clock frequency division control circuit and the pseudo-operation control circuit can make the difference in circuit power consumption between when the hardware Trojan simulation circuit is operating and when it is silent smaller, so that the hardware Trojan simulation circuit is also relatively concealed in the operating state. Then, use a hardware Trojan detection algorithm to detect the circuit to be detected to obtain a detection result. That is to say, improving the concealment of the operation of the hardware Trojan simulation circuit, then the performance evaluation result obtained when performing performance evaluation on the hardware Trojan detection algorithm based on the detection result is also more reliable, thereby helping the user to optimize the circuit to be detected and improve the security of the circuit to be detected. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained according to the provided drawings.

[0045] Figure 1 It is a flowchart of a method for evaluating the performance of a hardware Trojan detection algorithm disclosed in this application;

[0046] Figure 2 It is a schematic diagram of a specific hardware Trojan simulation circuit disclosed in this application;

[0047] Figure 3 Structural schematic diagram of a performance evaluation device for a hardware Trojan detection algorithm disclosed in this application;

[0048] Figure 4 Structural diagram of an electronic device disclosed in this application. Specific implementation manners

[0049] Next, the technical solutions in the embodiments of this application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0050] For the implantation of hardware Trojans in the cryptographic algorithms of encrypted circuits, it is usually to use a combination of one or more gate circuit nodes with low switching probabilities and activate the hardware Trojan circuit under specific circumstances. Usually, after activation, the hardware Trojan will use the communication module of the chip to send the algorithm key to the outside. After the Trojan implantor obtains the key, the ciphertext encrypted by the chip's encryption algorithm is decrypted to obtain the plaintext. Further, when the hardware Trojan circuit is activated and deactivated, due to the invocation of the communication module, there is an obvious difference in the circuit operating power consumption, that is, activating the hardware Trojan circuit enables the hardware Trojan detection algorithm to detect whether there is a hardware Trojan in the circuit to be detected. Therefore, the general process of the traditional hardware Trojan detection algorithm is to perform encryption and decryption of a large amount of data, collect power consumption curves, use statistical principles to find vectors with large offsets, and further analyze to find the trigger conditions of the hardware Trojan.

[0051] However, with the development of side-channel technology and cryptographic algorithm attack and defense technology, the current implantation of hardware Trojans has become increasingly concealed. For example, when activated, the key is replaced with all 0s, and the normal encryption and decryption process is still followed, using the mathematical loopholes of the algorithm itself to recover the plaintext. The power consumption difference between the activation and deactivation of such a Trojan is much smaller than that of traditional hardware Trojans, which poses higher requirements for the hardware Trojan detection algorithm.

[0052] To sum up, the performance of the hardware Trojan detection algorithm is very important for users. However, the current performance evaluation of the hardware Trojan detection algorithm still simulates traditional hardware Trojans as incentives. There is an urgent need to establish a new hardware Trojan detection algorithm evaluation method to determine whether different detection algorithms have the ability to deal with new types of hardware Trojans.

[0053] Therefore, this application correspondingly provides a performance evaluation scheme for the hardware Trojan detection algorithm to more reliably evaluate the performance of the hardware Trojan detection algorithm.

[0054] See Figure 1As shown in the figure, an embodiment of the present application discloses a method for evaluating the performance of a hardware Trojan detection algorithm, including:

[0055] Step S11: Control the hardware Trojan simulation circuit to generate a first pseudo-random sequence according to the random number seed sent by the host computer.

[0056] In this embodiment, the hardware Trojan simulation circuit further includes a random number register, a linear feedback shift register, a comparator, and a counter; wherein, the random number register is respectively connected to the linear feedback shift register and the comparator, the comparator is connected to the counter, and the counter is respectively connected to the clock division control circuit and the pseudo-operation control circuit.

[0057] For example Figure 2 As shown in a specific schematic diagram of the hardware Trojan simulation circuit, the hardware Trojan simulation circuit includes a random number register, a linear feedback shift register (linear feedback shift register, i.e., LFSR), a comparator, a counter, and an encryption protection removal circuit. The encryption protection removal circuit includes a clock division control circuit and a pseudo-operation control circuit. Among them, the random number register is respectively connected to the input end of the linear feedback shift register and the first input end of the comparator, the output end of the linear feedback shift register is connected to the second input end of the comparator, the output end of the comparator is connected to the input end of the counter, and the counter is respectively connected to the clock division control circuit and the pseudo-operation control circuit.

[0058] The circuit to be detected is a coupled circuit of the encryption circuit and the hardware Trojan simulation circuit. That is, in order to evaluate the performance of the hardware Trojan detection algorithm, a controllable circuit to be detected is set. That is, from the perspective of the evaluator, the evaluator knows that there is a hardware Trojan simulation circuit in the circuit to be detected, that is, the hardware Trojan simulation circuit is coupled in the encryption circuit. In this way, the performance of the hardware Trojan detection algorithm can be more reliably evaluated according to the subsequent generated detection results.

[0059] In this embodiment, it further includes: pulling up the random number input enable signal to trigger the transmission of the random number seed sent by the host computer and the second pseudo-random sequence into the random number register of the hardware Trojan simulation circuit through the advanced high-performance bus.

[0060] The encryption algorithm can specifically be the SM4 algorithm. The 32-round transformation of the SM4 algorithm encryption is X i+4 =F(X i , X i+1 , X i+2 , X i+3 , rk i ) = X i ⊕T(X ⊕ i+1 ⊕ X i+2 ⊕ Xi+3 ⊕rk i ), where ⊕ is the XOR operation and T is the synthetic permutation, i.e. ,in, , L(x)=x⊕(x<<2)⊕(x<<10)⊕(x<<18)⊕(x<<24), L(x) is the key linear diffusion function in the SM4 algorithm, where "<<" is a left shift operation, x is 32-bit plaintext data, and SBOX is four 8-input and 8-output S-boxes. In other words, the S-box is a predefined substitution table that maps a fixed number of input bits (such as 8 bits) to another fixed number of output bits (such as 8 bits), disrupting the statistical characteristics of the data through nonlinear transformation. In order to protect the encryption algorithm from attacks, the algorithm usually needs to add masking and hiding protection measures. Masking usually refers to the algorithm S-box needing to be masked by a random number. The masked S-box is recorded as , that is, SBOX'=SBOX^RAND, RAND is a 256-bit random number. Further, the table lookup operation OUTPUT=SBOX(INPUT) can be expressed as:

[0061] ;

[0062] RAND is a pseudo-random sequence generated by a random number seed, which is usually implemented as a linear feedback shift. Note that the polynomial expansion of the linear feedback shift is transparent to the designer of the hardware Trojan simulation circuit, but hidden from the hardware Trojan detector. In other words, given the random number seed, the designer can calculate the value of each round of pseudo-random numbers generated by the linear feedback shift register, but the detector cannot obtain it.

[0063] After the host computer generates the second pseudo-random sequence based on the random number seed, it pulls the random number input enable signal trig1 high to trigger the transmission of the random number seed and the second pseudo-random sequence issued by the host computer into the random number register of the hardware Trojan simulation circuit through the Advanced High Performance Bus (AHB). In this way, the hardware Trojan simulation circuit can be controlled to generate the corresponding first pseudo-random sequence based on the random number seed.

[0064] In this embodiment, controlling the hardware Trojan horse simulation circuit to generate the first pseudo-random sequence according to the random number seed sent by the host computer includes: controlling the linear feedback shift register of the hardware Trojan horse simulation circuit to generate the first pseudo-random sequence according to the random number seed sent by the host computer.

[0065] After the random number seed is written into the random number register of the hardware Trojan simulation circuit, the random number register sends the random number seed to the linear feedback shift register of the hardware Trojan simulation circuit. In this way, the linear feedback shift register generates a corresponding pseudo-random sequence according to the random number seed. It should be noted that for the designer of the hardware Trojan simulation circuit, the pseudo-random sequence is known, while for the detector, the pseudo-random sequence is not known.

[0066] In this embodiment, before controlling the hardware Trojan simulation circuit to generate the first pseudo-random sequence according to the random number seed sent by the host computer, it further includes: obtaining the first power consumption curve of the circuit to be detected currently. It can be understood that when there is a hardware Trojan running in the circuit to be detected, the circuit power consumption is different from that when there is no hardware Trojan running. Therefore, when using the hardware Trojan detection algorithm to detect the circuit to be detected, this feature can be used for hardware Trojan detection. And because the circuit to be detected is a fusion circuit of an encryption circuit and a hardware Trojan simulation circuit and is a controllable circuit, the first power consumption curve of the circuit to be detected currently can be obtained before the hardware Trojan simulation circuit is activated, that is, the circuit power consumption curve of the circuit to be detected when the hardware Trojan is silent is obtained in advance, so that the hardware Trojan detection algorithm can compare it with the power consumption curve of the circuit to be detected after the hardware Trojan simulation circuit is activated to complete the detection of the hardware Trojan.

[0067] Step S12: Compare the first pseudo-random sequence with the second pseudo-random sequence sent by the host computer to obtain a sequence comparison result.

[0068] In this embodiment, the comparing the first pseudo-random sequence with the second pseudo-random sequence sent by the host computer to obtain a sequence comparison result includes: using the comparator to compare the first value corresponding to the current clock in the first pseudo-random sequence with the second value corresponding to the current clock in the second pseudo-random sequence sent by the host computer to obtain a sequence comparison result at the current clock; if the sequence comparison result at the current clock indicates that the first value is the same as the second value, increment the value of the counter by 1; if the sequence comparison result at the current clock indicates that the first value is different from the second value, clear the value of the counter to zero.

[0069] The process of the comparator comparing the first pseudo-random sequence with the second pseudo-random sequence sent by the host computer is divided into sequence comparisons at several clocks. For example, if the pseudo-random sequence has 8 clocks, the comparison results of the sequences at each clock are obtained respectively. Taking the current clock as an example, the comparator compares the first value corresponding to the current clock in the first pseudo-random sequence with the second value corresponding to the current clock in the second pseudo-random sequence sent by the host computer to obtain the sequence comparison result at the current clock. If the sequence comparison result at the current clock indicates that the first value is the same as the second value, the signal sent by the comparator to the counter indicates that the value of the counter needs to be incremented by 1. For example, if the current clock is the 4th clock and the first value corresponding to the 4th clock in the first pseudo-random sequence is the same as the second value corresponding to the 4th clock in the second pseudo-random sequence, the value of the counter is incremented by 1. On the contrary, if the sequence comparison result at the current clock indicates that the first value is different from the second value, the signal sent by the comparator to the counter indicates that the value of the counter needs to be cleared until the sequence comparison results at each clock are obtained.

[0070] In this embodiment, after obtaining the sequence comparison results at each clock, it further includes: judging whether the current value of the counter is equal to a preset threshold; if the value of the counter is greater than the preset threshold, it is determined that the hardware Trojan simulation circuit meets the preset activation condition.

[0071] It can be understood that after obtaining the sequence comparison results at each clock, it is judged whether the current value of the counter is equal to the preset threshold. Among them, the size of the preset threshold is set based on the number of clocks corresponding to the pseudo-random sequence. For example, if the number of clocks corresponding to the pseudo-random sequence is 8 and the current value of the counter is equal to the preset threshold 8, it means that the first pseudo-random sequence is the same as the second pseudo-random sequence. Therefore, it is determined that the hardware Trojan simulation circuit meets the preset activation condition.

[0072] Step S13: If it is determined that the hardware Trojan simulation circuit meets the preset activation condition according to the sequence comparison result, enable the encryption protection removal circuit in the hardware Trojan simulation circuit to operate instead of the side-channel protection design circuit in the encryption circuit; wherein, the encryption protection removal circuit includes a clock frequency division control circuit and a pseudo-operation control circuit.

[0073] When the hardware Trojan simulation circuit meets the preset activation condition, the encryption protection removal circuit needs to be activated. That is, the counter will send a high signal trig2 to the encryption protection removal circuit to enable the encryption protection removal circuit in the hardware Trojan simulation circuit. That is to say, the clock division control circuit and the pseudo-operation control circuit are pulled high, so that it can operate instead of the side-channel protection design circuit in the encryption circuit. It can be understood that this embodiment realizes the controllability of hardware Trojan activation and silence, that is, the circuit to be detected is controllable. Therefore, the performance evaluator can clearly know whether there is an activated hardware Trojan in the current circuit to be detected, providing a basis for subsequent performance evaluation.

[0074] In this embodiment, after enabling the encryption protection removal circuit in the hardware Trojan simulation circuit, it further includes: the clock division control circuit determines the clock division coefficient corresponding to each round of encryption algorithm in the encryption circuit from the preset number set according to the preset sequence cyclic order; the pseudo-operation control circuit moves the pseudo-operations of the target number of rounds to before the first round of encryption algorithm; wherein, the target number corresponds to the preset anti-side-channel attack level.

[0075] When the clock division control circuit is in the low state, the clock division coefficient corresponding to each round of encryption algorithm in the encryption circuit is a random number in the preset number set. When the clock division control circuit is in the high state, the clock division control circuit determines the clock division coefficient corresponding to each round of encryption algorithm in the encryption circuit from the preset number set according to the preset sequence cyclic order. Among them, the encryption algorithm is specifically the SM4 algorithm. The 32-round encryption transformation of the SM4 algorithm corresponds to 32 clock division coefficients. The values in the preset number set are 1-7 values. Then, when the clock division control circuit is in the low state, the 32 clock division coefficients corresponding to the 32-round encryption transformation of the SM4 algorithm are random numbers with values from 1 to 7. When the clock division control circuit is in the high state, the division coefficient corresponding to each round of encryption transformation is a fixed value with values from 1 to 7. For example, the transformation division coefficients of the first to 32nd rounds are {1, 2, 3, 4, 5, 6, 7, 1, 2, 3...}; among them, the division coefficient refers to the clock division of this clock cycle, and it changes in each clock cycle. The purpose is to make the power consumption waveform of the algorithm difficult to align, which is a common anti-side-channel attack means. It can be understood that when the clock division control circuit is in the high state, the clock division control circuit determines the clock division coefficient corresponding to each round of encryption algorithm in the encryption circuit from the preset number set according to the preset sequence cyclic order. The clock division coefficient changes from the original random number to a fixed sequence. If the power consumption curve collected at this time is used for side-channel analysis, it is easy to find the feature points to align the originally difficult-to-align waveforms. However, for the detector, since it does not know this fixed sequence, the power consumption curve it sees still has some characteristics of random frequency conversion, so it is difficult to distinguish from the power consumption curve of the silent excitation circuit, improving the concealment of the hardware Trojan simulation circuit and increasing the difficulty of hardware Trojan detection.

[0076] When the dummy operation control circuit is pulled low, a target number of dummy operations are inserted into the encryption transformation of the encryption algorithm (i.e., dummy), and when the dummy operation control circuit is pulled high, the target number of rounds of dummy operations are moved to the front of the first round of the encryption algorithm. Here, the target number n corresponds to the preset anti-side-channel attack level, that is, the higher the preset anti-side-channel attack level, the more the target number. The encryption algorithm can specifically be the SM4 algorithm. Among them, the dummy operation refers to inserting a false operation participated by a pseudo-random sequence between the real operations of the encryption algorithm, and the purpose is to hide the real operations.

[0077] Step S14: Use the hardware Trojan detection algorithm to detect the circuit to be detected for hardware Trojans to obtain a detection result, and perform performance evaluation on the hardware Trojan detection algorithm based on the detection result; where the circuit to be detected is the coupled circuit of the encryption circuit and the hardware Trojan simulation circuit.

[0078] In this embodiment, the hardware Trojan detection algorithm is a hardware Trojan detection algorithm based on side-channel analysis. The key to analyzing the hardware Trojan circuit based on the side-channel analysis hardware Trojan detection algorithm lies in finding the power consumption difference between when the hardware Trojan circuit is activated and when it is silent.

[0079] In this embodiment, using the hardware Trojan detection algorithm to detect the circuit to be detected for hardware Trojans to obtain a detection result includes: obtaining the second power consumption curve of the current circuit to be detected, and using the hardware Trojan detection algorithm based on side-channel analysis to detect the first power consumption curve and the second power consumption curve for hardware Trojans to obtain a detection result.

[0080] After the hardware Trojan simulation circuit meets the activation condition, it runs instead of the side-channel protection design circuit in the encryption circuit, and then obtains the second power consumption curve of the current circuit to be detected. It can be understood that the first power consumption curve is equivalent to the power consumption curve when the hardware Trojan is silent, and the second power consumption curve is equivalent to the power consumption curve when the hardware Trojan is activated. Therefore, the hardware Trojan detection algorithm based on side-channel analysis can be used to detect the first power consumption curve and the second power consumption curve for hardware Trojans to obtain a detection result.

[0081] In this embodiment, after obtaining the second power consumption curve of the current circuit to be detected, it further includes: the hardware Trojan simulation circuit filters the power consumption curve corresponding to the target number of rounds of dummy operations in the second power consumption curve to obtain a filtered power consumption curve, and performs side-channel analysis on the filtered power consumption curve to obtain the key information used to implement encrypted communication in the encryption circuit.

[0082] When the pseudo-operation control circuit is pulled high, the pseudo-operations of the target number of rounds are moved to before the encryption algorithm in the first round. When analyzing the power consumption, the designer of the hardware Trojan simulation circuit only needs to filter out the first section of the waveform in the second power consumption curve, that is, filter out the power consumption curve corresponding to the pseudo-operations of the target number of rounds in the second power consumption curve to obtain the filtered power consumption curve, and then perform side-channel analysis on the filtered power consumption curve to obtain the key information used to implement encrypted communication in the encryption circuit.

[0083] It can be understood that the encryption protection removal circuit of the hardware Trojan simulation circuit includes a clock division control circuit and a pseudo-operation control circuit. Pulling up the clock division control circuit can make the hardware Trojan detector think that the power consumption curve still has the characteristic of random frequency conversion, that is, improve the concealment when the hardware Trojan runs. Pulling up the pseudo-operation control circuit can make the hardware Trojan simulation circuit only need to filter out the power consumption curve corresponding to the pseudo-operations of the target number of rounds in the second power consumption curve when obtaining the key information, and then the pseudo-operations in the encryption algorithm can be removed, improving the simplicity of the hardware Trojan simulation circuit to obtain the key information.

[0084] The beneficial effects of this application are as follows: This application controls a hardware Trojan simulation circuit to generate a first pseudo-random sequence according to a random number seed sent by a host computer; compares the first pseudo-random sequence with a second pseudo-random sequence sent by the host computer to obtain a sequence comparison result; if it is determined according to the sequence comparison result that the hardware Trojan simulation circuit meets a preset activation condition, enables an encryption protection removal circuit in the hardware Trojan simulation circuit to operate instead of a side-channel protection design circuit in the encryption circuit; wherein, the encryption protection removal circuit includes a clock frequency division control circuit and a pseudo-operation control circuit; uses a hardware Trojan detection algorithm to perform a hardware Trojan detection on a circuit to be detected to obtain a detection result, and performs a performance evaluation on the hardware Trojan detection algorithm based on the detection result; wherein, the circuit to be detected is a coupled circuit of the encryption circuit and the hardware Trojan simulation circuit. Thus, it can be seen that in this application, the circuit to be detected is a coupled circuit of an encryption circuit and a hardware Trojan simulation circuit. The first pseudo-random sequence generated by the hardware Trojan simulation circuit is compared with the second pseudo-random sequence sent by the host computer. When it is determined according to the sequence comparison result that the hardware Trojan simulation circuit meets the preset activation condition, the encryption protection removal circuit in the hardware Trojan simulation circuit is pulled high, that is, the hardware Trojan simulation circuit is changed from a silent state to an active state to operate instead of the side-channel protection design circuit in the encryption circuit. Pulling high the clock frequency division control circuit and the pseudo-operation control circuit can make the difference in circuit power consumption between when the hardware Trojan simulation circuit is operating and when it is silent relatively small, so that the hardware Trojan simulation circuit is also relatively concealed in the operating state. Then, a hardware Trojan detection algorithm is used to perform a hardware Trojan detection on the circuit to be detected to obtain a detection result. That is to say, improving the concealment of the operation of the hardware Trojan simulation circuit, then the performance evaluation result obtained when performing a performance evaluation on the hardware Trojan detection algorithm based on the detection result is also more reliable, thereby helping the user to optimize the circuit to be detected and improve the security of the circuit to be detected.

[0085] See Figure 3 As shown, an embodiment of this application discloses a performance evaluation device for a hardware Trojan detection algorithm, including:

[0086] A random sequence generation module 11, configured to control a hardware Trojan simulation circuit to generate a first pseudo-random sequence according to a random number seed sent by a host computer;

[0087] A comparison result generation module 12, configured to compare the first pseudo-random sequence with a second pseudo-random sequence sent by the host computer to obtain a sequence comparison result;

[0088] The Trojan horse operation simulation module 13 is configured to enable the encryption protection removal circuit in the hardware Trojan horse simulation circuit to operate instead of the side-channel protection design circuit in the encryption circuit if it is determined according to the sequence comparison result that the hardware Trojan horse simulation circuit meets the preset activation condition; wherein, the encryption protection removal circuit includes a clock frequency division control circuit and a pseudo-operation control circuit;

[0089] The algorithm performance evaluation module 14 is configured to perform hardware Trojan horse detection on the circuit to be detected by using a hardware Trojan horse detection algorithm to obtain a detection result, and perform performance evaluation on the hardware Trojan horse detection algorithm based on the detection result; wherein, the circuit to be detected is a coupled circuit of the encryption circuit and the hardware Trojan horse simulation circuit.

[0090] The beneficial effects of this application are as follows: This application controls the hardware Trojan horse simulation circuit to generate a first pseudo-random sequence according to the random number seed sent by the host computer; compares the first pseudo-random sequence with the second pseudo-random sequence sent by the host computer to obtain a sequence comparison result; if it is determined according to the sequence comparison result that the hardware Trojan horse simulation circuit meets the preset activation condition, enables the encryption protection removal circuit in the hardware Trojan horse simulation circuit to operate instead of the side-channel protection design circuit in the encryption circuit; wherein, the encryption protection removal circuit includes a clock frequency division control circuit and a pseudo-operation control circuit; performs hardware Trojan horse detection on the circuit to be detected by using a hardware Trojan horse detection algorithm to obtain a detection result, and performs performance evaluation on the hardware Trojan horse detection algorithm based on the detection result; wherein, the circuit to be detected is a coupled circuit of the encryption circuit and the hardware Trojan horse simulation circuit. It can be seen that in this application, the circuit to be detected is a coupled circuit of the encryption circuit and the hardware Trojan horse simulation circuit. The first pseudo-random sequence generated by the hardware Trojan horse simulation circuit is compared with the second pseudo-random sequence sent by the host computer. When it is determined according to the sequence comparison result that the hardware Trojan horse simulation circuit meets the preset activation condition, the encryption protection removal circuit in the hardware Trojan horse simulation circuit is pulled high, that is, the hardware Trojan horse simulation circuit is changed from the silent state to the excitation state to operate instead of the side-channel protection design circuit in the encryption circuit. Pulling high the clock frequency division control circuit and the pseudo-operation control circuit can make the difference in circuit power consumption between when the hardware Trojan horse simulation circuit is operating and when it is silent smaller, so that the hardware Trojan horse simulation circuit is also relatively concealed in the operating state. Then, a hardware Trojan horse detection algorithm is used to perform hardware Trojan horse detection on the circuit to be detected to obtain a detection result. That is to say, the concealment of the operation of the hardware Trojan horse simulation circuit is improved, and then the performance evaluation result obtained when performing performance evaluation on the hardware Trojan horse detection algorithm based on the detection result is more reliable, thereby helping the user to optimize the circuit to be detected and improve the security of the circuit to be detected.

[0091] Further, an embodiment of this application also provides an electronic device.Figure 4 It is a structural diagram of an electronic device 20 shown according to an exemplary embodiment. The content in the figure should not be considered as any limitation on the scope of use of this application.

[0092] Figure 4 It is a schematic structural diagram of an electronic device provided by an embodiment of this application. Specifically, it may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. Among them, the memory 22 is used to store a computer program, and the computer program is loaded and executed by the processor 21 to implement the relevant steps in the performance evaluation method of the hardware Trojan detection algorithm executed by the electronic device disclosed in any of the foregoing embodiments.

[0093] In this embodiment, the power supply 23 is used to provide a working voltage for each hardware device on the electronic device; the communication interface 24 can create a data transmission channel between the electronic device and external devices, and the communication protocol it follows is any communication protocol applicable to the technical solution of this application, and no specific limitation is imposed on it here; the input / output interface 25 is used to obtain external input data or output data to the outside, and its specific interface type can be selected according to specific application needs, and no specific limitation is made here.

[0094] Among them, the processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 21 can be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), PLA (Programmable Logic Array). The processor 21 may also include a main processor and a coprocessor. The main processor is a processor used to process data in the wake state, also known as the CPU (Central Processing Unit); the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 21 may be integrated with a GPU (Graphics Processing Unit), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 21 may also include an AI (Artificial Intelligence) processor, and the AI processor is used to process computing operations related to machine learning.

[0095] In addition, as a carrier for resource storage, the memory 22 can be a read-only memory, a random access memory, a magnetic disk, an optical disc, etc. The resources stored thereon include an operating system 221, a computer program 222, data 223, etc. The storage method can be temporary storage or permanent storage.

[0096] Among them, the operating system 221 is used to manage and control each hardware device and the computer program 222 on the electronic device, so as to implement the operation and processing of the massive data 223 in the memory 22 by the processor 21. It can be Windows, Unix, Linux, etc. In addition to the computer program capable of completing the performance evaluation method of the hardware Trojan detection algorithm executed by the electronic device disclosed in any of the foregoing embodiments, the computer program 222 can further include a computer program capable of completing other specific tasks. In addition to the data transmitted by the external device received by the electronic device, the data 223 can also include the data collected by its own input / output interface 25, etc.

[0097] Furthermore, the present application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the performance evaluation method of the foregoing disclosed hardware Trojan detection algorithm. For the specific steps of this method, reference can be made to the corresponding content disclosed in the foregoing embodiments, and details will not be repeated here.

[0098] In this specification, the various embodiments are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the various embodiments, reference can be made to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and reference can be made to the description in the method part for related parts.

[0099] Those skilled in the art may further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application. The steps of the methods or algorithms described in combination with the embodiments disclosed herein can be directly implemented by hardware, software modules executed by a processor, or a combination of the two. The software modules can be placed in a random access memory (RAM), memory, read-only memory (ROM), electrically programmable EPROM (Erasable Programmable Read Only Memory), electrically erasable programmable EEPROM (Electrically Erasable Programmable read only memory), registers, hard disks, removable disks, CD-ROM (Compact Disc Read-Only Memory), or any other form of storage medium well known in the technical field.

[0100] Finally, it should also be noted that in this document, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the existence of additional identical elements in the process, method, article or device comprising the element.

[0101] The above has introduced in detail a performance evaluation method, device, equipment and medium of a hardware Trojan detection algorithm provided by the present invention. Specific examples are used in this article to expound the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A method for evaluating the performance of a hardware Trojan detection algorithm, characterized in that Including: Controlling a hardware Trojan simulation circuit according to a random number seed sent by a host computer to generate a first pseudo-random sequence; Comparing the first pseudo-random sequence with a second pseudo-random sequence sent by the host computer to obtain a sequence comparison result; If it is determined according to the sequence comparison result that the hardware Trojan simulation circuit meets a preset activation condition, enabling an encryption protection removal circuit in the hardware Trojan simulation circuit to operate in place of a side-channel protection design circuit in an encryption circuit; wherein, the encryption protection removal circuit includes a clock division control circuit and a pseudo-operation control circuit; Using a hardware Trojan detection algorithm to perform hardware Trojan detection on a circuit to be detected to obtain a detection result, and performing performance evaluation on the hardware Trojan detection algorithm based on the detection result; wherein, the circuit to be detected is a coupled circuit of the encryption circuit and the hardware Trojan simulation circuit.

2. The performance evaluation method of the hardware Trojan detection algorithm according to claim 1, characterized in that Also including: Pulling up a random number input enable signal to trigger the transmission of a random number seed and a second pseudo-random sequence sent by a host computer into a random number register of a hardware Trojan simulation circuit through an advanced high-performance bus.

3. The performance evaluation method of the hardware Trojan detection algorithm according to claim 2, characterized in that The hardware Trojan detection algorithm is a hardware Trojan detection algorithm based on side-channel analysis; Before controlling the hardware Trojan simulation circuit to generate a first pseudo-random sequence according to a random number seed sent by the host computer, it further includes: Obtaining a first power consumption curve of the current circuit to be detected; Correspondingly, using the hardware Trojan detection algorithm to perform hardware Trojan detection on the circuit to be detected to obtain a detection result, including: Obtaining a second power consumption curve of the current circuit to be detected, and using the hardware Trojan detection algorithm based on side-channel analysis to perform hardware Trojan detection on the first power consumption curve and the second power consumption curve to obtain a detection result.

4. The performance evaluation method of the hardware Trojan detection algorithm according to claim 3, characterized in that After enabling the encryption protection removal circuit in the hardware Trojan simulation circuit, it further includes: The clock division control circuit determines a clock division coefficient corresponding to each round of encryption algorithm in the encryption circuit from a preset number set according to a preset sequence cycle order; The pseudo-operation control circuit moves a target number of rounds of pseudo-operations to before the first round of encryption algorithm; wherein, the target number corresponds to a preset anti-side-channel attack level.

5. The performance evaluation method of the hardware Trojan detection algorithm according to claim 4, wherein After obtaining the second power consumption curve of the current circuit to be detected, it further includes: The hardware Trojan simulation circuit filters a power consumption curve corresponding to the target number of rounds of pseudo-operations in the second power consumption curve to obtain a filtered power consumption curve, and performs side-channel analysis on the filtered power consumption curve to obtain key information for realizing encrypted communication in the encryption circuit.

6. The performance evaluation method of the hardware Trojan detection algorithm according to any one of claims 1 to 5, characterized in that, The hardware Trojan simulation circuit further includes a random number register, a linear feedback shift register, a comparator, and a counter; wherein, the random number register is respectively connected to the linear feedback shift register and the comparator, the comparator is connected to the counter, and the counter is respectively connected to the clock division control circuit and the pseudo-operation control circuit; Controlling the hardware Trojan simulation circuit to generate a first pseudo-random sequence according to a random number seed sent by the host computer, including: Control the linear feedback shift register of the hardware Trojan horse simulation circuit according to the random number seed sent by the host computer to generate a first pseudo-random sequence.

7. The performance evaluation method of the hardware Trojan detection algorithm according to claim 6, characterized in that Comparing the first pseudo-random sequence with the second pseudo-random sequence sent by the host computer to obtain a sequence comparison result includes: Using the comparator to compare the first value corresponding to the current clock in the first pseudo-random sequence with the second value corresponding to the current clock in the second pseudo-random sequence sent by the host computer to obtain the sequence comparison result at the current clock; If the sequence comparison result at the current clock indicates that the first value is the same as the second value, increment the value of the counter by 1; If the sequence comparison result at the current clock indicates that the first value is different from the second value, clear the value of the counter to zero; Correspondingly, after obtaining the sequence comparison results at each clock, it further includes: Judging whether the value of the current counter is equal to a preset threshold; If the value of the counter is greater than the preset threshold, it is determined that the hardware Trojan horse simulation circuit meets the preset activation condition.

8. A performance evaluation device for a hardware Trojan detection algorithm, characterized in that, It includes: A random sequence generation module, configured to control the hardware Trojan horse simulation circuit to generate a first pseudo-random sequence according to the random number seed sent by the host computer; A comparison result generation module, configured to compare the first pseudo-random sequence with the second pseudo-random sequence sent by the host computer to obtain a sequence comparison result; A Trojan horse operation simulation module, configured to enable the encryption protection removal circuit in the hardware Trojan horse simulation circuit to operate instead of the side-channel protection design circuit in the encryption circuit if it is determined according to the sequence comparison result that the hardware Trojan horse simulation circuit meets the preset activation condition; wherein, the encryption protection removal circuit includes a clock division control circuit and a pseudo-operation control circuit; An algorithm performance evaluation module, configured to use a hardware Trojan horse detection algorithm to perform hardware Trojan horse detection on a circuit to be detected to obtain a detection result, and perform performance evaluation on the hardware Trojan horse detection algorithm based on the detection result; wherein, the circuit to be detected is a coupled circuit of the encryption circuit and the hardware Trojan horse simulation circuit.

9. An electronic device, characterized in that, It includes: A memory, configured to store a computer program; A processor, configured to execute the computer program to implement the steps of the method for evaluating the performance of the hardware Trojan horse detection algorithm according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, For storing a computer program; wherein, when the computer program is executed by the processor, the steps of the method for evaluating the performance of the hardware Trojan horse detection algorithm according to any one of claims 1 to 7 are implemented.

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