Code analysis system for Chisel hardware design language
Through the code analysis system for the Chisel hardware design language, hardware behavior determination and security analysis are directly carried out at the Chisel level, solving the problem of poor readability after converting Chisel code to Verilog, and achieving fast, general and efficient hardware analysis.
Patent Information
- Application Number
- CN202510505872.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-22
- Publication Date
- 2025-08-01
AI Technical Summary
The prior art lacks tools for directly performing hardware correctness and security analysis at the Chisel hardware design language level, and the Chisel code is poorly readable after being converted to Verilog, making it difficult to modify.
It provides a code analysis system for the Chisel hardware design language, including code reading, intermediate hardware representation, basic analysis, application analysis and analysis template components, and directly conducts hardware behavior determination and security analysis at the Chisel level.
It realizes fast and direct hardware accuracy and security analysis at the Chisel level, avoids the readability problems caused by Verilog conversion, and the analysis method is faster and is suitable for a variety of hardware designs, without the need to write special code for each hardware design.
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Figure FT_1
Abstract
Description
Technical Field
[0001] The present invention relates to a code analysis system for the Chisel hardware design language, belonging to the technical field of hardware security analysis. Background Art
[0002] Hardware design refers to the planning, design, and implementation of the physical architecture of electronic devices or computing systems according to system requirements, including key components such as processors, storage, interface circuits, and communication modules. Hardware design plays a crucial role in the development of modern technology and is key in multiple fields such as computer systems, embedded systems, and automated devices.
[0003] Correctness and security are crucial in hardware design. A correct hardware design can accurately meet the computing needs of users, and a secure hardware design can prevent data leakage, private key theft, system tampering, and various physical attacks, ensuring the security and credibility of the entire system.
[0004] In the current hardware design process, hardware design engineers first write hardware design code, ensuring the correctness and security of the hardware at this stage. After ensuring that the hardware is problem-free, they continue with tape-out and manufacturing to finally obtain the actual hardware device.
[0005] In the current hardware assurance methods, the two main methods used are functional verification and formal verification: 1) Functional verification means that after the hardware design is completed, through simulation, testing, and debugging means, it is ensured that the circuit or chip operates according to the expected functions and meets the design specifications and performance requirements. Functional verification requires users to write test cases for the specific behavior of each hardware and observe whether the hardware behavior meets the requirements in simulation or a real system. It is the most common hardware assurance method. Hardware functional verification can improve the reliability of the hardware, reduce the risks brought by design defects, and ensure the stable operation of the final product in actual applications. The limitation of functional verification is that test cases need to be written for each individual hardware design, and the verifier needs to understand the behavior characteristics and timing characteristics of the hardware.
[0006] 2) Formal verification means that after the hardware design is completed, through logical reasoning and model checking, it is strictly proved whether the hardware design meets specific specification requirements. It is a verification technology based on mathematical methods. Its advantage is that it can cover all possible input states, ensuring that there are no design loopholes, especially suitable for critical security and high-reliability systems such as processors, encryption modules, and avionics equipment. However, the limitations of formal verification are high computational complexity, difficulty in scaling to large-scale systems, and the need for highly professional knowledge to write correct verification models.
[0007] Chisel is a new hardware design language developed by the University of California, Berkeley, and has been widely used in projects such as Google's TPU and SIFive's Rocket Chip. Hardware written in Chisel is usually functionally verified at the Chisel level and then compiled into Verilog, the most commonly used hardware design language, for formal verification on Verilog, and the subsequent tape-out and manufacturing are completed using Verilog's EDA tools. However, the limitation of this approach is that the compiled Verilog code has poor readability, and it is difficult to trace back to the Chisel side for modification after problems are found on the Verilog side. Currently, there is a lack of tools for directly analyzing the correctness and security of hardware at the Chisel side. Summary of the Invention
[0008] Objective of the Invention: Aiming at the problems and deficiencies in the prior art, the present invention provides a code analysis system for the Chisel hardware design language. Through analysis techniques based on intermediate hardware representations, the hardware behavior is determined and extracted, and the correctness and security of the hardware are analyzed based on the obtained results.
[0009] Technical Solution: A code analysis system for the Chisel hardware design language includes the following components: 1) A code reading component for reading and parsing the target hardware code; 2) An intermediate hardware representation component for converting the hardware code into intermediate hardware representations, including intermediate code, instance construction diagrams, data flow diagrams, and register diagrams; 3) A basic analysis component for analyzing the basic behavioral characteristics of the circuit based on the intermediate hardware representation, including timing relationship analysis, circuit constant analysis, circuit value range analysis, and redundant circuit simplification; 4) An application analysis component for performing application-level analysis by combining the results of the basic analysis and the intermediate hardware representation, including hardware defect analysis and hardware information flow leakage analysis; 5) An analysis template component for providing templates for common analysis modes, including data flow analysis templates and reachability analysis templates, to support the development of user-defined analysis functions based on templates.
[0010] Next, the content and specific technologies of each of these components will be introduced separately: 1) A code reading component for reading the target hardware code, calling the official Chisel compiler to convert the Chisel code into a FIRRTL format file, and parsing the FIRRTL format file and storing it in memory.
[0011] 2) Intermediate hardware representation component: After the code reading component finishes, it further processes the FIRRTL format file. First, it constructs the hardware representation at the intermediate representation level, including two most basic hardware representations: intermediate code and instance construction graph. The intermediate code is directly obtained by reading the FIRRTL code. Each statement in the intermediate code represents the connection relationship of the circuit. The instance construction graph extracts the construction statements of the instances from the intermediate code level and generates a directed tree with the highest module as the root node and each node as a sub-module. In this step, the representation form of the circuit is still the connection at the intermediate code level and the construction of module instances. After that, according to the aforementioned intermediate code and instance construction graph, the code is simplified to a certain extent, including using the dominance tree algorithm to remove branches, splitting some statements with more than two operations in the code into multiple simple single statements, and obtaining a more direct graph data structure, the data flow graph. In the data flow graph, each circuit variable will have only one assignment, that is, there will be only one circuit inflow, but there may be multiple references, that is, multiple circuit outflows. After further extraction of the data flow graph, the components such as registers and input / outputs in the circuit are separately extracted to obtain the register graph. In the register graph, each node can only be a constant, input, output, or register, and the edge represents the circuit flow direction.
[0012] 3) Basic analysis component: After obtaining the intermediate hardware representation, it conducts some basic analyses on the behavior of the circuit. These basic analyses will obtain the behavioral characteristic information of the circuit to assist subsequent application analyses. The basic analyses here include timing relationship analysis, circuit constant analysis, circuit value range analysis, and redundant circuit simplification: The timing relationship analysis will, according to the register graph, analyze the path length between each component from input to output and judge the timing cycle of the component. This analysis can be used to judge the timing cycle behavior of the circuit. The timing cycle behavior can help understand the structure of the circuit and be used to simply judge whether there are simple cycle problems in the circuit. For example, whether the adder wrongly adds or subtracts data of different cycles, and whether the same output contains input circuits of multiple cycles.
[0013] Both circuit constant analysis and circuit value interval analysis perform data flow analysis in the data flow graph. The values of each variable in the data flow graph need to be modeled as an algebraic lattice, and the worklist algorithm is used to iterate over the values of variables in the data flow graph to obtain a fixed point, and the properties of the analysis results at the fixed point are analyzed. Circuit constant analysis can determine whether a certain hardware node is a constant and can be utilized by other analyses. For example, by determining whether the conditional variable in a certain branch statement is a constant, it can be determined whether the branch is a redundant branch. A redundant branch may mean that this part of the circuit will not be enabled and there may be implicit correctness issues. Circuit interval analysis can analyze the actual value range of a certain hardware node, and the interval information can help judge some behavioral characteristics of the circuit. For example, whether some circuit variables may be out of bounds or the circuit bits are too wide.
[0014] Redundant circuit simplification performs graph search reachability on the data flow graph. Nodes that can be referenced by input and output are reachable nodes, that is, non-redundant circuits, and other circuits are all redundant circuits and will be simplified. Redundant circuit simplification also provides the function of further simplification by utilizing the results of other analyses. Users need to actively write rules to specify which statements can be simplified. For example, although a certain variable itself is not a simple unconnected redundant circuit, by utilizing the results of circuit constant analysis and interval analysis, the unreachable information of this branch is obtained. Therefore, users can mark the subsequent circuit of this branch as a redundant circuit, and the redundant circuit simplification module will accept this result and perform simplification.
[0015] 4) Application analysis components are analysis components designed according to application requirements. It mainly includes hardware defect analysis and hardware information flow leakage analysis: Hardware defect analysis includes some built-in analysis components for analyzing whether there are certain defects in the hardware. It is necessary to use the existing intermediate code and the results of other basic analyses in 3) above to perform targeted analysis on specific defects. The definition of defects here comes from current public literature, and the contribution of the present invention is the analysis method for these defects. Index out-of-bounds analysis will check all places involving index access based on interval analysis to determine whether there may be out-of-bounds index access. Register uninitialized analysis will determine whether each register has an initialized reset or a constant initialization with the highest priority. CPU cycle anomaly analysis will judge based on the register graph whether the timing can match at the ALU calculation of the CPU. If it cannot match, there is a cycle anomaly. Shift anomaly analysis will judge whether there is a possibility of overflow in the shift operation according to the results of circuit constant analysis. State machine anomaly analysis will construct the state transition graph of the state machine according to the results of interval analysis and data flow analysis, and determine whether there are unreachable states in the graph, and this state may indicate an error in the hardware design.
[0016] The analysis of hardware information flow leakage abstracts the issue of data security in hardware separately. With the help of intermediate code and basic analysis, it is determined whether there is a circuit path for data in the hardware from the source point Source to the end point Sink, mainly relying on the data flow analysis on the data flow graph. Information flow analysis is a hot issue in the field of hardware security. Currently, the main methods include dynamic verification and static verification methods. Dynamic verification requires modifying the circuit and running the circuit, which has nothing to do with the present invention. The method of the present invention belongs to static verification. In particular, the method of the present invention is different from the current static verification method based on the type system, but is a method based on reachability and data flow analysis. Specifically, it is necessary for the user to mark which hardware nodes are Source and Sink first, and then perform data flow analysis and reachability analysis on the circuit representation according to the data flow information to determine whether there is path information from Source to Sink.
[0017] 5) Analyze the template components, abstract the common analysis templates from the existing analysis, extract the common parts in the analysis, and the user can only write the rule parts of their own analysis to develop new custom analysis, including the data flow analysis template represented by the aforementioned circuit interval analysis and the reachability analysis template represented by the redundant circuit analysis. As long as the user's analysis is similar to the interval analysis or redundant circuit analysis, it can be directly completed on the template, reducing the workload. For example, analyzing whether a certain circuit variable is 0 is similar to the interval analysis and can be directly performed on the data flow analysis template.
[0018] Beneficial effects: Compared with the existing technical solutions, the present invention has the following advantages: 1) The present invention provides a code analysis system for the Chisel hardware design language, which can directly analyze the code at the Chisel level without the need to convert to Verilog.
[0019] 2) The analysis method and system of the present invention are faster in determining hardware problems compared to formal verification techniques.
[0020] 3) The application analysis in the present invention is an abstract analysis for hardware problems or behaviors, which can be generally carried out on a class of hardware. Compared with functional verification and formal verification, it does not need to know the specific hardware implementation and does not need to write special analysis codes for each hardware design separately. Description of the Drawings
[0021] Figure 1 It is the system implementation flow chart in the embodiment of the present invention. Detailed Implementation Modes
[0022] The present invention will be further illustrated below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and not to limit the scope of the present invention. After reading the present invention, those skilled in the art's various equivalent modifications of the present invention all fall within the scope defined by the appended claims of this application.
[0023] As Figure 1 shown, when analyzing a specific Chisel hardware design, a code analysis system for the Chisel hardware design language includes: 1) A code reading component. Input the Chisel source code of the hardware design into the code reading component. This component calls the official compiler of Chisel to convert the hardware design into a single FIRRTL-format hardware design file, and uses parsing techniques to parse the content of the FIRRTL-format hardware design and put it into memory.
[0024] 2) An intermediate hardware representation component. After the code reading component is completed, it further processes the FIRRTL-format hardware design. First, it constructs the two most basic hardware representations: intermediate code and instance construction graph at the intermediate representation level. Then, according to the intermediate code and instance construction graph, the code is simplified to a certain extent to obtain a data flow graph structure. After further extracting the data flow graph, components such as registers and input / outputs in the circuit are abstracted separately to obtain a register graph.
[0025] 3) A basic analysis component. After obtaining the intermediate hardware representation, it is necessary to perform the required basic analysis to obtain useful information: The timing relationship analysis will analyze the path length between each component from input to output according to the register graph to determine the timing cycle of the component. The circuit constant analysis and circuit interval analysis will perform data flow analysis on the data flow graph of the hardware design, model the value of each variable as an algebraic lattice, use the worklist algorithm to iterate the values of the variables on the data flow graph, and obtain a fixed point. According to the attributes of the state analysis results at the fixed point, the circuit constant analysis can determine whether a certain hardware node is a constant, and the circuit interval analysis can analyze the actual value range of a certain hardware node. The redundant circuit simplification analysis performs graph search reachability on the data flow graph, marks the unreachable circuits as redundant circuits, and determines whether more detailed redundant analysis is required according to the user's input, and simplifies the redundant circuit components.
[0026] 4) An application analysis component. This step will perform specific application analysis and determine which application analyses need to be performed according to the user's needs. It mainly includes two important types of analysis: Hardware defect analysis involves some built - in analyses to determine whether there are certain defects in the hardware design. It requires using existing intermediate code and other analysis results to conduct targeted analysis of specific defects. Index out - of - bounds analysis will, based on the results of interval analysis, check whether there is a possibility of out - of - bounds access in all places involving index access. Register un - initialization analysis will, based on the intermediate hardware representation, determine whether each register has an initialization reset, or whether there is a constant initialization with the highest priority in the register assignment. CPU cycle anomaly analysis will, based on the register graph, determine whether the timing can match at the ALU calculation of the CPU. If it cannot match, there is a cycle anomaly. Shift anomaly analysis will, according to the results of circuit constant analysis, determine whether a shift operation may cause a shift anomaly. State machine anomaly analysis will, according to the results of interval analysis and data - flow analysis, construct the state - transition graph of the state machine and determine whether there are unreachable states in the graph, which may indicate errors in the hardware design.
[0027] Hardware information - flow leakage analysis separately abstracts the issue of data security in hardware. With the help of intermediate code and basic analysis, it determines whether there is a circuit path for data in the hardware from the source (Source) to the sink (Sink), mainly relying on data - flow analysis on the data - flow graph. This analysis requires the user to provide additional input to label which hardware nodes are Source and Sink, and then the analysis component conducts data - flow analysis and reachability analysis on the circuit representation based on the data - flow information to determine whether there is path information from Source to Sink.
[0028] 5) Analysis template component: Users can write their own analyses based on the provided analysis templates and execute these analyses at this step. The templates that users can use are data - flow analysis templates represented by the previous circuit interval analysis and reachability analysis templates represented by redundant circuit analysis. In addition to the provided default templates, users can also design other analysis methods based on the previous hardware representation and basic analysis content by themselves. These analyses can all be loaded and executed at this stage to conduct targeted analysis on the hardware design written in Chisel.
[0029] According to the method of the present invention and the provided software system, users can directly use the built - in analysis components to quickly analyze existing hardware designs, obtain some characteristics of the hardware, and can also report whether there are certain hardware defects and information - flow leakage in the application analysis. In addition, users can also design their own custom analyses according to the analysis template component, basic hardware representation, and basic analysis provided by the software system of the present invention to specifically meet specific analysis requirements.
[0030] Obviously, those skilled in the art should understand that each step of the method of the embodiment of the present invention described above can be implemented by a general-purpose computing device. They can be concentrated on a single computing device or distributed on a network composed of multiple computing devices. Optionally, they can be implemented by program codes executable by the computing device. Thus, they can be stored in a storage device and executed by the computing device. And in some cases, the steps shown or described can be executed in a sequence different from that here, or they can be separately fabricated into individual integrated circuit modules, or multiple modules or steps among them can be fabricated into a single integrated circuit module for implementation. In this way, the embodiments of the present invention are not limited to any specific combination of hardware and software.
Claims
1. A code analysis system for the Chisel hardware design language, characterized in that It includes the following components: 1) Code reading component, which is used to read and parse the target hardware code; 2) Intermediate hardware representation component, which is used to convert the hardware code into an intermediate hardware representation, including intermediate code, instance construction diagram, data flow diagram and register diagram; 3) Basic analysis component, which is used to analyze the basic behavioral characteristics of the circuit based on the intermediate hardware representation, including timing relationship analysis, circuit constant analysis, circuit value range analysis and redundant circuit simplification; 4) Application analysis component, which is used to perform application-level analysis by combining the results of basic analysis and the intermediate hardware representation, including hardware defect analysis and hardware information flow leakage analysis; 5) Analysis template component, which is used to provide templates for common analysis modes, including data flow analysis template and reachability analysis template, and supports the development of user-defined analysis functions based on templates.
2. The code analysis system for the Chisel hardware design language according to claim 1, wherein The code reading component is used to read the target hardware code, call the compiler to convert the Chisel code into a FIRRTL format file, and parse the FIRRTL format file and store it in the memory.
3. The code analysis system for the Chisel hardware design language according to claim 1, wherein After the code reading component is completed, the intermediate hardware representation component further processes the FIRRTL format file; first, it constructs a hardware representation at the intermediate representation level, including two types of hardware representations: intermediate code and instance construction diagram. The intermediate code is obtained by reading the FIRRTL code, and each sentence of the intermediate code represents the connection relationship of the circuit. The instance construction diagram extracts the construction statements of the instances in the intermediate code level and generates a directed tree with the highest module as the root node and each node as a sub-module; According to the intermediate code and the instance construction diagram, the code is simplified, including removing branches using the dominance tree algorithm, splitting statements that are operated more than twice in the code into multiple single statements to obtain a data flow diagram; after further extracting the data flow diagram, the registers and input / output components in the circuit are separately extracted to obtain a register diagram. In the register diagram, each node can only be a constant, input, output or register, and the edge represents the circuit flow direction.
4. The code analysis system for Chisel hardware design language according to claim 1, characterized in that, In the basic analysis component, after obtaining the intermediate hardware representation, the behavior of the circuit is basically analyzed to obtain the circuit behavior characteristic information; the basic analysis includes timing relationship analysis, circuit constant analysis, circuit value range analysis, and redundant circuit simplification: The timing relationship analysis will analyze the path length between each component from input to output according to the register diagram and judge the timing cycle of the component; Both the circuit constant analysis and the circuit value range analysis are performed for data flow analysis in the data flow diagram; it is necessary to model the value of each variable in the data flow diagram as a lattice in algebra, use the worklist algorithm to iterate the value of the variable on the data flow diagram, and obtain a fixed point, and analyze the attributes of the state analysis result according to the state at the fixed point; the circuit value range analysis is used to analyze the actual value range of a certain hardware node, and the range information is used to judge the behavior characteristics of the circuit. Redundant circuit simplification performs graph search reachability on the data flow graph. Nodes that can be referenced by input and output are non-redundant circuits, and other circuits are all redundant circuits and will be simplified. Redundant circuit simplification also provides the function of further simplification by using other analysis results, and users need to actively write rules to specify which statements to simplify.
5. The code analysis system for Chisel hardware design language according to claim 1, characterized in that, The application analysis component is an analysis component designed according to application requirements, including hardware defect analysis and hardware information flow leakage analysis: Hardware defect analysis includes some built-in analysis components for analyzing whether there are certain defects in the hardware. It is necessary to use the existing intermediate code and the results of the basic analysis to conduct targeted analysis on specific defects. Hardware information flow leakage analysis, with the help of intermediate code and basic analysis, determines whether there is a circuit path for data from the source (Source) to the sink (Sink) in the hardware. It conducts data flow analysis and reachability analysis on the circuit representation according to the data flow information to determine whether there is path information from Source to Sink.
6. The code analysis system for the Chisel hardware design language according to claim 1, characterized in that The analysis template component abstracts common analysis templates from existing analyses, extracts the common parts in the analyses, and users can develop new custom analyses by only writing the rule parts of their own analyses.