Stackable thermal modeling method for 3D integrated circuit and storage medium

Abstract

The invention relates to the technical field of 3D integrated circuit thermal simulation, and particularly discloses a vertical interconnection layer equivalent thermal conductivity mapping method and a storage medium. According to the method, two-dimensional thermal simulation simplification of a complex three-dimensional structure is realized by establishing equivalent thermal conductivity calculation models of different interconnection structures. For a structure comprising a redistribution layer (RDL), a bilinear interpolation model is adopted to calculate equivalent thermal conductivity based on wiring spacing, line width and silicon dioxide thermal conductivity parameters. The method specifically comprises the following steps: obtaining a weight coefficient corresponding to a wiring parameter through a predefined two-dimensional lookup table, calculating a volume ratio by combining the thermal conductivity of metal and silicon dioxide, obtaining an initial value of equivalent thermal conductivity by using a linear mixing rule, and finally obtaining uniform equivalent thermal conductivity through bilinear interpolation correction. According to the method, the problem of complex multi-scale structure modeling in traditional thermal simulation is effectively solved, the thermal analysis efficiency of the 3D integrated circuit is remarkably improved, and meanwhile, the calculation precision is ensured.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and provides a stackable thermal modeling method and a storage medium for 3D integrated circuits. Background Art

[0002] In recent years, three-dimensional integrated circuits (3D ICs) have significantly improved integration density and performance by vertically stacking chips and adopting vertical interconnection technologies such as through-silicon vias (TSVs) and micro-bumps (μbumps), becoming an important way to continue Moore's Law. However, the 3D stacking structure exacerbates the complexity of thermal management. In particular, the thermal coupling effect between stacked layers may cause a sharp increase in local temperature, affecting device reliability and lifespan. Therefore, efficient and accurate thermal modeling techniques are crucial for the design optimization of 3D ICs.

[0003] Traditional thermal simulation methods are based on finite element analysis (FEA) or finite difference methods, and achieve high-precision temperature prediction by solving the heat conduction equation or the equivalent thermal resistance-capacitance (RC) circuit model. However, such methods require intensive mesh division for complex structures, consuming huge computing resources. Especially for multi-layer stacking designs, the simulation time can reach dozens of minutes or even hours, making it difficult to meet the rapid iteration requirements in the early design stage.

[0004] To improve efficiency, researchers have proposed thermal macro-modeling techniques, which abstract the complex structure of vertical interconnections through effective thermal conductivity (ETC). Existing macro-models are mainly divided into two categories: the equivalent volume method and the data-driven method. For example, Zhang et al. proposed an analytical model based on the contact thermal resistance of the TSV insulation layer, and Wang et al. calculated ETC through volume ratios. However, the equivalent volume method ignores the non-linear thermal interaction between materials, resulting in limited accuracy, especially with significant errors in the inter-die layers (IDLs) such as micro-bumps. Although the data-driven method can improve accuracy, the existing research still has the following defects:

[0005] Ignoring the influence of inter-die layers (IDLs): The thermal conductivity of IDLs (such as the μbumps layer) is much lower than that of the TSV layer, and the thickness ratio is small. However, its steep temperature gradient has a significant impact on the overall thermal distribution. Experiments show that ignoring IDLs can lead to a temperature deviation of up to 30K in the base chip (see Figure 2 (c)-(d) in

[0006] Lack of scalability: Existing data-driven models are trained for specific numbers of stacked layers. When the number of stacked layers changes, they need to be retrained, which is time-consuming and difficult to reuse.

[0007] Insufficient temperature-dependent treatment: The thermal conductivity of silicon materials in the TSV layer varies significantly with temperature, while existing models mostly assume a constant ETC, resulting in error accumulation under high-temperature conditions.

[0008] In addition, existing macro models mostly assume a uniform distribution of vertical interconnections. However, the local non-uniform distribution of TSVs and μbumps in actual designs will further introduce thermal field distortion, and traditional methods do not provide effective local equivalent modeling means.

[0009] In summary, existing 3D IC thermal modeling techniques are difficult to balance efficiency and accuracy and cannot flexibly adapt to different stacking configurations and non-uniform structure designs. Therefore, there is an urgent need for an extensible and high-precision stackable thermal model to support the rapid thermal optimization and verification of 3D ICs. Summary of the Invention

[0010] The object of the present invention is to solve the problem of low calculation accuracy and insufficient calculation efficiency of the equivalent thermal conductivity due to the complex and variable wiring parameters (spacing / line width) of the redistribution layer (RDL) in 3D integrated circuit thermal simulation.

[0011] To achieve the above object, the present invention adopts the following technical solutions:

[0012] The present invention provides a stackable thermal modeling method for 3D integrated circuits, including the following steps:

[0013] Step (a): Map at least one vertical interconnection layer in the 3D integrated circuit into an equivalent layer with a uniform effective thermal conductivity, where the vertical interconnection layer includes one or more structures of through-silicon vias (TSVs), micro-bumps (μbumps), controlled collapse chip connections (C4) bumps, or redistribution layers (RDLs);

[0014] Step (b): Establish a corresponding effective thermal conductivity look-up table (LUT) (the LUT table is obtained through experimental data) for each type of vertical interconnection layer, and the look-up table is generated based on the geometric parameters and material thermal conductivity parameters of the vertical interconnection layer;

[0015] Step (c): Stack the equivalent layers in a predetermined order according to the stacking structure of the target 3D integrated circuit, and calculate the overall temperature distribution after stacking based on the effective thermal conductivity in the look-up table through the heat conduction equation.

[0016] In the above solution, in step (a), the mapping process includes:

[0017] Step (a1): For the layer containing TSVs, calculate the equivalent thermal conductivity through a mixing coefficient model according to the TSV array density, radius, and temperature-dependent thermal conductivities of copper and silicon.

[0018] In step (a2), for the layer containing μbumps or C4 bumps, the equivalent thermal conductivity is calculated through a linear interpolation model according to the solder ball array density, radius, and the thermal conductivity of the epoxy resin.

[0019] In step (a3), for the layer containing RDL, the equivalent thermal conductivity is calculated through a bilinear interpolation model according to the wiring pitch, line width, and the thermal conductivity of silica.

[0020] In the above solution, the equivalent thermal conductivity of the TSV layer is determined through the following iterative process:

[0021] In step (i), a mixing coefficient is obtained based on the look-up table of the TSV array density and radius.

[0022] In step (ii), based on the thermal conductivities of copper and silicon at the current temperature and in combination with the mixing coefficient, an initial equivalent thermal conductivity is calculated.

[0023] In step (iii), temperature simulation is performed using the initial equivalent thermal conductivity, and after updating the temperature distribution, the thermal conductivities of copper and silicon are recalculated.

[0024] In step (iv), steps (ii) to (iii) are repeated until the equivalent thermal conductivity converges.

[0025] In the above solution, the geometric parameters include at least one of the following:

[0026] For the TSV layer: TSV array density, radius, and layer thickness;

[0027] For the μbumps or C4 bumps layer: solder ball array density, radius, and layer thickness;

[0028] For the RDL layer: wiring pitch, line width, and layer thickness.

[0029] In the above solution, step (b) includes the following steps:

[0030] (b1) For the through-silicon via TSV layer, based on the TSV array density, radius, and layer thickness parameters, and in combination with the temperature-dependent thermal conductivities of copper and silicon, a longitudinal and transverse effective thermal conductivity look-up table, i.e., the first type of LUT, is generated through a mixing coefficient model.

[0031] (b2) For the micro-bump μbumps or C4 bumps layer, based on the solder ball array density, radius, and layer thickness parameters and the thermal conductivity of the epoxy resin, an isotropic effective thermal conductivity look-up table, i.e., the second type of LUT, is generated through a linear interpolation model.

[0032] (b3) For the redistribution layer RDL, based on the wiring pitch, line width, and layer thickness parameters and the thermal conductivity of silica, an anisotropic effective thermal conductivity look-up table, i.e., the third type of LUT, is generated through a bilinear interpolation model.

[0033] (b4) Storing the lookup table as a multi-dimensional array structure.

[0034] In the above solution, the effective thermal conductivity lookup table LUT relationship is as follows:

[0035] k′ Bump =LUT(h,ρ Bump , r Bump )

[0036] k′ RDL =LUT(h,s RDL ,ω RDL )

[0037] k′ TSV =αk Cu +(1-α)k Si

[0038] α=LUT(h,ρ TSV , r TSV )

[0039] k′ Bump Represents the solder ball effective thermal conductivity, k′ TSV represents the effective thermal conductivity of the through-silicon via, k′ RDL represents the effective thermal conductivity of the redistribution layer, where S is the chip size, h is the layer height, and ρ Bump is the solder ball array density, r Bump is the solder ball radius, s RDL is the line spacing in RDL, ω RDL is the line width in RDL, ρ TSV is the TSV array density, r TSV is the TSV radius, k Si represents the thermal conductivity of silicon, k Cu Represents the thermal conductivity of copper.

[0040] In the above solution, in step (c), at least one equivalent layer of the stacked structure comprises a non-uniformly distributed vertical interconnection structure, and the layer is divided into a plurality of locally uniform sub-regions, each of which is modeled using a corresponding effective thermal conductivity.

[0041] In the above solution, the method further includes:

[0042] When equivalent layers are stacked, the inter-chip dielectric layer (IDL) is included in the calculation as an independent equivalent layer. The inter-chip dielectric layer includes μbumps and adjacent RDL structures.

[0043] The present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the stackable thermal modeling method for 3D integrated circuits.

[0044] The stackable thermal modeling method and storage medium for 3D integrated circuits provided by the present invention achieve the following remarkable technical effects through the equivalent thermal conductivity modeling and stackable design for the vertical interconnect structure:

[0045] I. High-precision thermal field prediction

[0046] By constructing effective thermal conductivity look-up tables (LUTs) based on geometric parameters and material properties for the TSV layer, μbumps / C4 bump layer, and RDL layer respectively, and introducing temperature-dependent iterative calculation (for the TSV layer), the modeling accuracy of the equivalent thermal conductivity is significantly improved. Experiments show that the maximum / minimum temperature and average temperature errors of the macro model of the present invention are less than 1% and 0.5% respectively in the multi-layer stack structure (see Figure 12 , Figure 14 ), especially in the scenario including the inter-chip dielectric layer (IDLs), avoiding the 30K temperature deviation caused by the traditional method due to ignoring the IDLs (see Figure 1 ).

[0047] II. Efficient calculation and fast iteration ability

[0048] By pre-computing and storing the multi-dimensional effective thermal conductivity LUT and solving the stacked temperature conduction equation of the equivalent layer, the mesh division and computing resources required for simulation are greatly reduced. Compared with the traditional finite element analysis (FEA) method, a 60-fold acceleration is achieved in the five-layer stack case, the simulation time is shortened from 30 minutes to 30 seconds, and the number of meshes is reduced by more than 80% (see Figure 13 ), meeting the rapid thermal optimization requirements in the early design stage.

[0049] III. Flexible adaptation to complex structure design

[0050] Support for modeling non-uniformly distributed vertical interconnect structures: By dividing the non-uniform layer into locally uniform sub-regions and assigning the corresponding LUT parameters to the sub-region thermal conductivity, the actual distribution characteristics of TSV, μbumps, and RDL (such as local density changes) are effectively processed, avoiding the thermal field distortion caused by the traditional uniform assumption (see Figure 7 and Table VII).

[0051] Scalability: The LUTs of various vertical interconnect layers are independently generated, supporting any combination of stacking layers, and there is no need to retrain the model for different numbers of layers (see Figure 12 ). For example, when the four-layer stack is extended to five layers, the model error is still stably less than 1%.

[0052] IV. Comprehensive coverage of key factors in thermal management

[0053] Targeted Modeling of Inter-Chip Dielectric Layers (IDLs): Treat the IDL composed of μbumps and adjacent RDL as an independent equivalent layer in the calculation, significantly reducing the prediction deviation of the substrate chip temperature caused by ignoring the steep temperature gradient of the IDLs.

[0054] Temperature-Dependent Dynamic Calibration: Considering the characteristic that the thermal conductivity of silicon material in the TSV layer varies with temperature, iteratively update the thermal conductivity weights of copper and silicon through a mixing coefficient to avoid error accumulation of traditional fixed-value ETC assumptions under high-temperature conditions (see Figure 6 ).

[0055] V. Efficiency and Practicality of Storage Media

[0056] Solidify the LUT data and modeling process through a computer-readable storage medium to achieve rapid invocation and reuse of the thermal model, support plug-and-play for different 3D IC design scenarios, and reduce the occupancy of hardware resources and deployment costs.

[0057] In summary, under the premise of ensuring high precision, the present invention significantly improves the efficiency and flexibility of 3D integrated circuit thermal simulation, providing effective tool support for the thermal reliability design of complex stacked structures. Description of the Drawings

[0058] Figure 1 : Schematic diagram of a typical 3D integrated multi-chip stacked structure (including TSV, μbumps, and RDL layer markings);

[0059] Figure 2 : Comparative experimental results of ignoring the influence of the IDL layer on the substrate chip temperature (temperature difference distribution between the traditional model and the present method), where Figure 2 (a) is the vertical temperature distribution of the stacked chips; Figure 2 (b) is the detailed vertical temperature distribution of the micro-bump layer; Figure 2 (c) is the temperature distribution on the surface of the substrate chip when the micro-bumps are included in the stack (highest temperature: 391.05K, average temperature: 382.58K); Figure 2 (d) is the temperature distribution on the surface of the substrate chip when the micro-bumps are not included in the stack (highest temperature: 365.65K, average temperature: 365.54K). Figure 2 The temperature difference between (c) and Figure 2 (d) is approximately 30K.

[0060] Figure 3 : Surrogate models for longitudinal and transverse ETC, where Figure 3 (a) is a schematic diagram of constructing the longitudinal thermal conductivity surrogate model; Figure 3 (b) is a schematic diagram of constructing the transverse thermal conductivity surrogate model;

[0061] Figure 4: Equivalent thermal conductivity change curves, where Figure 4 (a) shows the relationship between the transverse effective thermal conductivity (ETC) of the solder ball layer and the array density and area; Figure 4 (b) shows the relationship between the transverse effective thermal conductivity (ETC) of the RDL and the RDL density and width;

[0062] Figure 5 : Macro models of each layer, where Figure 5 (a) shows the variation of the equivalent thermal conductivity of the solder ball layer with the solder ball density and radius; Figure 5 (b) shows the variation of the equivalent thermal conductivity of the RDL layer with the wire width and pitch; Figure 5 (c) shows the mixing coefficient α of the materials in the TSV layer;

[0063] Figure 6 : Equivalent thermal conductivity curve of the TSV layer varying with temperature. Figure 6 (a) shows the variation of the equivalent thermal conductivity with temperature at different TSV densities; Figure 6 (b) shows the variation of the equivalent thermal conductivity with temperature at different TSV radii.

[0064] Figure 7 : Thermal field verification of three 4-layer stacking cases, where Figure 7 (a) is a uniform distribution; Figure 7 (b) is globally non-uniform and locally uniform (GNLU); Figure 7 (c) is a random reduction of solder balls, TSVs, and wires based on GNLU.

[0065] Figure 8 : Table I, showing the structural parameters and material properties used in this application;

[0066] Figure 9 : Table II, equivalent thermal conductivity curves of the micro solder ball layer and the RDL varying with temperature. The temperature rises from 350K to 380K, and the equivalent thermal conductivities of both decrease by no more than 0.5%, where K μbump，z represents the equivalent thermal conductivity in the vertical direction of the solder ball layer, K μbump，xy represents the equivalent thermal conductivity in the horizontal direction of the solder ball layer, K RDL，z represents the equivalent thermal conductivity in the vertical direction of the redistribution layer, K RDL,xy represents the equivalent thermal conductivity in the horizontal direction of the redistribution layer.

[0067] Figure 10 : Table III, temperature-dependent mixing coefficient α curve of the TSV layer, where α TSV，Z represents the mixing coefficient in the horizontal direction, α TSV,Zy represents the mixing coefficient in the vertical direction;

[0068] Figure 11: Table IV, Modeling Methods for Solder Ball Layer, RDL, and TSV Layer in Total;

[0069] Figure 12 For Table V, Quantitative Comparison of Four Different Chip Stacking Configurations. "#Stacks" represents the number of stacked chips. The best items are highlighted in bold font.

[0070] Figure 13 : Table VI, Computational Resource Consumption of Fine Model and Equivalent Model.

[0071] Figure 14 : Table VII, Quantitative Evaluation of Three 4-Layer Stacking Cases: Uniform Distribution (uniform), Global Non-Uniform Local Uniform (GNLU), and Randomly Reduced GNLU. The indices of the chips from the surface to the bottom are 1 to 4 respectively.

[0072] Figure 15 、 Figure 16 is an implementation of the LUT table. Detailed Implementation Manner

[0073] The following will give a detailed description of the embodiments of the present invention. Although the present invention will be described and illustrated in conjunction with some specific implementation manners, it should be noted that the present invention is not limited to these implementation manners only. On the contrary, any modifications or equivalent replacements made to the present invention should be covered within the scope of the claims of the present invention.

[0074] In addition, for better illustration of the present invention, numerous specific details are given in the following detailed implementation manners. Those skilled in the art will understand that the present invention can also be implemented without these specific details.

[0075] The concept of the present invention is proposed based on actual production requirements. For the convenience of those skilled in the art to understand the technical concept of the present invention, the following further explanation is made:

[0076] To this end, the present invention provides an efficient and accurate stackable thermal model, considering the thermal effects of the inter-die dielectric layers (IDLs) to overcome the problems proposed in the background art. Specifically, first, for various functional layers (including IDLs) in the 3D integration structure, a corresponding thermal macro-model is constructed by mapping the layers with TSVs or solder balls into equivalent layers with uniform thermal conductivity. Such thermal conductivity is parameterized and pre-calculated separately for each type of layer. Then, the temperature calculation stacks the models of the above corresponding layers in 3D integration, so that any combination of different types of layers can be achieved. Generally speaking, the main contributions of the present invention are as follows:

[0077] Utility Model: Considering the inter-dielectrics (IDLs) between stacked chips and the temperature-dependent effective thermal conductivity (ETC), a thermal macro-model is constructed to comprehensively abstract the vertical interconnections in 3DICs.

[0078] Scalability: The effective thermal conductivity (ETC) of different types of layers is trained separately and combined for stacked layers. This makes it easier to expand the layers.

[0079] Efficient and Accurate: Experiments show that the maximum / minimum temperature and average temperature of the macro-model of the present invention in 3D integration have errors of only 1% and 0.5% respectively compared to the benchmark model. In addition, our macro-model achieves a 60-fold acceleration compared to the fine-grid benchmark model using COMSOL (reducing the simulation time from 30 minutes to 30 seconds).

[0080] II. Preparation Conditions

[0081] A. 3D Integrated Multi-Chip Stacked Structure

[0082] Figure 1 A typical 3D integrated multi-chip stacked structure is shown, where each stacked unit contains a chip layer and several inter-dielectrics (IDLs). From top to bottom, a stacked unit consists of the following:

[0083] (i) A silicon substrate that contains transistors and through-silicon vias (TSVs) for supporting vertical electrical connections and heat conduction inside the chip;

[0084] (ii) An underfill layer containing micro-bumps (μbumps) for establishing electrical connections between chips;

[0085] (iii) A redistribution layer (RDLs) adjacent to the bottom TSVs that provides lateral connections inside the silica.

[0086] Below these layers, the stacked unit is connected to an organic substrate through C4 (controlled-collapse chip connection) solder balls. Ball grid array (BGA) solder balls are located at the bottom of the organic substrate for connecting to the printed circuit board (PCB).

[0087] B. Structure Construction

[0088] The geometric structure includes stacked chips, a substrate, and an array consisting of through-silicon vias (TSVs), micro-bumps (μbumps), redistribution layers (RDLs), and C4 bumps. The TSVs and bumps are both evenly distributed and modeled as cylinders. The bumps are composed of copper pillars and Sn-Pb solder. The RDLs form a uniformly spaced wiring network both laterally and longitudinally, and a TSV copper pillar is placed below each intersection. This structure not only reflects the real 3D interconnect structure but also establishes a complete heat dissipation channel in the inter-chip dielectric layer. In the present invention, the RDLs and micro-bumps together constitute the inter-chip dielectric layer. In addition, the size of the base chip is 20mm×20mm and it is located at the bottom of the stacked structure, and the other stacked chips are placed on top of the base chip. All stacked chips are in a normal working state during the simulation process. Figure 8 Table I in [reference] lists the detailed structural parameters and material properties.

[0089] C. Boundary Conditions

[0090] The steady-state thermal simulation adopts boundary conditions defined by the equivalent heat transfer coefficient (h). Different cooling effects can be flexibly reflected by adjusting the variable parameters. Therefore, an equivalent heat transfer coefficient of 5000

[0091] W / (m 2 ·K) is applied to the top surface of the geometric structure to represent the cooling effect of the heat sink, while a heat transfer coefficient of 20W / (m 2 ·K) is set for the bottom surface of the substrate to simulate the natural convection with the ambient air. At the same time, the surrounding surfaces are set to be adiabatic, and the ambient air temperature is set to 293.15K. These settings are for data collection but do not affect the principle of the model construction and verification of this application.

[0092] III. Methodology

[0093] A. Single-layer Thermal Conductivity Modeling

[0094] A chip stack consists of three parts: TSV, RDL, and bump layers. Usually, the bottom surface of the stacked chips is the transistor layer, which is also the heat source of the chip stack. When these units are stacked vertically, the heat source (transistor layer) exists between the upper and lower boundaries of each unit. The part between the two heat sources contains all the components of the chip stack. Therefore, there are three boundary conditions:

[0095] a) Two heat sources at the upper and lower boundaries;

[0096] b) Heat transfer from the upper and lower boundaries to the rest of the chip stack, with heat transfer coefficients of h1 and h2 respectively;

[0097] c) Adiabatic or convective boundary conditions at the edges.

[0098] Simulating designs with multiple stacks is very time-consuming. Modeling the relationship between thermal conductivity and structural design by generating a large number of simulation cases is both computationally intensive and difficult to scale. To improve the modeling and simulation efficiency, a surrogate model is created for each type of layer, and the effective thermal conductivity (ETC) of this model is close to that of the complete model. In addition, this surrogate model can be pre-computed once and used in cases with different numbers of stacked chips. Here, the surrogate model refers to a thermal abstraction model that simplifies the vertical interconnect structures (such as TSVs, μbumps, C4 solder balls, etc.) in complex three-dimensional integrated circuits (3D ICs) into homogeneous layers through the Effective Thermal Conductivity (ETC) and Look-Up Table (LUT) techniques.

[0099] In Figure 3 (a), a surrogate model of the longitudinal thermal conductivity is constructed for pre-computation. The yellow area in the figure is the heat source, which is used to simulate multiple chip stacks. For each layer, there is an equivalent heat source (q1 and q2) for the μbump in both the up and down directions, and convective heat transfer boundary conditions (h1 and h2) on both sides. The left and right sides are considered adiabatic boundary conditions. The heat flow through the μbump layer is:

[0100]

[0101] where T1 is the temperature at the top of the solder ball layer, T2 is the temperature at the bottom of the solder ball layer, and T ∞ is the room temperature. Then, the longitudinal effective thermal conductivity k z of the surrogate model is:

[0102]

[0103] where t is the thickness of the layer. To model the transverse thermal conductivity, a surrogate model as shown in Figure 3 (b) is constructed, and the top and bottom surfaces are set as adiabatic boundary conditions. A heat source is added on one side, and a convective heat transfer boundary h is set on the other side. The transverse effective thermal conductivity k' xy is:

[0104]

[0105] where l is the size of the chip, T is the temperature on the convective boundary side, and T0 is the temperature near the heat source side. For the solder ball layer, RDL layer, and TSV layer, longitudinal and transverse surrogate models with heat sources and convective heat transfer boundary conditions are used to obtain the effective thermal conductivity (ETC) of each layer.

[0106] B. Bump Modeling

[0107] The solder ball layer consists of two parts: solder and the surrounding epoxy resin. Compared with the epoxy resin, the solder balls occupy a relatively small volume. Due to the main presence of the resin, the thermal conductivity of the solder ball layer remains at a low level. Therefore, solving the thermal conductivity of the solder ball layer by the equivalent volume ratio will introduce a large relative error.

[0108] To establish a surrogate model of the solder ball layer with a fixed chip size, experiments were conducted to study the variation of the longitudinal and transverse equivalent thermal conductivities with the solder ball array density and radius. The results are as Figure 4 (a), Figure 5 (a) and Figure 9 shown in Table II in

[0109] 1) The longitudinal effective thermal conductivity (ETC) of the solder ball layer shows a strong linear relationship with the radius of the solder balls, which is contrary to previous experience that considered ETC to be linearly related to the volume distribution of the solder balls. In addition, there is also a linear relationship between the transverse effective thermal conductivity and the area of the solder balls;

[0110] 2) The array density of the solder balls has a significant impact on the longitudinal and transverse equivalent thermal conductivities, and there is an obvious linear correlation between them;

[0111] 3) Under the fixed solder ball layer structure, the equivalent thermal conductivity of this layer only changes slightly within the operating temperature range of the chip.

[0112] Based on the above observations, the equivalent thermal conductivity of the solder ball layer can be expressed as a linear combination of the solder ball radius and the array density within a specific chip size. Since most of the solder ball layer consists of epoxy resin with a high thermal resistance, its equivalent thermal conductivity is insensitive to temperature changes. Based on the above analysis, a look-up table (LUT) was constructed for the solder ball layer, and the parameters of this look-up table include the array density and radius of the solder balls.

[0113] C. Redistribution Layer Modeling (RDL Modeling)

[0114] Similar to the solder ball layer, the redistribution layer (RDL) consists of copper and silicon dioxide, and silicon dioxide is usually a medium with a low thermal conductivity. For this reason, a uniformly wired RDL was constructed and its equivalent thermal conductivity was measured.

[0115] Figure 9 in Table II of Figure 4 (b) and Figure 5 (b) show the following:

[0116] 1) The equivalent thermal conductivity of the RDL is linearly and positively correlated with the line width of the wiring;

[0117] 2) The equivalent thermal conductivity of the RDL is approximately linearly correlated with the wiring array density. When the line width of the wiring layer increases relative to the chip size to an extent that cannot be ignored, the marginal effect of the equivalent thermal conductivity changing with the wiring array density gradually becomes apparent;

[0118] 3) The equivalent thermal conductivity of the RDL hardly changes with temperature. When the temperature rises from 350K to 380K, the change amplitude of the equivalent thermal conductivity is less than 0.5%.

[0119] Based on the above observations, the thermal conductivity can be expressed as a function of the wiring pitch and line width for RDL modeling, as shown in Figure 5 (b). When constructing the look-up table (LUT) of the RDL equivalent thermal conductivity, the parameters of the look-up table are set as the wiring pitch and line width, so that the equivalent thermal conductivity can be obtained through bilinear interpolation. The marginal effect of the line width is due to the overlap between the horizontal and vertical wirings when constructing a uniform wiring layer, resulting in a slower growth rate of the area of the RDL equivalent heat conduction region as the line width increases.

[0120] D. Through-Silicon Via Modeling (TSV Modeling)

[0121] The TSV layer is the most effective heat conduction path inside the chip stack. The thermal conductivities of copper and the surrounding silicon are both higher than the equivalent thermal conductivities of the solder ball layer and the RDL. The thermal conductivity of silicon shows an obvious downward trend with temperature. Therefore, it is inaccurate to directly deduce the equivalent thermal conductivity of the TSV layer by querying the array density and radius of the TSV.

[0122] As shown in Figure 6 , the downward trend of the equivalent thermal conductivity of the TSV layer with temperature is close to the thermal conductivity curve of silicon. As the TSV array density and radius increase, the equivalent thermal conductivity of the TSV layer also increases and maintains its original downward trend with temperature.

[0123] Due to the sensitivity of the TSV layer thermal conductivity to temperature, avoid directly calculating its equivalent thermal conductivity through the array density and size of the TSV, but consider it as a weighted mixture of the thermal conductivities of silicon and copper,

[0124] k TSV = αk Cu +(1 - α)k Si #(4)

[0125] where α is the mixing coefficient. For this reason, the relationship between the equivalent thermal conductivity of the TSV layer and the mixing coefficient α at multiple temperatures was measured, and the results are shown in Figure 7 . The change of the mixing coefficient α of the thermal conductivities of the two materials with temperature can be ignored. At Figure 5(c), we plotted the relationship between α and the TSV array density and radius. The mixing coefficient α shows an approximately linear relationship with the array density and cross-sectional area of the TSVs. In this way, a look-up table (LUT) based on the TSV array density and radius parameters was constructed for the thermal conductivity mixing coefficient α of the TSV layer. We used an iterative method to obtain the equivalent thermal conductivity of the TSV layer:

[0126] 1) Obtain the value of the mixing coefficient α through the look-up table (LUT);

[0127] 2) Query the initial thermal conductivities of copper and silicon at the expected operating temperature of the chip;

[0128] 3) Calculate the equivalent thermal conductivity of the TSV layer according to Equation 4;

[0129] 4) Use the macro model containing the equivalent thermal conductivity for simulation, calculate the temperature of the TSV layer, and update the thermal conductivities of copper and silicon;

[0130] 5) Update the equivalent thermal conductivity of the TSV layer.

[0131] Since the thermal conductivity of the TSV layer is better than that of the RDL and solder ball layers and its temperature gradient is smaller, in our dataset, this process converges after one iteration.

[0132] F. Summary

[0133] In summary, the present invention constructs look-up tables (LUTs) for the solder ball layer, RDL, and TSV layer for each chip size and height respectively. The modeling method is as shown in Table IV in Figure 11 :

[0134] k′ Bump = LUT(h, ρ Bump , r Bump )

[0135] k′ RDL = LUT(h, s RDL , ω RDL )

[0136] α = LUT(h, ρ TSV , r TSV )

[0137] k′ TSV = αk Cu + (1 - α)k Si

[0138] k′ Bump represents the effective thermal conductivity of the solder ball, k′ TSV represents the effective thermal conductivity of the through-silicon via, k′ RDL represents the effective thermal conductivity of the redistribution layer, where S is the chip size, h is the layer height, ρBump is the solder ball array density, r Bump is the solder ball radius, s RDL is the line pitch in the RDL, ω RDL is the line width in the RDL, ρ TSV is the TSV array density, r TSV is the TSV radius, k Si represents the thermal conductivity of silicon, k Cu represents the thermal conductivity of copper.

[0139] In the design space exploration, once the material parameters of each layer are determined, the equivalent models of the solder ball, RDL, and TSV layers can be quickly established using the modeling method we proposed. In a typical design scenario, the distributions of TSVs, solder balls, and RDLs within a layer are usually not uniform, but the layer can be subdivided into multiple uniform small blocks. We build a macro model for each small block (a macro model refers to a high-level simplification of a refined model, representing a complex refined model with a (parameterized) simple model), and the combined macro models of multiple small blocks form an equivalent layer. These models can be directly stacked and used to simulate chip stacking in 3D integrated circuits. Based on the above models, the temperature distribution of multi-layer stacking can be quickly explored. In addition, the number of stacked chips, and the array densities of TSVs and solder balls can be quickly evaluated to optimize the thermal field.

[0140] IV. Experiments

[0141] A. Experimental Setup

[0142] 1) Simulation Setup: To verify the accuracy of the model, five chip stacking configurations were designed, with the number of stacked chips ranging from 2 to 5. Each chip stack includes a TSV layer, a solder ball layer, an RDL, and a heat source. We record the temperature on the surface of each chip to measure the accuracy of the macro model we proposed (one macro model corresponds to each inter-chip layer). The power was randomly set for each case, resulting in an internal temperature range of 350K to 420K for the bottom chip. Other material and structure parameters are shown in Figure 8 Table I in. A sufficiently fine grid was used for each case, and COMSOL Multiphysics was used for simulation as the gold standard model.

[0143] 2) Evaluation Metrics: The proposed macro model was simulated using COMSOL on a sparse grid, and the maximum temperature, minimum temperature, and average temperature on the surface of each chip were recorded. In addition, the mean absolute error (MAE) and mean absolute relative error (MARE) based on temperature were also recorded. These temperatures were calculated on the grid according to the TSV or solder ball pitch to evaluate the effectiveness of the model. To accurately calculate the relative error, the Kelvin temperature was converted to Celsius when calculating MARE.

[0144] B. Quantitative Comparison

[0145] The method of this application was compared with other equivalent methods in four cases, as described in the experimental setup section. Since these two equivalent methods did not report results of non-uniform distribution, for fair comparison, the TSVs, solder balls, and RDLs were evenly distributed in each layer. The temperatures of the bottom chips in the four cases are as Figure 12 shown in Table V. The experimental results show that the model of this application exhibits good accuracy in all four cases. When there are only two layers of chips, the errors of the other two methods are smaller. However, as the number of stacked chips increases, neither of the existing two methods can maintain a small error (the errors of the different models reach 17.02% and 5.71% respectively), while the error of the model of this application is negligible (the maximum error is only 0.45%).

[0146] C. Efficiency Evaluation

[0147] To further verify the efficiency of our macro model, we compared the running times of the above four cases. Although the work of building the ETC in COMSOL is different from our calculation, the computational efficiency of the macro model is not affected. Therefore, we only compare it with the gold standard model using COMSOL, as Figure 13 shown in Table VI. It can be seen that the macro model reduces the number of meshes and improves the calculation speed. In the case of five-layer chip stacking, we can reduce more than 80% of the meshes and accelerate by more than 60 times (the simulation time is reduced from 30 minutes to 30 seconds). It should be noted that as the number of stacked chips increases, the growth rate of the running time of the macro model is expected to be less than that of the gold standard simulation, thus achieving a greater acceleration effect.

[0148] D. Thermal Field Verification

[0149] To better evaluate the effectiveness of our stackable macro model, we constructed three groups of cases to simulate design cases with different complexities, namely uniform distribution, globally non-uniform locally uniform (GNLU), and randomly reducing solder balls, TSVs, and wirings based on GNLU. The experimental results are as Figure 7 and Figure 14 shown in Table VII.

[0150] 1) Uniform distribution: We first constructed a uniform case with four-layer stacking, where the TSVs, RDLs, and Bumps are evenly distributed within each layer. From the results, it can be seen that the relative error of our macro model in each layer is less than 1%, and the error in the maximum, minimum, or average temperature is less than 0.5%. The lower-layer chip stacks face worse working conditions. However, the simulation error of our macro model remains almost constant and does not show an increasing trend as the stacking depth increases, demonstrating that our model is stackable.

[0151] 2) Global Non-uniform Local Uniform (GNLU): In a typical design scenario, TSVs, bumps, and RDLs are usually non-uniformly distributed within a layer, but tend to be uniformly distributed within each sub-region. We constructed a global non-uniform local uniform case with four stacked layers, each layer being divided into four regions, and the TSVs, RDLs, and bumps within each region having different array densities. The pitch of TSVs and bumps ranges from 200μm to 2000μm. The experimental results (see Figure 7 and Figure 14 Table VII therein) show that our model still maintains a relative error of less than 1%.

[0152] 3) Randomly reduced GNLU: We randomly reduce 5% - 10% of the TSVs and bumps in each region based on GNLU, so that the distribution of TSVs and bumps within each local region is no longer strictly uniform. Compared with GNLU, an increase in temperature is observed for both our model and the golden result. The experimental results (see Table VII) show that despite this change, the macro-model can still maintain a high-precision simulation result (error less than 1%). The influence of individual TSVs and bumps on the temperature distribution is limited. In the design, the pitch of TSVs and bumps is less than the effective diffusion distance of heat in the horizontal direction. Therefore, by using statistical density to calculate ETC, we can still obtain highly accurate simulation results.

[0153] In summary, the present invention proposes a stackable thermal model considering inter-die layers (IDLs). This application proves that inter-die layers cannot be ignored as assumed in existing studies. Subsequently, we map each chip or IDL layer to an equivalent homogeneous layer and construct a look-up table for each type of layer separately. The finally generated layer-by-layer model can be stacked in temperature calculation. The experimental results show that our modeling method achieves more than 60 times acceleration (simulation time is reduced from 30 minutes to 30 seconds) in the case of five-chip stacking, while the accuracy loss is less than 1%. In contrast, the best result of existing studies has an error of up to 5.71%.

[0154] This application presupposes that the power density of each chip is uniform. This presupposition is applicable to early design exploration and conforms to the design practice that a single chip usually adopts a single circuit type and process. In this case, future research can achieve acceleration by calculating the temperature through an analytical method. But more importantly, subsequent research will further consider the non-uniform power density distribution within the chip.

Claims

1. A stackable thermal modeling method for 3D integrated circuits, characterized in that, Including the following steps: Step (a): Map at least one vertical interconnection layer in a 3D integrated circuit into an equivalent layer with uniform effective thermal conductivity, where the vertical interconnection layer includes one or more of through-silicon vias (TSVs), micro-bumps (μbumps), controlled collapse chip connections (C4) bumps, or redistribution layers (RDLs); Step (b): Establish a corresponding effective thermal conductivity look-up table (LUT) for each type of vertical interconnection layer, and the look-up table is generated based on the geometric parameters and material thermal conductivity parameters of the vertical interconnection layer; Step (c): According to the stacking structure of the target 3D integrated circuit, stack the equivalent layers in a predetermined order, and calculate the overall temperature distribution after stacking based on the effective thermal conductivity in the look-up table through the heat conduction equation.

2. The method according to claim 1, wherein In step (a), the mapping process includes: Step (a1): For the layer containing TSVs, calculate the equivalent thermal conductivity through a mixing coefficient model according to the TSV array density, radius, and temperature-dependent thermal conductivities of copper and silicon; Step (a2): For the layer containing μbumps or C4 bumps, calculate the equivalent thermal conductivity through a linear interpolation model according to the solder ball array density, radius, and epoxy resin thermal conductivity; Step (a3): For the layer containing RDLs, calculate the equivalent thermal conductivity through a bilinear interpolation model according to the wiring pitch, line width, and silica thermal conductivity.

3. The method according to claim 2, wherein The equivalent thermal conductivity of the TSV layer is determined through the following iterative process: Step (i): Obtain the mixing coefficient based on the look-up table of TSV array density and radius; Step (ii): Calculate the initial equivalent thermal conductivity according to the thermal conductivities of copper and silicon at the current temperature, in combination with the mixing coefficient; Step (iii): Use the initial equivalent thermal conductivity for temperature simulation, update the temperature distribution, and recalculate the thermal conductivities of copper and silicon; Step (iv): Repeat steps (ii) to (iii) until the equivalent thermal conductivity converges.

4. The method according to claim 1, characterized in that The geometric parameters include at least one of the following: For the TSV layer: TSV array density, radius, and layer thickness; For the μbumps or C4 bump layer: solder ball array density, radius, and layer thickness; For the RDL layer: wiring pitch, line width, and layer thickness.

5. The method according to claim 2, characterized in that, Step (b) includes the following steps: (b1) For the through-silicon via (TSV) layer, generate a longitudinal and transverse effective thermal conductivity look-up table, i.e., the first type of LUT, through a mixing coefficient model according to the TSV array density, radius, and layer thickness parameters, in combination with the temperature-dependent thermal conductivities of copper and silicon; (b2) For the micro-bump (μbumps) or C4 bump layer, generate an isotropic effective thermal conductivity look-up table, i.e., the second type of LUT, through a linear interpolation model according to the solder ball array density, radius, and layer thickness parameters, based on the epoxy resin thermal conductivity; (b3) For the redistribution layer (RDL), generate an anisotropic effective thermal conductivity look-up table, i.e., the third type of LUT, through a bilinear interpolation model according to the wiring pitch, line width, and layer thickness parameters, based on the silica thermal conductivity; (b4) Store the look-up table as a multi-dimensional array structure.

6. The method according to claim 5, wherein The relationship of the effective thermal conductivity look-up table (LUT) is as follows: k′ Bump = LUT(h, ρ Bump , r Bump ) k′ RDL = LUT(h, s RDL , ω RDL ) k′ TSV = αk Cu + (1 - α)k Si α = LUT(h, ρ TSV , r TSV ) k' Bump represents the effective thermal conductivity of solder balls, k' TSV represents the effective thermal conductivity of through - silicon vias, k' RDL represents the effective thermal conductivity of the redistribution layer, where S is the chip size, h is the layer height, ρ Bump is the solder ball array density, r Bump is the solder ball radius, S RDL is the line pitch in the RDL, ω RDL is the line width in the RDL, ρ TSV is the TSV array density, r TSV is the TSV radius, k Si represents the thermal conductivity of silicon, k Cu represents the thermal conductivity of copper.

7. The method according to claim 1, wherein In step (c), at least one equivalent layer of the stacked structure includes a vertically interconnected structure with non-uniform distribution, and by dividing the layer into multiple locally uniform sub-regions, each sub-region is modeled with a corresponding effective thermal conductivity.

8. The method according to claim 1, wherein The method further includes: When stacking equivalent layers, the inter-chip dielectric layer IDL is included in the calculation as an independent equivalent layer, and the inter-chip dielectric layer includes μ bumps and adjacent RDL structures.

9. A computer-readable storage medium storing a computer program, characterized in that, When the program is executed by a processor, it implements the steps of the method according to any one of claims 1-8.

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