Circuit model of neutral time-delay neural network system and design method

Abstract

The invention relates to the technical field of artificial intelligence, in particular to a circuit model of a neutral time-delay neural network system and a design method, and the circuit model comprises a time-delay circuit, an activation function circuit, an integrating circuit, a differentiating circuit, a summing circuit and a gain circuit, wherein the output of the time delay circuit is connected with the input of the activation function circuit to serve as a first forward channel, the output of the time delay circuit is connected with the input of the differentiating circuit to serve as a second forward channel, the gain circuit is independently used as a third forward channel, and the integrating circuit is used as a feedback channel; according to the invention, the neutral item is added in the neuron circuit, so that the circuit can show the oscillation and unstable influence caused by the time-delay change rate of the signal in the neuron transmission process, and is of great significance to the dynamics research of the time-delay neural network, thereby more accurately designing the simulation neural network circuit, and improving the reliability of the simulation neural network circuit. Meanwhile, a thought is provided for the design of the neutral time-delay neural network circuit.

Description

Technical Field

[0001] The present invention relates to the field of artificial intelligence technology, and in particular to a circuit model and a design method for a neutral time-delay neural network system. Background Art

[0002] The cellular neural network (CNN), originally proposed by Hung C. Lin, Chua, and others in 1988, is a computational model inspired by biological neural systems. Its structure consists of cells (elements) connected in a regular pattern to enable parallel computing and information processing. Subsequently, researchers have continuously explored and improved upon this foundation, driving the continued development of CNNs. Time delays are ubiquitous in real-world systems, such as those in biology, chemistry, and electrical engineering, which suffer from delays in signal transmission and processing.

[0003] To better simulate and address time-delay issues in real-world systems, researchers have begun introducing time-delay into cellular neural networks. These delay cellular neural networks build upon the basic cellular neural network structure by incorporating time-delay components to simulate the time-delay effects in the system. The introduction of time-delay enables the network to handle more complex dynamic systems and enhances modeling capabilities. Neutrality refers to the fact that certain components in the network do not directly respond to changes in certain variables. Neutral time-delay cellular neural networks take this neutrality into account, making the network more flexible and better able to adapt to diverse system dynamics.

[0004] Neutral time-delay cellular neural networks have a wide range of applications in the modeling, simulation, and control of dynamical systems. They have been successfully applied to complex nonlinear systems such as biological systems, power systems, and ecosystems, providing an effective tool for solving practical problems. However, research on neutral time-delay cellular neural networks faces several challenges, including network stability and the impact of time delay on network performance.

[0005] Researchers are continuously driving innovation in networks by introducing new methods and technologies, such as optimization algorithms and deep learning. In the future, neutral time-delay cellular neural networks are expected to find widespread application in even more fields, particularly in adaptive control and complex system modeling and simulation. Researchers will continue to refine network structures and algorithms to enhance their performance and adaptability, driving further development in this field.

[0006] At present, most research on neutral time-delay neural networks is still at the theoretical level, and no circuit model of neutral time-delay neural networks has been established.

[0007] Therefore, a circuit model and design method of a neutral time-delay neural network system are proposed. Summary of the Invention

[0008] The object of the present invention is to provide a circuit model and design method for a neutral time-delay neural network system to solve the above problems, and to prove its stability from an actual physical circuit through simulation experiments.

[0009] The present invention realizes the above object through the following technical solutions. A circuit model and design method for a neutral time-delay neural network system includes a time-delay circuit, an activation function circuit, an integration circuit, a differential circuit, a summation circuit, and a gain circuit. The output of the time-delay circuit is connected to the input of the activation function circuit as the first forward channel, the output of the time-delay circuit is connected to the input of the differential circuit as the second forward channel, the gain circuit is used alone as the third forward channel, and the integration circuit is used as the feedback channel. Three signals are respectively led from the state signal of neuron X1 through the first, second, and third forward channels to converge with the disturbance signal and the state feedback signal of neuron X2 to the first-order differential signal of the state signal of neuron X1. One signal is led from the state signal of neuron X1 through the third forward channel to the input terminal of the summation circuit of neuron X2. Then, the first-order differential signal of the state signal of neuron X1 returns to the state signal of neuron X1 through the integration circuit. The state signal of X1 reaches the activation function circuit and the differential circuit in two paths through the time-delay circuit. The signal output from the activation function circuit reaches the input terminal of the adder circuit of this neuron after passing through the gain circuit, and the signal output from the differential circuit also reaches the input terminal of the adder circuit of this neuron after being amplified by the gain circuit. The external input enters the adder circuit from a fixed 2V power supply. All the input signals entering the adder circuit reach the first-order differential signal of the state signal of this neuron after passing through the adder circuit, and the first-order differential signal returns to the state signal of this neuron through the integration circuit.

[0010] The state signal of neuron X2 reaches the input terminal of the summation circuit of neuron X2 together with the state feedback signal of neuron X1, the state feedback signal of neuron X3, and the disturbance signal of neuron X2 through the third forward channel of neuron X2. The output terminal of the summation circuit of neuron X2 is the first-order differential signal of the state signal of neuron X2. Then, the first-order differential signal of the state signal of neuron X2 returns to the state signal of neuron X2 through the integration circuit.

[0011] The state signal of neuron X3 reaches the input terminal of the adder circuit of neuron X2 through the third forward channel of neuron X3. The state signal of neuron X2 enters the input terminal of the summation circuit of neuron X3 together with the disturbance signal of neuron X3 through the first and third forward channels of neuron X2 respectively. The output terminal of the summation circuit of neuron X3 is the first-order differential signal of the state signal of neuron X3. Then, the first-order differential signal of the state signal of neuron X3 returns to the state signal of neuron X3 through the integration circuit.

[0012] Among them, further, in the neuron X1, the input end of the time-delay circuit is connected to the state signal of the neuron X1, and its output end is respectively connected to the input end of the differential circuit and the input end of the activation function circuit; the output end of the activation function circuit is connected to the input end of the gain circuit 2, and the output end of the gain circuit 2 is connected to one input end of the summing circuit of the neuron X1;

[0013] The output end of the differential circuit is connected to the input end of the gain circuit 3, and the output end of the gain circuit 3 is connected to one input end of the summing circuit of the neuron X1;

[0014] The input end of the gain circuit 1 is connected to the state signal of the neuron X1, and its output end is connected to one input end of the summing circuit of the neuron X1;

[0015] The external input signal is directly connected to one input end of the summing circuit of the neuron X1 by a 2V power supply signal;

[0016] The last input end of the summing circuit of the neuron X1 is connected to the state feedback signal from the neuron X2, and the output end of the summing circuit of the neuron X1 is connected to the first-order differential signal of the state signal of the neuron X1;

[0017] The input end of the integration circuit is connected to the first-order differential signal of the state signal of the neuron X1, and its output end is connected to the state signal of the neuron X1.

[0018] Among them, further, in the neuron X2, the input end of the time-delay circuit is connected to the state signal of the neuron X2, and its output end is connected to the input end of the activation function circuit;

[0019] The output end of the activation function circuit is connected to the input end of the gain circuit 5, and the output end of the gain circuit 5 is connected to one input end of the summing circuit of the neuron X3;

[0020] The input end of the gain circuit 4 is connected to the state signal of the neuron X2, and its output end is connected to one input end of the summing circuit of the neuron X2; the external input signal is directly connected to one input end of the summing circuit of the neuron X2 by a 2V power supply signal;

[0021] The input end of the gain circuit 6 is connected to the state signal of the neuron X3, and its output end is connected to one input end of the summing circuit of the neuron X2;

[0022] The last input end of the summing circuit of the neuron X2 is connected to the state feedback signal from the neuron X1, and the output end of the summing circuit of the neuron X2 is connected to the first-order differential signal of the state signal of the neuron X2;

[0023] The input terminal of the integrating circuit of neuron X2 is connected to the first-order differential signal of the state signal of neuron X2, and its output terminal is connected to the state signal of neuron X2.

[0024] In neuron X3, the input terminals of the summing circuit are respectively connected to the state feedback signal of neuron X2, the output terminal of the activation function circuit of neuron X2, and the perturbation signal of neuron X3. Its output terminal is connected to the first-order differential signal of the state signal of neuron X3. The input terminal of the integrating circuit of neuron X3 is connected to the first-order differential signal of the state signal of neuron X3, and its output terminal is connected to the state signal of neuron X3.

[0025] Among them, further, the time-delay circuit includes a signal input terminal and a signal output terminal. The two signal terminals inside the time-delay circuit are respectively connected to two operational amplifier circuits and are connected by an LCL network in the middle. Corresponding matching resistors are added at both ends of the LCL filter circuit. However, the introduction of the matching resistor will cause a certain degree of attenuation to the input signal. Therefore, an operational amplifier is required for gain adjustment.

[0026] The activation function circuit includes a signal input terminal and an output terminal. The two signal terminals of the activation function circuit are respectively used as the input and output signals of the internal function circuit. Its internal is a function circuit composed of an absolute value circuit and an addition and subtraction circuit. The mathematical model of the activation function is f(x) = 0.5(|x + 1| - |x - 1|).

[0027] Among them, further, the time-delay circuit includes two operational amplifier units OP1 and OP2 at both ends, and an LCL filter network in the middle. The front end of the LCL filter network is connected to OP1, and the back end is connected to OP2.

[0028] For the activation function circuit described above, its internal input signal is respectively sent to an addition circuit and a subtraction circuit, then passes through an absolute value circuit and a 0.5-fold gain circuit, converges into a subtraction circuit, and then outputs.

[0029] The integrating circuit, differentiating circuit, and gain circuit are all composed of a combination of operational amplifiers.

[0030] Among them, further, the differentiating circuit is composed of a feedback resistor Rf, a forward input terminal resistor Rc, a reverse input terminal capacitor C1, and an operational amplifier; the integrating circuit is composed of a reverse input terminal resistor R44, a forward input terminal resistor Rc1, a feedback capacitor C2, and an operational amplifier.

[0031] The gain circuit 1 is composed of a forward input terminal resistor R29, a feedback resistor R28, and an operational amplifier.

[0032] The described absolute value circuit has the input signal reaching the positive input terminals of U1 and U2 respectively through two paths. The output terminal of U1 is connected to diode D5, and the other end of D5 reaches the negative input terminal of U1 and R59 respectively. The output terminal of U2 is connected to resistor R62, and the other end of R62 reaches the negative input terminal of U2 and R61 respectively. R61 is connected to diode D6 and resistor R60 respectively. The other end of R60 reaches the negative input terminal of U1 and R59 respectively. The other end of R59 is grounded;

[0033] The described LCL filter circuit has the input signal reaching one end of inductor L1 through matching resistor R7. The other end of L1 is connected to inductor L2 and capacitor C3 respectively. The other end of C3 is grounded. The other end of L2 is connected to matching resistors R8 and R9 respectively. The other end of R8 is grounded, and the other end of R9 outputs.

[0034] Another object of the present invention is to provide a design method for a neutral type time-delay neural network circuit model, including the following steps:

[0035] Step 1: Select a suitable time constant τ according to requirements, then design an LCL filter network according to the time constant τ. Secondly, select suitable matching resistors at both ends of the LCL. Finally, select a suitable gain coefficient to design an amplifier circuit at both ends. Finally, build a time-delay circuit according to the method described in claim 3;

[0036] Step 2: Select a suitable neural network activation function according to requirements, then perform an approximate transformation according to the mathematical model of the activation function to make the activation function easier to process in the circuit. Secondly, select a calculation unit circuit according to the activation function. Finally, build an activation function circuit according to the method described in claim 3;

[0037] Step 3: Select a suitable amplification factor for the gain circuit according to requirements and circuit stability analysis, then select the resistance ratio of the amplifier circuit according to the amplification factor. Finally, build a gain circuit according to the basic operational amplifier circuit structure;

[0038] Step 4: Select the component parameters of a suitable integral circuit and differential circuit through circuit parameter analysis. Generally, an empirical method is adopted for processing. By referring to the general selection of differential circuits and integral circuits in engineering under the input of signals at this magnitude for building;

[0039] Step 5: After completing the design of the above sub-circuits, the design of the neuron circuit can be carried out. First, understand the state equation and dynamic equation of the built neural network, then connect the circuit according to the known stable parameters to build the neuron circuit. Finally, build a neural network model according to the relationship between neurons.

[0040] The beneficial effects of the present invention are:

[0041] The present invention adds a neutral item to the neuron circuit, enabling the circuit to exhibit the oscillation and instability effects brought about by the time-delay change rate during the signal transmission in neurons, which is of great significance for the dynamic research of time-delay neural networks. Thus, the analog neural network circuit can be designed more accurately, and at the same time, a design idea for the neutral-type time-delay neural network circuit is provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 is the main circuit diagram of the present invention;

[0043] Figure 2 is the time-delay circuit diagram of the present invention;

[0044] Figure 3 is the activation function circuit diagram of the present invention;

[0045] Figure 4 is the simulation result diagram of the present invention.

[0046] In the drawings: Neuron X1, the state response curve of neuron X1; Neuron X2, the state response curve of neuron X2; Neuron X3, the state response curve of neuron X3. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0047] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0048] Embodiment 1

[0049] A circuit model of a neutral-type time-delay neural network mainly includes: an integration circuit, a differential circuit, a time-delay circuit, an activation function circuit, an addition circuit, and a gain circuit.

[0050] The time-delay circuit includes a signal input terminal and a signal output terminal. Inside the two signal terminals of the time-delay circuit, they are respectively connected to two operational amplifier circuits, and are connected by an LCL network in the middle. Corresponding matching resistors are added at both ends of the LCL filter circuit. However, the introduction of the matching resistors will cause a certain degree of attenuation to the input signal. Therefore, an operational amplifier is required for gain adjustment. The function of the time-delay circuit is to generate a time-delay signal of the state signal.

[0051] The activation function circuit includes a signal input terminal and an output terminal. The two signal terminals of the activation function circuit serve as the input and output signals of the internal function circuit respectively. Internally, it is a function circuit composed of an absolute value circuit and an addition and subtraction circuit. The internal input signals are respectively sent to the addition circuit and the subtraction circuit, then pass through the absolute value circuit and the 0.5-fold gain circuit, converge into the subtraction circuit, and then output. The role of the activation function is to make the signal non-linear, improve the accuracy of the model, and alleviate the disappearance of the gradient.

[0052] The integral circuit, differential circuit, summation circuit, and gain circuit are all composed of combinations of basic operational amplifier circuits.

[0053] Embodiment 2

[0054] A design method for the circuit model of a neutral time-delay neural network includes the following steps:

[0055] Step 1: Select a suitable time constant τ according to requirements, then design an LCL filter network based on the time constant τ. Secondly, select appropriate matching resistors at both ends of the LCL, and finally select a suitable gain coefficient to design the two-end amplifier circuit. Finally, build the time-delay circuit according to the method introduced in claim 3.

[0056] Step 2: Select a suitable neural network activation function according to requirements, then perform an approximate transformation according to the mathematical model of the activation function to make the activation function easier to process in the circuit. Secondly, select the calculation unit circuit according to the activation function, and finally build the activation function circuit according to the method introduced in claim 3.

[0057] Step 3: Select the appropriate amplification factor of the gain circuit according to requirements and circuit stability analysis, then select the resistance ratio of the amplifier circuit according to the amplification factor, and finally build the gain circuit according to the basic operational amplifier circuit structure.

[0058] Step 4: Select the component parameters of the appropriate integral circuit and differential circuit through circuit parameter analysis. Generally, the empirical method is adopted for processing. By referring to the engineering selection of differential circuits and integral circuits for building under the signal input of this magnitude.

[0059] Step 5: After completing the design of the above sub-circuits, the design of the neuron circuit can be carried out. First, understand the state equation and dynamic equation of the built neural network, then connect the circuits according to the known stable parameters to build the neuron circuit, and finally build the neural network model according to the relationship between neurons.

[0060] Among them, the dynamic characteristics of the neutral time-delay neural network can be described by the following state equation:

[0061]

[0062] Among them, \(x(t)\) is the state variable, \(f(x(t))\) is the output vector, \(A\) and \(D\) are state feedback matrices, \(B\) is the state time-delay feedback matrix, \(J\) is the constant external input vector. In the present invention, the activation function is set as \(f(x)=0.5(|x + 1|-|x - 1|)\), and its dynamic equation is:

[0063]

[0064] Considering the global asymptotic stability problem of neutral neural time-delay networks, the present invention innovatively constructs a Lyapunov-Krasovskii functional and uses the free-weight matrix technique to successfully derive some linear matrix inequalities with more relaxed constraints for the new stability conditions. When considering the global exponential stability problem of neutral time-delay neural networks, previous scholars have proposed new sufficient conditions that are easy to verify and provided an estimation method for the exponential convergence degree, providing a theoretical guarantee for the design of such neural networks. In this research, the present invention adopts the method of semi-free weight matrices, that is, the matrices used are used to express the relationships between the terms in the Leibniz–Newton formula and are not completely independent. These matrices are related to the relevant matrices in the traditional Lyapunov-Krasovskii functional. By using this method, it is possible to avoid involving too many free weight matrices, simplify the analysis process, and reduce the computational complexity. Through the above theory, the parameters for maintaining the system stability can be easily found.

[0065] In addition, it should be understood that although this specification is described according to the embodiments, not every embodiment only contains an independent technical solution. This narrative way of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A circuit model of a neutral time-delay neural network system, characterized in that, It includes a time-delay circuit, an activation function circuit, an integration circuit, a differentiation circuit, a summation circuit, and a gain circuit. The output of the time-delay circuit is connected to the input of the activation function circuit as the first forward channel, the output of the time-delay circuit is connected to the input of the differentiation circuit as the second forward channel, the gain circuit is alone as the third forward channel, and the integration circuit is used as the feedback channel. Three signals are respectively led from the state signal of neuron X1 through the first, second, and third forward channels of neuron X1, and are combined with the perturbation signal of neuron X1 and the state feedback signal of neuron X2 through the summation circuit to reach the first-order differential signal of the state signal of neuron X1. One signal is led from the state signal of neuron X1 through the first forward channel of neuron X1 and connected to the input end of the summation circuit of neuron X2. Then, the first-order differential signal of the state signal of neuron X1 returns to the state signal of neuron X1 through the integration circuit. The state signal of X1 reaches the activation function circuit and the differentiation circuit in two paths through the time-delay circuit, and then reaches the input end of the summation circuit of neuron X1 after being amplified by the gain circuit respectively. The state signal of neuron X2 reaches the input end of the summation circuit of neuron X2 together with the state feedback signal of neuron X1, the state feedback signal of neuron X3, and the perturbation signal of neuron X2 through the third forward channel of neuron X2. The output end of the summation circuit of neuron X2 is the first-order differential signal of the state signal of neuron X2. Then, the first-order differential signal of the state signal of neuron X2 returns to the state signal of neuron X2 through the integration circuit. The state signal of neuron X3 reaches the input end of the addition circuit of neuron X2 through the third forward channel of neuron X3. The state signal of neuron X2 enters the input end of the summation circuit of neuron X3 together with the perturbation signal of neuron X3 through the first and third forward channels of neuron X2 respectively. The output end of the summation circuit of neuron X3 is the first-order differential signal of the state signal of neuron X3. Then, the first-order differential signal of the state signal of neuron X3 returns to the state signal of neuron X3 through the integration circuit. The perturbation inputs of neurons X1, X2, and X3 respectively enter their respective addition circuits from a fixed 2V power supply. All the input signals entering the addition circuit reach the first-order differential signal of the state signal of this neuron after passing through the addition circuit, and the first-order differential signal returns to the state signal of this neuron through the integration circuit.

2. The circuit model of the neutral time-delay neural network system according to claim 1, characterized in that: In the neuron X1, the input end of the time-delay circuit is connected to the state signal of neuron X1, and its output end is respectively connected to the input end of the differentiation circuit and the input end of the activation function circuit; the output end of the activation function circuit is connected to the input end of gain circuit 2, and the output end of gain circuit 2 is connected to one input end of the summation circuit of neuron X1; The output end of the differentiation circuit is connected to the input end of gain circuit 3, and the output end of gain circuit 3 is connected to one input end of the summation circuit of neuron X1; The input end of gain circuit 1 is connected to the state signal of neuron X1, and its output end is connected to one input end of the summation circuit of neuron X1; The external input signal is directly connected to an input terminal of the summing circuit of neuron X1 by a 2V power supply signal; The last input terminal of the summing circuit of neuron X1 is connected to the state feedback signal from neuron X2, and the output terminal of the summing circuit of neuron X1 is connected to the first-order differential signal of the state signal of neuron X1; The input terminal of the integration circuit is connected to the first-order differential signal of the state signal of neuron X1, and its output terminal is connected to the state signal of neuron X1.

3. The circuit model of the neutral time-delay neural network system according to claim 1, characterized in that: In neuron X2, the input terminal of the time-delay circuit is connected to the state signal of neuron X2, and its output terminal is connected to the input terminal of the activation function circuit; The output terminal of the activation function circuit is connected to the input terminal of gain circuit 5, and the output terminal of gain circuit 5 is connected to an input terminal of the summing circuit of neuron X3; The input terminal of gain circuit 4 is connected to the state signal of neuron X2, and its output terminal is connected to an input terminal of the summing circuit of neuron X2; the external input signal is directly connected to an input terminal of the summing circuit of neuron X2 by a 2V power supply signal; The input terminal of gain circuit 6 is connected to the state signal of neuron X3, and its output terminal is connected to an input terminal of the summing circuit of neuron X2; The last input terminal of the summing circuit of neuron X2 is connected to the state feedback signal from neuron X1, and the output terminal of the summing circuit of neuron X2 is connected to the first-order differential signal of the state signal of neuron X2; The input terminal of the integration circuit of neuron X2 is connected to the first-order differential signal of the state signal of neuron X2, and its output terminal is connected to the state signal of neuron X2. According to the circuit model of the neutral time-delay neural network system described in claim 1, it is characterized in that: in neuron X3, the input terminals of the summing circuit are respectively connected to the state feedback signal of neuron X2, the output terminal of the activation function circuit of neuron X2, and the perturbation signal of neuron X3, and its output terminal is connected to the first-order differential signal of the state signal of neuron X3. The input terminal of the integration circuit of neuron X3 is connected to the first-order differential signal of the state signal of neuron X3, and its output terminal is connected to the state signal of neuron X3.

4. The circuit model of the neutral type time-delay neural network system according to claim 1, characterized in that: The time-delay circuit includes a signal input terminal and a signal output terminal. The two signal terminals inside the time-delay circuit are respectively connected to two operational amplifier circuits and are connected by an LCL network in the middle. Corresponding matching resistors are added at both ends of the LCL filter circuit. However, the introduction of the matching resistor will cause a certain degree of attenuation to the input signal. Therefore, an operational amplifier is required for gain adjustment; The activation function circuit includes a signal input terminal and an output terminal. The two signal terminals of the activation function circuit are respectively used as the input and output signals of the internal function circuit. Its internal is a function circuit composed of an absolute value circuit and an addition and subtraction circuit. The mathematical model of the activation function is f(x) = 0.5(|x + 1| - |x - 1|).

5. The circuit model of the neutral time-delay neural network system according to claim 4, characterized in that: The time-delay circuit includes two operational amplifier units OP1 and OP2 at both ends, and an LCL filter network in the middle. The front end of the LCL filter network is connected to OP1, and the rear end is connected to OP2; For the described activation function circuit, its internal input signals are respectively sent to an addition circuit and a subtraction circuit, then pass through an absolute value circuit and a 0.5 - fold gain circuit, converge and enter the subtraction circuit, and then output. The described integration circuit, differentiation circuit, and gain circuit are all composed of operational amplifier combinations.

6. The circuit model of the neutral time-delay neural network system according to any one of claims 1 or 5, characterized in that: The described differentiation circuit is composed of a feedback resistor Rf, a forward - input - terminal resistor Rc, a reverse - input - terminal capacitor C1, and an operational amplifier; the described integration circuit is composed of a reverse - input - terminal resistor R44, a forward - input - terminal resistor Rc1, a feedback capacitor C2, and an operational amplifier. The described gain circuit 1 is composed of a forward - input - terminal resistor R29, a feedback resistor R28, and an operational amplifier. For the described absolute value circuit, the input signal is divided into two paths and reaches the positive input terminals of U1 and U2 respectively. The output terminal of U1 is connected to diode D5, and the other end of D5 reaches the reverse input terminal of U1 and R59 respectively. The output terminal of U2 is connected to resistor R62, and the other end of R62 reaches the reverse input terminal of U2 and R61 respectively. R61 is respectively connected to diode D6 and resistor R60, the other end of R60 reaches the reverse input terminal of U1 and R59 respectively, and the other end of R59 is grounded. The described LCL filter circuit: The input signal passes through a matching resistor R7 and reaches one end of an inductor L1. The other end of L1 is respectively connected to an inductor L2 and a capacitor C3. The other end of C3 is grounded. The other end of L2 is respectively connected to matching resistors R8 and R9. The other end of R8 is grounded, and the other end of R9 outputs.

7. A design method for a circuit model of a neutral type time-delay neural network system according to any one of claims 1-6, characterized in that: It includes the following steps: S1. Select a suitable time constant τ according to requirements, then design an LCL filter network according to the time constant τ. Secondly, select appropriate matching resistors at both ends of the LCL. Finally, select a suitable gain coefficient to design the two - end amplifier circuit, and finally build the time - delay circuit according to the method introduced in claim 3. S2. Select a suitable neural network activation function according to requirements, then perform an approximate transformation according to the mathematical model of the activation function to make the activation function easier to process in the circuit. Secondly, select the calculation unit circuit according to the activation function. Finally, build the activation function circuit according to the method introduced in claim 3. S3. Select a suitable amplification multiple of the gain circuit according to requirements and circuit stability analysis, then select the resistance ratio of the amplifier circuit according to the amplification multiple, and finally build the gain circuit according to the basic operational amplifier circuit structure. S4. Select appropriate component parameters of the integration circuit and differentiation circuit through circuit parameter analysis. Generally, the empirical method is adopted for processing. By referring to the general selection of differentiation circuits and integration circuits for signal inputs at this magnitude in engineering to build them. S5. After completing the above sub - circuit designs, the neuron circuit can be designed. First, understand the state equation and dynamic equation of the built neural network, then connect the circuits according to the known stable parameters to build the neuron circuit, and finally build the neural network model according to the relationship between neurons.

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