Data stream analysis method, analysis module, central control board card and storage medium

Abstract

The embodiment of the invention provides a data stream analysis method, an analysis module, a central control board card and a storage medium. According to the scheme, in the process of receiving a serial data stream sent by a target routing board card, frame header detection is carried out on the serial data stream, and the serial data stream comprises a plurality of ready instruction packets; when the target frame header is detected, first data and second data are obtained from the serial data stream according to the first data volume and the second data volume based on the target frame header, and the first data in the serial data stream is arranged before the second data; when the second data is the target frame tail, generating a target ready instruction packet comprising the target frame header, the first data and the target frame tail; and sending the target ready instruction packet to a thread module, so that the thread module generates a trigger signal according to the first data in the target ready instruction packet. Through the technical scheme provided by the embodiment of the invention, the effective analysis of the serial data stream sent by the routing board card is realized.

Description

Technical Field

[0001] The present application relates to the field of quantum computing technology, and particularly to a data stream parsing method, a parsing module, a central control board card and a storage medium. Background Art

[0002] Quantum computing is a computing mode that uses the basic characteristics of quantum mechanics to solve problems. By constructing a quantum physical hardware system that can be precisely operated and running quantum computing software to implement quantum algorithms, computing problems are solved, and the application of quantum computing in specific problems or fields is realized.

[0003] As an important part of a quantum computer, a quantum computing measurement and control system needs to provide corresponding pulse signals for qubits participating in quantum computing during the quantum computing process. Summary of the Invention

[0004] The purpose of the embodiments of the present application is to provide a data stream parsing method, a parsing module, a central control board card and a storage medium to effectively parse the serial data stream sent by a routing board card. The specific technical solutions are as follows:

[0005] The embodiments of the present application provide a data stream parsing method, which is applied to a parsing module in a central control board card. The central control board card and multiple routing board cards form a quantum computing measurement and control system. The parsing module is respectively communicatively connected to each routing board card. The central control board card further includes a thread module, and the thread module is communicatively connected to the parsing module. The method includes:

[0006] During the process of receiving a serial data stream sent by a target routing board card, perform frame header detection on the serial data stream, and the serial data stream includes multiple ready instruction packets;

[0007] When a target frame header is detected, based on the target frame header, respectively obtain first data and second data from the serial data stream according to a first data volume and a second data volume, and the first data in the serial data stream is arranged before the second data;

[0008] When the second data is a target frame tail, generate a target ready instruction packet including the target frame header, the first data and the target frame tail;

[0009] Send the target ready instruction packet to the thread module so that the thread module generates a trigger signal according to the first data in the target ready instruction packet.

[0010] The embodiment of the present application also provides a parsing module, which is deployed in the central control board of the quantum computing measurement and control system. The quantum computing measurement and control system also includes multiple routing boards. The parsing module is respectively communicatively connected to each routing board. The central control board also includes a thread module, and the thread module is communicatively connected to the parsing module;

[0011] A detection unit, configured to perform a frame header detection on the serial data stream during the process of receiving the serial data stream sent by the target routing board. The serial data stream includes multiple ready instruction packets;

[0012] An acquisition unit, configured to respectively acquire first data and second data from the serial data stream based on the target frame header according to a first data volume and a second data volume. In the serial data stream, the first data is arranged before the second data;

[0013] A generation unit, configured to generate a target ready instruction packet including the target frame header, the first data, and the target frame tail when the second data is a target frame tail;

[0014] A sending unit, configured to send the target ready instruction packet to the thread module, so that the thread module generates a trigger signal according to the first data in the target ready instruction packet.

[0015] The embodiment of the present application also provides a central control board, including a parsing module, a communication interface, a memory, and a communication bus. Among them, the parsing module, the communication interface, and the memory complete mutual communication through the communication bus;

[0016] The memory is used to store a computer program;

[0017] The parsing module, when executing the program stored on the memory, implements the steps of the data stream parsing method described in any one of the above;

[0018] The embodiment of the present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by the parsing module, the steps of the data stream parsing method described in any one of the above are implemented.

[0019] The embodiment of the present application also provides a computer program product including instructions. When it runs on a computer, it enables the computer to execute the data stream parsing method described in any one of the above.

[0020] Advantageous effects of the embodiment of the present application:

[0021] The technical solution provided by the embodiment of the present application can perform frame header detection on the serial data stream during the process of receiving the serial data stream sent by the target routing board. When the target frame header is detected, based on the target frame header, the first data and the second data are respectively obtained according to the trigger information carried in the ready instruction packet and the data volume corresponding to the frame tail, that is, the first data volume and the second data volume. When the second data is the target frame tail, a target ready instruction packet including the first data is generated and sent to the thread module.

[0022] In the embodiment of the present application, the data volume of the information carried in each ready instruction packet in the serial data packet is fixed, and the data volume and form corresponding to the frame header and the frame tail are both fixed. Therefore, when the target frame header is detected, if the obtained second data is the target frame tail, the parsing module can accurately determine all the data carried in a trigger instruction packet included in the serial data stream, ensuring the accuracy of the parsed ready instruction packet, which realizes the effective parsing of the serial data stream sent by the routing board.

[0023] In addition, after parsing all the data carried in the trigger instruction packet, the parsing module generates a target ready instruction packet including the first data and sends the target ready instruction packet to the thread module, which enables the thread module to generate a trigger signal according to the first data in the target ready instruction packet while receiving the ready instruction packet sent by the routing board. This ensures the effective transmission of the ready instruction packet and the effective generation of the trigger signal, and further ensures the effectiveness and accuracy of the trigger in the quantum computing process.

[0024] Of course, any product or method implementing the present application does not necessarily need to achieve all the above-mentioned advantages simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0026] Figure 1 It is the first flow schematic diagram of the data stream parsing method provided by the embodiment of the present application;

[0027] Figure 2 It is a schematic structural diagram of a quantum computing measurement and control system provided by the embodiment of the present application;

[0028] Figure 3 It is a schematic structural diagram of a ready instruction packet provided by the embodiment of the present application;

[0029] Figure 4 The second process schematic diagram of the data stream parsing method provided by the embodiment of the present application;

[0030] Figure 5 The third process schematic diagram of the data stream parsing method provided by the embodiment of the present application;

[0031] Figure 6 The fourth process schematic diagram of the data stream parsing method provided by the embodiment of the present application;

[0032] Figure 7 The fifth process schematic diagram of the data stream parsing method provided by the embodiment of the present application;

[0033] Figure 8 A schematic structural diagram of the parsing module provided by the embodiment of the present application;

[0034] Figure 9 A schematic structural diagram of the central control board provided by the embodiment of the present application. Detailed implementation manners

[0035] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0036] In the related art, a quantum computing system may include a central control board, a routing board, and a lower-layer board. When performing quantum computing using a quantum computer, after the quantum computing measurement and control system is ready, corresponding pulse signals need to be provided for the quantum bits. Specifically, when the lower-layer board is ready, it can send a ready signal to the routing board. After receiving the ready signal, the routing board sends a ready instruction to the central control board. After receiving the ready instruction, the central control board generates a first trigger signal and sends the first trigger signal to the routing board. After receiving the first trigger signal, the routing board generates a second trigger signal and sends the second trigger signal to the lower-layer board. The lower-layer board will generate corresponding pulse signals according to the received second trigger signal, such as the flux modulation signal, pulse modulation signal, etc. required for the quantum bits to participate in the quantum computing process.

[0037] The ready instruction sent by the above routing board to the central control board is only a high-level signal and does not carry any information. Therefore, this ready instruction is only applicable to triggering the execution process of a single quantum computing task. However, with the application of multi-threading technology in the quantum computing process, the number of routing boards will increase, that is, the quantum computing measurement and control system can include multiple routing boards, and the number of quantum computing tasks triggered and executed by each routing board will also increase. Therefore, when multiple ready instruction packets carrying trigger information are sent to the central control board in the form of a serial data stream, the central control board needs to effectively interpret the received serial data stream.

[0038] To solve the problems in the related art, an embodiment of the present application provides a data stream parsing method. As Figure 1 shown, Figure 1 is the first flowchart of the data stream parsing method provided by the embodiment of the present application. This method is applied to the parsing module in the central control board. The central control board and multiple routing boards form a quantum computing measurement and control system. The parsing module is communicatively connected to each routing board respectively, and the central control board further includes a thread module, and the thread module is communicatively connected to the parsing module. In the Figure 1 shown method, the following steps are included.

[0039] Step S101, during the process of receiving the serial data stream sent by the target routing board, perform frame header detection on the serial data stream, and the serial data stream includes multiple ready instruction packets.

[0040] Step S102, when the target frame header is detected, based on the target frame header, obtain the first data and the second data from the serial data stream respectively according to the first data volume and the second data volume, and the first data in the serial data stream is arranged before the second data.

[0041] Step S103, when the second data is the target frame tail, generate a target ready instruction packet including the target frame header, the first data, and the target frame tail.

[0042] Step S104, send the target ready instruction packet to the thread module so that the thread module generates a trigger signal according to the first data in the target ready instruction packet.

[0043] For the above quantum computing measurement and control system, as Figure 2 shown, Figure 2 is a schematic structural diagram of a quantum computing measurement and control system provided by the embodiment of the present application. In the Figure 2 shown quantum computing measurement and control system, it includes: a central control board, multiple routing boards (such as Figure 2 the routing board 1 - routing board 3 shown) and multiple lower-level boards (such as Figure 2 the lower-level board 1 - lower-level board 3 shown). Figure 2The physical devices of the quantum computing measurement and control system shown can be represented as: a cabinet composed of multiple chassis. Among them, Figure 2 The shown central control board, each routing board, and each lower-level board can all be represented as a chassis in the cabinet.

[0044] In Figure 2 the quantum computing measurement and control system shown, each routing board has a lower-level board communicatively connected thereto. As Figure 2 shown, routing board 1 is communicatively connected to lower-level board 1, routing board 2 is communicatively connected to lower-level board 2, and routing board 3 is communicatively connected to lower-level board 3. Additionally, each routing board can be communicatively connected to the parsing module in the central control board through different transmission links respectively.

[0045] In the chassis corresponding to each lower-level board included in the above quantum computing measurement and control system, there can be various different types and quantities of boards. For example: Arbitrary Waveform Generator (AWG) boards, Analog Digital Digital Analog (ADDA) boards, Digital to Analog Converter (DAC) boards, etc. Different types of boards can be used to generate different types of pulse signals. Here, no specific limitations are imposed on the board data and types included in the lower-level boards.

[0046] The quantities of the routing boards and lower-level boards included in the above quantum computing measurement and control system can be set according to the number of qubits on the quantum chip, user requirements, etc. For example, a quantum computing measurement and control system corresponding to a known 72-qubit quantum chip can be as Figure 2 shown. This quantum system can include 3 routing boards and 3 lower-level boards. Here, no specific limitations are imposed on the quantities of the routing boards and central control boards included in the above quantum computing measurement and control system.

[0047] By Figure 1 the method shown, during the process of receiving the serial data stream sent by the target routing board, the serial data stream can be subjected to frame header detection. When the target frame header is detected, based on this target frame header, according to the trigger information carried in the ready instruction packet and the data volume corresponding to the frame tail, that is, the first data volume and the second data volume, the first data and the second data are respectively obtained. And when the second data is the target frame tail, a target ready instruction packet including the first data is generated, and this target ready instruction packet is sent to the thread module.

[0048] In the embodiment of the present application, the data volume of the information carried by each ready instruction packet in the serial data packet is fixed, and the data volume and form corresponding to the frame header and the frame tail are both fixed. Therefore, when the target frame header is detected, if the obtained second data is the target frame tail, the parsing module can accurately determine all the data carried by a trigger instruction packet included in the serial data stream, ensuring the accuracy of the parsed ready instruction packet, which realizes the effective parsing of the serial data stream sent by the routing board.

[0049] In addition, after the parsing module parses all the data carried by the trigger instruction packet, it generates a target ready instruction packet including the first data and sends the target ready instruction packet to the thread module, which enables the thread module to generate a trigger signal according to the first data in the target ready instruction packet while receiving the ready instruction packet sent by the routing board. This ensures the effective transmission of the ready instruction packet and the effective generation of the trigger signal, and further ensures the effectiveness and accuracy of the trigger in the quantum computing process.

[0050] The embodiments of the present application will be described below through specific examples.

[0051] Regarding the above step S101, that is, during the process of receiving the serial data stream sent by the target routing board, frame header detection is performed on the serial data stream, and the serial data stream includes multiple ready instruction packets.

[0052] In the embodiment of the present application, for each routing board in the above quantum computing measurement and control system, when the lower-layer board communicatively connected to the routing board is ready, that is, after the lower-layer board completes the loading of the task data corresponding to the corresponding quantum computing task, it can send a ready signal to the routing board. Each time the routing board receives a ready signal, it will generate a ready instruction packet based on the ready signal. The ready instruction packets generated by the routing board can be sent to the parsing module in the central control board in the form of a serial data stream according to a preset order. The parsing module will also receive the serial data stream.

[0053] In the embodiment of the present application, for each routing board, before the lower-layer board communicatively connected to the routing board is ready, the routing board is already ready, that is, the routing board has completed the loading of the trigger data corresponding to the corresponding quantum computing task. Here, the loading processes of the trigger data and the task data in the above routing board and the lower-layer board will not be specifically described herein.

[0054] In an optional embodiment, the ready signal sent by the lower-layer board to the routing board carries a thread identifier, and the thread identifier is used to indicate the thread that executes the quantum computing task in the lower-layer board. After receiving the ready signal from the lower-layer board, the routing board can generate the above ready instruction packet according to the thread identifier in the ready signal and the chassis mask cached by itself.

[0055] The above chassis mask is the mask information corresponding to the routing board required to trigger the parallel execution of the quantum computing task. The thread module in the central control board needs to send a trigger signal to the corresponding routing board according to this chassis mask, so as to trigger the corresponding routing board to start the execution process of the quantum computing task.

[0056] In an optional embodiment, due to the application of multi-threading technology in the quantum computing measurement and control system, the masks included in the above chassis mask can be the mask information of two or more routing boards corresponding to the chassis. Here, the number of mask information of the routing board carried in the above ready instruction packet is not specifically limited.

[0057] In the embodiment of the present application, the above quantum computing measurement and control system includes multiple routing boards. Since each routing board can be respectively communicatively connected to the parsing module in the central control board through different transmission links, at the same time, the parsing module may receive serial data streams sent by one or more routing boards. For ease of understanding, the embodiment of the present application only takes the parsing module receiving a serial data stream as an example for illustration. For the case where multiple routing boards send serial data streams simultaneously, the parsing process of a serial data stream can be referred to, and the parsing module performs parallel processing. Here, the parallel processing process is not specifically described.

[0058] The above serial data stream includes multiple ready instruction packets. For each ready instruction packet, as Figure 3 shown, Figure 3 FIG. 15 is a schematic structural diagram of a ready instruction packet provided by an embodiment of the present application. The ready instruction packet may include a frame header, a thread identifier, a chassis mask, and a frame tail. Among them, the thread identifier and the chassis mask are recorded as the trigger information carried in the ready instruction packet.

[0059] In the embodiment of the present application, the value corresponding to the frame header in the above ready instruction packet is a fixed value (denoted as the first preset data), and the data volume of the first preset data is also a fixed data volume (i.e., the third data volume in the following text). The data volume of the trigger information in the above ready instruction packet is a fixed data volume (denoted as the first data volume). The value corresponding to the frame tail in the above ready instruction packet is a fixed value (denoted as the second preset data), and the data volume of the second preset data is also a fixed data volume (denoted as the second data volume).

[0060] During the process of the parsing module receiving the serial data stream sent by the target routing board, the parsing module can perform frame header detection on the serial data stream.

[0061] The above target routing board can be any one or more routing boards among the above multiple routing boards. Here, the above target routing board is not specifically limited.

[0062] In an alternative embodiment, according to the method described above Figure 1 the embodiments of the present application further provide a data stream parsing method. As Figure 4 shown, Figure 4 Figure 2 is the second flowchart of the data stream parsing method provided by the embodiments of the present application. In the method shown in Figure 4 above, step S101 can be refined into the following steps, namely step S1011-step S1015.

[0063] Step S1011, according to the arrangement order of each value in the serial data stream, obtain the first third data volume of values arranged in the front as the frame header to be detected.

[0064] In this step, during the process of receiving the above serial data stream, the parsing module can obtain the first third data volume of values arranged in the front in the serial data stream according to the arrangement order of each value as the frame header to be detected.

[0065] In an alternative embodiment, the above third data volume can be 2 bits (bit). At this time, when the parsing module receives the serial data stream, it can obtain the first 2-bit value as the frame header to be detected.

[0066] Step S1012, match the frame header to be detected with the first preset data.

[0067] In this step, after obtaining the above frame header to be detected, the parsing module can match the frame header to be detected with the first preset data. When the frame header to be detected is the same as the first preset data, the parsing module can determine that the frame header to be detected matches the first preset data; when the frame header to be detected is different from the first preset data, the parsing module can determine that the frame header to be detected does not match the first preset data.

[0068] In an alternative embodiment, the above first preset data can be the value 10. At this time, after obtaining the above frame header to be detected, the parsing module can determine whether the frame header to be detected is 10. When the frame header to be detected is 10, the parsing module can determine that the frame header to be detected matches 10; when the frame header to be detected is other values than 10, such as the values 00, 01 or 11, the parsing module can determine that the frame header to be detected does not match 10.

[0069] Step S1013, when the frame header to be detected matches the first preset data, determine that the target frame header is detected.

[0070] When the above frame header to be detected matches the above first preset data, the parsing module can determine that the target frame header is detected, that is, the above frame header to be detected is the detected target frame header.

[0071] Step S1014, when the frame header to be detected does not match the first preset data, it is determined that the target frame header is not detected, and the frame header to be detected is re-obtained according to the arrangement order of each value in the serial data stream and the preset shift step size.

[0072] When the frame header to be detected does not match the first preset data, the parsing module can determine that the target frame header is not detected. At this time, the parsing module can re-obtain the frame header to be detected from the serial data stream it receives. That is, the parsing module can re-obtain the frame header to be detected according to the arrangement order of each value in the serial data stream and the preset shift step size.

[0073] In an optional embodiment, the process of re-obtaining the frame header to be detected can be specifically represented as:

[0074] The parsing module moves the preset shift step size with the first value in the frame header to be detected as the first starting point according to the arrangement order of each value in the serial data stream to obtain a second starting point; based on the second starting point, the parsing module obtains the third data volume of values from the serial data stream to obtain a new frame header to be detected.

[0075] In an optional embodiment, the preset shift step size can be 1 bit. For ease of understanding, take the values arranged at the front in the serial data stream as: 00110 as an example for illustration.

[0076] When the parsing module receives the above serial data stream, the first frame header to be detected obtained is the first 2 bits of the serial data stream, that is, the value 00. Since 00 is not the above 10, 00 does not match the first preset data, that is, the target frame header is not detected. At this time, the parsing module can shift 1 bit backward with the first 0 in 00 as the first starting point to obtain a second starting point, that is, the second 0 in 00. After the second starting point is determined, the parsing module can obtain 01 in the serial data stream as the frame header to be detected. And so on. Since the frame header to be detected 01 is not the above 10, the parsing module can re-obtain the frame header to be detected in the same way until the target frame header, that is, 10 in the serial data stream, is detected.

[0077] In the embodiment of the present application, since the above serial data stream includes multiple ready instruction packets, during the process of receiving the above serial data stream, the parsing module will definitely detect the target frame header.

[0078] Compared with using an 8-bit hexadecimal number as the frame header of the data packet in the related art, the embodiment of the present application uses the above first preset data as the target frame header, effectively reducing the data volume of the frame header in the ready instruction packet, facilitating the transmission of the ready instruction packet and the detection of the frame header in the ready instruction packet by the parsing module.

[0079] In the embodiments of the present application, the above steps S1013 and S1014 are steps respectively executed when the matching results of the to-be-detected frame header and the above first preset data are different. Here, the execution of the above steps S1013 and S1014 is not specifically limited.

[0080] Step S1015: Based on the re-obtained to-be-detected frame header, return to execute the step of matching the to-be-detected frame header with the first preset data.

[0081] In this step, after the parsing module re-obtains the to-be-detected frame header, it can perform frame header detection according to the re-obtained to-be-detected frame header, that is, return to execute the above step S1012, that is, return to execute the step of matching the to-be-detected frame header with the first preset data.

[0082] Through the above steps S1011 - S1015, the parsing module can accurately identify the target frame header in the serial data stream by matching the to-be-detected frame header with the above first preset data, ensuring the accuracy of target frame header identification.

[0083] In addition, when the parsing module does not detect the target frame header, the acquisition starting point of the to-be-detected frame header is updated by a preset shift step size, and the to-be-detected frame header is re-obtained according to the updated starting point, effectively ensuring the orderliness of frame header detection and improving the accuracy of frame header detection.

[0084] Regarding the above step S102, that is, when the target frame header is detected, based on the target frame header, the first data and the second data are respectively obtained from the serial data stream according to the first data volume and the second data volume, and the first data in the serial data stream is arranged before the second data.

[0085] Regarding the above Figure 3 For the shown ready instruction packet, since the data volume corresponding to the trigger information (that is, the above thread identifier and chassis mask) carried in the ready instruction packet is the first data volume, and the data volume corresponding to the frame tail is the second data volume, therefore, when the parsing module detects the above target frame header, it can, based on the target frame header, obtain the first data from the serial data stream according to the above first data volume, and obtain the second data from the serial data stream according to the above second data volume. That is, according to the position of the target frame header in the serial data stream, the first data and the second data are respectively obtained from the values after the target frame header.

[0086] In an optional embodiment, according to the above Figure 1 shown method, the embodiments of the present application further provide a data stream parsing method. As Figure 5 shown, Figure 5 is the third process schematic diagram of the data stream parsing method provided by the embodiments of the present application. In Figure 5In the method shown above, the above step S102 can be refined into the following steps, namely step S1021 - step S1022.

[0087] Step S1021, when the target frame header is detected, obtain the first data volume of values after the target frame header from the serial data stream as the first data.

[0088] In an alternative embodiment, when the parsing module obtains the above first data, it directly obtains the first data volume of values to obtain the first data. For example, the parsing module can directly obtain the 12-bit value arranged after the target frame header from the serial data stream to obtain the first data.

[0089] In an alternative embodiment, the position and data volume of the above first data in the serial data stream match the position and data volume of the trigger information in the ready instruction packet. Since the trigger information included in the above ready instruction packet includes the above thread identifier and chassis mask. Among them, the thread identifier can include the fourth data volume of values, and the chassis mask can include the fifth data volume of values. The data volume of the thread identifier can be 4 bits, and the data volume of the chassis mask can be 8 bits.

[0090] In an alternative embodiment, the sum of the above fourth data volume and the above fifth data volume is the above first data volume.

[0091] In another alternative embodiment, when the parsing module obtains the above first data, it can separately obtain the fourth data volume of values and the fifth data volume of values, and combine the obtained values to obtain the first data. For example, the parsing module can obtain the 4-bit value (denoted as data 1) arranged after the target frame header from the serial data stream, obtain the 8-bit value (denoted as data 2) arranged after data 1, and merge data 1 and data 2 to obtain the first data.

[0092] In the embodiment of the present application, for the trigger information carried in the above ready instruction packet, the arrangement order corresponding to the thread identifier and the chassis mask in the trigger information can be as shown above Figure 3 shown, or the chassis mask can be arranged in the front and the thread identifier can be arranged in the back. When obtaining the first data according to the above fourth data volume and fifth data volume, the method of obtaining the first data will be different according to the different arrangement orders of the thread identifier and the chassis mask in the trigger information. Here, the method of obtaining the above first data is not specifically limited.

[0093] Step S1022, obtain the second data volume of values after the first data from the serial data stream as the second data.

[0094] In this step, after obtaining the above first data, the parsing module can, according to the position of the first data in the serial data stream, obtain the second data quantity of values after this position to obtain the second data.

[0095] In an optional embodiment, the position and data quantity of the above second data in the serial data stream both match the position and data quantity of the frame tail in the ready instruction packet. The data quantity of the frame tail carried in the above ready instruction packet can be 2 bits.

[0096] When the above second data quantity is 2 bits, the parsing module can obtain the 2-bit value arranged after the first data in the serial data stream to obtain the second data.

[0097] Through the above steps S1021 - S1022, after detecting the above target frame header, the parsing module, according to the trigger information, the position where the frame tail is located, and the corresponding data quantity in the ready instruction packet, obtains the first data and the second data from the values after the target frame tail in the serial data stream. While realizing the acquisition of the first data and the second data, it can ensure that the acquired first data and second data match the trigger information, the position where the frame tail is located, and the data quantity in the ready instruction packet, facilitating the subsequent frame tail detection by the parsing module, thereby ensuring the accuracy and effectiveness of the ready instruction packet parsed by the parsing module from the serial data stream.

[0098] Regarding the above step S103, that is, when the second data is the target frame tail, generate a target ready instruction packet including the target frame header, the first data, and the target frame tail.

[0099] Regarding the above second data, since the position and data quantity of this second data match those corresponding to the frame tail in the ready instruction packet, therefore, after obtaining the above second data, the parsing module can determine whether this second data is the target frame tail. When determining that the above second data is the target frame tail, the parsing module can determine that the above to-be-detected frame header (i.e., the target frame header), the first data, and the second data (i.e., the target frame tail) are all the data carried in a ready instruction packet. That is, the parsing module parses out the data carried in a ready instruction packet from the serial data packet.

[0100] The parsing module can generate a ready instruction packet according to the target frame header, the first data, and the target frame tail. That is, the parsing module assembles the to-be-detected frame header, the first data, and the second data parsed from the serial data stream to obtain the target ready instruction packet.

[0101] In an optional embodiment, when determining that the above second data is the target frame tail, the parsing module can determine that the above first data is the trigger information carried in a ready instruction packet, and the trigger information includes: a thread identifier having the fourth data quantity of values, and a chassis mask having the fifth data quantity of values;

[0102] Among them, the thread identifier indicates the thread that executes the quantum computing task in the lower-layer board card communicatively connected to the routing board card. The chassis mask is the mask information corresponding to the routing board card required to trigger the parallel execution of the quantum computing task. The sum of the fourth data volume and the fifth data volume is the first data volume.

[0103] Regarding the above step S104, that is, sending a target ready instruction packet to the thread module so that the thread module generates a trigger signal according to the first data in the target ready instruction packet.

[0104] In this step, after generating the above target ready instruction packet, the parsing module can send the target ready instruction packet to the thread module in the central control board card. After receiving the above target ready instruction packet, the thread module can generate a trigger signal according to the first data carried in the target ready instruction packet.

[0105] In the embodiment of the present application, the above trigger signal is used to instruct the routing board card to start the parallel execution of the quantum computing task. That is, after generating the above trigger signal, the thread module can send the trigger signal to the corresponding routing board card. The routing board card can start the parallel execution process of the quantum computing task according to the received trigger signal, that is, generate a corresponding trigger signal and send it to the lower-layer board card communicatively connected, so that the lower-layer board card generates a pulse signal required for the execution of the quantum computing task when receiving the trigger signal.

[0106] In an optional embodiment, according to the above Figure 1 shown method, the embodiment of the present application further provides a data stream parsing method. As Figure 6 shown, Figure 6 This is the fourth process schematic diagram of the data stream parsing method provided by the embodiment of the present application. In the Figure 6 shown method, the following step is added, that is, step S105.

[0107] Step S105: Use the fourth data after the second data as a serial data stream, and return to execute the step of detecting the frame header of the serial data stream.

[0108] In this step, after detecting the above target frame header and performing frame tail detection on the above second data, the parsing module needs to continue to parse the data after the second data (denoted as the fourth data) to parse out all the ready instruction packets carried in the serial data stream. At this time, the parsing module can use the fourth data as the above serial data stream and return to execute the step of detecting the frame header of the serial data stream in the above step S101.

[0109] Through the above step S105, the parsing module can continue to parse the data after the second data in the above serial data stream, facilitating the parsing module to accurately parse all the ready instruction packets included in the received serial data stream, ensuring the accuracy of the parsing process and the integrity of the parsing result.

[0110] In an alternative embodiment, according to the above Figure 1 method shown, an embodiment of the present application further provides a data stream parsing method. As Figure 7 shown, Figure 7 This is the fifth process schematic diagram of the data stream parsing method provided by the embodiment of the present application. The method includes the following steps.

[0111] Step S701, during the process of receiving the serial data stream sent by the target routing board, perform frame header detection on the serial data stream, and the serial data stream includes multiple ready instruction packets.

[0112] Step S702, when the target frame header is detected, based on the target frame header, obtain the first data and the second data from the serial data stream respectively according to the first data volume and the second data volume, and the first data in the serial data stream is arranged before the second data.

[0113] The above steps S701 - step S702 are the same as the above steps S101 - step S102.

[0114] Step S703, match the second data with the second preset data.

[0115] In this step, after obtaining the above first data and second data, the parsing module can perform frame tail detection on the second data. Since the frame tail in the above ready instruction packet is a fixed value (denoted as the second preset data), the parsing module can match the above second data with the second preset data. When the above second data is the same as the second preset data, the parsing module can determine that the second data matches the second preset data. When the above second data is different from the above second preset data, the parsing module can determine that the second data does not match the second preset data.

[0116] In an alternative embodiment, the above second preset data can be the value 01. After obtaining the second data, the parsing module can determine whether the second data is 01.

[0117] Compared with the related art that uses an 8-bit hexadecimal number as the frame tail of the data packet, the embodiment of the present application uses the above second preset data as the target frame tail, effectively reducing the data volume of the frame tail in the ready instruction packet, facilitating the transmission of the ready instruction packet and the detection of the frame tail by the parsing module.

[0118] Step S704, when the second data matches the second preset data, determine that the second data is the target frame tail.

[0119] Step S705, when the second data does not match the second preset data, determine that the second data is not the target frame tail.

[0120] In the embodiments of the present application, the above steps S704 and S705 are steps respectively executed when the matching results of the second data and the second preset data are different. Here, the execution of the above steps S704 and S705 is not specifically limited.

[0121] By comparing the second data with the second preset data, the parsing module can accurately determine whether the second data is the target frame tail in the ready instruction packet, ensuring the accuracy of the frame tail detection result, thereby ensuring the accuracy of the parsing of the ready instruction packet in the serial data stream, and further ensuring the accuracy of the serial data stream parsing process.

[0122] In an optional embodiment, when it is determined that the second data is not the target frame tail, the parsing module may determine that the first data or the second data obtained from the serial data stream is not the data carried in the ready instruction packet, or there is an abnormality in the first data or the second data. At this time, the parsing module may discard the target data in the serial data stream, and the target data is the second data and the third data arranged before the second data.

[0123] In the case where the target frame head is detected but the target frame tail is not detected, by discarding the above target data, the parsing module can effectively avoid the influence of the abnormality of the target data on the serial data stream parsing process, improve the security of data transmission, and improve the accuracy of data stream parsing, thereby ensuring the accuracy of the later quantum computing process.

[0124] Step S706, when the second data is the target frame tail, generate a target ready instruction packet including the target frame head, the first data, and the target frame tail.

[0125] Step S707, send the target ready instruction packet to the thread module so that the thread module generates a trigger signal according to the first data in the target ready instruction packet.

[0126] The above steps S706 - S707 are the same as the above steps S103 - S104.

[0127] Based on the same inventive concept, according to the data stream parsing method provided by the embodiments of the present application, the embodiments of the present application also provide a parsing module. As Figure 8 shown, Figure 8It is a schematic structural diagram of an analysis module provided by an embodiment of this application. The analysis module is deployed in the central control board of the quantum computing measurement and control system. The quantum computing measurement and control system further includes multiple routing boards. The analysis module is communicatively connected to each routing board respectively. The central control board further includes a thread module, and the thread module is communicatively connected to the analysis module. In Figure 8 The analysis module shown may include the following units:

[0128] A detection unit 801, configured to perform a frame header detection on the serial data stream during the process of receiving the serial data stream sent by the target routing board. The serial data stream includes multiple ready instruction packets;

[0129] An acquisition unit 802, configured to, when detecting the target frame header, based on the target frame header, acquire first data and second data from the serial data stream respectively according to a first data volume and a second data volume. The first data in the serial data stream is arranged before the second data;

[0130] A generation unit 803, configured to generate a target ready instruction packet including the target frame header, the first data, and the target frame tail when the second data is the target frame tail;

[0131] A sending unit 804, configured to send the target ready instruction packet to the thread module, so that the thread module generates a trigger signal according to the first data in the target ready instruction packet.

[0132] Optionally, the above detection unit 801 may specifically be configured to, according to the arrangement order of each value in the serial data stream, acquire the first third data volume of values arranged in the front as the frame header to be detected;

[0133] Match the frame header to be detected with a first preset data;

[0134] When the frame header to be detected matches the first preset data, it is determined that the target frame header is detected;

[0135] When the frame header to be detected does not match the first preset data, it is determined that the target frame header is not detected, and according to the arrangement order of each value in the serial data stream and a preset shift step, the frame header to be detected is re-acquired;

[0136] Based on the re-acquired frame header to be detected, return to execute the step of matching the frame header to be detected with the first preset data.

[0137] Optionally, the above detection unit 801 may further be configured to, according to the arrangement order of each value in the serial data stream, use the first value in the frame header to be detected as the first starting point, move a preset shift step, and obtain a second starting point;

[0138] Based on the second starting point, acquire the first third data volume of values from the serial data stream to obtain a new frame header to be detected.

[0139] Optionally, the above-mentioned obtaining unit 802 may be specifically configured to, when detecting a target frame header, obtain the first data volume of values after the target frame header from the serial data stream as the first data;

[0140] Obtain the second data volume of values after the first data from the serial data stream as the second data.

[0141] Optionally, the above-mentioned parsing module may further include:

[0142] A first determination unit, configured to, when determining that the second data is a target frame tail, determine that the first data is the trigger information carried in a ready instruction packet, where the trigger information includes: a thread identifier with the fourth data volume of values, and a chassis mask with the fifth data volume of values;

[0143] Wherein, the thread identifier indicates the thread that executes the quantum computing task in the lower-layer board card communicatively connected to the routing board card, the chassis mask is the mask information corresponding to the routing board card required to trigger the parallel execution of the quantum computing task, and the sum of the fourth data volume and the fifth data volume is the first data volume.

[0144] Optionally, the above-mentioned parsing module may further include:

[0145] A first matching unit, configured to match the second data with a second preset data after obtaining the first data and the second data;

[0146] A second determination unit, configured to determine that the second data is a target frame tail when the second data matches the second preset data;

[0147] A third determination unit, configured to determine that the second data is not a target frame tail when the second data does not match the second preset data.

[0148] Optionally, the above-mentioned parsing module may further include:

[0149] A discard unit, configured to discard the target data in the serial data stream after determining that the second data is not a target frame tail, where the target data is the second data and the third data arranged before the second data.

[0150] Optionally, the above-mentioned parsing module may further include:

[0151] A call unit, configured to use the fourth data after the second data as the serial data stream, and call the detection unit 801 to return to execute the step of detecting the frame header of the serial data stream.

[0152] Through the parsing module provided by the embodiments of the present application, during the process of receiving the serial data stream sent by the target routing board, the serial data stream can be detected for the frame header. When the target frame header is detected, based on the target frame header, according to the trigger information carried in the ready instruction packet and the data volume corresponding to the frame tail, that is, the first data volume and the second data volume, the first data and the second data are respectively obtained. When the second data is the target frame tail, a target ready instruction packet including the first data is generated and sent to the thread module.

[0153] In the embodiments of the present application, the data volume of the information carried in each ready instruction packet in the serial data packet is fixed, and the data volume and form corresponding to the frame header and the frame tail are both fixed. Therefore, when the target frame header is detected, if the obtained second data is the target frame tail, the parsing module can accurately determine all the data carried in a trigger instruction packet included in the serial data stream, ensuring the accuracy of the parsed ready instruction packet, which realizes the effective parsing of the serial data stream sent by the routing board.

[0154] In addition, after parsing all the data carried in the trigger instruction packet, the parsing module generates a target ready instruction packet including the first data and sends the target ready instruction packet to the thread module, which enables the thread module to generate a trigger signal according to the first data in the target ready instruction packet while receiving the ready instruction packet sent by the routing board. This ensures the effective transmission of the ready instruction packet and the effective generation of the trigger signal, and further ensures the effectiveness and accuracy of the trigger in the quantum computing process.

[0155] Based on the same inventive concept, according to the data stream parsing method provided by the above embodiments of the present application, the embodiments of the present application also provide a central control board, as Figure 9 shown, including a parsing module 901, a communication interface 902, a memory 903, and a communication bus 904. Among them, the parsing module 901, the communication interface 902, and the memory 903 complete communication with each other through the communication bus 904.

[0156] The memory 903 is used to store computer programs.

[0157] The parsing module 901 is used to implement the data stream parsing method in any of the above when executing the program stored on the memory 903.

[0158] The communication bus mentioned in the above central control board can be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. This communication bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of convenience of representation, only a thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0159] The communication interface is used for communication between the above central control board and other devices.

[0160] The memory can include a Random Access Memory (RAM), or can also include a Non-Volatile Memory (NVM), such as at least one disk memory. Optionally, the memory can also be at least one storage device located far from the aforementioned parsing module.

[0161] Or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0162] Based on the same inventive concept, according to the data stream parsing method provided in the above embodiments of the present application, the embodiments of the present application also provide a quantum computer, which includes the above quantum computing measurement and control system, and the quantum computing measurement and control system executes the steps of implementing any one of the above data stream parsing methods.

[0163] Based on the same inventive concept, according to the data stream parsing method provided in the above embodiments of the present application, the embodiments of the present application also provide a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed by the parsing module, it implements the steps of any one of the above data stream parsing methods.

[0164] Based on the same inventive concept, according to the data stream parsing method provided in the above embodiments of the present application, the embodiments of the present application also provide a computer program product containing instructions, which when running on a computer, causes the computer to execute any one of the data stream parsing methods in the above embodiments.

[0165] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer, server, or data center to another website, computer, server, or data center by wire (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more integrated available media. The available medium can be a magnetic medium (such as a floppy disk, hard disk, magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state disk (SSD)).

[0166] It should be noted that in this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the presence of additional identical elements in the process, method, article or device including the element.

[0167] Each embodiment in this specification is described in a related manner. The same or similar parts among the embodiments can be referred to each other, and the differences between each embodiment and other embodiments are emphasized. In particular, for embodiments such as the thread module, the central control board, the quantum computer, the computer-readable storage medium, the computer program product, etc., since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0168] The above are only the preferred embodiments of the present application and are not intended to limit the protection scope of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application are all included in the protection scope of the present application.

Claims

1. A data stream parsing method, characterized in that, An analysis module applied to a central control board. The central control board and multiple routing boards form a quantum computing measurement and control system. The analysis module is communicatively connected to each routing board respectively. The central control board further includes a thread module, and the thread module is communicatively connected to the analysis module. The method includes: During the process of receiving a serial data stream sent by a target routing board, performing frame header detection on the serial data stream, where the serial data stream includes multiple ready instruction packets; When a target frame header is detected, based on the target frame header, respectively obtain first data and second data from the serial data stream according to a first data volume and a second data volume, and the first data in the serial data stream is arranged before the second data; When the second data is a target frame tail, generate a target ready instruction packet including the target frame header, the first data, and the target frame tail; Send the target ready instruction packet to the thread module so that the thread module generates a trigger signal according to the first data in the target ready instruction packet.

2. The method according to claim 1, wherein The step of performing frame header detection on the serial data stream includes: According to the arrangement order of each value in the serial data stream, obtain the first third data volume of values arranged in the front as the frame header to be detected; Match the frame header to be detected with a first preset data; When the frame header to be detected matches the first preset data, determine that a target frame header is detected; When the frame header to be detected does not match the first preset data, determine that no target frame header is detected, and according to the arrangement order of each value in the serial data stream and a preset shift step, re-obtain the frame header to be detected; Based on the re-obtained frame header to be detected, return to execute the step of matching the frame header to be detected with the first preset data.

3. The method according to claim 2, wherein The step of re-obtaining the frame header to be detected according to the arrangement order of each value in the serial data stream and a preset shift step includes: According to the arrangement order of each value in the serial data stream, with the first value in the frame header to be detected as the first starting point, move a preset shift step to obtain a second starting point; Based on the second starting point, obtain the first third data volume of values from the serial data stream to get a new frame header to be detected.

4. The method according to claim 1, wherein The step of, when a target frame header is detected, based on the target frame header, respectively obtain first data and second data from the serial data stream according to a first data volume and a second data volume includes: When a target frame header is detected, obtain the first first data volume of values after the target frame header from the serial data stream as the first data; Obtain the second second data volume of values after the first data from the serial data stream as the second data.

5. The method according to claim 1, characterized in that When it is determined that the second data is a target frame tail, the method further includes: Determine that the first data is the trigger information carried in a ready instruction packet, where the trigger information includes: a thread identifier with a fourth data volume of values, and a chassis mask with a fifth data volume of values; Wherein, the thread identifier indicates a thread that executes a quantum computing task in a lower-layer board card communicatively connected to a routing board card, the chassis mask is mask information corresponding to the routing board card required to trigger parallel execution of the quantum computing task, and the sum of the fourth data volume and the fifth data volume is the first data volume.

6. The method according to claim 1, characterized in that After obtaining the first data and the second data, the method further includes: matching the second data with a second preset data; when the second data matches the second preset data, determining that the second data is a target frame tail; when the second data does not match the second preset data, determining that the second data is not a target frame tail.

7. The method according to claim 6, characterized in that, After determining that the second data is not a target frame tail, the method further includes: discarding target data in the serial data stream, where the target data is the second data and third data arranged before the second data.

8. The method according to claim 1, wherein The method further includes: using fourth data located after the second data as the serial data stream, and returning to execute the step of performing frame header detection on the serial data stream.

9. A parsing module, characterized in that, The parsing module is deployed in a central control board card of a quantum computing measurement and control system. The quantum computing measurement and control system further includes multiple routing board cards. The parsing module is communicatively connected to each routing board card respectively. The central control board card further includes a thread module, and the thread module is communicatively connected to the parsing module; a detection unit, configured to perform frame header detection on the serial data stream during the process of receiving the serial data stream sent by a target routing board card, where the serial data stream includes multiple ready instruction packets; an acquisition unit, configured to respectively obtain first data and second data from the serial data stream according to a first data volume and a second data volume based on the target frame header, where the first data in the serial data stream is arranged before the second data; a generation unit, configured to generate a target ready instruction packet including the target frame header, the first data, and the target frame tail when the second data is a target frame tail; a sending unit, configured to send the target ready instruction packet to the thread module, so that the thread module generates a trigger signal according to the first data in the target ready instruction packet.

10. A central control board, characterized in that, including a parsing module, a communication interface, a memory, and a communication bus. Among them, the parsing module, the communication interface, and the memory complete mutual communication through the communication bus; a memory, configured to store a computer program; a parsing module, configured to implement the method steps described in any one of claims 1-8 when executing the program stored on the memory.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, and when the computer program is executed by the parsing module, the method steps described in any one of claims 1-8 are implemented.

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