Display substrate and display device

Abstract

The display substrate comprises a display area and a peripheral area, the peripheral area comprises a first peripheral area, a bending area and a binding area which are located on the side, in the second direction, of the display area, and the display substrate comprises a substrate; a plurality of sub-pixels; the gate driving circuit is located on at least one side of the display area in the first direction, and the gate driving circuit is electrically connected with the multiple sub-pixels; the plurality of binding pads are located in the binding area; the plurality of gate signal leads are located in the peripheral area, and the gate drive circuit is electrically connected with the plurality of binding pads through the plurality of gate signal leads; the crack detection wire is located on the substrate, the crack detection wire is located in the peripheral area, and the two ends of the crack detection wire are electrically connected with the at least two binding bonding pads respectively; wherein the crack detection wire comprises a first part which is positioned on one side, close to the display area, of the bending area, and the orthographic projection of the first part on the substrate is partially overlapped with the orthographic projection of the gate signal lead on the substrate.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to a display substrate and a display device. Background Art

[0002] A flexible display substrate is a display technology that uses a flexible substrate instead of a traditional glass substrate and has characteristics such as bendability, foldability, and curliness. Due to its "soft" characteristics, a flexible display substrate is prone to cracks under the influence of external forces. Therefore, in the production process, monitoring of cracks is particularly important. How to accurately detect whether there are cracks in a flexible display substrate is one of the topics that researchers of display products are concerned about.

[0003] The above information disclosed in this section is only used to understand the background of the inventive concept of the present disclosure. Therefore, the above information may include information that does not constitute prior art. Summary of the Invention

[0004] In one aspect, a display substrate is provided.

[0005] It includes a display area and a peripheral area located around the display area. The peripheral area includes a first peripheral area on one side of the display area along a second direction, a bending area on a side of the first peripheral area away from the display area, and a bonding area on a side of the bending area away from the display area. The display substrate includes:

[0006] A substrate;

[0007] A plurality of sub-pixels located on the substrate, and the plurality of sub-pixels are arranged in the display area along a first direction and a second direction, and the first direction intersects with the second direction;

[0008] A gate driving circuit located on the substrate, the gate driving circuit is located in the peripheral area and on at least one side of the display area along the first direction, and the gate driving circuit is electrically connected to the plurality of sub-pixels;

[0009] A plurality of bonding pads located on the substrate, and the plurality of bonding pads are located in the bonding area;

[0010] A plurality of gate signal leads located on the substrate, the plurality of gate signal leads are located in the peripheral area, and the gate driving circuit is electrically connected to the plurality of bonding pads through the plurality of gate signal leads; and

[0011] A crack detection trace located on the substrate, the crack detection trace is located in the peripheral area, and both ends of the crack detection trace are electrically connected to two of the bonding pads;

[0012] Wherein, the crack detection trace includes a first part, the first part is located on a side of the bending area close to the display area, and a positive projection of the first part on the substrate overlaps with a positive projection of the gate signal lead on the substrate partially.

[0013] According to some exemplary embodiments, the plurality of bonding pads include a plurality of first bonding pads and at least two second bonding pads. The gate driving circuit is electrically connected to the plurality of first bonding pads through a plurality of the gate signal leads, and two ends of the crack detection trace are electrically connected to the two second bonding pads respectively; and

[0014] The display area includes a virtual central axis extending along the second direction, and at least two of the second bonding pads are located on a side of the plurality of first bonding pads close to the virtual central axis.

[0015] According to some exemplary embodiments, an extending direction of the first part intersects with an extending direction of the gate signal lead overlapping with the first part.

[0016] According to some exemplary embodiments, the crack detection trace further includes a second part, the second part is located on a side of the plurality of gate signal leads away from the display area along the second direction, one end of the second part is electrically connected to the first part, and the other end of the second part extends along an edge of the plurality of gate signal leads away from the display area to a side away from the virtual central axis.

[0017] According to some exemplary embodiments, the first part includes a first sub - part and a second sub - part, and the first sub - part is connected between the second part and the second sub - part;

[0018] The plurality of gate signal leads include a first lead part and a second lead part. A positive projection of the first sub - part on the substrate overlaps with a positive projection of the first lead part on the substrate partially, and a positive projection of the second sub - part on the substrate overlaps with a positive projection of the second lead part on the substrate partially; and

[0019] An extending direction of the first sub - part intersects with an extending direction of the first lead part, and / or an extending direction of the second sub - part intersects with an extending direction of the second lead part.

[0020] According to some exemplary embodiments, an extending direction of the first sub - part intersects with both the first direction and the second direction; and / or,

[0021] The second sub - part extends along the first direction.

[0022] According to some exemplary embodiments, the display substrate further includes a plurality of transfer signal lines and a plurality of transfer portions. The plurality of transfer portions are located in the first peripheral region, and at least a part of the plurality of transfer signal lines is located in the bending region;

[0023] The gate signal lead is electrically connected to one end of the transfer signal line through the transfer portion, and the other end of the transfer signal line is electrically connected to the bonding pad; and

[0024] The second sub-portion is located on a side of the plurality of transfer portions close to the display region and is spaced apart from the plurality of transfer portions. The first sub-portion is located on a side of the transfer portion away from the virtual central axis and is spaced apart from the plurality of transfer portions.

[0025] According to some exemplary embodiments, the display substrate further includes a plurality of data lines, and the plurality of bonding pads further include a plurality of third bonding pads. The plurality of data lines are respectively electrically connected to the plurality of third bonding pads, and the plurality of third bonding pads are located on a side of at least two of the second bonding pads away from the plurality of first bonding pads.

[0026] According to some exemplary embodiments, the display substrate includes multiple conductive layers, and the conductive layer where the first portion is located is on a side of the conductive layer where the plurality of gate signal leads are located away from the substrate.

[0027] According to some exemplary embodiments, a part of the first portion is on a side of the gate signal lead away from the substrate, and another part of the first portion is between adjacent gate signal leads.

[0028] According to some exemplary embodiments, the first portion includes at least two first trace segments arranged in parallel, and at least a part of one first trace segment and at least a part of another first trace segment are located in different conductive layers.

[0029] According to some exemplary embodiments, the multiple conductive layers include a first gate metal layer, a second gate metal layer located on a side of the first gate metal layer away from the substrate, a third gate metal layer located on a side of the second gate metal layer away from the substrate, a first source-drain metal layer located on a side of the third gate metal layer away from the substrate, and a second source-drain metal layer located on a side of the first source-drain metal layer away from the substrate;

[0030] The gate signal leads are located in the first gate metal layer and the second gate metal layer; and

[0031] The at least two first trace segments are located in at least two of the third gate metal layer, the first source-drain metal layer, and the second source-drain metal layer.

[0032] According to some exemplary embodiments, the second part includes at least two second routing segments arranged in parallel, the display substrate includes multiple conductive layers, at least a part of one second routing segment and at least a part of another second routing segment are located in different conductive layers.

[0033] According to some exemplary embodiments, at least a part of at least one second routing segment and the gate signal lead are located in at least the same conductive layer; and / or,

[0034] At least a part of at least one second routing segment is located in a conductive layer on a side of the conductive layer where the gate signal lead is located away from the substrate.

[0035] According to some exemplary embodiments, the multiple conductive layers include a first gate metal layer, a second gate metal layer located on a side of the first gate metal layer away from the substrate, a third gate metal layer located on a side of the second gate metal layer away from the substrate, a first source-drain metal layer located on a side of the third gate metal layer away from the substrate, and a second source-drain metal layer located on a side of the first source-drain metal layer away from the substrate;

[0036] The gate signal lead is located in the first gate metal layer and the second gate metal layer; and

[0037] The at least two second routing segments are located in at least two of the first gate metal layer, the second gate metal layer, the third gate metal layer, the first source-drain metal layer, and the second source-drain metal layer.

[0038] According to some exemplary embodiments, at least a part of the second part includes four second routing segments arranged in parallel, and the four second routing segments are sequentially located in the first gate metal layer, the second gate metal layer, the third gate metal layer, and the first source-drain metal.

[0039] According to some exemplary embodiments, the first part includes at least two first routing segments arranged in parallel, and the line width of at least a part of the second routing segment is smaller than the line width of at least a part of the first routing segment.

[0040] In another aspect, a display device is provided, and the display device includes the display substrate as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Other objects and advantages of the present disclosure will be apparent from the following description of the present disclosure with reference to the accompanying drawings, and can help to have a comprehensive understanding of the present disclosure.

[0042] Figure 1 A schematic plan view of a display panel according to some embodiments of the present disclosure is schematically shown.

[0043] Figure 2 Schematically shows Figure 1 An enlarged view of region A therein.

[0044] Figure 3 Schematically shows Figure 2 An enlarged view of region B1 therein.

[0045] Figure 4 Schematically shows Figure 2 An enlarged view of region B2 therein.

[0046] Figure 5 Schematically shows Figure 2 An enlarged view of region B3 therein.

[0047] Figure 6 Schematically shows Figure 2 An enlarged view of region B4 therein.

[0048] Figure 7 Schematically shows Figure 2 An enlarged view of region B5 therein.

[0049] Figure 8 Schematically shows Figure 2 Another enlarged view of region B1 therein.

[0050] Figure 9 Schematically shows Figure 2 Another enlarged view of region B4 therein.

[0051] Figure 10 Schematically shows Figure 9 An enlarged view of region C therein.

[0052] Figure 11 Schematically shows a cross-sectional view taken along Figure 10 The center line DD'.

[0053] Figure 12 Schematically shows Figure 11 An enlarged view of region E therein.

[0054] Figure 13 Schematically shows a plan view of a display panel according to some embodiments of the present disclosure.

[0055] Figure 14 Schematically shows Figure 13 An enlarged view of region F therein.

[0056] Figure 15 Schematically shows Figure 14 An enlarged view of region G therein.

[0057] Figure 16 Schematically shows Figure 15 An enlarged view of the H1 region.

[0058] Figure 17 Schematic diagram showing the Figure 16 A cross-sectional view taken along the center line II'.

[0059] Figure 18 Schematically shows Figure 15 An enlarged view of the H2 region.

[0060] Figure 19 Schematic diagram showing the Figure 18 Cross-section taken along the center line JJ'.

[0061] Figure 20 Schematic diagram showing the Figure 15 A cross-sectional view taken along the center line KK'.

[0062] Figure 21 Schematically shows Figure 16 An enlarged view of the middle region L.

[0063] Figure 22 Schematic diagram showing the Figure 21 A cross-sectional view taken along the midline MM'.

[0064] Figure 23 Schematically shows Figure 16 Another magnified view of the middle region L.

[0065] Figure 24 Schematic diagram showing the Figure 23 A cross-sectional view taken along the midline NN'.

[0066] Figure 25 Schematically shows Figure 16 Another enlarged view of the middle area L.

[0067] Figure 26 Schematic diagram showing the Figure 25 A cross-sectional view taken along the center line OO'.

[0068] Figure 27 Schematically shows Figure 14 An enlarged view of the middle region P.

[0069] Figure 28 Schematically shows Figure 27 An enlarged view of the middle region Q.

[0070] Figure 29 Schematic diagram showing the Figure 28 A cross-sectional view taken along the center line RR'.

[0071] Figure 30 Schematically shows Figure 27 an enlarged view of region S therein.

[0072] Figure 31 Schematically shows a cross-sectional view taken along Figure 30 the center line TT'.

[0073] It should be noted that, for clarity, in the drawings used to describe the embodiments of the present disclosure, the dimensions of layers, structures or regions may be enlarged or reduced, that is, these drawings are not drawn to actual scale. Detailed implementation manners

[0074] In the following description, for purposes of explanation, numerous specific details are set forth to provide a thorough understanding of various exemplary embodiments. However, it is evident that the various exemplary embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. Moreover, the various exemplary embodiments may be different but not necessarily exclusive. For example, without departing from the inventive concept, the specific shapes, configurations and characteristics of an exemplary embodiment may be used or implemented in another exemplary embodiment.

[0075] In the drawings, for clarity and / or for descriptive purposes, the dimensions of elements may be enlarged and relative dimensions. Thus, the dimensions and relative dimensions of the respective elements need not be limited to the dimensions and relative dimensions shown in the figures. When the exemplary embodiments can be implemented differently, the specific process sequences may be performed in an order different from the described order. For example, two consecutively described processes may be performed substantially simultaneously or in an order opposite to the described order. Moreover, like reference numerals denote like elements.

[0076] When an element is described as "on", "connected to", or "coupled to" another element, the element can be directly on, directly connected to, or directly coupled to the other element, or there can be intervening elements. However, when an element is described as "directly on", "directly connected to", or "directly coupled to" another element, there are no intervening elements. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, e.g., "between" versus "directly between", "adjacent" versus "directly adjacent", or "on" versus "directly on", etc. In addition, the term "connected" can refer to physical connection, electrical connection, communication connection, and / or fluid connection. Further, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a rectangular coordinate system and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as XYZ, XY, YZ, and XZ. As used herein, the term "and / or" includes any combination and all combinations of one or more of the listed related items.

[0077] It should be understood that although terms such as first, second, etc. may be used herein to describe different elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the exemplary embodiments, a first element can be named a second element, and similarly, a second element can be named a first element.

[0078] Figure 1 A plan view schematically showing a display panel according to some embodiments of the present disclosure. Figure 2 Schematically shown is Figure 1 An enlarged view of region A in Figure 3 Schematically shown is Figure 2 An enlarged view of region B1 in Figure 4 Schematically shown is Figure 2 An enlarged view of region B2 in Figure 5 Schematically shown is Figure 2 An enlarged view of region B3 in Figure 6 Schematically shown is Figure 2 An enlarged view of region B4 in Figure 7 Schematically shown is Figure 2 An enlarged view of region B5 in

[0079] Referring to Figure 1, the display substrate includes a display area AA and a peripheral area NA located around the display area AA. The peripheral area NA includes a bending area NA2 on one side of the display area AA along the second direction Y and a bonding area NA3 on the side of the bending area NA2 away from the display area AA. In the peripheral area NA, a crack detection trace 200 is provided. When a crack appears in the film layer above or below the crack detection trace 200, the crack detection trace 200 will also have a crack along with the film layer above or below. By detecting the change in the electrical signal in the crack detection trace 200, it is determined whether the crack detection trace 200 is cracked, and further whether a crack appears in the display substrate.

[0080] With reference to Figure 1 , Figure 2 and Figure 3 , two crack detection traces 200 can be provided in the display substrate. The two crack detection traces 200 are respectively located on both sides of the display area AA along the first direction X. The signal input end 200A and the signal output end 200B of the crack detection trace 200 are arranged adjacent to each other. For example, they can be arranged outside the rounded corner of the display area AA close to the bending area NA2. The crack detection trace 200 starts from the signal input end 200A, winds around the edge of the display area AA along one side in the first direction X for at least one round and then returns to the signal output end 200B. For example, it can wind around the edge of the display area AA for three rounds, thereby forming six parallel sub-trace segments 201 outside the display area AA.

[0081] It should be noted that in Figure 1 , only a relatively thick line is used to indicate the setting position of the crack detection trace 200, but the crack detection trace 200 is not a single-wire structure, but a loop trace structure that reciprocally extends around the position indicated by the relatively thick line for at least one round.

[0082] With reference to Figure 1 , Figure 2 , Figure 4 and Figure 6 , in the area between the bending area NA2 and the rounded corner of the display area AA close to the bending area NA2, since it is close to the cutting line and the space is small, in this area, the crack detection trace 200 only winds around for one round, forming two parallel sub-trace segments 201. The two parallel sub-trace segments 201 can be located in the same conductive layer. For example, they can both be located in the second gate metal layer.

[0083] With reference to Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 and Figure 7, the signal input terminal 200A and the signal output terminal 200B are transferred towards the direction close to the display area AA through the transfer traces 251, 252, 253, and 254. The transfer trace 254 extends to the side of the plurality of gate signal leads L1 close to the display area AA, and then extends through the transfer trace 255 to be electrically connected to the bonding pad BP in the bonding area NA3, realizing the input and output of the detection signal.

[0084] Through the research of the inventor, it is found that at the position marked by the dotted circular frame line in Figure 1 , it is the transition area where the display substrate narrows towards the bending area NA2, that is, the area between the lower rounded corner of the display substrate and the chamfer of the bending area NA2. Cracks are likely to occur in this area during several manufacturing processes of the display substrate. First, during the laser cutting of the outer contour of the display panel, due to the influence of heat generation, stress is likely to concentrate in this area; second, because this area is close to the bending area NA2, stress is likely to concentrate during the bending process; third, in the display substrate with a curved screen design, during the bonding process with the cover glass, the left and right sides of the flexible panel generate arcs and stress concentration occurs. Based on the above reasons, the crack detection in this area becomes particularly important, so the setting method of the crack detection trace 200 is optimized, as described in detail later.

[0085] Figure 8 Schematically shows Figure 2 Another enlarged view of the area B1 in Figure 9 Schematically shows Figure 2 Another enlarged view of the area B4 in Figure 10 Schematically shows Figure 9 An enlarged view of the area C in Figure 11 Schematically shows a cross-sectional view taken along the Figure 10 center line DD’ Figure 12 Schematically shows Figure 11 An enlarged view of the area E in

[0086] With reference to Figure 1 , Figure 8 , Figure 9 , Figure 10 , Figure 11 and Figure 12, in order to improve the crack detection rate of the area between the lower rounded corner of the display substrate and the chamfer of the bending area NA2, the two sub-wire segments 201 in this area can be located in two conductive layers ML respectively. For example, one sub-wire segment 201 close to the display area AA is located in the first source-drain metal layer SD1, and the other sub-wire segment 201 far from the display area AA is located in the second gate metal layer Gate2. These two sub-wire segments 201 are connected by vias when extending in the first direction X towards the vicinity of the gate signal lead L1 in the direction close to the bending area NA2.

[0087] One sub-wire segment 201 located in the first source-drain metal layer SD1 is sandwiched between the interlayer insulating layer ILD and the passivation layer PVX, and the other sub-wire segment 201 located in the second gate metal layer Gate2 is sandwiched between the second gate insulating layer GI2 and the interlayer insulating layer ILD. The crack detection trace 200 in this area is distributed between more insulating layers, so as to effectively improve the crack detection rate.

[0088] With reference to Figure 8 、 Figure 10 and Figure 11 , on the outer side of the crack detection trace 200 far from the display area AA, multiple grooves S extending along the cutting line can also be etched on the inorganic insulating layer, such as the interlayer insulating layer ILD, so as to effectively prevent the cracks generated at the cutting line from extending towards the display area.

[0089] Furthermore, the inventors also found through research that, with reference to Figure 1 and Figure 6 , in the area on the side of the bending area NA2 close to the display area AA, that is, Figure 6 the area indicated by the dashed box in

[0090] Figure 13 is prone to cracks due to stress concentration during the bending process, and a crack detection structure also needs to be set in this area for crack detection. Figure 14 Schematically shows a plan view of a display panel according to some embodiments of the present disclosure. Figure 13 Schematically shows an enlarged view of area F in Figure 15 Schematically shows Figure 14 an enlarged view of area G in Figure 16 Schematically shows Figure 15 an enlarged view of area H1 in Figure 17 Schematically shows a cross-sectional view taken along the line II' in Figure 16 Figure 18 Schematically shows Figure 15 an enlarged view of area H2 in Figure 19 Schematically shows a cross-sectional view taken along the line JJ' in Figure 18 ​​

[0091] Referring to Figure 13 , the display substrate includes a display area AA and a peripheral area NA located around the display area AA. The peripheral area NA includes a first peripheral area NA1 located on one side of the display area AA along the second direction Y, a bending area NA2 located on the side of the first peripheral area NA1 away from the display area AA, and a bonding area NA3 located on the side of the bending area NA2 away from the display area AA. The bending area NA2 and the bonding area NA3 can be arranged at intervals, and the interval area can be used to arrange structures such as test pads and driving chips.

[0092] The part of the display substrate located in the bending area NA2 is bent toward the side of the display substrate away from the light-emitting surface, so that a part of the display substrate located in the bending area NA2 away from the display area AA is bent to the back of the part of the display substrate located in the display area AA. In the drawings and text descriptions of this article, in order to more clearly illustrate the setting method of structures such as the crack detection trace 200 in the display substrate, the bending area NA2, the bonding area NA3, and the display area AA are all shown in the same plane.

[0093] The display substrate includes a substrate 100 and a plurality of sub-pixels SP, a gate driving circuit GOA, a plurality of bonding pads BP, and a plurality of gate signal leads L1 located on the substrate 100. The plurality of sub-pixels SP are arranged in the display area AA along the first direction X and the second direction Y, and the first direction X and the second direction Y intersect. For example, the first direction X and the second direction Y are perpendicular. The plurality of sub-pixels SP emit light independently to display a picture with image information.

[0094] The gate driving circuit GOA is located in the peripheral area NA and on at least one side of the display area AA along the first direction X. For example, gate driving circuits GOA are provided on both sides of the display area AA along the first direction X. The gate driving circuit GOA is electrically connected to the plurality of sub-pixels SP through a plurality of scan lines SL to write scan signals to the plurality of sub-pixels SP. The plurality of bonding pads BP are located in the bonding area NA3, and the plurality of gate signal leads L1 are located in the peripheral area NA. The gate driving circuit GOA is electrically connected to the plurality of bonding pads BP through the plurality of gate signal leads L1. The plurality of bonding pads BP are used to be electrically connected to the pins of the driving components, so that the display driving signals in the driving components can be connected into the display substrate. After the part of the display substrate located in the bending area NA2 is bent, the plurality of bonding pads BP are bent to the back.

[0095] In order to detect whether cracks occur in the display substrate during the manufacturing process, crack detection traces 200 are also provided in the peripheral region NA. For example, two crack detection traces 200 are respectively provided on both sides of the display region AA along the first direction X. The two crack detection traces 200 are respectively used to independently detect the crack conditions in the regions on both sides of the display region AA along the first direction X. The display region AA includes a virtual central axis Y1 extending along the second direction Y. These two crack detection traces 200 can be symmetrically arranged with respect to the virtual central axis Y1. In the following text, only the structure of the crack detection trace 200 on one side (left side) in the first direction X will be schematically described.

[0096] It should be noted that the virtual central axis Y1 is a virtual definition set for more clearly describing the relevant structure of the display substrate, and is not an actual structure in the display substrate.

[0097] In addition, in Figure 13 , only the position of the crack detection trace 200 is schematically shown by a relatively thick line, but the crack detection trace 200 is not a single trace structure, but a loop trace structure that reciprocally extends at least one round around the position indicated by the relatively thick line. The specific structure of the crack detection trace 200 will be described in detail later.

[0098] With reference to Figure 13 、 Figure 14 and Figure 15 , the crack detection trace 200 has a signal input end 200A and a signal output end 200B. The signal input end 200A and the signal output end 200B are arranged adjacent to each other. The signal input end 200A is electrically connected to at least one bonding pad BP, and the signal output end 200B is electrically connected to at least another bonding pad BP. The crack detection trace 200 starts from the signal input end 200A, extends along the lower edge of the display region AA, the left edge of the display region AA to the middle position of the upper edge of the display substrate, then turns back and extends along the same path to the lower edge of the display substrate, and returns to the signal output end 200B after winding around at least one round according to the foregoing path, so as to detect cracks in the region outside the edge of the display region AA.

[0099] The crack detection trace 200 includes a first portion 210 located in the first peripheral region NA1. The first portion 210 is located on the side of the bending region NA2 close to the display region AA. The orthographic projection of the first portion 210 on the substrate 100 partially overlaps with the orthographic projection of the gate signal lead L1 on the substrate 100. By providing the crack detection trace 200 at the position overlapping with the gate signal lead L1 in the first peripheral region NA1, the breakage condition of the gate signal lead L1 in this region can be detected.

[0100] According to some exemplary embodiments, with reference to Figure 13 , Figure 14 and Figure 15 , a plurality of bonding pads BP include a plurality of first bonding pads BP1 and at least two second bonding pads BP2. The gate driving circuit GOA is electrically connected to the plurality of first bonding pads BP1 through a plurality of gate signal leads L1. The signal input end 200A of the crack detection trace 200 is electrically connected to at least one second bonding pad BP2, and the signal output end 200B of the crack detection trace 200 is electrically connected to at least another second bonding pad BP2. At least two second bonding pads BP2 are located on one side of the plurality of first bonding pads BP1 close to the virtual central axis Y1.

[0101] According to some exemplary embodiments, with reference to Figure 13 , Figure 14 and Figure 15 , the plurality of gate signal leads L1 may include a plurality of first gate signal leads L11 and a plurality of second gate signal leads L12. The first gate signal leads L11 are used to transmit some AC signals, such as clock signals, etc., to the gate driving circuit GOA, and the second gate signal leads L12 are used to transmit some DC signals, such as power supply signals, etc., to the gate driving circuit GOA, for example, may include a high-level gate turn-on voltage VGH and a low-level gate turn-on voltage VGL. The second bonding pad BP2 may be located between the plurality of first bonding pads BP1 electrically connected to the plurality of first gate signal leads L11 and the plurality of first bonding pads BP1 electrically connected to the plurality of second gate signal leads L12. The orthographic projection of the first portion 210 on the substrate 100 overlaps with the orthographic projection of the plurality of first gate signal leads L11 on the substrate 100, and the orthographic projection of the first portion 210 on the substrate 100 is spaced from the orthographic projection of the plurality of second gate signal leads L12 on the substrate 100. Since the inventors found that in the bilateral-driven gate driving circuit GOA, there may be a situation where some of the first gate signal leads L11 are broken or partially broken, which is not directly reflected in the display defect, but it is very likely to appear display defects during use as the working time increases. Therefore, the necessity of detecting whether there are cracks in the first gate signal leads L11 is higher to avoid potential defective products from flowing out.

[0102] Exemplarily, according to needs, the second bonding pad BP2 may also be disposed on one side of the plurality of first bonding pads BP1 electrically connected to the plurality of first gate signal leads L11 and the plurality of first bonding pads BP1 electrically connected to the plurality of second gate signal leads L12 close to the virtual central axis Y1. The orthographic projection of the first portion 210 on the substrate 100 overlaps with the orthographic projection of the plurality of first gate signal leads L11 on the substrate 100, and the orthographic projection of the first portion 210 on the substrate 100 also overlaps with the orthographic projection of the plurality of second gate signal leads L12 on the substrate 100.

[0103] According to some exemplary embodiments, with reference to Figure 13 , the display substrate further includes a plurality of data lines DL, the plurality of data lines DL are arranged along a first direction X and extend along a second direction Y, the plurality of data lines DL are electrically connected to a plurality of sub-pixels SP, the plurality of bonding pads BP further include a plurality of third bonding pads BP3, and the plurality of data lines DL are respectively electrically connected to the plurality of third bonding pads BP3 through a plurality of data line leads L2. The plurality of third bonding pads BP3 are located on a side of at least two second bonding pads BP2 away from the plurality of first bonding pads BP1, and the orthographic projection of the first portion 210 on the substrate 100 is spaced apart from the orthographic projection of the data line lead L2 on the substrate 100. Since the inventor found that if the data line DL breaks, it will cause a bright line defect in a column of sub-pixels SP electrically connected to the data line DL, and the breakage problem of the data line DL can be directly reflected in the display defect. Therefore, there is no need to provide an additional crack detection trace 200 for detection.

[0104] According to some exemplary embodiments, with reference to Figure 14 , Figure 15 , Figure 18 and Figure 19 , the display substrate includes a plurality of conductive layers ML, and the conductive layer ML where the first portion 210 is located is on a side of the conductive layer ML where the plurality of gate signal leads L1 are located away from the substrate 100. The extending direction of the first portion 210 intersects with the extending direction of the gate signal lead L1 overlapping with the first portion 210, so that a part of the first portion 210 is located on a side of the gate signal lead L1 away from the substrate 100, and another part of the first portion 210 is located between adjacent gate signal leads L1. This can make the first portion 210 of the crack detection trace 200 have an undulating morphology, and the extending length of the first portion 210 increases, making the first portion 210 of the crack detection trace 200 more likely to crack following the cracking of the upper and lower film layers, thereby achieving a higher crack detection rate.

[0105] According to some exemplary embodiments, with reference to Figure 14 , Figure 18 and Figure 19 , the plurality of conductive layers ML include a first gate metal layer Gate1, a second gate metal layer Gate2 located on a side of the first gate metal layer Gate1 away from the substrate 100, and a first source-drain metal layer SD1 located on a side of the second gate metal layer Gate2 away from the substrate 100. The gate signal lead L1 can be a double-layer trace located in the first gate metal layer Gate1 and the second gate metal layer Gate2, and the first portion 210 can be located in the first source-drain metal layer SD1.

[0106] According to some exemplary embodiments, with reference to Figure 13and Figure 14 The crack detection trace 200 further includes a second portion 220 and a third portion 230. The second portion 220 is located on a side of the plurality of gate signal leads L1 away from the display area AA along the second direction Y. One end of the second portion 220 is electrically connected to the first portion 210, and the other end of the second portion 220 extends along the edge of the plurality of gate signal leads L1 away from the display area AA toward a side away from the virtual central axis Y1. The third portion 230 is electrically connected to the end of the second portion 220 away from the first portion 210, and the other end of the third portion 230 extends from the outside of the lower rounded corner of the display area AA, passes through the outside of the side of the display area AA in the first direction X, and extends to a side of the display area AA away from the bending area NA2.

[0107] According to some exemplary embodiments, with reference to Figure 13 , Figure 14 , Figure 15 , Figure 16 and Figure 18 , the first portion 210 includes a first sub-portion 210A and a second sub-portion 210B, and the first sub-portion 210A is connected between the second portion 220 and the second sub-portion 210B. One end of the first sub-portion 210A is located on a side of the plurality of gate signal leads L1 away from the display area AA along the second direction Y and is electrically connected to the second portion 220. The other end of the second sub-portion 210B extends along a direction close to the display area AA and close to the virtual central axis Y1, and the extending direction of the first sub-portion 210A intersects both the first direction X and the second direction Y. One end of the second sub-portion 210B is electrically connected to the first sub-portion 210A, and the other end of the second sub-portion 210B extends along the first direction X toward the direction close to the virtual central axis Y1 until it crosses the plurality of first gate signal leads L11.

[0108] As Figure 16 shown, the plurality of gate signal leads L1 includes a first lead portion L1A and a second lead portion L1B. The orthographic projection of the first sub-portion 210A on the substrate 100 overlaps with the orthographic projection of the first lead portion L1A on the substrate 100, and the orthographic projection of the second sub-portion 210B on the substrate 100 overlaps with the orthographic projection of the second lead portion L1B on the substrate 100. Both the first lead portion L1A and the second lead portion L1B extend along a direction close to the display area AA and away from the virtual central axis Y1. The extending direction of the first sub-portion 210A intersects the extending direction of the first lead portion L1A, and the extending direction of the second sub-portion 210B intersects the extending direction of the second lead portion L1B.

[0109] According to some exemplary embodiments, with reference to Figure 13 , Figure 15 , Figure 16 and Figure 17The display substrate further includes a plurality of transfer signal lines 310 and a plurality of transfer portions 320. The plurality of transfer portions 320 are located in the first peripheral area NA1, and at least a portion of the plurality of transfer signal lines 310 are located in the bending area NA2. The gate signal lead L1 is electrically connected to one end of the transfer signal line 310 via the transfer portion 320. The other end of the transfer signal line 310 extends to the binding area NA3 and is electrically connected to the binding pad BP. Similarly, the signal input end 200A and the signal output end 200B of the crack detection trace 200 are respectively electrically connected to the binding pad BP via the transfer signal line 310. The data line lead L2 is also electrically connected to the binding pad BP via the transfer signal line 310.

[0110] The multilayer conductive layer ML includes a first gate metal layer Gate1, a second gate metal layer Gate2 located on the side of the first gate metal layer Gate1 away from the substrate 100, a first source / drain metal layer SD1 located on the side of the second gate metal layer Gate2 away from the substrate 100, and a second source / drain metal layer SD2 located on the side of the first source / drain metal layer SD1 away from the substrate 100. The gate signal lead L1 is a double-layer trace located in the first gate metal layer Gate1 and the second gate metal layer Gate2. The transfer portion 320 is located in the first source / drain metal layer SD1, and the transfer signal line 310 is located in the second source / drain metal layer SD2. Placing the trace in the bending area NA2 in the second source / drain metal layer SD2 effectively prevents breakage during bending.

[0111] The transfer portion 320 is electrically connected to the portion of the gate signal lead L1 located on the first gate metal layer Gate1 through vias in the interlayer insulating layer ILD and the second gate insulating layer GI2. The transfer portion 320 is also electrically connected to the portion of the gate signal lead L1 located on the second gate metal layer Gate2 through vias in the interlayer insulating layer ILD. The transfer signal line 310 is electrically connected to the transfer portion 320 through vias in the first planarization layer PLN1 and the passivation layer PVX, thereby achieving electrical connection between the transfer signal line 310 and the gate signal lead L1.

[0112] The first portion 210 of the crack detection trace 200 is located in the first source / drain metal layer SD1. The first portion 210 and the transition portion 320 are located on the same layer. Therefore, the first portion 210 is configured with a curved structure having a first sub-portion 210A and a second sub-portion 210B to avoid the multiple transition portions 320. The second sub-portion 210B is located on the side of the multiple transition portions 320 that is closer to the display area AA and is spaced apart from the multiple transition portions 320. The first sub-portion 210A is located on the side of the transition portion 320 that is farther from the virtual central axis Y1 and is spaced apart from the multiple transition portions 320.

[0113] Figure 20 Schematic diagram showing the Figure 15 A cross-sectional view taken along the center line KK'.

[0114] According to some exemplary embodiments, with reference to Figure 15 and Figure 20 , the first portion 210 includes at least two first trace segments 211 arranged in parallel, and at least a portion of one first trace segment 211 and at least a portion of another first trace segment 211 are located in different conductive layers ML. By disposing the first portion 210 in different conductive layers ML, the crack detection rate can be further improved.

[0115] According to some exemplary embodiments, with reference to Figure 15 and Figure 20 , the multi-layer conductive layer ML includes a first gate metal layer Gate1, a second gate metal layer Gate2 located on the side of the first gate metal layer Gate1 away from the substrate 100, a first source / drain metal layer SD1 located on the side of the second gate metal layer Gate2 away from the substrate 100, and a second source / drain metal layer SD2 located on the side of the first source / drain metal layer SD1 away from the substrate 100. The gate signal lead L1 is a double-layer trace located in the first gate metal layer Gate1 and the second gate metal layer Gate2. One first trace segment 211 can be located in the first source / drain metal layer SD1, and another first trace segment 211 can be located in the second source / drain metal layer SD2.

[0116] According to some exemplary embodiments, the multi-layer conductive layer may further include a third gate metal layer located between the second gate metal layer and the first source / drain metal layer, and at least two first trace segments can be located in at least two of the third gate metal layer, the first source / drain metal layer, and the second source / drain metal layer. For example, a portion of one first trace segment is located in the first source / drain metal layer, another portion of this first trace segment is located in the second source / drain metal layer, and another first trace segment is located in the third gate metal layer.

[0117] According to some exemplary embodiments, in order to improve the crack detection rate on the side of the bending region close to the display region, the first portion may also be provided with a trace structure having at least two back-and-forths, that is, the first portion includes at least four first trace segments arranged in parallel, and at least four first trace segments can be located in the third gate metal layer, the first source / drain metal layer, and the second source / drain metal layer.

[0118] Figure 21 Schematically shows Figure 16 an enlarged view of region L in Figure 22 Schematically shows Figure 21 a cross-sectional view taken along the center line MM' in

[0119] According to some exemplary embodiments, with reference to Figure 14 , Figure 16 , Figure 21 and Figure 22, the second part 220 includes at least two second trace segments 221 arranged in parallel. The multi-layer conductive layer ML includes a first gate metal layer Gate1, a second gate metal layer Gate2 on the side of the first gate metal layer Gate1 away from the substrate 100, and a first source / drain metal layer SD1 on the side of the second gate metal layer Gate2 away from the substrate 100. The gate signal lead L1 is a double-layer trace located in the first gate metal layer Gate1 and the second gate metal layer Gate2, and at least two second trace segments 221 can all be located in the first source / drain metal layer SD1.

[0120] Figure 23 Schematically shows Figure 16 Another enlarged view of region L in Figure 24 Schematically shows along Figure 23 A cross-sectional view taken along the center line NN'.

[0121] According to some exemplary embodiments, with reference to Figure 14 , Figure 23 and Figure 24 , the second part 220 includes at least two second trace segments 221 arranged in parallel. The multi-layer conductive layer ML includes a first gate metal layer Gate1, a second gate metal layer Gate2 on the side of the first gate metal layer Gate1 away from the substrate 100, and a first source / drain metal layer SD1 on the side of the second gate metal layer Gate2 away from the substrate 100. The gate signal lead L1 is a double-layer trace located in the first gate metal layer Gate1 and the second gate metal layer Gate2. At least a part of one second trace segment 221 and at least a part of another second trace segment 221 are located in different conductive layers ML. For example, at least one second trace segment 221 is located in the first source / drain metal layer SD1, and at least another second trace segment 221 is located in the second gate metal layer Gate2.

[0122] Making at least a part of one second trace segment 221 and at least a part of another second trace segment 221 be located in different conductive layers ML, and at the same time, making at least a part of at least one second trace segment 221 be located in a conductive layer ML on the side of the conductive layer ML where the gate signal lead L1 is located away from the substrate 100, and at least a part of at least one second trace segment 221 be located in the same conductive layer ML as at least a part of the gate signal lead L1. In this way, the crack detection rate of the second part 220 of the crack detection trace can be effectively improved.

[0123] Figure 25 Schematically shows Figure 16 Another enlarged view of region L in Figure 26 Schematically shows along Figure 25 A cross-sectional view taken along the center line OO'.

[0124] According to some exemplary embodiments, with reference to Figure 14 , Figure 25 and Figure 26 , the multi-layer conductive layer ML includes a first gate metal layer Gate1, a second gate metal layer Gate2 on a side of the first gate metal layer Gate1 away from the substrate 100, a third gate metal layer Gate3 on a side of the second gate metal layer Gate2 away from the substrate 100, and a first source / drain metal layer SD1 on a side of the third gate metal layer Gate3 away from the substrate 100. The gate signal lead L1 is a double-layer trace located in the first gate metal layer Gate1 and the second gate metal layer Gate2, and the second portion 220 may be located in at least two of the first gate metal layer Gate1, the second gate metal layer Gate2, the third gate metal layer Gate3, and the first source / drain metal layer SD1.

[0125] According to some exemplary embodiments, with reference to Figure 14 , Figure 25 and Figure 26 , at least a part of the second portion 220 includes four second trace segments 221 arranged in parallel. The four second trace segments 221 may be sequentially located in the first gate metal layer Gate1, the second gate metal layer Gate2, the third gate metal layer Gate3, and the first source / drain metal layer SD1, so as to further improve the crack detection rate.

[0126] According to some exemplary embodiments, the conductive layer may further include a second source / drain metal layer on a side of the first source / drain metal layer away from the substrate. At least a part of the second portion may also be located in the second source / drain metal layer.

[0127] According to some exemplary embodiments, with reference to Figure 16 , the line width of at least a part of the second trace segment 221 is smaller than the line width of at least a part of the first trace segment 211. For example, the line width of the second trace segment 221 is smaller than the line width of the part of the first trace segment 211 located in the second sub-portion 210B. Of course, according to actual requirements, the line width of the part of the first trace segment 211 located in the second sub-portion 210B may also be set to be the same as the line width of the part located in the first sub-portion 210A, so that the line width of the second trace segment 221 is smaller than the line width of the parts of the first trace segment 211 located in the first sub-portion 210A and the second sub-portion 210B.

[0128] The inventors have found through research that the smaller the line width of the crack detection trace 200, the higher the crack detection rate. However, the set area of the second portion 220 is more likely to have the problem of missed crack detection. Therefore, the line width of the second trace segment 221 can be set to be slightly narrower. For example, the line width of the second trace segment 221 is 3.5 μm, and the line width of the part of the first trace segment 211 located in the second sub-portion 210B is 4 μm.

[0129] It should be noted that in this text, the line width of a trace should be understood as the width of the trace in the direction perpendicular to its extending direction.

[0130] Figure 27 Schematically shows Figure 14 an enlarged view of region P in Figure 28 Schematically shows Figure 27 an enlarged view of region Q in Figure 29 Schematically shows along Figure 28 a cross-sectional view taken along the line RR' in Figure 30 Schematically shows Figure 27 an enlarged view of region S in Figure 31 Schematically shows along Figure 30 a cross-sectional view taken along the line TT' in

[0131] According to some exemplary embodiments, with reference to Figure 14 , Figure 27 , Figure 28 and Figure 29 , the third part 230 can be arranged to extend around the outer edge of the power supply trace VSS. To improve the crack detection rate, the third part 230 can extend around three loops to form six parallel third trace segments 231. For example, one of the third trace segments 231 closest to the power supply trace VSS can be located in the first source-drain metal layer SD1, and the remaining five third trace segments 231 can be located in the second gate metal layer Gate2.

[0132] Of course, according to the actual crack detection requirements, these six third trace segments 231 can be located in more conductive layers ML. For example, the multi-layer conductive layers include a first gate metal layer, a second gate metal layer located on the side of the first gate metal layer away from the substrate, a third gate metal layer located on the side of the second gate metal layer away from the substrate, a first source-drain metal layer located on the side of the third gate metal layer away from the substrate, and a second source-drain metal layer located on the side of the first source-drain metal layer away from the substrate. The six third trace segments can be located in at least three of the first gate metal layer, the second gate metal layer, the third gate metal layer, the first source-drain metal layer, and the second source-drain metal layer, and the specific arrangement thereof is not limited in the embodiments of the present disclosure.

[0133] It should be noted that in Figure 14 , only a part of the third part 230 located outside the rounded corner edge of the bending region NA2 close to the display region AA is schematically shown, and the structure of the part of the third part 230 located in other regions can be kept consistent, which is not limited in the embodiments of the present disclosure.

[0134] According to some exemplary embodiments, with reference to Figure 27 , Figure 28 and Figure 29 , the second part 220 includes two second routing segments 221, and both of the second routing segments 221 are located in the first source-drain metal layer SD1. The third part 230 includes six third routing segments 231. One of the third routing segments 231 closest to the power supply trace VSS is located in the first source-drain metal layer SD1, and the remaining five third routing segments 231 are located in the second gate metal layer Gate2. One of the third routing segments 231 closest to the power supply trace VSS is connected to one of the second routing segments 221 to form an integral structure, and one of the third routing segments 231 farthest from the power supply trace VSS is electrically connected to the other second routing segment 221 through a via hole.

[0135] With reference to Figure 30 and Figure 31 , an interlayer insulating layer ILD is included between the first source-drain metal layer SD1 and the second gate metal layer Gate2. The interlayer insulating layer ILD includes at least one via hole VH, and one of the third routing segments 231 farthest from the power supply trace VSS is electrically connected to the other second routing segment 221 through at least one via hole VH in the interlayer insulating layer ILD.

[0136] At least some embodiments of the present disclosure further provide a display device, and the display device includes the display substrate as described above. The display device may include any device or product having a display function. For example, the display device may be a smart phone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (such as a head-mounted device, electronic clothing, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, etc.

[0137] It should be understood that the display device according to some exemplary embodiments of the present disclosure has all the features and advantages of the above display substrate, and these features and advantages can be referred to the description of the display substrate above and will not be elaborated here.

[0138] As used herein, the terms "substantially", "about", "approximate" and other similar terms are used as approximate terms rather than as terms of degree, and they are intended to explain the inherent deviation of measured or calculated values that will be recognized by those of ordinary skill in the art. Considering factors such as process fluctuations, measurement problems, and errors related to the measurement of a specific quantity (i.e., limitations of the measurement system), "about" or "approximate" as used herein includes the stated value and represents within an acceptable deviation range for a specific value determined by those of ordinary skill in the art. For example, "about" may mean within one or more standard deviations, or within ±10% or ±5% of the stated value.

[0139] While some embodiments in accordance with the general inventive concept of the present disclosure have been illustrated and described, those of ordinary skill in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the general inventive concept of the present disclosure, and the scope of the present disclosure is defined by the claims and their equivalents.

Claims

1. A display substrate, wherein, It includes a display area and a peripheral area located around the display area. The peripheral area includes a first peripheral area located on one side of the display area along a second direction, a bending area located on the side of the first peripheral area away from the display area, and a bonding area located on the side of the bending area away from the display area. The display substrate includes: A substrate; Multiple sub-pixels located on the substrate. The multiple sub-pixels are arranged in the display area along a first direction and a second direction, and the first direction intersects with the second direction; A gate driving circuit located on the substrate. The gate driving circuit is located in the peripheral area and on at least one side of the display area along the first direction. The gate driving circuit is electrically connected to the multiple sub-pixels; Multiple bonding pads located on the substrate. The multiple bonding pads are located in the bonding area; Multiple gate signal leads located on the substrate. The multiple gate signal leads are located in the peripheral area. The gate driving circuit is electrically connected to the multiple bonding pads through the multiple gate signal leads; and A crack detection trace located on the substrate. The crack detection trace is located in the peripheral area. Two ends of the crack detection trace are electrically connected to two of the bonding pads respectively; Wherein, the crack detection trace includes a first part located on the side of the bending area close to the display area. A positive projection of the first part on the substrate overlaps with a positive projection of the gate signal lead on the substrate in part; 2. The display substrate according to claim 1, wherein, The multiple bonding pads include multiple first bonding pads and at least two second bonding pads. The gate driving circuit is electrically connected to the multiple first bonding pads through the multiple gate signal leads. Two ends of the crack detection trace are electrically connected to two of the second bonding pads respectively; and The display area includes a virtual central axis extending along the second direction. At least two of the second bonding pads are located on the side of the multiple first bonding pads close to the virtual central axis; 3. The display substrate according to claim 1 or 2, wherein An extending direction of the first part intersects with an extending direction of the gate signal lead overlapping with the first part; 4. The display substrate according to claim 3, wherein, The crack detection trace further includes a second part located on the side of the multiple gate signal leads away from the display area along the second direction. One end of the second part is electrically connected to the first part, and the other end of the second part extends along an edge of the multiple gate signal leads away from the display area to the side away from the virtual central axis; 5. The display substrate according to claim 4, wherein, The first part includes a first sub-part and a second sub-part, and the first sub-part is connected between the second part and the second sub-part; The multiple gate signal leads include a first lead part and a second lead part. A positive projection of the first sub-part on the substrate overlaps with a positive projection of the first lead part on the substrate in part, and a positive projection of the second sub-part on the substrate overlaps with a positive projection of the second lead part on the substrate in part; And The extending direction of the first sub - part intersects with the extending direction of the first lead part, and / or the extending direction of the second sub - part intersects with the extending direction of the second lead part.

6. The display substrate according to claim 5, wherein, The extending direction of the first sub - part intersects with both the first direction and the second direction; and / or The second sub - part is arranged to extend along the first direction.

7. The display substrate according to claim 5 or 6, wherein, The display substrate further includes a plurality of transfer signal lines and a plurality of transfer parts. The plurality of transfer parts are located in the first peripheral area, and at least a part of the plurality of transfer signal lines is located in the bending area; The gate signal lead is electrically connected to one end of the transfer signal line through the transfer part, and the other end of the transfer signal line is electrically connected to the bonding pad; And The second sub - part is located on a side of the plurality of transfer parts close to the display area and is spaced apart from the plurality of transfer parts. The first sub - part is located on a side of the transfer parts away from the virtual central axis and is spaced apart from the plurality of transfer parts.

8. The display substrate according to claim 2, wherein The display substrate further includes a plurality of data lines. The plurality of bonding pads further include a plurality of third bonding pads. The plurality of data lines are respectively electrically connected to the plurality of third bonding pads. The plurality of third bonding pads are located on a side of at least two of the second bonding pads away from the plurality of first bonding pads.

9. The display substrate according to any one of claims 1-8, wherein The display substrate includes multiple conductive layers. The conductive layer where the first part is located is on a side of the conductive layer where the plurality of gate signal leads are located away from the substrate.

10. The display substrate according to claim 9, wherein A part of the first part is on a side of the gate signal lead away from the substrate, and another part of the first part is between adjacent gate signal leads.

11. The display substrate according to claim 9 or 10, wherein, The first part includes at least two first trace segments arranged in parallel. At least a part of one first trace segment and at least a part of another first trace segment are located in different conductive layers.

12. The display substrate according to claim 11, wherein The multiple conductive layers include a first gate metal layer, a second gate metal layer located on a side of the first gate metal layer away from the substrate, a third gate metal layer located on a side of the second gate metal layer away from the substrate, a first source - drain metal layer located on a side of the third gate metal layer away from the substrate, and a second source - drain metal layer located on a side of the first source - drain metal layer away from the substrate; The gate signal leads are located in the first gate metal layer and the second gate metal layer; and The at least two first trace segments are located in at least two of the third gate metal layer, the first source - drain metal layer, and the second source - drain metal layer.

13. The display substrate according to any one of claims 4-8, wherein, The second part includes at least two second trace segments arranged in parallel. The display substrate includes multiple conductive layers. At least a part of one second trace segment and at least a part of another second trace segment are located in different conductive layers.

14. The display substrate according to claim 13, wherein, At least a part of at least one second trace segment and the gate signal leads are located in at least the same conductive layer; and / or The conductive layer where at least a part of at least one second trace segment is located is on a side of the conductive layer where the gate signal leads are located away from the substrate.

15. The display substrate according to claim 13 or 14, wherein The multiple conductive layers include a first gate metal layer, a second gate metal layer on a side of the first gate metal layer away from the substrate, a third gate metal layer on a side of the second gate metal layer away from the substrate, a first source / drain metal layer on a side of the third gate metal layer away from the substrate, and a second source / drain metal layer on a side of the first source / drain metal layer away from the substrate; The gate signal lead is located in the first gate metal layer and the second gate metal layer; and The at least two second line segments are located in at least two of the first gate metal layer, the second gate metal layer, the third gate metal layer, the first source / drain metal layer, and the second source / drain metal layer.

16. The display substrate according to claim 15, wherein, At least a part of the second portion includes four second line segments arranged in parallel, and the four second line segments are sequentially located in the first gate metal layer, the second gate metal layer, the third gate metal layer, and the first source / drain metal layer.

17. The display substrate according to any one of claims 13-16, wherein, The first portion includes at least two first line segments arranged in parallel, and the line width of at least a part of the second line segment is smaller than the line width of at least a part of the first line segment.

18. A display device, wherein, The display device includes the display substrate according to any one of claims 1-17.

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