Method for identifying defects on substrate and apparatus for identifying defective driver circuits on substrate

Abstract

A method for identifying defects on a substrate having a plurality of pixels of a display located on the substrate is described. The method includes providing a clock signal for driving a portion of the display with a driver circuit disposed on the substrate; imaging at least one portion of the driver circuit in synchronization with a clock signal to obtain at least one image of the at least one portion of the driver circuit; and identifying a defect of the driver circuit within the at least one image.

Description

[0001] This application is a divisional application of the invention patent application with the application date of June 5, 2019, the application number of 201980097163.7, and the invention title of "Method for Identifying Defects on a Substrate and Apparatus for Identifying Defective Driver Circuits on a Substrate". Technical Field

[0002] Embodiments of the present disclosure relate to the testing of substrates, particularly the testing of large-area substrates for display manufacturing. Embodiments relate to defect identification. Embodiments of the present disclosure generally relate to a test system for a large-area substrate on which electronic devices are formed, and more particularly, to locating driver defects of these electronic devices. In particular, embodiments relate to a method for identifying defects on a substrate (the substrate having a plurality of pixels of a display located thereon), a computer-readable medium containing a program for a corresponding method, and an apparatus for identifying defective driver circuits on a substrate. Background Art

[0003] In many applications, substrates must be inspected to monitor the quality of the substrates. For example, glass substrates on which coating material layers are deposited are manufactured for the display market. Since defects may occur during the processing of the substrates, such as during the coating or structuring of the coated layers of the substrates, it is necessary to inspect the substrates for reviewing defects and monitoring the quality of the displays.

[0004] Displays are often manufactured on large-area substrates with continuously increasing substrate sizes. In addition, displays such as TFT-displays are undergoing continuous improvement. For example, the display bezels are getting narrower, OLED displays are increasingly used in laptop computers, desktop PC screens, and TVs in addition to mobile devices, and the first μ-LED displays are commercially available.

[0005] Active matrix liquid crystal displays (LCDs) and OLED displays are commonly used in applications such as computer and television screens, cellular phone displays, personal digital assistants (PDAs), and a growing number of other devices. Typically, an active matrix LCD or OLED display includes two plates or panels having a layer of liquid crystal material or OLED material, respectively, sandwiched therebetween. The plates are typically made of glass, polymer, or other materials suitable for forming electronic devices thereon. The display typically includes an array of thin film transistors (TFTs), each thin film transistor being coupled to a pixel. Each pixel is activated by providing signals to driver circuitry such as data and gate lines and transistors, and activation of the pixel can be provided by simultaneously addressing appropriate data and gate lines. The TFT can be turned on or off to create an electric field between the corresponding TFT and a portion of a color filter. The TFT can be turned on or off to drive current through an OLED or μ-LED. Due to the high pixel density, the close proximity of the gate and data lines, and the complexity of forming the TFTs, there is a high probability of defects during the manufacturing process.

[0006] As described above, a TFT array can be used in an LCD display. However, OLED and μ-LED displays, as well as other displays, can also be based on a TFT array backplane, where pixel electrodes are charged to activate the pixels of the display.

[0007] To reduce the manufacturing cost of the display and narrow the bezel of the display, the gate driver (i.e., the driver circuitry) can be fabricated on a substrate having a TFT array and can also be tested with a test device. For example, US2008 / 0284760 describes a method for identifying a defective driver circuit on a substrate having a plurality of pixels located thereon. The method includes: testing at least a portion of the plurality of pixels to determine the operability of the pixels in the portion of the plurality of pixels; locating defective pixels within the plurality of pixels; testing the driver circuit associated with the defective pixels; and locating the defect within the driver circuit.

[0008] To further increase the number of defects that can be identified, it is beneficial to further improve the test method and test device. SUMMARY OF THE INVENTION

[0009] In view of the above, a method for identifying defects on a substrate, a computer-readable medium containing a program for identifying defects on a substrate, and a device for identifying a defective driver circuit on a substrate having a plurality of pixels located thereon are provided. Other aspects, advantages, and features are apparent from the dependent claims, the description, and the drawings.

[0010] According to one embodiment, a method for identifying defects on a substrate having a plurality of pixels of a display disposed on the substrate is provided. The method includes: providing a clock signal for driving a portion of the display using a driver circuit provided on the substrate; imaging at least a portion of the driver circuit synchronously with the clock signal to obtain at least one image of at least a portion of the driver circuit; and identifying defects of the driver circuit within the at least one image.

[0011] According to one embodiment, a computer-readable medium containing a program for identifying defects on a substrate having a plurality of pixels disposed thereon is provided, the program performing a method according to an embodiment of the present disclosure when executed by a processor.

[0012] According to one embodiment, an apparatus for identifying a defective driver circuit on a substrate having a plurality of pixels disposed thereon is provided. The apparatus includes: a detector configured to generate a voltage contrast image of the driver circuit on the substrate; and a controller that provides a synchronization signal for synchronizing image generation with a clock signal for activating the driver circuit on the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] To enable a detailed understanding of the manner in which the above-recited features of the present disclosure are used, a more particular description of the present disclosure briefly summarized above may be obtained by reference to the embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only exemplary embodiments and are thus not to be considered limiting of its scope, and may admit other equivalent embodiments.

[0014] Figure 1A An exemplary large-area flat substrate having an array of thin-film transistors (TFTs) and a testable gate driver according to an embodiment described herein is shown, each thin-film transistor being coupled to a pixel.

[0015] Figure 1B is a schematic diagram of a driver circuit to be tested according to an embodiment of the present disclosure.

[0016] Figure 2 A portion of a substrate tested using a method according to an embodiment of the present disclosure or an apparatus according to an embodiment of the present disclosure is shown.

[0017] Figure 3 A timeline of signals is shown, showing a method for identifying defects on a substrate having a plurality of pixels of a display disposed on the substrate according to the present disclosure.

[0018] Figure 4Shows a charged particle beam device according to an embodiment of the present disclosure.

[0019] Figure 5 Shows an electron beam test device according to an embodiment of the present disclosure that can be used for electron beam testing.

[0020] Figure 6 Is a flowchart of an example operation for identifying whether there are defects in a pixel or a driver circuit according to an embodiment of the present disclosure.

[0021] For ease of understanding, wherever possible, the same reference numerals have been used to denote the same elements common to the figures. It is contemplated that elements and features of one embodiment may be advantageously combined in other embodiments without further elaboration. Detailed Embodiments

[0022] Reference will now be made in detail to exemplary embodiments, one or more examples of which are illustrated in the figures. Each example is provided by way of explanation and not meant as a limitation. For example, features shown or described as part of one embodiment can be used in other embodiments or combined with other embodiments to yield further embodiments. The present disclosure is intended to embrace such modifications and variations.

[0023] In the following description of the figures, the same reference numerals refer to the same components. Only the differences with respect to each embodiment are described. The structures shown in the figures are not necessarily drawn to scale but are used to better understand the embodiments.

[0024] Embodiments of the present disclosure provide techniques and devices for determining whether a driver circuit (e.g., a gate driver) provided on a substrate is defective. Modern display manufacturing may include driver circuits on a substrate (i.e., the substrate on which the TFT array is fabricated). This may be referred to as a gate driver on array (GOA), especially since it is easier to fabricate a gate driver on a substrate. Signal drivers that can be fabricated on a substrate can be similarly tested using methods and devices according to embodiments of the present disclosure.

[0025] Methods for testing a display substrate (especially during the manufacture of a display, i.e., before the manufacturing process is completed) and corresponding devices typically include testing of the substrate pixels. Additionally, the testing methods and testing devices can be used to provide testing of the driver circuits on the substrate. Embodiments of the present disclosure provide an option for synchronous testing of driver circuits. For example, methods and devices for synchronously testing gate driver circuits on an array of a display panel are provided. Determining defective pixels in a large-area substrate such as a liquid crystal display (LCD) panel or an organic light-emitting diode (OLED) panel can be based on the pixels, the driver circuits of the pixels, lines (gate lines or signal lines), or combinations thereof. Additionally, it is beneficial to locate driver circuit defects.

[0026] Figure 1A Shows a portion of a flat panel substrate 110 having a plurality of pixels 12. The flat panel substrate 110 is typically a flat rectangular sheet of glass, polymer material, or other suitable material on which electronic devices can be formed, and typically has a large surface area. One or more thin film transistors 18 (TFTs) and, for example, one or more capacitors may be associated with each pixel 12. The flat panel substrate 110 further includes data lines 14 and gate lines 16. Additionally, if necessary, common lines and other lines may be provided. The pixels 12, thin film transistors 18, data lines 14, and gate lines 16 may be formed on the flat panel substrate 110 by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), photolithography, or other suitable manufacturing processes.

[0027] The driver circuit may be connected to the data line or the gate line, particularly the gate line. The driver circuit 20 (e.g., a gate driver circuit) is connected to the corresponding line (e.g., the gate line 16). During testing of the flat panel substrate 110, the driver circuit 20 can be operated to drive the pixels 12. The driver circuit 20, as a gate driver circuit, can be operated in combination with the operation of the data line (i.e., the signal line). By biasing one or more shorting bars or by another operating method, the data line can be operated by an external driver circuit.

[0028] The pixels 12 can be tested, for example, by measuring the voltage contrast of the charge provided on the pixels. For example, the transistor 18 of the pixel 12 can be turned off by applying +15V to its gate, a voltage of 5V can be provided to the pixel electrode via the signal line, the transistor can be turned on by a gate voltage of -15V, and with the transistor on, a voltage of -10V can be provided to the signal line. In the absence of defects such as shorts or opens, a charge of 5V should be maintained on the pixel electrode for the on transistor. Depending on how much the measured voltage value deviates from the expected value of one or more pixels in the rows and / or columns of the display, defects and even the type may be identified. Multiple patterns and test algorithms can be provided to detect line defects, defects in the transistors 18, or other defects. Defects on the flat panel substrate can include pixel defects, line defects, and / or defects in the driver circuit. Pixel defects can include shorts to the pixel gate line and shorts to the pixel data line. Line defects can include line-to-line shorts (e.g., data line to data line or gate line to gate line), cross shorts (e.g., data line to gate line), and open line defects. According to various embodiments described herein, other flat circuit panels, such as printed circuit boards and multi-chip modules, can also be tested.

[0029] According to an embodiment of the present disclosure, a voltage contrast image of a driver circuit or at least a part of the driver circuit can be provided. Thereby, in particular in addition to the testing of pixels, an image of the driver circuit can be provided. According to an embodiment of the present disclosure, a method for identifying a defect (i.e., the presence of a defect on a substrate) on a substrate having a plurality of pixels of a display located on the substrate is provided. The method may optionally include testing at least a part of the plurality of pixels to determine the operability of the pixels in the said part of the plurality of pixels. The method includes: providing a clock signal for driving a part of the display using a driver circuit provided on the substrate; imaging at least one part of the driver circuit synchronously with the clock signal to obtain at least one image of at least one part of the driver circuit (the image may be reduced to the size of a single pixel); and determining the presence of a defect or localizing a defect of the driver circuit within at least one image. Imaging at least one part of the driver circuit includes at least one of electron beam imaging, voltage image capture, charge sensing using an electro-optical sensing device, or capacitive coupling to an electrode of the driver circuit.

[0030] Figure 1B A schematic diagram of a driver circuit 20, such as a gate driver, is shown. As will be explained in more detail with respect to Figure 2 As explained in more detail, a plurality of driver circuits can be provided on the substrate. The plurality of gate drivers can operate as shift registers, where the gate drivers operate one after another. For example, the gate driver can operate at the repetition frequency of the display multiplied by the number of gate lines, e.g., for a full HD display, at 60 Hz × 1080.

[0031] The driver circuit 20 includes a terminal 21 for operating the voltage, and an input terminal 22, a clock terminal 24, an output terminal 26, and a reset terminal 27. The combination of the signal at the input terminal and the signal at the clock terminal can activate the driver circuit. The output terminal can drive, for example, the gate lines of the display and can further activate a subsequent driver circuit. The reset terminal can be used to deactivate an active driver circuit. According to an embodiment of the present disclosure, at least one clock terminal is provided. The embodiment may include the terminals described above and may include additional terminals. A plurality of transistors may be included in the driver circuit 20. Figure 1B A transistor 120 is shown by way of example. For example, the transistor 120 can operate as a diode.

[0032] For example, in addition to the pixels on the substrate, testing of the driver circuit on the substrate may include voltage contrast imaging. For example, as described below, a scanning electron microscope (SEM) image including voltage contrast may be provided. Imaging of portions of the driver circuit may allow identification of some of the defects that may occur. According to embodiments of the present disclosure, imaging of at least a portion of the driver circuit is synchronized with the clock signal of the driver circuit. Thereby, the operation of the driver circuit and the imaging of the driver circuit are synchronized.

[0033] According to some embodiments that may be combined with other embodiments described herein, imaging of the driver circuit may be provided during operation of the driver circuit or with a predetermined delay relative to the operation of the driver circuit. For example, the imaging operation may be provided shortly after or even shortly before the operation of the driver circuit. The imaging is synchronized with a clock signal (e.g., the clock signal for the driver circuit). In view of the above, embodiments of the present disclosure have the advantage of being able to identify defect types whose identification may occur only during operation or with a predetermined timing relative to the operation of the driver circuit. Thereby, according to some embodiments, when dynamically driving a display and activating a defective gate driver, a defect is recognized.

[0034] According to some embodiments that may be combined with other embodiments described herein, at least a portion of the gate driver is imaged when the gate driver is active. For example, transistor 120 used as a diode may have a defect that appears only during operation of the driver circuit. For example, when an input signal and a clock signal are received at input terminal 22 and clock terminal 24, respectively, the driver circuit operates.

[0035] The test procedures described herein are described by way of example using an electron beam or a charged particle emitter, but certain embodiments described herein may be equally effective using optical means, charge sensing, optical means, capacitively coupled electrode arrangements, or other test applications configured to test electronic devices on large substrates under vacuum conditions or at or near atmospheric pressure.

[0036] Figure 2 A substrate 110 is shown having a plurality of pixels of a display located on the substrate. Figure 2 A schematic pixel diagram 212 adjacent to an array of driver circuits is shown. Facilitation of the manufacture of the display is based on the ability to fabricate an array of driver circuits (e.g., GOA) in a small edge region of the display (e.g., a region of 5 mm or less or even 2 mm or less). However, the driver circuits provided on the substrate are advantageously tested together with the TFT array on the substrate.

[0037] The array of driver circuits includes driver circuits 20-1, 20-2, 20-3, and 20-4. For example, the driver circuits can be drivers fabricated either simultaneously with or after fabricating the TFT array. For example, the gate driver can be fabricated from amorphous silicon or LTPS or a metal oxide such as IGZO (InGaZnO). Thus, some of the transistors in the driver circuits can be relatively large to provide the desired current. Figure 2 The driver circuits 20-1, 20-2, 20-3, and 20-4 illustrated in Figure 2 exemplarily include a first region 221, a second region 222, and a third region 223. Each of these regions can include one or more transistors, capacitors, and / or connection lines.

[0038] The driver circuits 20-1, 20-2, 20-3, and 20-4 are connected in an array as a shift register. One or more clock signals 124 are provided. Additionally, a start signal 122 can be provided. The start signal can be provided at the input terminals 22 of, for example, the first driver circuit 20-1 and optionally the second driver circuit 20-2. The input terminals 22 of the subsequent driver circuits (e.g., driver circuits 20-3, 20-4, etc.) are connected to the output terminal 26 of one of the previous driver circuits. In Figure 2 the example shown, driver circuits N and N+2 (where N is an integer) are connected to each other. According to other modifications, driver circuits N and N+3, N and N+4, N and N+5, N and N+6 can be connected to each other. The arrangement of the connected driver circuits depends on the display size, the number of clock signals provided to the display, and other parameters that may vary from display manufacturer to display manufacturer.

[0039] During operation, one driver circuit operates after another, starting, for example, from the first driver circuit 20-1. The successive operation of the driver circuits (e.g., Figure 2 top-down in Figure 2 ) is especially based on one or more clock signals 124, the start signal 122, and the output of the previous driver circuit that serves as an input to another driver circuit. Additionally, with respect to the shift register defined by multiple driver circuits, an output is provided to the pixels illustrated as schematic pixel diagrams 212 in Figure 2 Figure 2 . In Figure 2 the example shown, the output to the gate lines is provided separately from the output to the shift register. However, the output terminal 26 can also be connected to the gate lines for driving the pixels.

[0040] Embodiments of the present disclosure provide test capabilities for a driver circuit of multiple driver circuits, and in particular test synchronization with activation of the driver circuit. For example, testing of the driver circuit can be synchronized with at least one of one or more clock signals. The sensed voltage can relate to non-contact testing, where voltage is measured without making contact. In one embodiment, contact is made only at the driver circuit input pads, shorting bars, other conductive contact points or pads on the TFT array disposed at the periphery of the pixel array, and combinations thereof. Various devices can be used to sense voltage or charge. Examples include electron beams, electro-optic sensors, and electrodes adjacent to the surface of the pixel and / or driver, which are capacitively coupled to the pixel or driver. In the case of electron beam testing, the primary beam can be deflected to a specific region of the driver circuit. SEM images can be obtained, where voltage contrast measurements are provided, for example, as described with respect to Figure 4 as described.

[0041] If the voltage sensed in the driver circuit or a region of the driver circuit is approximately equal to the expected voltage (i.e., within the measurement tolerance), the driver circuit or the region of the driver circuit can be considered operable. In this case, the driver circuit or a portion of the driver circuit is free of defects. If one or more pixels associated with the corresponding driver circuit are inoperative, the pixel (or the line coupled to the pixel) can be inferred to be defective. Appropriate steps can be taken to repair the pixel or the line coupled to the pixel.

[0042] If the voltage sensed in the driver circuit or a region of the driver circuit is different from the expected voltage, the driver can be considered inoperable, and a defect within the driver circuit can be identified and reported, for example. For some embodiments, the defective driver circuit can be repaired. Repair can include severing incorrect connections (e.g., shorts) within the driver circuit, depositing conductive material to close open circuits, and connecting redundant driver structures to the circuit. Lasers can facilitate severing connections, repairing connections, and / or coupling connections.

[0043] Figure 3 A diagram showing a signal timing (i.e., synchronized signal timing) of a method for identifying defects on a substrate having a plurality of pixels of a display disposed on the substrate is shown. The operating voltage VSS is illustrated by reference numeral 321. The start signal 122 starts the operation of multiple driver circuits. One or more clock signals 124 (e.g., a first clock signal and a second clock signal) are, for example, from Figure 2The driver circuits G1 to G7 are operated in sequence from the top down (or optionally from the bottom up). Synchronized with the operation of the driver circuit, an image of the operated driver circuit is captured. This is illustrated by signal 300, which is an image synchronization signal. For example, when the first trigger signal 300 occurs, an image of driver circuit G1 is captured, when the second trigger signal 300 occurs, an image of driver circuit G2 is captured, and so on. Imaging of the driver circuit or a part of the driver circuit is synchronized with the operation of the driver circuit. For example, there may be a predetermined delay relative to the start of the operation of the driver circuit, or there may be another predetermined time relationship. According to an embodiment of the present disclosure, the synchronized imaging related to the operation of the driver circuit involves a predetermined time relationship. In particular, imaging occurs during a time period that overlaps with the operation of the driver circuit.

[0044] Figure 3 The exemplary diagram shown further indicates that the time for imaging the driver circuit or one or more parts of the driver circuit is about 50 μs. A display driven at an operating frequency of, for example, 60 Hz results in a typical time during which a single driver circuit (e.g., a gate driver) of a plurality of driver circuits is active. For example, for the dynamic driving of a display during testing, the clock time can be approximately 50 μs to 100 μs. Thus, rapid imaging of the driver circuit or one or more parts of the driver circuit is advantageous for embodiments of the present disclosure. According to some embodiments that can be combined with other embodiments described herein, the driver circuit is imaged within 500 μs or less (particularly 300 μs or less). For example, imaging can occur during 60 μs or less.

[0045] According to some embodiments, the resolution of an image of one or more parts of the driver circuit can be 50 μm or less, particularly 20 μm or less, such as about 15 μm. Thus, for synchronized imaging of the driver circuit, a resolution and a predetermined clock time that are beneficial for identifying defects within the driver circuit, rapid imaging is advantageous. As Figure 2As shown, each of driver circuits 20-1 to 20-4 includes a first region 221, a second region 222, and a third region 223. According to some embodiments that can be combined with other embodiments described herein, imaging at least one part of a driver circuit includes imaging two or more different parts of the driver circuit. For example, only imaging the first region, the second region, and the third region. Additionally, only one region can be imaged. In particular, according to some embodiments, some parts of the driver circuit may not be imaged. Thereby, image generation can be delimited to specific regions of interest. Limiting the regions to be imaged can increase the imaging speed of a particular driver circuit. Limiting the regions of the driver circuit imaged during testing further helps to reduce the charging of the driver circuit, especially for image generation using a scanning electron beam.

[0046] According to some embodiments that can be combined with other embodiments described herein, a voltage contrast image is generated in one or more regions of a driver circuit. For example, a scanning charged particle beam can be used to provide a voltage contrast image. As Figure 2 shown, a first feature 231 can display voltages, such as expected voltages, in the first driver circuit 20-1, the second driver circuit 20-2, the fourth driver circuit 20-4, and the fifth driver circuit 20-5. For example, the first feature 231 may not be visible at the expected voltage in the third driver circuit 20-3. Thereby, a part of the second region 222 in the third driver circuit 20-3 can be marked as defective.

[0047] According to some embodiments that can be combined with other embodiments described herein, identifying a defective feature in a driver circuit can be based on a comparison, particularly a comparison with one or more corresponding features in adjacent driver circuits. According to some embodiments that can be combined with other embodiments described herein, an imaging device for testing a display may include a large field of view, for example, a field of view having a size of 200 mm or greater, such as a field of view having a size of 400 mm or greater. Imaging operations at high resolution and a large field of view may provide reduced image uniformity, for example, contrast uniformity, distortion uniformity, or uniformity of other imaging characteristics across the entire field of view. Thereby, a comparison with regions or features of adjacent driver circuits can result in comparable imaging characteristics. Thereby, according to some embodiments of the present disclosure, defect identification based on a comparison with adjacent driver circuits can be beneficially provided. As another example, a second feature 232 is only displayed in the third driver circuit 20-3, and a comparison with one or more of a plurality of adjacent driver circuits (e.g., immediately adjacent driver circuits or a plurality of adjacent driver circuits within 10 or fewer adjacent driver circuits) can indicate that the second feature 232 corresponds to a defective feature in the first region 221 of the third driver circuit 20-3.

[0048] Figure 4 An electron beam (e-beam) test apparatus is shown, for example, a charged particle beam microscope 400 for locating defects such as pixels and / or driver circuits, the defects being associated with faulty pixels of a large area substrate such as a TFT array. In the test apparatus, power can be supplied from a power source to a charged particle beam gun (e.g., an e-beam gun). The controller can also control the operation of deflection elements (e.g., deflection coils or deflection plates) (e.g., via executable software) to scan the electron beam to individual pixels of a pixel array fabricated on a TFT array or to scan to generate a voltage contrast image, e.g., an SEM image. A detector can be provided to sense the voltage from signal particles (e.g., backscattered or secondary electrons).

[0049] Figure 4 A charged particle beam device or a charged particle beam microscope 400 is shown. According to some embodiments that can be combined with other embodiments described herein, the charged particle beam device or the charged particle beam microscope has a field of view with a size of 200 mm or greater. Those skilled in the art will appreciate that such a device may not be a suitable device for high-speed testing of large area substrates given the limited field of view size of, for example, scanning electron microscopes used in the semiconductor industry for high-resolution imaging. An electron beam (dashed line) can be generated by an electron beam source 412. Inside the gun chamber 410, additional beam shaping elements such as a suppressor, an extractor, and / or an anode can be provided. The electron beam source can include a TFE emitter. The gun chamber can be evacuated to a pressure of 10 -8 mbar to 10 - 9 mbar. Although a scanning electron beam device is referenced in the example, charged particle beam devices can generally be utilized.

[0050] In another vacuum chamber 420 of the column of the charged particle beam microscope 400, a focusing lens can be provided. Additional electron optical elements can be provided in additional vacuum chambers. The additional electron optical elements can be selected from the group consisting of: an astigmatism corrector, correction elements for chromatic aberration and / or spherical aberration.

[0051] The primary electron beam or primary charged particle beam can be focused on the substrate 110 by the objective lens 424. The substrate 110 is located in a substrate position on the substrate support 435. When the electron beam impinges on the substrate 110, signal electrons (e.g., secondary and / or backscattered electrons) and / or x-rays are released from the substrate 110, which can be detected by the detector 440. According to some embodiments that can be combined with other embodiments described herein, a voltage contrast filter, such as a grid 441, can be provided. The grid 441 can be biased to a potential so as to allow electrons above a certain voltage to pass through the grid while repelling electrons with energies below the corresponding voltage. According to another embodiment that can be combined with other embodiments described herein, a voltage can be provided to the substrate (the voltage provided can be offset) to generate a field for energy filtering of the secondary electrons, i.e., to generate a voltage contrast image.

[0052] In About Figure 4 In the exemplary embodiment described, a focusing lens 423 is provided. Figure 4 As shown, the objective lens 424 may have a magnetic lens component having a pole piece and a coil. The objective lens focuses the primary electron beam on the substrate 110. The objective lens may be an electrostatic-magnetic composite lens having, for example, an axial gap or a radial gap, or an electrostatic hysteresis field lens.

[0053] Additionally, a scanning deflector assembly may be provided. The scanning deflector assembly may be, for example, a magnetic and / or electrostatic scanning deflector assembly configured for high pixel rates. The scanning deflector assembly may be a single-stage assembly. Alternatively, a two-stage or even three-stage deflector assembly may be provided for scanning. Each stage may be provided at a different position along the optical axis.

[0054] According to some embodiments that may be combined with other embodiments described herein, a magnetic scanning deflector 471 and an electrostatic scanning deflector 472 may be combined. The combination of the magnetic scanning deflector and the electrostatic scanning deflector allows for a large field of view, for example, provided by the magnetic scanning deflector. Additionally, within a larger field of view, sub-regions of the field of view can be scanned at a faster speed with the electrostatic scanning deflector. Thus, fast image acquisition may be provided by the combination of the magnetic scanning deflector and the electrostatic scanning deflector. According to some embodiments, the magnetic scanning deflector may steer the beam to a sub-region. The electrostatic scanning deflector may scan the beam within the sub-region, for example, with a resolution of 20 μm or less (such as 5 μm). After the sub-region has been scanned, the magnetic scanning deflector may steer the beam to another interval, which is then scanned by the electrostatic scanning deflector. Thus, the precision of the magnetic scanning deflector may be combined with the lack of hysteresis (and corresponding reduced scanning speed) of the electrostatic deflector. Figure 4The charged particle beam microscope 400 shown includes a detector 440. The detector 440 includes a scintillator arrangement and, for example, a photomultiplier.

[0055] According to an embodiment of the present disclosure, a charged particle beam device and / or a test system including a charged particle beam device includes a controller 430 that is connected to the charged particle beam device using a signal line 432 to provide a synchronization signal, in particular to trigger imaging of an area on a substrate. The synchronization signal allows at least a part of a driver circuit to be imaged synchronously with a clock signal to obtain at least one image of at least a part of the driver circuit.

[0056] The controller of the charged particle beam device and / or the test system may include a central processing unit (CPU), a memory, and, for example, support circuits. To facilitate control of the charged particle beam device, the CPU can be one of any form of general computer processor that can be used in an industrial setting to control various components and sub-processors. The memory is coupled to the CPU. The memory, or computer-readable medium, can be one or more readily available memory devices, such as random access memory, read-only memory, floppy disks, hard disks, or any other form of local or remote digital storage device. The support circuits can be coupled to the CPU to support the processor in a conventional manner. These circuits include caches, power supplies, clock circuits, input / output circuitry systems, and associated subsystems, etc. Instructions for the inspection process and / or instructions for synchronous imaging of at least a part of the driver circuit are generally stored in the memory as software routines commonly referred to as programs. The software routines can also be stored and / or executed by a second CPU that is located remotely from the hardware controlled by the CPU. When executed by the CPU, according to any one of the embodiments of the present disclosure, the software routines convert the general computer into a dedicated computer (controller) for controlling the charged particle beam device and can provide synchronous imaging of the driver circuit, for example, synchronous gate driver imaging. Although the methods and / or processes of the present disclosure are discussed as being implemented as software routines, some of the method operations disclosed therein can be performed in hardware as well as by a software controller. Thus, the embodiments can be implemented in the following forms: software executed on a computer system and hardware or other types of hardware implementations as application specific integrated circuits, or a combination of software and hardware. According to an embodiment of the present disclosure, the controller can execute or perform a method for identifying defects on a substrate that has a plurality of pixels of a display located on the substrate, for example, for display manufacturing.

[0057] According to the embodiments described herein, the methods of the present disclosure can be carried out using a computer program, software, a computer software product, and an associated controller that can have a CPU, a memory, a user interface, and input and output devices for communicating with corresponding components of the device.

[0058] Figure 5 Shows an external view of an exemplary electron beam test system 500 (e-beam test system) that can be combined with one or more embodiments of the present disclosure for electron beam testing. The electron beam test system 500 is an integrated system that requires minimal space and is capable of testing large glass panel substrates, up to and exceeding 1.25 m × 1.5 m, for example, up to and exceeding 2.94 m × 3.37 m. The electron beam test system 500 may include a load lock chamber 504 and a test chamber 550. Additionally, optionally, a probe storage assembly and / or a probe transfer assembly may be provided.

[0059] According to some embodiments, a large area substrate may have a size of at least 1.375 m 2 The size may be from about 1.375 m 2 (1100 mm × 1250 mm - GEN 5) to about 9 m 2 and more specifically from about 2 m 2 to about 9 m 2 or even up to 12 m 2 . The substrate or substrate receiving area for which the structures, devices, and methods according to the embodiments described herein are provided may be a large area substrate as described herein. For example, the large area substrate or carrier may be GEN 5 (corresponding to a substrate of about 1.375 m 2 (1.1 m x 1.25 m)), GEN 7.5 (corresponding to a substrate of about 4.39 m 2 (1.95 m x 2.25 m)), GEN 8.5 (corresponding to a substrate of about 5.7 m 2 (2.2 m x 2.5 m)), or even GEN 10.5 (corresponding to a substrate of about 10.5 m 2 (2.94 m x 3.37 m)). Even larger generations (such as GEN 11 and GEN 12) and corresponding substrate areas can be similarly achieved.

[0060] A probe storage assembly may be provided and may, for example, accommodate one or more probes or may include a probe shaft near the test chamber 550 for easy use and retrieval. According to advantageous embodiments that can be combined with other embodiments described herein, the test chamber 550 includes a probe shaft that can be adapted to various configurations or designs of displays on large area substrates. Thus, special probes for the display layout on the substrate can be avoided, and a probe storage assembly can also be avoided.

[0061] The electron beam test system 500 may further include four or more electron beam test (EBT) columns 525, such as 10 or more EBT columns. The EBT columns may be disposed on the upper surface of the test chamber 550. During electron beam testing, certain voltages may be applied to the TFTs using one or more probes, and the electron beams from the EBT columns are directed to the respective pixels under study and / or to the contact pads of the driver circuits. The secondary electrons emitted from the pixels or contact pads may be sensed to determine the TFT or driver circuit voltages, respectively.

[0062] According to some embodiments that may be combined with other embodiments described herein, testing of a large area substrate may include operating two or more electron beam test columns. In a particular implementation, the operation of adjacent test columns may be synchronized to reduce crosstalk between adjacent columns. Thus, for example, it may be advantageous to operate each column, for example, every 50 μs to test the driver circuit in synchronization with the driver circuit operation.

[0063] Figure 6 A flowchart is shown that illustrates a method 600 for identifying defects on a substrate having a plurality of pixels of a display located on the substrate. As described above, at operation 602, at least a portion of the plurality of pixels may be tested to determine the operability of the pixels in the portion of the plurality of pixels. Optional pixel testing may be provided before or after testing of the driver circuit. The advantage of testing one or more driver circuits and one or more pixels is that the driver testing can be provided using the same test equipment as the pixel testing. At operation 604, a clock signal is provided on the substrate for driving a portion of the display using the driver circuit. At least a portion of the driver circuit is imaged, wherein at operation 606, the imaging is synchronized with the clock signal to obtain at least one image of at least a portion of the driver circuit. At operation 608, a defect in the driver circuit is identified within the at least one image.

[0064] According to some embodiments that may be combined with other embodiments described herein, identifying a defect within a driver circuit includes sensing a voltage that is different from an expected voltage, particularly where the expected voltage is derived from another driver circuit. According to some modifications, identifying the defect may further include localizing the defect. According to some embodiments that may be combined with other embodiments described herein, the method may further include repairing the defect within the driver circuit.

[0065] While the foregoing is directed to embodiments of the present disclosure, other and additional embodiments of the present disclosure may be devised without departing from the basic scope thereof, and the scope of the present disclosure is determined by the appended claims.

Claims

1. A method for identifying defects on a substrate, the substrate having a plurality of pixels of a display located on the substrate, the method comprising: Providing a clock signal for driving a portion of the display for sequentially operating a plurality of driver circuits provided on the substrate; Obtaining a plurality of images of at least one portion of each of the plurality of driver circuits during operation, wherein the step of obtaining the plurality of images includes imaging at least one portion of each of the driver circuits during operation synchronously with the clock signal to obtain at least one image of at least one portion of each of the driver circuits during operation, wherein the plurality of images includes the at least one image of at least one portion of each of the driver circuits during operation; And Identifying a defect of a first driver circuit among the plurality of driver circuits in at least one first image of the plurality of images, the at least one first image corresponding to the first driver circuit.

2. The method according to claim 1, wherein the step of imaging at least one portion of each of the driver circuits during operation includes scanning an area on the substrate for imaging at least one portion of each of the driver circuits during operation synchronously with the clock signal.

3. The method according to claim 1, wherein the resolution of each of the plurality of images is 20 μm or less.

4. The method according to claim 1, wherein the step of imaging at least one portion of each of the driver circuits during operation synchronously with the clock signal includes using voltage image capture, wherein the step of identifying the defect in the first driver circuit includes determining a voltage in the at least one first image of the first driver circuit, wherein the voltage is different from an expected voltage.

5. The method according to claim 4, wherein the expected voltage is derived from another driver circuit.

6. The method according to any one of claims 1 to 5, wherein the step of identifying the defect includes locating the defect in the at least one first image.

7. The method according to any one of claims 1 to 5, wherein the step of identifying the defect of the first driver circuit in the at least one first image includes identifying a type of the defect.

8. The method according to any one of claims 1 to 5, further comprising: Repairing the defect in the first driver circuit.

9. The method according to any one of claims 1 to 5, wherein the step of providing a clock signal for driving a portion of the display includes providing the clock signal to a clock terminal of each of the plurality of driver circuits of the display for driving a portion of the display for causing the plurality of driver circuits provided on the substrate to operate sequentially as a shift register.

10. The method according to any one of claims 1 to 5, further comprising: Testing at least a portion of the plurality of pixels to determine operability of the pixels of the portion of the plurality of pixels.

11. A method for identifying defects on a substrate, the substrate having a plurality of pixels of a display located on the substrate, the method comprising: Providing a clock signal for driving a portion of the display for sequentially operating a plurality of driver circuits provided on the substrate; Imaging at least one portion of the driver circuit of each operation of the plurality of driver circuits synchronously with the clock signal to obtain at least one image of the at least one portion of the driver circuit of each operation, wherein the resolution of the at least one image of the at least one portion of the driver circuit of each operation is 20 μm or less; And Identifying a defect of a driver circuit among the plurality of driver circuits in the at least one image of the driver circuit.

12. The method according to claim 11, wherein the resolution is 15 μm or less.

13. The method according to claim 11 or 12, wherein the step of imaging at least one portion of the driver circuit of each operation comprises using electron beam imaging or voltage image capture.

14. A method for identifying defects on a substrate, the substrate having a plurality of pixels of a display located on the substrate, the method comprising: Providing a clock signal for driving a portion of the display for sequentially operating a plurality of driver circuits provided on the substrate; Imaging at least one portion of the driver circuit of each operation of the plurality of driver circuits synchronously with the clock signal to obtain at least one scanning electron microscope (SEM) image of the at least one portion of the driver circuit of each operation; And Identifying a defect of a driver circuit among the plurality of driver circuits in the at least one SEM image of the driver circuit.

15. The method according to claim 14, wherein the step of imaging at least one portion of the driver circuit of each operation comprises scanning an area on the substrate for imaging at least one portion of the driver circuit of each operation synchronously with the clock signal.

16. The method according to claim 14 or 15, wherein the step of identifying the defect comprises locating the defect in the at least one SEM image of the driver circuit.

17. A method for identifying defects on a substrate, the substrate having a plurality of pixels of a display located on the substrate, the method comprising: Providing a clock signal for driving a portion of the display for sequentially operating a plurality of driver circuits provided on the substrate; Imaging two or more different portions of the driver circuit of each operation of the plurality of driver circuits synchronously with the clock signal to obtain images of the two or more different portions of the driver circuit of each operation; And Identifying a defect of a driver circuit among the plurality of driver circuits in the images of the driver circuit.

18. The method according to claim 17, wherein imaging of a plurality of portions of the driver circuit of each operation of the plurality of driver circuits is not performed.

19. The method according to claim 17 or 18, wherein the step of identifying the defect comprises locating the defect within the image of the driver circuit.

20. An apparatus for identifying a defective driver circuit on a substrate having a plurality of pixels located on the substrate, the apparatus comprising: a detector configured to generate a voltage contrast image of a driver circuit on the substrate; and a controller that provides a synchronization signal for synchronizing image generation with a clock signal for activating the driver circuit on the substrate; The apparatus further comprises: a computer-readable medium containing a program for identifying defects on a substrate having a plurality of pixels located on the substrate, the program performing the method according to any one of claims 1 to 5, 11, 12, 14, 15, 17 or 18 when executed by a processor.

Images