Display device

Abstract

The invention provides a display device. The display device includes a pixel circuit. The pixel circuit comprises a first driving transistor, a second driving transistor and a light emitting diode. The first driving transistor is electrically connected to a first voltage terminal. The second driving transistor is electrically connected to the first voltage terminal. The light-emitting diode has a first end and a second end. The first end is electrically connected to the first driving transistor and the second driving transistor. The second terminal is electrically connected to a second voltage terminal. When the pixel circuit presents a first brightness, the light emitting diode obtains a first current through the first driving transistor. When the pixel circuit presents the second brightness, the light emitting diode obtains the second current through the second driving transistor. The first brightness is higher than the second brightness. A current value of the first current is higher than a current value of the second current.

Description

Technical Field

[0001] The present disclosure relates to a display device, and more particularly to a display device capable of precisely controlling a wide brightness range. Background Art

[0002] Current display devices have a high-brightness display requirement. However, in order to meet the high-brightness display requirement, it is difficult for a display device to make fine adjustments to low-brightness gray levels. For example, the display device may be, for example, any form of light emitting diode (LED) display. In the pixel circuit of the display device, the brightness provided by the LED is determined according to the duty cycle of the light-emitting enabling signal. The relationship between different duty cycles of the light-emitting enabling signal and the brightness is limited by the setting of the driving circuit of the display device. Therefore, it is difficult for the display device to make fine adjustments to low-brightness gray levels by using different duty cycles of the light-emitting enabling signal. Summary of the Invention

[0003] The present disclosure is directed to a display device capable of precisely controlling a wide brightness range.

[0004] According to an embodiment of the present disclosure, the display device includes at least one pixel circuit. Each of the at least one pixel circuit includes a first driving transistor, a second driving transistor, and a light-emitting diode. The first driving transistor is electrically connected to a first voltage terminal. The second driving transistor is electrically connected to the first voltage terminal. The light-emitting diode has a first terminal and a second terminal. The first terminal is electrically connected to the first driving transistor and the second driving transistor. The second terminal is electrically connected to a second voltage terminal. When the at least one pixel circuit exhibits a first brightness, the light-emitting diode obtains a first current through the first driving transistor. When the at least one pixel circuit exhibits a second brightness, the light-emitting diode obtains a second current through the second driving transistor. The first brightness is higher than the second brightness. The current value of the first current is higher than the current value of the second current.

[0005] According to an embodiment of the present disclosure, a display device includes at least one pixel circuit. Each of the at least one pixel circuits includes a first driving transistor, a second driving transistor, a first light-emitting diode, and a second light-emitting diode. The first driving transistor is electrically connected to a first voltage terminal. The second driving transistor is electrically connected to the first voltage terminal. The first light-emitting diode has a first terminal and a second terminal. The first terminal of the first light-emitting diode is electrically connected to the first driving transistor. The second terminal of the first light-emitting diode is electrically connected to the second voltage terminal. The second light-emitting diode has a first terminal and a second terminal. The first terminal of the second light-emitting diode is electrically connected to the second driving transistor. The second terminal of the second light-emitting diode is electrically connected to the second voltage terminal. When the at least one pixel circuit presents a first brightness, the first light-emitting diode obtains a first current through the first driving transistor. When the at least one pixel circuit presents a second brightness, the second light-emitting diode obtains a second current through the second driving transistor. The first brightness is higher than the second brightness. The current value of the first current is higher than the current value of the second current.

[0006] Based on the above, the first brightness range is higher than the second brightness range. When the pixel circuit presents the first brightness, the pixel circuit operates based on the first current. When the pixel circuit presents the second brightness, the pixel circuit operates based on the second current. The current value of the first current is higher than the current value of the second current. Brightness and grayscale are positively correlated. In this way, the display device can accurately control grayscale. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic diagram of a pixel circuit of a display device according to an embodiment of the present disclosure;

[0008] Figure 2 is a signal timing diagram according to an embodiment of the present disclosure;

[0009] Figure 3 is a schematic diagram showing a brightness range according to an embodiment of the present disclosure;

[0010] Figure 4 is a schematic diagram of a pixel circuit of a display device according to an embodiment of the present disclosure;

[0011] Figure 5 is a schematic diagram of a pixel circuit according to an embodiment of the present disclosure;

[0012] Figure 6 is a schematic diagram showing a brightness range according to an embodiment of the present disclosure;

[0013] Figure 7 is a schematic diagram of a pixel circuit according to an embodiment of the present disclosure;

[0014] Figure 8is a schematic diagram of a pixel circuit according to an embodiment of the present disclosure;

[0015] Figure 9 is a signal timing diagram according to an embodiment of the present disclosure;

[0016] Figure 10 is a schematic diagram of a pixel circuit according to an embodiment of the present disclosure;

[0017] Figure 11 is a schematic diagram of a pixel circuit of a display device according to an embodiment of the present disclosure;

[0018] Figure 12 FIG. 1 is a schematic diagram of a driving transistor according to an embodiment of the present disclosure.

[0019] Description of Reference Numerals

[0020] 100, 200, 300: Display devices

[0021] 110, 210, 310, 410: Control signal generation circuit

[0022] 120, 220: Logic circuits

[0023] AA: Active Area

[0024] B1: First brightness

[0025] B2: Second brightness

[0026] B3: Third brightness

[0027] BG: Bottom Gate

[0028] C1, C2: capacitors

[0029] D: Drain

[0030] EM: luminous enable signal

[0031] EMS: Scan enable signal

[0032] EQE1, EQE2: EQE characteristics

[0033] GA: AND logic gate

[0034] GN: NOR logic gate

[0035] I1: first current

[0036] I2: Second current

[0037] I3: third current

[0038] I4: fourth current

[0039] L1, L2: The first grayscale value range

[0040] L3: The second grayscale value range

[0041] LE: Light-emitting diode

[0042] LE1: The first light-emitting diode

[0043] LE2: The second light-emitting diode

[0044] PVDD, PVSS: Voltage terminals

[0045] PX1, PX2, PX3, PX4, PX5, PX6, PX7: Pixel circuits

[0046] S: Source electrode

[0047] SD, SD1, SD2: Data signals

[0048] SF1: The first sub-frame time

[0049] SF2: The second sub-frame time

[0050] SG1, SG2: Control signals

[0051] SR: Reference signal

[0052] SS: Scan signal

[0053] SS1: The first scan signal

[0054] SS: The second scan signal

[0055] SSB: Inverted scan signal

[0056] t1, t2, t3, t4, t5, t6: Time points

[0057] TD1: The first driving transistor

[0058] TD2: The second driving transistor

[0059] TD-1, TD-2, TD-3: Driving transistors

[0060] TE1, TE2, TE3, TE4: Light-emitting control transistors

[0061] TG: Gate electrode

[0062] TPC: Compensation period

[0063] TPE: Light-emitting period

[0064] TP1, TP2, TP3: Signal timing diagrams

[0065] TPR: During reset

[0066] TR1, TR2: Control transistors

[0067] TS1, TS2, TS3, TS4: Scan transistors

[0068] VDC: DC voltage source

[0069] VR, VR1, VR2: Reference voltages Detailed implementation manners

[0070] The present disclosure can be understood by referring to the following detailed description in conjunction with the accompanying drawings described below. It should be noted that, for the purpose of clear illustration and easy understanding by the reader, each of the accompanying drawings of the present disclosure shows a part of the electronic device, and some components in each of the accompanying drawings may not be drawn to scale. In addition, the number and size of each device shown in the accompanying drawings are only illustrative and are not intended to limit the scope of the present disclosure.

[0071] Certain terms are used throughout the description and the following claims to refer to specific components. As those skilled in the art will understand, electronic device manufacturers may use different names to refer to components. This document does not intend to distinguish between components with different names but the same functions. In the following description and in the claims, the terms "comprising", "including" and "having" are used in an open-ended manner and should therefore be interpreted as meaning "including but not limited to...". Thus, when the terms "comprising", "including" and / or "having" are used in the description of the present disclosure, it will indicate the presence of corresponding features, regions, steps, operations and / or components, but not limited to the presence of one or more corresponding features, regions, steps, operations and / or components.

[0072] It should be understood that when a component is referred to as being "coupled to", "connected to" or "conducted to" another component, the component can be directly connected to the other component and can directly establish an electrical connection, or there may be intermediate components between these components for relaying the electrical connection (indirect electrical connection). In contrast, when a component is referred to as being "directly coupled to", "directly conducted to" or "directly connected to" another component, there are no intermediate components.

[0073] Although terms such as first, second, third, etc. may be used to describe different component parts, such component parts are not limited by these terms. The terms are only used to distinguish the component parts in the description from other component parts. The claims may not use the same terms, but may use terms such as first, second, third, etc. relative to the order required for the components. Thus, in the following description, the first component part may be the second component part in the claims.

[0074] The electronic device disclosed herein may, for example, include a display device, a sensing device, an antenna device, a touch device, a packaging device, a splicing device, or other suitable electronic devices, but is not limited thereto. The display device can be any type of display device, such as a color display device, a monochrome display device, a transparent display device, a dual-sided display device, a virtual reality display device, an augmented reality display device, a 3D display device, a splicing display device, a flexible display device, a foldable display device, a stretchable display device, a rollable display device, but is not limited thereto. In some embodiments, the display device may include a self-luminous display device, a non-self-luminous display device. The display device disclosed herein may include a pixel circuit. The pixel circuit may include a light-emitting diode, which may, for example, include an organic light-emitting diode (OLED), a mini light-emitting diode (mini LED), a micro light-emitting diode (micro LED), or a quantum dot light-emitting diode (quantum dot LED, which may include QLED, QDLED), or other suitable materials, or a combination of the above, but is not limited thereto. The antenna device may, for example, be a liquid crystal antenna, but is not limited thereto. The antenna device may, for example, include an antenna splicing device, but is not limited thereto. It should be noted that the electronic device may be any permutation and combination of the foregoing, but is not limited thereto. In addition, the shape of the electronic device may be rectangular, circular, polygonal, a shape with curved edges, or other suitable shapes. The electronic device may have peripheral systems such as a driving system, a control system, a light source system... to support the display device, the antenna device, or the splicing device, but the disclosure is not limited thereto. The sensing device may include a camera, an infrared sensor, a fingerprint sensor, etc., and the disclosure is not limited thereto. In some embodiments, the sensing device may further include a flash, an infrared (IR) light source, other sensors, electronic components, or a combination of the above, but is not limited thereto. It should be noted that the electronic device disclosed herein may be various combinations of the above devices, but is not limited thereto. The electronic device disclosed herein is exemplified by a display device, but the disclosure is not limited thereto.

[0075] In the present disclosure, embodiments use "pixel" or "pixel unit" as a unit for describing a specific area containing at least one functional circuit for at least one specific function. The area of a "pixel" depends on the unit for providing a specific function, and adjacent pixels may share the same part or wire, but may also include its own specific part therein. For example, adjacent pixels may share the same scan line or the same data line, but a pixel may also have its own transistor or capacitor.

[0076] It should be noted that the technical features in the different embodiments described below can be replaced, recombined, or mixed with each other without departing from the spirit of the present disclosure to form another embodiment.

[0077] Please refer to Figure 1 , Figure 1 FIG. is a schematic diagram of a pixel circuit of a display device according to an embodiment of the present disclosure. In this embodiment, the display device 100 includes at least one pixel circuit PX1. The pixel circuit PX1 includes a first driving transistor TD1, a second driving transistor TD2, and a light-emitting diode LE. The first driving transistor TD1 is electrically connected to a voltage terminal PVDD. The second driving transistor TD2 is electrically connected to the voltage terminal PVDD. The light-emitting diode LE has a first end and a second end. The first end (e.g., anode) of the light-emitting diode LE is electrically connected to the first driving transistor TD1 and the second driving transistor TD2. The second end (e.g., cathode) of the light-emitting diode LE is electrically connected to a voltage terminal PVSS. The voltage value of the voltage terminal PVDD is higher than the voltage value of the voltage terminal PVSS.

[0078] In this embodiment, the light-emitting diode LE can provide light in a first brightness range using a first current I1 and provide light in a second brightness range using a second current I2, where the first brightness range is greater than the second brightness range. For example, when the pixel circuit PX1 presents a first brightness (e.g., the highest brightness in the first brightness range), the light-emitting diode LE obtains the first current I1 through the first driving transistor TD1. When the pixel circuit PX1 presents a second brightness (e.g., any brightness in the second brightness range), the light-emitting diode LE obtains the second current I2 through the second driving transistor TD2. The first brightness is higher than the second brightness. The current value of the first current I1 is higher than the current value of the second current I2.

[0079] It is worth mentioning here that brightness is positively correlated with gray scale. In this way, the display device 100 can accurately control the gray-scale change in the first brightness range using the first current I1 and accurately control the gray-scale change in the second brightness range using the second current I2. For a detailed description, please refer to Figure 3 the description, which will not be elaborated here.

[0080] In this embodiment, the first end of the first driving transistor TD1 is electrically connected to the voltage terminal PVDD. The second end of the first driving transistor TD1 is electrically connected to the first end of the light-emitting diode LE. The control terminal of the first driving transistor TD1 receives a control signal SG1. The first end of the second driving transistor TD2 is electrically connected to the voltage terminal PVDD. The second end of the second driving transistor TD2 is electrically connected to the first end of the light-emitting diode LE. The control terminal of the second driving transistor TD2 receives a control signal SG2.

[0081] In this embodiment, the design of the first driving transistor TD1 is different from that of the second driving transistor TD2. Therefore, the current value of the first current I1 generated by the first driving transistor TD1 is higher than the current value of the second current I2 generated by the second driving transistor TD2. For example, the material of the semiconductor layer in the first driving transistor TD1 is different from the material of the semiconductor layer in the second driving transistor TD2. In some embodiments, the first driving transistor TD1 is an LTPS thin film transistor (TFT). The second driving transistor TD2 is an IGZO TFT. Taking this embodiment as an example, the first driving transistor TD1 can be a P-type LTPS TFT. The second driving transistor TD2 can be an N-type IGZO TFT, but the present disclosure is not limited thereto. In some embodiments, although the material of the semiconductor layer in the first driving transistor TD1 is the same as the material of the semiconductor layer in the second driving transistor TD2, the purpose of the current value of the first current I1 being higher than the current value of the second current I2 can be achieved by other means. For example, it can be achieved by different channel doping concentrations in the semiconductor layer, different channel width-to-length ratios, different connection methods of the bottom gate, different biases of the bottom gate, or a combination of the above methods. In some embodiments, the different semiconductor materials of the first driving transistor TD1 and the second driving transistor TD2 can be combined with different channel doping concentrations in the semiconductor layer, different channel width-to-length ratios, different connection methods of the bottom gate, different biases of the bottom gate, or the above methods. In some embodiments, the first driving transistor TD1 and the second driving transistor TD2 can be N-type transistors. In some embodiments, the first driving transistor TD1 and the second driving transistor TD2 can be P-type transistors.

[0082] In some embodiments, the doping concentration of the channel in the first driving transistor TD1 is higher than the doping concentration of the channel in the second driving transistor TD2. Another example is that the channel width-to-length ratio in the first driving transistor TD1 is higher than the channel width-to-length ratio in the second driving transistor TD2. In addition, in some embodiments, the connection method of the bottom gate of the first driving transistor TD1 is different from the connection method of the bottom gate of the second driving transistor TD2 or the bias of the bottom gate of the first driving transistor TD1 is different from the bias of the bottom gate of the second driving transistor TD2 (for detailed description, please refer to Figure 9 the description). The embodiment in which the current value of the first current I1 generated by the first driving transistor TD1 of the pixel circuit PX1 is higher than the current value of the second current I2 generated by the second driving transistor TD2 is applicable to all embodiments of the present disclosure, so it will not be elaborated below.

[0083] Taking this embodiment as an example, the pixel circuit PX1 further includes light-emitting control transistors TE1, TE2, and scanning transistors TS1 to TS4. The first end of the light-emitting control transistor TE1 is electrically connected to the voltage terminal PVDD. The second end of the light-emitting control transistor TE1 is electrically connected to the first end of the first driving transistor TD1 and the first end of the second driving transistor TD2. The control end of the light-emitting control transistor TE1 electrically receives the light-emitting enable signal EM. The first end of the light-emitting control transistor TE2 is electrically connected to the second end of the first driving transistor TD1 and the second end of the second driving transistor TD2. The second end of the light-emitting control transistor TE2 is electrically connected to the first end of the light-emitting diode LE. The control end of the light-emitting control transistor TE2 electrically receives the light-emitting enable signal EM.

[0084] The first end of the scanning transistor TS1 receives the data signal SD. The second end of the scanning transistor TS1 is electrically connected to the first end of the first driving transistor TD1 and the first end of the second driving transistor TD2. The control end of the scanning transistor TS1 receives the first scanning signal SS1. The first end of the scanning transistor TS2 receives the data signal SD. The second end of the scanning transistor TS2 is electrically connected to the first end of the first driving transistor TD1 and the first end of the second driving transistor TD2. The control end of the scanning transistor TS2 receives the second scanning signal SS2.

[0085] The first end of the scanning transistor TS3 is electrically connected to the control end of the first driving transistor TD1. The second end of the scanning transistor TS3 is electrically connected to the second end of the first driving transistor TD1. The control end of the scanning transistor TS3 receives the first scanning signal SS1. The first end of the scanning transistor TS4 is electrically connected to the control end of the second driving transistor TD2. The second end of the scanning transistor TS4 is electrically connected to the second end of the second driving transistor TD2. The control end of the scanning transistor TS3 receives the second scanning signal SS2.

[0086] In this embodiment, the light-emitting control transistors TE1 and TE2 are respectively implemented by, for example, P-type transistors, but the present disclosure is not limited thereto. The scanning transistors TS1 to TS4 are respectively implemented by, for example, N-type transistors, but the present disclosure is not limited thereto.

[0087] In this embodiment, the pixel circuit PX1 further includes a control signal generation circuit 110. The control signal generation circuit 110 generates control signals SG1 and SG2 based on a reference voltage VR and a reference signal SR. The control signal generation circuit 110 includes control transistors TR1 and TR2, and capacitors C1 and C2. A first terminal of the control transistor TR1 is electrically connected to the reference voltage VR. A control terminal of the control transistor TR1 receives the reference signal SR. A second terminal of the control transistor TR1 provides the control signal SG1. A first terminal of the control transistor TR2 is electrically connected to the reference voltage VR. A control terminal of the control transistor TR2 receives the reference signal SR. A second terminal of the control transistor TR2 provides the control signal SG2. The capacitor C1 is electrically connected between the second terminal of the control transistor TR1 and a voltage terminal PVDD. The capacitor C2 is electrically connected between the second terminal of the control transistor TR2 and a voltage terminal PVSS.

[0088] In this embodiment, the control transistors TR1 and TR2 are respectively implemented by N-type transistors, for example, but the present disclosure is not limited thereto.

[0089] In this embodiment, the display device 100 further includes a logic circuit 120. The logic circuit 120 is electrically connected to the pixel circuit PX1. The logic circuit 120 generates a first scan signal SS1 and a second scan signal SS2 based on a scan enable signal EMS, a scan signal SS, and an inverted scan signal SSB. The inverted scan signal SSB may be a complementary signal of the scan signal SS. The scan signal SS and the inverted scan signal SSB may be generated by a gate driving circuit (such as, GOP), but are not limited thereto.

[0090] In this embodiment, the logic circuit 120 includes a NOR logic gate GN and an AND logic gate GA. A first input terminal of the NOR logic gate GN receives the scan signal SS. A second input terminal of the NOR logic gate GN receives the scan enable signal EMS. The NOR logic gate GN performs a NOR logic operation on the scan signal SS and the scan enable signal EMS to generate the first scan signal SS1. An output terminal of the NOR logic gate GN outputs the first scan signal SS1. A first input terminal of the AND logic gate GA receives the inverted scan signal SSB. A second input terminal of the AND logic gate GA receives the scan enable signal EMS. The AND logic gate GA performs an AND logic operation on the inverted scan signal SSB and the scan enable signal EMS to generate the second scan signal SS2. An output terminal of the AND logic gate GA outputs the second scan signal SS2.

[0091] In this embodiment, the pixel circuit PX1 and the control signal generation circuit 110 may be disposed within the active area AA of the display device 100. The logic circuit 120 may be disposed outside the active area AA of the display device 100, but the present disclosure is not limited thereto. For example, the scan signal SS and the inverted scan signal SSB may be provided by a gate driver circuit (e.g., Gatedriver on panel, GOP), but the present disclosure is not limited thereto. Please refer to Figure 1 and Figure 2 , Figure 2 is a signal timing diagram shown according to an embodiment of the present disclosure. Figure 2 The signal timing diagram TP1 presenting the first brightness range and the signal timing diagram TP2 presenting the second brightness range are shown. In this embodiment, the first driving transistor TD1 is a P-type LTPS TFT. The second driving transistor TD2 is an N-type IGZO TFT. In this embodiment, taking the presentation of the first brightness range as an example, the voltage value of the reference voltage VR is a low voltage value. The voltage value of the scan enable signal EMS is a low voltage value. When presenting the first brightness range (e.g., the first brightness), the first driving transistor TD1 receives the data signal SD according to the first scan signal SS1 and generates a first current I1 according to the data signal SD.

[0092] During the reset period TPR between the time points t1 and t2, the voltage value of the reference signal SR is a high voltage value. The control transistors TR1 and TR2 are turned on. Therefore, the voltage values of the control signals SG1 and SG2 are low voltage values respectively. The first driving transistor TD1 is turned on according to the control signal SG1. The second driving transistor TD2 is turned off.

[0093] During the reset period TPR, the voltage value of the scan signal SS is a high voltage value. The voltage values of the first scan signal SS1 and the second scan signal SS2 are low voltage values respectively. Therefore, the scan transistors TS1 to TS4 are turned off. In addition, during the reset period TPR, the voltage value of the emission enable signal EM is a high voltage value. Therefore, the emission control transistors TE1 and TE2 are turned off.

[0094] During the compensation period TPC between time points t3 and t4, the voltage value of the reference signal SR is a low voltage value. The control transistors TR1 and TR2 are turned off. The control terminal of the first driving transistor TD1 is floated. During the compensation period TPC, the voltage value of the scan signal SS is a low voltage value. The voltage value of the first scan signal SS1 is a high voltage value. The voltage value of the second scan signal SS2 is a low voltage value. Therefore, the scan transistors TS1 and TS3 are turned on. The scan transistors TS2 and TS4 are turned off. The scan transistor TS1 transmits the data signal SD to the first terminal of the first driving transistor TD1. Since the first driving transistor TD1 and the scan transistor TS3 are turned on, the voltage value at the control terminal of the first driving transistor TD1 is equal to the sum of the threshold voltage value (Vth) of the first driving transistor TD1 and the voltage value (VSD) of the data signal SD (i.e., VSD + Vth). Therefore, during the compensation period TPC, the voltage value at the control terminal of the first driving transistor TD1 has the voltage value of the data signal SD and is compensated based on the threshold voltage value of the first driving transistor TD1.

[0095] During the light-emitting period TPE between time points t5 and t6, the voltage value of the reference signal SR is a low voltage value. The control transistors TR1 and TR2 are turned off. The voltage value of the scan signal SS is a high voltage value. The voltage values of the first scan signal SS1 and the second scan signal SS2 are low voltage values, respectively. Therefore, the scan transistors TS1 to TS4 are turned off. In addition, during the light-emitting period TPE, the voltage value of the light-emission enabling signal EM is a low voltage value. The light-emitting control transistors TE1 and TE2 are turned on. Therefore, the first driving transistor TD1 generates a first current I1 based on the voltage value at the control terminal of the first driving transistor TD1.

[0096] Taking the presentation of the second brightness range as an example, the voltage value of the reference voltage VR is a high voltage value. The voltage value of the scan enabling signal EMS is a high voltage value. When presenting the second brightness range (such as the second brightness), the second driving transistor TD2 receives the data signal SD according to the second scan signal SS2 and generates a second current I2 according to the data signal SD.

[0097] During the reset period TPR between time points t1 and t2, the voltage value of the reference signal SR is a high voltage value. The control transistors TR1 and TR2 are turned on. Therefore, the voltage values of the control signals SG1 and SG2 are high voltage values, respectively. The first driving transistor TD1 is turned off. The second driving transistor TD2 is turned on according to the control signal SG2.

[0098] During the compensation period TPC between time point t3 and time point t4, the voltage value of the reference signal SR is a low voltage value. The control transistors TR1 and TR2 are turned off. The control terminal of the second driving transistor TD2 is floating. During the compensation period TPC, the voltage value of the scan signal SS is a low voltage value. The voltage value of the first scan signal SS1 is a low voltage value. The voltage value of the second scan signal SS2 is a high voltage value. Therefore, the scan transistors TS1 and TS3 are turned off. The scan transistors TS2 and TS4 are turned on. The scan transistor TS2 transmits the data signal SD to the first end of the second driving transistor TD2. Since the second driving transistor TD2 and the scan transistor TS4 are turned on, the voltage value at the control terminal of the second driving transistor TD2 is equal to the sum of the threshold voltage value (Vth) of the second driving transistor TD2 and the voltage value (VSD) of the data signal SD (i.e., VSD + Vth). Therefore, during the compensation period TPC, the voltage value at the control terminal of the second driving transistor TD2 has the voltage value of the data signal SD and is compensated based on the threshold voltage value of the second driving transistor TD2.

[0099] During the light-emitting period TPE between time point t5 and time point t6, the voltage value of the reference signal SR is a low voltage value. The control transistors TR1 and TR2 are turned off. The voltage value of the scan signal SS is a high voltage value. The voltage values of the first scan signal SS1 and the second scan signal SS2 are low voltage values respectively. Therefore, the scan transistors TS1 to TS4 are turned off. In addition, during the light-emitting period TPE, the voltage value of the light-emitting enable signal EM is a low voltage value. The light-emitting control transistors TE1 and TE2 are turned on. Therefore, the second driving transistor TD2 generates a second current I2 according to the voltage value at the control terminal of the second driving transistor TD2.

[0100] In this embodiment, all the pixel circuits PX1 in the display device 100 can uniformly perform the operation of the signal timing diagram TP1 or uniformly perform the operation of the signal timing diagram TP2. The above operations can be referred to as a full-screen driving mode. In this embodiment, all the pixels PX1 can uniformly perform the operation of the signal timing diagram TP1 when the ambient brightness is high, and uniformly perform the operation of the signal timing diagram TP2 when the ambient brightness is low, but this is not limited thereto.

[0101] Please refer to Figure 1 and Figure 3 , Figure 3 is a schematic diagram of the brightness range shown according to an embodiment of the present disclosure. Figure 3The first luminance range L1 and the second luminance range L2 are shown. The first luminance range is greater than the second luminance range, and the first luminance range L1 partially overlaps the second luminance range L2. The first luminance B1 can correspond to any luminance in the first luminance range L1, the second luminance B2 can correspond to any luminance in the second luminance range L2, and the first luminance B1 is higher than the second luminance B2. In some embodiments, the first luminance B1 can be the highest luminance of the display device 100, or rather, the first luminance B1 is the highest luminance in the first luminance range L1, but this is not limiting. In this embodiment, the display device 100 can be driven by the first driving transistor TD1 so that the pixel circuit PX1 can present the gray-scale change of the first luminance range L1. The display device 100 can be driven by the second driving transistor TD2 so that the pixel circuit PX1 can present the gray-scale change of the second luminance range L2.

[0102] In this embodiment, the first luminance range L1 is determined by the first gray-scale value (e.g., "0" to "255"). The first gray-scale value is determined by the first current I1 provided by the first driving transistor TD1. The first current I1 is determined by the voltage value of the data signal SD. Similarly, the second luminance range L2 is determined by the second gray-scale value (e.g., "0" to "255"). The second gray-scale value is determined by the second current I2 provided by the second driving transistor TD2. The second current I2 is determined by the voltage value of the data signal SD. It should be noted that the current value of the second current I2 is lower than the current value of the first current I1. Therefore, based on the same gray-scale value, the luminance presented by driving through the first driving transistor TD1 is different from the luminance presented by driving through the second driving transistor TD2. For example, when the first gray-scale and the second gray-scale are both "255", the luminance presented by driving through the first driving transistor TD1 is the first luminance B1, and the luminance presented by driving through the second driving transistor TD2 is the third luminance B3, where the first luminance B1 is greater than the third luminance B3. Refer to Figure 3 , the difference in luminance of different levels divided by the gray-scale value in the first luminance range L1 is greater than the difference in luminance of different levels divided by the gray-scale value in the second luminance range L2. Therefore, based on the second current I2 and the second luminance range L2, the pixel circuit PX1 can present a finer luminance change. In some embodiments, the above design can enable the display device 100 to present a better image gray-scale change and reduce the discomfort of the human eye when viewing the image in a low ambient luminance, but this is not limiting.

[0103] In the full-screen driving mode, when all pixel circuits PX1 in the display device 100 present a first gray-scale value, the gray-scale values presented by all pixel circuits PX1 are within a first brightness range L1. In the full-screen driving mode, when all pixel circuits PX1 in the display device 100 present a second gray-scale value, the gray-scale values presented by all pixel circuits PX1 are within a second brightness range L2.

[0104] Please refer to Figure 4 , Figure 4 FIG. is a schematic diagram of a pixel circuit of a display device according to an embodiment of the present disclosure. In this embodiment, the display device 200 includes at least one pixel circuit PX2. The pixel circuit PX2 includes a first driving transistor TD1, a second driving transistor TD2, light-emitting control transistors TE1, TE2, scanning transistors TS1 to TS4, and a light-emitting diode LE. In this embodiment, when the pixel circuit PX2 presents a first brightness (e.g., the highest brightness of the first brightness range), the light-emitting diode LE obtains a first current I1 through the first driving transistor TD1. When the pixel circuit PX2 presents a second brightness (e.g., any brightness of the second brightness range), the light-emitting diode LE obtains a second current I2 through the second driving transistor TD2. The first brightness is higher than the second brightness. The current value of the first current I1 is higher than the current value of the second current I2.

[0105] In this embodiment, the first end of the light-emitting control transistor TE1 is electrically connected to the voltage terminal PVSS. The second end of the light-emitting control transistor TE1 is electrically connected to the first end of the first driving transistor TD1 and the first end of the second driving transistor TD2. The control end of the light-emitting control transistor TE1 electrically receives the light-emitting enable signal EM. The first end of the light-emitting control transistor TE2 is electrically connected to the second end of the first driving transistor TD1 and the second end of the second driving transistor TD2. The second end of the light-emitting control transistor TE2 is electrically connected to the first end (e.g., cathode) of the light-emitting diode LE. The control end of the light-emitting control transistor TE2 electrically receives the light-emitting enable signal EM. The second end (e.g., anode) of the light-emitting diode LE is connected to the voltage terminal PVDD. The voltage value of the voltage terminal PVDD is higher than the voltage value of the voltage terminal PVSS.

[0106] The first end of the scanning transistor TS1 receives the data signal SD. The second end of the scanning transistor TS1 is electrically connected to the first end of the first driving transistor TD1 and the first end of the second driving transistor TD2. The control end of the scanning transistor TS1 receives the first scanning signal SS1. The first end of the scanning transistor TS2 receives the data signal SD. The second end of the scanning transistor TS2 is electrically connected to the first end of the first driving transistor TD1 and the first end of the second driving transistor TD2. The control end of the scanning transistor TS2 receives the second scanning signal SS2.

[0107] The first terminal of the scanning transistor TS3 is electrically connected to the control terminal of the first driving transistor TD1. The second terminal of the scanning transistor TS3 is electrically connected to the second terminal of the first driving transistor TD1. The control terminal of the scanning transistor TS3 receives the first scanning signal SS1. The first terminal of the scanning transistor TS4 is electrically connected to the control terminal of the second driving transistor TD2. The second terminal of the scanning transistor TS4 is electrically connected to the second terminal of the second driving transistor TD2. The control terminal of the scanning transistor TS3 receives the second scanning signal SS2.

[0108] In this embodiment, the light-emitting control transistors TE1, TE2, and the scanning transistors TS1 to TS4 are respectively implemented by, for example, N-type transistors, but the present disclosure is not limited thereto.

[0109] In this embodiment, the design of the first driving transistor TD1 is different from the design of the second driving transistor TD2. Therefore, the current value of the first current I1 generated by the first driving transistor TD1 is higher than the current value of the second current I2 generated by the second driving transistor TD2. For example, the material of the semiconductor layer in the first driving transistor TD1 is different from the material of the semiconductor layer in the second driving transistor TD2. Taking this embodiment as an example, the first driving transistor TD1 may be an N-type LTPS TFT. The second driving transistor TD2 may be an N-type IGZO TFT, but the present disclosure is not limited thereto. In some embodiments, the purpose that the current value of the first current I1 is higher than the current value of the second current I2 can be achieved by doping different concentrations in the channel, different channel width-to-length ratios, different connection methods of the lower gate, different biases of the lower gate, or a combination of the above methods. In some embodiments, the first driving transistor TD1 and the second driving transistor TD2 may be N-type transistors. In some embodiments, the first driving transistor TD1 and the second driving transistor TD2 may be P-type transistors.

[0110] In this embodiment, the pixel circuit PX2 further includes a control signal generation circuit 210. The control signal generation circuit 210 is electrically connected to the pixel circuit PX2. The control signal generation circuit 210 generates control signals SG1 and SG2. The control signal generation circuit 210 includes control transistors TR1 and TR2, and capacitors C1 and C2. A first end of the control transistor TR1 is electrically connected to a reference voltage VR1. A control end of the control transistor TR1 receives a reference signal SR. A second end of the control transistor TR1 provides the control signal SG1. A first end of the control transistor TR2 is electrically connected to a reference voltage VR2. A control end of the control transistor TR2 receives the reference signal SR. A second end of the control transistor TR2 provides the control signal SG2. The capacitor C1 is electrically connected between the second end of the control transistor TR1 and a voltage terminal PVSS (or a voltage terminal PVDD). The capacitor C2 is electrically connected between the second end of the control transistor TR2 and the voltage terminal PVSS (or the voltage terminal PVDD).

[0111] In this embodiment, when the pixel circuit PX2 presents a first brightness range (such as a first brightness), the voltage value of the reference voltage VR1 is equal to a high voltage value. The voltage value of the reference voltage VR2 is equal to a low voltage value. When the pixel circuit PX2 presents a second brightness range (such as a second brightness), the voltage value of the reference voltage VR1 is equal to a low voltage value. The voltage value of the reference voltage VR2 is equal to a high voltage value.

[0112] In this embodiment, a first driving transistor TD1 receives the control signal SG1. A second driving transistor TD2 receives the control signal SG2. When the pixel circuit PX2 presents a first brightness range (such as a first brightness), the first driving transistor TD1 is turned on according to the control signal SG1 during a reset period. When the pixel circuit PX2 presents a second brightness range (such as a second brightness), the second driving transistor TD2 is turned on according to the control signal SG2 during the reset period.

[0113] In this embodiment, the control transistors TR1 and TR2 are respectively implemented by N-type transistors, for example, but the present disclosure is not limited thereto.

[0114] In this embodiment, the display device 200 further includes a logic circuit 220. The logic circuit 220 is electrically connected to the pixel circuit PX2. The logic circuit 220 generates a first scan signal SS1 and a second scan signal SS2 according to a scan enable signal EMS, a scan signal SS, and an inverted scan signal SSB. The inverted scan signal SSB may be a complementary signal of the scan signal SS. The scan signal SS and the inverted scan signal SSB may be generated by a gate driving circuit (such as, GOP), but are not limited thereto.

[0115] In this embodiment, the logic circuit 220 includes an AND logic gate GA and a NOR logic gate GN. The first input terminal of the AND logic gate GA receives a scan signal SS. The second input terminal of the AND logic gate GA receives a scan enable signal EMS. The AND logic gate GA performs an AND logic operation on the scan signal SS and the scan enable signal EMS to generate a first scan signal SS1. The output terminal of the AND logic gate GA outputs the first scan signal SS1. The first input terminal of the NOR logic gate GN receives an inverted scan signal SSB. The second input terminal of the NOR logic gate GN receives a scan enable signal EMS. The NOR logic gate GN2 performs a NOR logic operation on the inverted scan signal SSB and the scan enable signal EMS to generate a second scan signal SS2. The output terminal of the NOR logic gate GN outputs the second scan signal SS2. Please refer to Figure 1 and Figure 4 , in a modified embodiment of the pixel circuits PX1 and PX2, the scan transistors TS1 and TS2 can be replaced by a single scan transistor. The first end of the scan transistor receives a data signal SD. The second end of the scan transistor is electrically connected to the first end of a first driving transistor TD1 and the first end of a second driving transistor TD2. The control end of the scan transistor receives a scan signal SS. The control signals SG1 and SG2 can be provided by a control signal generation circuit 210.

[0116] In a modified embodiment of the pixel circuit PX1, the first driving transistor TD1 and the second driving transistor TD2 can be P-type LTPS TFTs. In the above-mentioned modified embodiment, the control signals SG1 and SG2 can be provided by a control signal generation circuit. Different from the control signal generation circuit 110 in the above-mentioned modified embodiment, the first end of the control transistor TR1 is electrically connected to a reference voltage VR1. The first end of the control transistor TR2 is electrically connected to a reference voltage VR2. A capacitor C2 is electrically connected between the second end of the control transistor TR2 and a voltage terminal PVDD. In a modified embodiment of the pixel circuit PX2, the first driving transistor TD1 and the second driving transistor TD2 can be N-type LTPS TFTs.

[0117] In this embodiment, the pixel circuit PX2 is applicable to a first brightness range L1 and a second brightness range L2 as shown in Figure 3 . The pixel circuit PX2 can be applicable to the above-mentioned full-screen driving mode.

[0118] Please refer to Figure 5 , Figure 5It is a schematic diagram of a pixel circuit shown according to an embodiment of the present disclosure. In this embodiment, the pixel circuit PX3 includes a first driving transistor TD1, a second driving transistor TD2, light-emitting control transistors TE1 to TE4, scanning transistors TS1 to TS4, and a light-emitting diode LE. In this embodiment, when the pixel circuit PX3 exhibits a first brightness (for example, the highest brightness of a first brightness range or any brightness), the light-emitting diode LE obtains a first current I1 through the first driving transistor TD1 and a third current I3 through the second driving transistor TD2. When the pixel circuit PX3 exhibits a second brightness (for example, any brightness of a second brightness range), the light-emitting diode LE obtains a fourth current I4 through the first driving transistor TD1 and a second current I2 through the second driving transistor TD2. The first brightness is higher than the second brightness. The current value of the first current I1 is higher than the current value of the second current I2.

[0119] In some embodiments, when the pixel circuit PX3 exhibits a first brightness, the first current I1 provided by the first driving transistor TD1 is higher than the third current I3 provided by the second driving transistor TD2. In some embodiments, when the pixel circuit PX3 exhibits a second brightness, the fourth current I4 provided by the first driving transistor TD1 is lower than the second current I2 provided by the second driving transistor TD2. For example, the fourth current I4 can be equal to 0.

[0120] It is worth mentioning here that the display device can use the first current I1 and the third current I3 to accurately control the gray-scale change of the first brightness range, and use the second current I2 and the fourth current I4 to accurately control the gray-scale change of the second brightness range. For a detailed description, reference can be made to Figure 6 the description, which will not be elaborated here.

[0121] In this embodiment, the first end of the light-emitting control transistor TE1 is electrically connected to the voltage terminal PVDD. The second end of the light-emitting control transistor TE1 is electrically connected to the first end of the first driving transistor TD1. The control end of the light-emitting control transistor TE1 electrically receives the light-emitting enable signal EM. The first end of the light-emitting control transistor TE2 is electrically connected to the voltage terminal PVDD. The second end of the light-emitting control transistor TE2 is electrically connected to the first end of the second driving transistor TD2. The control end of the light-emitting control transistor TE2 electrically receives the light-emitting enable signal EM.

[0122] The first terminal of the light-emission control transistor TE3 is electrically connected to the second terminal of the first driving transistor TD1. The second terminal of the light-emission control transistor TE3 is electrically connected to the first terminal of the light-emitting diode LE. The control terminal of the light-emission control transistor TE3 electrically receives the light-emission enabling signal EM. The first terminal of the light-emission control transistor TE4 is electrically connected to the second terminal of the second driving transistor TD2. The second terminal of the light-emission control transistor TE4 is electrically connected to the first terminal (e.g., anode) of the light-emitting diode LE. The control terminal of the light-emission control transistor TE4 electrically receives the light-emission enabling signal EM.

[0123] The second terminal (e.g., cathode) of the light-emitting diode LE is connected to the voltage terminal PVSS. The voltage value of the voltage terminal PVDD is higher than the voltage value of the voltage terminal PVSS.

[0124] The first terminal of the scan transistor TS1 receives the data signal SD1. The second terminal of the scan transistor TS1 is electrically connected to the first terminal of the first driving transistor TD1. The control terminal of the scan transistor TS1 receives the scan signal SS. The first terminal of the scan transistor TS2 receives the data signal SD2. The second terminal of the scan transistor TS2 is electrically connected to the first terminal of the second driving transistor TD2. The control terminal of the scan transistor TS2 receives the scan signal SS.

[0125] The first terminal of the scan transistor TS3 is electrically connected to the control terminal of the first driving transistor TD1. The second terminal of the scan transistor TS3 is electrically connected to the second terminal of the first driving transistor TD1. The control terminal of the scan transistor TS3 receives the scan signal SS. The first terminal of the scan transistor TS4 is electrically connected to the control terminal of the second driving transistor TD2. The second terminal of the scan transistor TS4 is electrically connected to the second terminal of the second driving transistor TD2. The control terminal of the scan transistor TS4 receives the scan signal SS.

[0126] In this embodiment, the light-emission control transistors TE1 to TE4 are respectively implemented by, for example, P-type transistors, but the present disclosure is not limited thereto. The scan transistors TS1 to TS4 are respectively implemented by, for example, N-type transistors, but the present disclosure is not limited thereto.

[0127] In this embodiment, the design of the first driving transistor TD1 is different from that of the second driving transistor TD2. Therefore, the current value of the first current I1 generated by the first driving transistor TD1 is higher than the current value of the second current I2 generated by the second driving transistor TD2. For example, the material of the semiconductor layer in the first driving transistor TD1 is different from that of the semiconductor layer in the second driving transistor TD2. In some embodiments, the first driving transistor TD1 is an LTPS TFT. The second driving transistor TD2 is an IGZO TFT. Taking this embodiment as an example, the first driving transistor TD1 may be a P-type LTPS TFT. The second driving transistor TD2 may be an N-type IGZO TFT, but the present disclosure is not limited thereto. In some embodiments, the purpose that the current value of the first current I1 is higher than the current value of the second current I2 can be achieved by doping the channel with different concentrations, having different channel width-to-length ratios, different connection methods of the lower gate, different biases of the lower gate, or a combination of the above methods. In some embodiments, the first driving transistor TD1 and the second driving transistor TD2 may be N-type transistors. In some embodiments, the first driving transistor TD1 and the second driving transistor TD2 may be P-type transistors.

[0128] In this embodiment, the first driving transistor TD1 receives the first data signal SD1 according to the scan signal SS and generates the first current I1 or the fourth current I4 according to the first data signal SD1. The second driving transistor TD2 receives the data signal SD2 according to the scan signal SS and generates the second current I2 or the third current I3 according to the data signal SD2.

[0129] In this embodiment, similar to Figure 1 the pixel circuit PX1 and Figure 4 the pixel circuit PX2, the control terminal of the first driving transistor TD1 receives the control signal SG1. The control terminal of the second driving transistor TD2 receives the control signal SG2. The pixel circuit PX3 includes a control signal generation circuit 310. The control signals SG1 and SG2 may be provided by the control signal generation circuit 310.

[0130] In this embodiment, the control signal generation circuit 310 generates control signals SG1 and SG2. The control signal generation circuit 310 includes control transistors TR1 and TR2, and capacitors C1 and C2. A first end of the control transistor TR1 is electrically connected to the reference voltage VR1. A control end of the control transistor TR1 receives the reference signal SR. A second end of the control transistor TR1 provides the control signal SG1. A first end of the control transistor TR2 is electrically connected to the reference voltage VR2. A control end of the control transistor TR2 receives the reference signal SR. A second end of the control transistor TR2 provides the control signal SG2. The capacitor C1 is electrically connected between the second end of the control transistor TR1 and the voltage terminal PVDD. The capacitor C2 is electrically connected between the second end of the control transistor TR2 and the voltage terminal PVSS.

[0131] In this embodiment, the voltage value of the reference voltage VR1 is a low voltage value. The voltage value of the reference voltage VR2 is a high voltage value. It should be noted that when the pixel circuit PX3 presents a first luminance (e.g., the highest luminance in the first luminance range or any luminance) and a second luminance (e.g., any luminance in the second luminance range), the first driving transistor TD1 is turned on according to the control signal SG1 during reset. When the pixel circuit PX3 presents the first luminance and the second luminance, the second driving transistor TD2 is turned on according to the control signal SG2 during reset.

[0132] In this embodiment, control ends of the scanning transistors TS1 to TS4 receive the same scanning signal SS. Therefore, during compensation, the scanning transistors TS1 to TS4 are turned on. The voltage value at the control end of the first driving transistor TD1 has the voltage value of the data signal SD1 and is compensated based on the threshold voltage value of the first driving transistor TD1. The voltage value at the control end of the second driving transistor TD2 has the voltage value of the data signal SD2 and is compensated based on the threshold voltage value of the second driving transistor TD2.

[0133] During light emission, the light emission control transistors TE1 to TE4 are turned on. Therefore, the first driving transistor TD1 generates a first current I1 or a fourth current I4 according to the first data signal SD1. The second driving transistor TD2 generates a second current I2 or a third current I3 according to the data signal SD2.

[0134] Please refer to [[ID= and ​ , ​It is a schematic diagram of the brightness range shown in an embodiment of the present disclosure. In this embodiment, the first brightness range L1 is different from the second brightness range L2. For example, the first brightness range L1 and the second brightness range L2 have non-overlapping brightness ranges. The first brightness B1 can be any brightness in the first brightness range L1, the second brightness B2 can be any brightness in the second brightness range L2, and the first brightness B1 is higher than the second brightness B2. In some embodiments, the first brightness B1 can be the maximum brightness of the display device 100, or rather, the first brightness B1 is the maximum brightness in the first brightness range L1, but not limited thereto. In this embodiment, the display device can be driven by the first driving transistor TD1 and the second driving transistor TD2 so that the pixel circuit PX3 can present the gray-scale change of the first brightness range L1. The display device can be driven by the first driving transistor TD1 and the second driving transistor TD2 so that the pixel circuit PX3 can present the gray-scale change of the second brightness range L2. This design can enable the pixel circuit PX3 to present more gray-scale changes and / or provide finer brightness changes.

[0135] For example, when the pixel circuit PX3 presents any brightness (such as the first brightness B1) in the first brightness range L1, the data signal SD1 has a voltage value corresponding to the first gray-scale value range of the first brightness range L1. The first gray-scale value range is, for example, from "0" to "255", but the present disclosure is not limited thereto. The data signal SD2 has a voltage value corresponding to the maximum gray-scale value of the gray-scale value range of the first brightness range L2 (such as the gray-scale value being "255") or other gray-scale values, but the present disclosure is not limited thereto.

[0136] For example, when the pixel circuit PX3 presents any brightness (such as the second brightness B2) in the second brightness range L2, the data signal SD1 has a voltage value corresponding to the minimum gray-scale value of the gray-scale value range of the second brightness range L2 (such as the gray-scale value being "0"), but the present disclosure is not limited thereto. The data signal SD2 has a voltage value corresponding to the second gray-scale value range of the second brightness range L2. The second gray-scale value range is, for example, from "0" to "255" or from "0" to "50", but the present disclosure is not limited thereto.

[0137] In a modified embodiment of the pixel circuit PX3, the first driving transistor TD1 and the second driving transistor TD2 can be P-type LTPS TFTs. In the above-mentioned modified embodiment, the control signals SG1 and SG2 can be provided by a control signal generation circuit. In the above-mentioned modified embodiment, different from the control signal generation circuit 310, the first end of the control transistor TR1 is electrically connected to the reference voltage VR. The first end of the control transistor TR2 is electrically connected to the reference voltage VR. The capacitor C2 is electrically connected between the second end of the control transistor TR2 and the voltage terminal PVDD.

[0138] In this embodiment, the pixel circuit PX3 can operate in an individual driving mode. In the individual driving mode, when one of the multiple pixel circuits PX3 presents a first brightness, another one of the multiple pixel circuits PX3 can present the first brightness, a second brightness, or other brightness levels.

[0139] In the above-described modified embodiment, the object that the current value of the first current I1 is higher than the current value of the second current I2 can be achieved by different channel doping concentrations in the semiconductor layer, different channel width-to-length ratios, different connection methods of the lower gate, different biases of the lower gate, or a combination of the above methods. For example, the doping concentration of the channel in the first driving transistor TD1 is higher than the doping concentration of the channel in the second driving transistor TD2. Another example is that the channel width-to-length ratio in the first driving transistor TD1 is higher than the channel width-to-length ratio in the second driving transistor TD2. Please refer to ​ , ​ is a schematic diagram of a pixel circuit shown according to an embodiment of the present disclosure. In this embodiment, the pixel circuit PX4 includes a first driving transistor TD1, a second driving transistor TD2, light-emitting control transistors TE1 to TE4, scanning transistors TS1 to TS4, and a light-emitting diode LE. In this embodiment, when the pixel circuit PX4 presents a first brightness (for example, the highest brightness or any brightness in the first brightness range), the light-emitting diode LE obtains a first current I1 through the first driving transistor TD1 and obtains a third current I3 through the second driving transistor TD2. When the pixel circuit PX4 presents a second brightness (for example, any brightness in the second brightness range), the light-emitting diode LE obtains a fourth current I4 through the first driving transistor TD1 and obtains a second current I2 through the second driving transistor TD2. The first brightness is higher than the second brightness. The current value of the first current I1 is higher than the current value of the second current I2.

[0140] In some embodiments, when the pixel circuit PX3 presents a first brightness, the first current I2 provided by the first driving transistor TD1 is higher than the third current I3 provided by the second driving transistor TD2. In some embodiments, when the pixel circuit PX4 presents a second brightness, the fourth current I4 provided by the first driving transistor TD1 is lower than the second current I2 provided by the second driving transistor TD2. For example, the fourth current I4 can be equal to 0.

[0141] In this embodiment, the first end of the light-emitting control transistor TE1 is electrically connected to the voltage terminal PVSS. The second end of the light-emitting control transistor TE1 is electrically connected to the first end of the first driving transistor TD1. The control end of the light-emitting control transistor TE1 electrically receives the light-emitting enable signal EM. The first end of the light-emitting control transistor TE2 is electrically connected to the voltage terminal PVSS. The second end of the light-emitting control transistor TE2 is electrically connected to the first end of the second driving transistor TD2. The control end of the light-emitting control transistor TE2 electrically receives the light-emitting enable signal EM.

[0142] The first end of the light-emitting control transistor TE3 is electrically connected to the second end of the first driving transistor TD1. The second end of the light-emitting control transistor TE3 is electrically connected to the first end of the light-emitting diode LE. The control end of the light-emitting control transistor TE3 electrically receives the light-emitting enable signal EM. The first end of the light-emitting control transistor TE4 is electrically connected to the second end of the second driving transistor TD2. The second end of the light-emitting control transistor TE4 is electrically connected to the first end of the light-emitting diode LE. The control end of the light-emitting control transistor TE4 electrically receives the light-emitting enable signal EM.

[0143] The second end of the light-emitting diode LE is connected to the voltage terminal PVDD. The voltage value of the voltage terminal PVDD is higher than the voltage value of the voltage terminal PVSS.

[0144] The first end of the scanning transistor TS1 receives the data signal SD1. The second end of the scanning transistor TS1 is electrically connected to the first end of the first driving transistor TD1. The control end of the scanning transistor TS1 receives the scanning signal SS. The first end of the scanning transistor TS2 receives the data signal SD2. The second end of the scanning transistor TS2 is electrically connected to the first end of the second driving transistor TD2. The control end of the scanning transistor TS2 receives the scanning signal SS.

[0145] The first end of the scanning transistor TS3 is electrically connected to the control end of the first driving transistor TD1. The second end of the scanning transistor TS3 is electrically connected to the second end of the first driving transistor TD1. The control end of the scanning transistor TS3 receives the scanning signal SS. The first end of the scanning transistor TS4 is electrically connected to the control end of the second driving transistor TD2. The second end of the scanning transistor TS4 is electrically connected to the second end of the second driving transistor TD2. The control end of the scanning transistor TS4 receives the scanning signal SS.

[0146] In this embodiment, the light-emitting control transistors TE1 to TE4 and the scanning transistors TS1 to TS4 are respectively implemented by N-type transistors, for example, but the present disclosure is not limited thereto.

[0147] In this embodiment, the design of the first driving transistor TD1 is different from that of the second driving transistor TD2. Therefore, the current value of the first current I1 generated by the first driving transistor TD1 is higher than the current value of the second current I2 generated by the second driving transistor TD2. For example, the material of the semiconductor layer in the first driving transistor TD1 is different from that of the semiconductor layer in the second driving transistor TD2. Taking this embodiment as an example, the first driving transistor TD1 can be an N-type LTPS TFT. The second driving transistor TD2 can be an N-type IGZO TFT, but the present disclosure is not limited thereto.

[0148] In this embodiment, similar to ​ the pixel circuit PX1 and ​ the pixel circuit PX2, the control terminal of the first driving transistor TD1 receives the control signal SG1. The control terminal of the second driving transistor TD2 receives the control signal SG2. The pixel circuit PX4 includes a control signal generation circuit 410. The control signals SG1 and SG2 can be provided by the control signal generation circuit 410.

[0149] In this embodiment, the control signal generation circuit 410 generates the control signals SG1 and SG2. The control signal generation circuit 410 includes control transistors TR1 and TR2 and capacitors C1 and C2. The first terminal of the control transistor TR1 is electrically connected to the reference voltage VR. The control terminal of the control transistor TR1 receives the reference signal SR. The second terminal of the control transistor TR1 provides the control signal SG1. The first terminal of the control transistor TR2 is electrically connected to the reference voltage VR. The control terminal of the control transistor TR2 receives the reference signal SR. The second terminal of the control transistor TR2 provides the control signal SG2. The capacitor C1 is electrically connected between the second terminal of the control transistor TR1 and the voltage terminal PVSS (or the voltage terminal PVDD). The capacitor C2 is electrically connected between the second terminal of the control transistor TR2 and the voltage terminal PVSS (or the voltage terminal PVDD).

[0150] In this embodiment, the voltage value of the reference voltage VR is a high voltage value. It should be noted that when the pixel circuit PX4 presents a first brightness (e.g., the highest brightness in the first brightness range or any brightness) and a second brightness (e.g., any brightness in the second brightness range), the first driving transistor TD1 is turned on according to the control signal SG1 during the reset period. When the pixel circuit PX4 presents the first brightness and the second brightness, the second driving transistor TD2 is turned on according to the control signal SG2 during the reset period.

[0151] In this embodiment, the control terminals of the scanning transistors TS1 to TS4 receive the same scanning signal SS. Therefore, during the compensation period, the scanning transistors TS1 to TS4 are turned on. The voltage value at the control terminal of the first driving transistor TD1 has the voltage value of the data signal SD1 and is compensated based on the threshold voltage value of the first driving transistor TD1. The voltage value at the control terminal of the second driving transistor TD2 has the voltage value of the data signal SD2 and is compensated based on the threshold voltage value of the second driving transistor TD2.

[0152] During the light emission period, the light emission control transistors TE1 to TE4 are turned on. Therefore, the first driving transistor TD1 generates the first current I1 or the fourth current I4 according to the first data signal SD1. The second driving transistor TD2 generates the second current I2 or the third current I3 according to the data signal SD2.

[0153] The first data signal SD1 and the data signal SD2 when presenting the first brightness range or the second brightness range have been illustrated in the ​ embodiment, so they will not be restated here. In this embodiment, the pixel circuit PX4 is applicable to the first brightness range L1 and the second brightness range L2 as shown in ​ . The pixel circuit PX4 can be applicable to the above individual driving modes.

[0154] In a modified embodiment of the pixel circuit PX4, the first driving transistor TD1 and the second driving transistor TD2 can be N-type LTPS TFTs.

[0155] Please refer to ​ , ​ which is a schematic diagram of a pixel circuit shown according to an embodiment of the present disclosure. In this embodiment, the pixel circuit PX5 includes a first driving transistor TD1, a second driving transistor TD2, light emission control transistors TE1 to TE3, scanning transistors TS1 to TS3, and a light emitting diode LE. In this embodiment, when the pixel circuit PX5 presents the first brightness (for example, the highest brightness of the first brightness range), the light emitting diode LE obtains the first current I1 through the first driving transistor TD1 and obtains the second current I2 through the second driving transistor TD2. When the pixel circuit PX5 presents the second brightness (for example, any brightness of the second brightness range), the light emitting diode LE obtains the second current I2 through the second driving transistor TD2. The first brightness is higher than the second brightness. The current value of the first current I1 is higher than the current value of the second current I2.

[0156] In this embodiment, the first end of the light-emitting control transistor TE1 is electrically connected to the voltage terminal PVDD. The second end of the light-emitting control transistor TE1 is electrically connected to the first end of the first driving transistor TD1. The control end of the light-emitting control transistor TE1 electrically receives the light-emitting enable signal EM. The first end of the light-emitting control transistor TE2 is electrically connected to the second end of the first driving transistor TD1. The second end of the light-emitting control transistor TE2 is electrically connected to the first end of the light-emitting diode LE. The control end of the light-emitting control transistor TE2 electrically receives the light-emitting enable signal EM. The first end of the light-emitting control transistor TE3 is electrically connected to the second end of the second driving transistor TD2. The second end of the light-emitting control transistor TE3 is electrically connected to the first end of the light-emitting diode LE. The control end of the light-emitting control transistor TE3 electrically receives the light-emitting enable signal EM.

[0157] The second end of the light-emitting diode LE is connected to the voltage terminal PVSS. The voltage value of the voltage terminal PVDD is higher than the voltage value of the voltage terminal PVSS.

[0158] The first end of the scanning transistor TS1 receives the data signal SD. The second end of the scanning transistor TS1 is electrically connected to the first end of the first driving transistor TD1 and the first end of the second driving transistor TD2. The control end of the scanning transistor TS1 receives the scanning signal SS. The first end of the scanning transistor TS2 is electrically connected to the control end of the first driving transistor TD1. The second end of the scanning transistor TS2 is electrically connected to the second end of the first driving transistor TD1. The control end of the scanning transistor TS2 receives the scanning signal SS. The first end of the scanning transistor TS3 is electrically connected to the control end of the second driving transistor TD2. The second end of the scanning transistor TS3 is electrically connected to the second end of the second driving transistor TD2. The control end of the scanning transistor TS3 receives the scanning signal SS.

[0159] In this embodiment, the light-emitting control transistors TE1 to TE3 are respectively implemented by, for example, P-type transistors, but the present disclosure is not limited thereto. The scanning transistors TS1 to TS3 are respectively implemented by, for example, N-type transistors, but the present disclosure is not limited thereto.

[0160] In this embodiment, the design of the first driving transistor TD1 is different from that of the second driving transistor TD2. Therefore, the current value of the first current I1 generated by the first driving transistor TD1 is higher than the current value of the second current I2 generated by the second driving transistor TD2. For example, the material of the semiconductor layer in the first driving transistor TD1 is different from that of the semiconductor layer in the second driving transistor TD2. In some embodiments, the first driving transistor TD1 is an LTPS TFT. The second driving transistor TD2 is an IGZO TFT. Taking this embodiment as an example, the first driving transistor TD1 can be a P-type LTPS TFT. The second driving transistor TD2 can be an N-type IGZO TFT, but the present disclosure is not limited thereto. In some embodiments, the purpose that the current value of the first current I1 is higher than the current value of the second current I2 can be achieved by doping the channel with different concentrations, having different channel width-to-length ratios, different connection methods of the lower gate, different biases of the lower gate, or a combination of the above methods.

[0161] In this embodiment, the first driving transistor TD1 receives the data signal SD according to the scan signal SS and generates the first current I1 according to the data signal SD. The second driving transistor TD2 receives the data signal SD according to the scan signal SS and generates the second current I2 according to the data signal SD.

[0162] In this embodiment, the control terminal of the first driving transistor TD1 receives the control signal SG1. The control terminal of the second driving transistor TD2 receives the control signal SG2. For example, the control signals SG1 and SG2 can be provided by ​ the control signal generation circuit 110 in

[0163] Please refer to ​ and ​ , ​It is the signal timing diagram TP3 shown according to an embodiment of the present disclosure. In this embodiment, a frame time can be divided into a first sub-frame time SF1 and a second sub-frame time SF2, but it is not limited thereto. In the first sub-frame time SF1, the first driving transistor TD1 is turned on. The light-emitting diode LE can provide light in a first brightness range using the first current I1. In the second sub-frame time SF2, the second driving transistor TD2 is turned on. The light-emitting diode LE can provide light in a second brightness range using the second current I2. The first brightness range is greater than the second brightness range. For example, the first sub-frame time SF1 and the second sub-frame time SF2 each include a reset period TPR, a scan period TPS, and a light-emitting period TPE. The reference signal SR is at a high voltage value during the reset period TPR and at a low voltage value during the scan period TPS and the light-emitting period TPE. The scan signal SS is at a high voltage value during the scan period TPS and at a low voltage value during the reset period TPR and the light-emitting period TPE. The light-emission enabling signal EM is at a high voltage value during the reset period TPR and the scan period TPS and at a low voltage value during the light-emitting period TPE.

[0164] In this embodiment, in the first sub-frame time SF1, the voltage values of the reference voltage VR are all high voltage values, so that the first driving transistor TD1 can be turned on, and during the light-emitting period TPE, a first current I1 is generated according to the voltage value at the control terminal of the first transistor TD1. In the second sub-frame time SF2, the voltage values of the reference voltage VR are all low voltage values, so that the second driving transistor TD2 can be turned on, and during the light-emitting period TPE, a second current I2 is generated according to the voltage value at the control terminal of the second transistor TD2. In this embodiment, the first driving transistor TD1 and the second driving transistor TD2 are not turned on simultaneously. That is to say, when the first driving transistor TD1 is turned on, the second driving transistor TD2 is turned off. When the second driving transistor TD2 is turned on, the first driving transistor TD1 is turned off. The data signal SD when the first driving transistor TD1 is turned on can be the same as or different from the data signal SD when the second driving transistor TD2 is turned on.

[0165] In this embodiment, the pixel circuit PX5 can meet the usage requirements for high resolution.

[0166] In a modified embodiment of the pixel circuit PX5, the first driving transistor TD1 and the second driving transistor TD2 may be P-type LTPS TFTs. In the above-mentioned modified embodiment, the control signals SG1 and SG2 may be provided by a control signal generation circuit. In the above-mentioned modified embodiment, different from the control signal generation circuit 110, the first end of the control transistor TR1 is electrically connected to the reference voltage VR1. The first end of the control transistor TR2 is electrically connected to the reference voltage VR2. The capacitor C2 is electrically connected between the second end of the control transistor TR2 and the voltage terminal PVDD.

[0167] In this embodiment, the pixel circuit PX5 is applicable to ​ the first brightness range L1 and the second brightness range L2 as shown. The pixel circuit PX5 can be applicable to the above-mentioned individual driving modes.

[0168] Please refer to ​ , ​ which is a schematic diagram of a pixel circuit shown according to an embodiment of the present disclosure. In this embodiment, the pixel circuit PX6 includes a first driving transistor TD1, a second driving transistor TD2, light-emitting control transistors TE1 to TE3, scanning transistors TS1 to TS3, and a light-emitting diode LE. In this embodiment, when the pixel circuit PX6 presents a first brightness (for example, the highest brightness of the first brightness range), the light-emitting diode LE obtains a first current I1 through the first driving transistor TD1 and obtains a second current I2 through the second driving transistor TD2. When the pixel circuit PX3 presents a second brightness (for example, any brightness of the second brightness range), the light-emitting diode LE obtains the second current I2 through the second driving transistor TD2. The first brightness is higher than the second brightness. The current value of the first current I1 is higher than the current value of the second current I2.

[0169] In this embodiment, the first end of the light-emitting control transistor TE1 is electrically connected to the voltage terminal PVSS. The second end of the light-emitting control transistor TE1 is electrically connected to the first end of the first driving transistor TD1. The control end of the light-emitting control transistor TE1 electrically receives the light-emitting enable signal EM. The first end of the light-emitting control transistor TE2 is electrically connected to the second end of the first driving transistor TD1. The second end of the light-emitting control transistor TE2 is electrically connected to the first end of the light-emitting diode LE. The control end of the light-emitting control transistor TE2 electrically receives the light-emitting enable signal EM. The first end of the light-emitting control transistor TE3 is electrically connected to the second end of the second driving transistor TD2. The second end of the light-emitting control transistor TE3 is electrically connected to the first end of the light-emitting diode LE. The control end of the light-emitting control transistor TE3 electrically receives the light-emitting enable signal EM.

[0170] The second terminal of the light-emitting diode LE is connected to the voltage terminal PVDD. The voltage value of the voltage terminal PVDD is higher than the voltage value of the voltage terminal PVSS.

[0171] The first terminal of the scanning transistor TS1 receives the data signal SD. The second terminal of the scanning transistor TS1 is electrically connected to the first terminal of the first driving transistor TD1 and the first terminal of the second driving transistor TD2. The control terminal of the scanning transistor TS1 receives the scanning signal SS. The first terminal of the scanning transistor TS2 is electrically connected to the control terminal of the first driving transistor TD1. The second terminal of the scanning transistor TS2 is electrically connected to the second terminal of the first driving transistor TD1. The control terminal of the scanning transistor TS2 receives the scanning signal SS. The first terminal of the scanning transistor TS3 is electrically connected to the control terminal of the second driving transistor TD2. The second terminal of the scanning transistor TS3 is electrically connected to the second terminal of the second driving transistor TD2. The control terminal of the scanning transistor TS3 receives the scanning signal SS.

[0172] In this embodiment, the light-emitting control transistors TE1 to TE3 and the scanning transistors TS1 to TS3 are respectively implemented by, for example, N-type transistors, but the present disclosure is not limited thereto.

[0173] In this embodiment, the material of the semiconductor layer in the first driving transistor TD1 is different from the material of the semiconductor layer in the second driving transistor TD2. In some embodiments, the first driving transistor TD1 is an LTPS TFT. The second driving transistor TD2 is an IGZO TFT. Taking this embodiment as an example, the first driving transistor TD1 can be an N-type LTPS TFT. The second driving transistor TD2 can be an N-type IGZO TFT, but the present disclosure is not limited thereto. In some embodiments, the difference in the semiconductor materials of the first driving transistor TD1 and the second driving transistor TD2 can be combined with different channel doping concentrations in the semiconductor layer, different channel width-to-length ratios, different connection methods of the lower gate, different biases of the lower gate, or the above methods to achieve the purpose that the current value of the first current I1 is higher than the current value of the second current I2.

[0174] In this embodiment, the first driving transistor TD1 receives the data signal SD according to the scanning signal SS and generates a first current I1 according to the data signal SD. The second driving transistor TD2 receives the data signal SD according to the scanning signal SS and generates a second current I2 according to the data signal SD.

[0175] In this embodiment, the control terminal of the first driving transistor TD1 receives the control signal SG1. The control terminal of the second driving transistor TD2 receives the control signal SG2. The control signals SG1 and SG2 can be provided by ​ the control signal generation circuit 210 therein.

[0176] In this embodiment, the first driving transistor TD1 and the second driving transistor TD2 of the pixel circuit PX6 are not turned on simultaneously. When the first driving transistor TD1 is turned on, the second driving transistor TD2 is turned off. When the second driving transistor TD2 is turned on, the first driving transistor TD1 is turned off. The data signal SD when the first driving transistor TD1 is turned on may be the same as or different from the data signal SD when the second driving transistor TD2 is turned on.

[0177] In this embodiment, the pixel circuit PX6 can meet the usage requirements for high resolution.

[0178] In a modified embodiment of the pixel circuit PX6, the first driving transistor TD1 and the second driving transistor TD2 can be N-type LTPS TFTs.

[0179] In this embodiment, the pixel circuit PX6 is applicable to ​ the first brightness range L1 and the second brightness range L2 as shown. The pixel circuit PX6 can be applicable to the above-mentioned individual driving modes.

[0180] Please refer to ​ , ​ FIG. is a schematic diagram of a pixel circuit of a display device according to an embodiment of the present disclosure. In this embodiment, the display device 300 includes at least one pixel circuit PX7. The pixel circuit PX7 includes a first driving transistor TD1, a second driving transistor TD2, a first light-emitting diode LE1, and a second light-emitting diode LE2. The first driving transistor TD1 is electrically connected to the voltage terminal PVDD. The second driving transistor TD2 is electrically connected to the voltage terminal PVDD. The first light-emitting diode LE1 has a first end and a second end. The first end of the first light-emitting diode LE1 is electrically connected to the first driving transistor TD1. The second end of the first light-emitting diode LE1 is electrically connected to the voltage terminal PVSS. The second light-emitting diode LE2 has a first end and a second end. The first end of the second light-emitting diode LE2 is electrically connected to the second driving transistor TD2. The second end of the second light-emitting diode LE2 is electrically connected to the second voltage terminal PVSS.

[0181] When the pixel circuit PX7 presents a first brightness (for example, the highest brightness or any brightness in the first brightness range), the first light-emitting diode LE1 obtains a first current I1 through the first driving transistor TD1. When the pixel circuit PX7 presents a second brightness (for example, any brightness in the second brightness range), the second light-emitting diode LE2 obtains a second current I2 through the second driving transistor TD2. The first brightness is higher than the second brightness. The current value of the first current I1 is higher than the current value of the second current I2.

[0182] In this embodiment, the first light-emitting diode LE1 can use the first current I1 to provide light within a first brightness range. The second light-emitting diode LE2 can use the second current I2 to provide light within a second brightness range.

[0183] It is worth mentioning here that the pixel circuit PX7 is applicable to the first brightness range L1 and the second brightness range L2 as shown in ​ However, this is not limiting. Therefore, the display device 300 can use the first current I1 to accurately control the grayscale change within the first brightness range and use the second current I2 to accurately control the grayscale change within the second brightness range. In some embodiments, the pixel circuit PX7 can be applicable to the first brightness range L1 and the second brightness range L2 as shown in ​ However, this is not limiting.

[0184] In this embodiment, the first end of the first driving transistor TD1 is electrically connected to the voltage terminal PVDD. The second end of the first driving transistor TD1 is electrically connected to the first end of the light-emitting diode LE1. The control terminal of the first driving transistor TD1 receives the control signal SG1. The first end of the second driving transistor TD2 is electrically connected to the voltage terminal PVDD. The second end of the second driving transistor TD2 is electrically connected to the first end of the light-emitting diode LE2. The control terminal of the second driving transistor TD2 receives the control signal SG2.

[0185] The control terminal of the first driving transistor TD1 receives the control signal SG1. The control terminal of the second driving transistor TD2 receives the control signal SG2. The control signals SG1 and SG2 can be provided by ​ the control signal generation circuit 110 in

[0186] In this embodiment, the design of the first driving transistor TD1 is different from that of the second driving transistor TD2. Therefore, the current value of the first current I1 generated by the first driving transistor TD1 is higher than the current value of the second current I2 generated by the second driving transistor TD2. For example, the material of the semiconductor layer in the first driving transistor TD1 is different from the material of the semiconductor layer in the second driving transistor TD2. In some embodiments, the first driving transistor TD1 is an LTPS TFT. The second driving transistor TD2 is an IGZO TFT. Taking this embodiment as an example, the first driving transistor TD1 can be a P-type LTPS TFT. The second driving transistor TD2 can be an N-type IGZO TFT, but the present disclosure is not limited thereto. In some embodiments, the purpose of the current value of the first current I1 being higher than the current value of the second current I2 can be achieved by doping the channel with different concentrations, having different channel width-to-length ratios, different connection methods of the lower gate, different biases of the lower gate, or a combination of the above methods. Taking this embodiment as an example, the pixel circuit PX7 further includes light-emitting control transistors TE1 to TE3 and scanning transistors TS1 to TS3. The first end of the light-emitting control transistor TE1 is electrically connected to the voltage terminal PVDD. The second end of the light-emitting control transistor TE1 is electrically connected to the first end of the first driving transistor TD1. The control end of the light-emitting control transistor TE1 electrically receives the light-emitting enable signal EM. The first end of the light-emitting control transistor TE2 is electrically connected to the second end of the first driving transistor TD1. The second end of the light-emitting control transistor TE2 is electrically connected to the first end of the light-emitting diode LE1. The control end of the light-emitting control transistor TE2 electrically receives the light-emitting enable signal EM. The first end of the light-emitting control transistor TE3 is electrically connected to the second end of the second driving transistor TD2. The second end of the light-emitting control transistor TE3 is electrically connected to the first end of the light-emitting diode LE2. The control end of the light-emitting control transistor TE3 electrically receives the light-emitting enable signal EM.

[0187] The first end of the scanning transistor TS1 receives the data signal SD. The second end of the scanning transistor TS1 is electrically connected to the first ends of the first driving transistor TD1 and the second driving transistor TD2. The control end of the scanning transistor TS1 receives the scanning signal SS. The first end of the scanning transistor TS2 is electrically connected to the control end of the first driving transistor TD1. The second end of the scanning transistor TS2 is electrically connected to the second end of the first driving transistor TD1. The control end of the scanning transistor TS2 receives the scanning signal SS. The first end of the scanning transistor TS3 is electrically connected to the control end of the second driving transistor TD2. The second end of the scanning transistor TS3 is electrically connected to the second end of the second driving transistor TD2. The control end of the scanning transistor TS3 receives the scanning signal SS.

[0188] In this embodiment, the first light-emitting diode LE1 has an external quantum efficiency (EQE) characteristic EQE1. The second light-emitting diode LE2 has an external quantum efficiency (EQE) characteristic EQE2. Based on the EQE characteristic EQE1 and the EQE characteristic EQE2, the second current density required for the second light-emitting diode LE2 to reach the optimal EQE is lower than the first current density required for the first light-emitting diode LE1 to reach the optimal EQE. A low current density is suitable for presenting low gray levels or low brightness. A high current density is suitable for presenting high gray levels or high brightness. Therefore, the second light-emitting diode LE2 is suitable for presenting gray level variations in a low brightness range (i.e., the second brightness range). The first light-emitting diode LE1 is suitable for presenting high brightness (i.e., the first brightness range).

[0189] Generally, the peak optical wavelength of the first light-emitting diode LE1 and the peak optical wavelength of the second light-emitting diode LE2 decrease with the current density. In this embodiment, the first light-emitting diode LE1 is designed to present a first brightness range (e.g., gray level values from "128" to "255") based on the first current density. The second light-emitting diode LE2 is designed to present a second brightness range (e.g., gray level values from "0" to "127") based on the second current density. The first current density and the second current density are limited. Therefore, the offset amounts of the peak optical wavelength of the first light-emitting diode LE1 and the peak optical wavelength of the second light-emitting diode LE2 can be reduced.

[0190] In this embodiment, the pixel circuit PX7 can be applied to the above individual driving mode or full-screen driving mode.

[0191] Please refer to ​ and ​ , ​It is a schematic diagram of a driving transistor shown according to an embodiment of the present disclosure. The driving transistor of the present disclosure can be, for example, a single-gate transistor or a dual-gate transistor. The single gate can be, for example, a top gate or a bottom gate. This embodiment shows that the driving transistors TD-1, TD-2, and TD-3 are dual-gate transistors. Among them, the bottom gates of the driving transistors TD-1, TD-2, and TD-3 have different connection methods. The driving transistors TD-1, TD-2, and TD-3 respectively have a source S (i.e., the first end), a top gate TG (i.e., the control end), a bottom gate BG, and a drain D (i.e., the second end). The bottom gate BG of the driving transistor TD-1 is electrically connected to the top gate TG of the driving transistor TD-1. The bottom gate BG of the driving transistor TD-2 is electrically connected to the source S of the driving transistor TD-2. The current generated by the driving transistor TD-1 is greater than the current generated by the driving transistor TD-2. The current generated by the driving transistor TD-1 is greater than the current generated by a single-gate driving transistor (such as ​ the driving transistor TD1 or the driving transistor TD2). The current generated by the single-gate driving transistor is greater than the current generated by the driving transistor TD-2. In this embodiment, the driving transistors TD-1 and TD-2 are both taken as P-type TFTs as an example, but the relationship of the current magnitudes generated by the above different driving transistors is not limited to the same or different types of TFTs. Therefore, in order to make the first current I1 generated by the first driving transistor TD1 greater than the second current I2 generated by the second driving transistor TD2, there can be the following implementation manners. For example, the first driving transistor TD1 and the second driving transistor TD2 are respectively implemented by the driving transistor TD-1 and a single-gate transistor. For example, the first driving transistor TD1 and the second driving transistor TD2 are respectively implemented by the driving transistor TD-1 and the driving transistor TD-2. For example, the first driving transistor TD1 and the second driving transistor TD2 are respectively implemented by a single-gate transistor and the driving transistor TD-2.

[0192] In this embodiment, the bottom gate BG of the driving transistor TD-3 is electrically connected to a DC voltage source VDC. Taking the driving transistor TD-3 as an N-type TFT as an example, the lower the bias voltage value of the DC voltage source VDC, the lower the current generated by the driving transistor TD-3. Taking the driving transistor TD-3 as a P-type TFT as an example, the higher the bias voltage value of the DC voltage source VDC, the lower the current generated by the driving transistor TD-3. Therefore, when the first driving transistor TD1 and the second driving transistor TD2 are both implemented by the driving transistor TD-3, the bias voltage of the bottom gate of the first driving transistor TD1 can be different from the bias voltage of the bottom gate of the second driving transistor TD21. For example, when the first driving transistor TD1 and the second driving transistor TD2 are both P-type TFTs, the bias voltage value of the DC voltage source VDC provided to the bottom gate of the first driving transistor TD1 is lower than the bias voltage value of the DC voltage source VDC provided to the bottom gate of the second driving transistor TD2. Another example is that when the first driving transistor TD1 and the second driving transistor TD2 are both N-type TFTs, the bias voltage value of the DC voltage source VDC provided to the bottom gate of the first driving transistor TD1 is higher than the bias voltage value of the DC voltage source VDC provided to the bottom gate of the second driving transistor TD2.

[0193] Based on the above, the bias voltage of the bottom gate of the first driving transistor TD1 and the bias voltage of the bottom gate of the second driving transistor TD2 can be adjusted so that the first current I1 is greater than the second current I2.

[0194] In summary, when the pixel circuit presents the first brightness, the pixel circuit operates based on the first current. When the pixel circuit presents the second brightness, the pixel circuit operates based on the second current. The first brightness is higher than the second brightness. The current value of the first current is higher than the current value of the second current. In this way, the display device can accurately control the gray-scale changes in different brightness ranges.

[0195] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, and are not intended to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A display device, characterized in that, The display device includes: At least one pixel circuit, each including: A first driving transistor electrically connected to a first voltage terminal; A second driving transistor electrically connected to the first voltage terminal; and A light-emitting diode having a first end and a second end, the first end being electrically connected to the first driving transistor and the second driving transistor, and the second end being electrically connected to a second voltage terminal, wherein, when the at least one pixel circuit presents a first brightness, the light-emitting diode obtains a first current through the first driving transistor, and when the at least one pixel circuit presents a second brightness, the light-emitting diode obtains a second current through the second driving transistor, the first brightness is higher than the second brightness, and the current value of the first current is higher than the current value of the second current.

2. The display device according to claim 1, wherein The material of the semiconductor layer in the first driving transistor is different from the material of the semiconductor layer in the second driving transistor.

3. The display device according to claim 1, wherein The channel width-to-length ratio in the first driving transistor is higher than the channel width-to-length ratio in the second driving transistor.

4. The display device according to claim 1, wherein: When the at least one pixel circuit presents the first brightness, the first driving transistor receives a data signal according to a first scan signal and generates the first current according to the data signal, and When the at least one pixel circuit presents the second brightness, the second driving transistor receives the data signal according to a second scan signal and generates the second current according to the data signal.

5. The display device according to claim 4, wherein The display device further includes: A logic circuit electrically connected to the at least one pixel circuit and configured to generate the first scan signal and the second scan signal according to a scan enable signal, a scan signal, and an inverted scan signal.

6. The display device according to claim 1, characterized in that, When the at least one pixel circuit presents a first brightness, the light-emitting diode obtains a third current through the second driving transistor.

7. The display device according to claim 1, wherein: When the at least one pixel circuit presents the first brightness, the first driving transistor is turned on according to a first control signal during a reset period, and When the at least one pixel circuit presents the second brightness, the second driving transistor is turned on according to a second control signal during the reset period.

8. The display device according to claim 7, characterized in that Each of the at least one pixel circuits further includes: A control signal generation circuit configured to generate the first control signal and the second control signal according to a reference signal and at least one reference voltage.

9. The display device according to claim 1, wherein: The first driving transistor has a first lower gate terminal, The second driving transistor has a second lower gate terminal, and The bias voltage at the first lower gate terminal is different from the bias voltage at the second lower gate terminal.

10. A display device, characterized in that, The display device includes: At least one pixel circuit, each including: A first driving transistor electrically connected to a first voltage terminal; A second driving transistor electrically connected to the first voltage terminal; and A first light-emitting diode having a first end and a second end, the first end of the first light-emitting diode being electrically connected to the first driving transistor, and the second end of the first light-emitting diode being electrically connected to a second voltage terminal; and A second light-emitting diode having a first end and a second end, the first end of the second light-emitting diode being electrically connected to the second driving transistor, and the second end of the second light-emitting diode being electrically connected to the second voltage terminal, wherein when the at least one pixel circuit exhibits a first brightness, the first light-emitting diode obtains a first current through the first driving transistor, and when the at least one pixel circuit exhibits a second brightness, the second light-emitting diode obtains a second current through the second driving transistor, the first brightness being higher than the second brightness, and the current value of the first current being higher than the current value of the second current.

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