Display device and driving method thereof

Abstract

There is provided a display device including: a display panel including a plurality of sub-pixels connected to a high potential voltage line and a plurality of low potential voltage lines; a driver configured to drive the display panel; and a circuit configured to sense and compensate a characteristic of a sub-pixel selected from the plurality of sub-pixels through the plurality of low potential voltage lines.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2024-0015256, filed on Jan. 31, 2024, which is incorporated herein by reference in its entirety as if fully set forth herein. Technical Field

[0002] The present disclosure relates to a display device and a driving method thereof. Background Art

[0003] With the development of information technology, the market for display devices as a connection medium between users and information has grown. Accordingly, display devices such as light-emitting display (LED) devices, quantum dot displays (QDDs), and liquid crystal displays (LCDs) are increasingly used.

[0004] Each of the above display devices includes a display panel having sub-pixels, a driver configured to output a driving signal for driving the display panel, and a power supply configured to generate power supplied to the display panel or the driver.

[0005] In such a display device, when a driving signal (e.g., a scan signal and a data signal) is provided to the sub-pixels formed in the display panel, one of the selected sub-pixels in the sub-pixels may transmit light or emit light directly to display an image. Summary of the Invention

[0006] Accordingly, the present disclosure relates to a display device and a driving method thereof that substantially eliminate one or more problems caused by limitations and disadvantages of the related art.

[0007] The present disclosure improves display quality and lifespan by sensing elements included in sub-pixels via a low-potential voltage line, determining whether characteristics (threshold voltage, current mobility, etc.) of the elements have changed, and compensating the sub-pixels according to the degree of change in the characteristics. In addition, the present disclosure improves sensing accuracy and sensing reliability of the elements included in the sub-pixels.

[0008] Additional advantages, objects, and features of the present disclosure will be partly set forth in the description below, and partly will become apparent to those of ordinary skill in the art upon examination of the following, or may be learned from practice of the present disclosure. The objects and other advantages of the present disclosure may be realized and attained by the structure particularly pointed out in the written description and claims as well as the drawings.

[0009] To achieve these objects and other advantages and in accordance with the purpose of the present disclosure, as embodied and broadly described herein, a display device includes: a display panel including a plurality of sub-pixels connected to a high-potential voltage line and a plurality of low-potential voltage lines; a driver configured to drive the display panel; and a circuit configured to sense and compensate for characteristics of a sub-pixel selected from the plurality of sub-pixels through the plurality of low-potential voltage lines.

[0010] The plurality of low-potential voltage lines may be parallel to data lines on the display panel and may be spaced apart.

[0011] The display panel may include a plurality of switches, each switch electrically connecting two adjacent low-potential voltage lines among the plurality of low-potential voltage lines.

[0012] During a display period of displaying an image based on the plurality of sub-pixels, the plurality of switches may be turned on, and during a sensing period of sensing characteristics of a sub-pixel selected from the plurality of sub-pixels, at least one of the plurality of switches may be turned off.

[0013] During the sensing period, the circuit may use at least one of the plurality of low-potential voltage lines as a sensing line to sense characteristics of a sub-pixel selected from the plurality of sub-pixels.

[0014] The plurality of switches may be selectively disposed in one of an active area and a non-active area of the display panel.

[0015] During the sensing period, a reference voltage may be applied to at least one of the low-potential voltage lines used as the sensing line, the reference voltage being higher than the low-potential voltage applied during the display period.

[0016] The display panel may further include a plurality of short-circuit bars, each short-circuit bar electrically connecting two adjacent low-potential voltage lines among the plurality of low-potential voltage lines, and the display panel may include a switch arrangement area where the plurality of switches are disposed and a short-circuit bar arrangement area where the plurality of short-circuit bars are disposed.

[0017] In another aspect of the present disclosure, a method of driving a display device is provided. The display device includes a display panel, a driver, a circuit, and a plurality of switches. The display panel includes a plurality of sub-pixels connected to a high-potential voltage line and a plurality of low-potential voltage lines. The driver is configured to drive the display panel. The circuit is configured to sense and compensate for the characteristics of a sub-pixel selected from the plurality of sub-pixels through the plurality of low-potential voltage lines. Each switch is electrically connected to two adjacent low-potential voltage lines among the plurality of low-potential voltage lines. The method includes: a display step of turning on the plurality of switches to display an image based on the plurality of sub-pixels; a sensing step of turning off at least one of the plurality of switches to sense the characteristics of a sub-pixel selected from the plurality of sub-pixels; and a compensation step of preparing a compensation value based on a sensed value obtained from the selected sub-pixel to compensate for the selected sub-pixel.

[0018] The display panel may further include a plurality of short-circuit bars. Each short-circuit bar is electrically connected to two adjacent low-potential voltage lines among the plurality of low-potential voltage lines. The display panel may include a switch arrangement area provided with the plurality of switches and a short-circuit bar arrangement area provided with the plurality of short-circuit bars.

[0019] During the sensing step, at least one of the plurality of low-potential voltage lines may be used as a sensing line.

[0020] During the sensing step, a reference voltage may be applied to at least one low-potential voltage line used as the sensing line, and the reference voltage is higher than the low-potential voltage applied during the display step.

[0021] It should be understood that the foregoing summary and the following detailed description of the present disclosure are both exemplary and explanatory, and are intended to provide further explanation of the claimed present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The drawings that provide a further understanding of the present disclosure and are incorporated into and constitute a part of this application illustrate embodiments of the present disclosure and, together with the description, are used to explain the principles of the present disclosure. In the drawings:

[0023] Figure 1 is a block diagram schematically showing an LED device;

[0024] Figure 2 and Figure 3 is a diagram describing the configuration of a gate (GIP) type scan driver in a panel;

[0025] Figure 4 is a module configuration diagram of an LED device;

[0026] Figure 5is an exemplary circuit configuration diagram of sub-pixels included in a display panel of Figure 4 ;

[0027] Figure 6 is a diagram schematically showing a configuration of a circuit for sensing sub-pixels through a low-potential voltage line according to an embodiment;

[0028] Figure 7 is Figure 6 an example diagram of the pixel sensing circuit shown in

[0029] Figure 8 and Figure 9 are diagrams describing a sensing operation of the pixel sensing circuit;

[0030] Figure 10 is a diagram showing a display module according to an experimental example;

[0031] Figure 11 is a diagram showing a display module according to a first embodiment;

[0032] Figures 12 to 15 are diagrams respectively describing the display module according to the first embodiment for each driving period;

[0033] Figure 16 and Figure 17 are diagrams describing a sensing process of sub-pixels connected to one low-potential voltage line according to the first embodiment;

[0034] Figure 18 and Figure 19 are diagrams showing a connection relationship between sub-pixels included in a display module and a low-potential voltage line;

[0035] Figure 20 and Figure 21 are diagrams describing a reference voltage variable operation of a pixel sensing circuit according to a second embodiment;

[0036] Figure 22 and Figure 23 are diagrams describing advantages of the second embodiment;

[0037] Figure 24 is a diagram showing a display module according to a third embodiment;

[0038] Figures 25 to 28 are diagrams respectively describing the display module according to the third embodiment for each driving period. DETAILED DESCRIPTION

[0039] Now, preferred embodiments of the present disclosure will be described in detail, and examples thereof are shown in the drawings. Whenever possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts.

[0040] The display device according to the present disclosure may be implemented as a television, a video player, a personal computer (PC), a home theater, an automotive electrical device, or a smart phone, but is not limited thereto. The display device according to the present disclosure may be implemented as an LED device, a QDD, or an LCD. For ease of description, hereinafter, an LED device that directly emits light based on an inorganic light emitting diode or an organic light emitting diode will be taken as an example.

[0041] In addition, the thin film transistor (TFT) described below may be implemented as an n-type TFT, a p-type TFT, or a form in which both n-type and p-type exist. The TFT is a three-electrode element including a gate, a source, and a drain. The source is an electrode that supplies carriers to the transistor. In the TFT, carriers flow starting from the source. The drain is an electrode from which carriers leave the TFT. That is, in the TFT, carriers flow from the source to the drain.

[0042] In the case of a p-type TFT, since the carriers are holes, the source voltage is higher than the drain voltage, so that holes can flow from the source to the drain. In the p-type TFT, holes flow from the source to the drain side, and thus current flows from the source to the drain side. On the contrary, in the case of an n-type TFT, since electrons are carriers, the source voltage is lower than the drain voltage, so that electrons can flow from the source to the drain. In the n-type TFT, electrons flow from the source to the drain side, and thus current flows from the drain to the source side. However, the source and drain of the TFT may change according to the applied voltage. Reflecting this, in the following description, one of the source and the drain will be described as the first electrode, and the other of the source and the drain will be described as the second electrode.

[0043] Figure 1 is a block diagram schematically showing the LED device, Figure 2 and Figure 3 is a diagram describing the configuration of the gate (GIP) type scan driver in the panel, Figure 4 is a module configuration diagram of the LED device, Figure 5 is included in Figure 4 is an exemplary circuit configuration diagram of sub-pixels in the display panel.

[0044] As Figure 1 shown, the LED device may include an image provider 110, a timing controller 120, a scan driver 130, a data driver 140, a display panel 150, a power supply 180, etc.

[0045] The image provider (device or host system) 110 may output various driving signals and an image data signal provided externally or an image data signal stored in an internal memory. The image provider 110 may provide the data signal and various driving signals to the timing controller 120.

[0046] The timing controller 120 may output a gate timing control signal GDC for controlling the operation timing of the scan driver 130, a data timing control signal DDC for controlling the operation timing of the data driver 140, various synchronization signals (vertical synchronization signal Vsync and horizontal synchronization signal Hsync), etc. The timing controller 120 may provide the data signal DATA provided from the image provider 110 to the data driver 140 together with the data timing control signal DDC. The timing controller 120 may be in the form of an integrated circuit (IC) and mounted on a printed circuit board, but is not limited thereto.

[0047] The scan driver 130 may output a scan signal (or scan voltage) in response to the gate timing control signal GDC provided from the timing controller 120. The scan driver 130 may provide the scan signal to each sub-pixel included in the display panel 150 through the gate lines GL1 to GLm. The scan driver 130 may be in the form of an IC, or may be directly formed on the display panel 150 in a GIP manner, but is not limited thereto.

[0048] The data driver 140 may sample and latch the data signal DATA in response to the data timing control signal DDC provided from the timing controller 120, convert the obtained digital data signal into an analog data voltage based on a gamma reference voltage, and output the converted analog data voltage. The data driver 140 may provide the data voltage to the sub-pixels included in the display panel 150 through the data lines DL1 to DLn. The data driver 140 may be in the form of an IC and mounted on the display panel 150 or a printed circuit board, but is not limited thereto.

[0049] The power supply 180 may generate a high-potential voltage and a low-potential voltage based on an externally provided external input voltage, and output the high-potential voltage and the low-potential voltage through a high-potential voltage power supply line EVDD and a low-potential voltage power supply line EVSS. The power supply 180 may not only generate and output the high-potential voltage and the low-potential voltage, but also generate and output the voltage required to drive the scan driver 130 (e.g., gate high potential and gate low voltage) or the voltage required to drive the data driver 140 (e.g., drain voltage and half-drain voltage).

[0050] The display panel 150 may be manufactured based on a rigid or flexible substrate such as glass, silicon, polyimide, etc. The display panel 150 may include a plurality of sub-pixels SP for displaying an image based on a scan signal, a driving signal including a data voltage, a high potential voltage, a low potential voltage, etc. The sub-pixel SP may be connected to a first data line DL1, a first gate line GL1, a high potential voltage line EVDD, and a low potential voltage line EVSS. At least one of a plurality of high potential voltage lines EVDD or a plurality of low potential voltage lines EVSS may be disposed parallel to the first data line DL1. The sub-pixel SP may emit light directly. The sub-pixel SP may emit light of one color among red, green, blue, white, etc.

[0051] Meanwhile, the timing controller 120, the scan driver 130, the data driver 140, etc. have been described above as having separate configurations. However, according to the implementation scheme of the LED device, one or more of the timing controller 120, the scan driver 130, and the data driver 140 may be integrated into one IC.

[0052] As Figure 2 and Figure 3 shown, the GIP type scan driver may include a shift register 131 and a level shifter 135. The level shifter 135 may generate a scan clock signal Clks, a start signal Vst, etc. based on signals and voltages output from the timing controller 120 and the power supply 180.

[0053] The shift register 131 may operate based on the signals Clks and Vst output from the level shifter 135 and output scan signals Scan[1] to Scan[m] capable of turning on or off transistors formed in the display panel. The shift register 131 may adopt the form of a thin film on the display panel using the GIP method.

[0054] Different from the shift register 131, the level shifter 135 may independently adopt the form of an IC or be included in the power supply 180. However, this is only an example, and the present disclosure is not limited thereto.

[0055] As Figure 4 shown, the display panel 150 may include an active area AA for displaying an image and an inactive area NA for not displaying an image. The sub-pixel SP may be located in the active area AA. The shift registers 131a and 131b configured to output scan signals in the GIP type scan driver may be located in the inactive area NA.

[0056] The display panel 150 can be configured as a module (hereinafter referred to as a display module) by a plurality of data drivers 140a to 140n mounted on a plurality of flexible printed circuit boards 141a to 141n and a timing controller 120 mounted on a control board 125. The plurality of data drivers 140a to 140n and the timing controller 120 can be electrically connected through at least two printed circuit boards 145a to 145b, at least two cables 121a to 121b, etc. However, Figure 4 The configuration diagram of the display module shown in

[0057] is only for helping understanding, and the present disclosure is not limited thereto. Figure 5 As shown in

[0058] a sub-pixel SP can include a switching transistor SW, a capacitor CST, a driving transistor DT, and an organic light-emitting diode OLED.

[0059] The switching transistor SW can transfer the data voltage applied through the first data line DL1 to the first electrode of the capacitor CST. The switching transistor SW can have a gate electrode connected to the first gate line GL1, a first electrode connected to the first data line DL1, and a second electrode connected to the gate electrode of the driving transistor DT.

[0060] The capacitor CST can store the data voltage for driving the driving transistor DT. The capacitor CST can have a first electrode connected to the gate electrode of the driving transistor DT, and a second electrode connected to the second electrode of the driving transistor DT and the low potential voltage line EVSS.

[0061] The driving transistor DT can generate a driving current in response to the data voltage stored in the capacitor CST. The driving transistor DT can have a gate electrode connected to the first electrode of the capacitor CST, a first electrode connected to the cathode of the organic light-emitting diode OLED, and a second electrode connected to the low potential voltage line EVSS.

[0062] Figure 6 is a diagram schematically showing the configuration of a circuit for sensing a sub-pixel through a low potential voltage line according to an embodiment, Figure 7 is Figure 6 [[ID=[]27]]an example diagram of the pixel sensing circuit shown in Figure 8 and Figure 9 is a diagram describing the sensing operation of the pixel sensing circuit.

[0063] As shown in Figure 6As shown, the data driver 140 may include a voltage output circuit 143 configured to output a data voltage and a pixel sensing circuit 147 configured to obtain a sensed value. A first output channel DCH1 of the voltage output circuit 143 may be connected to a first data line DL1 of the sub-pixel SP, and a first sensing channel SCH1 of the pixel sensing circuit 147 may be connected to a low potential voltage line EVSS of the sub-pixel SP.

[0064] The pixel sensing circuit 147 may sense whether there is deterioration in the driving transistor DT and the organic light emitting diode OLED. The pixel sensing circuit 147 may sense whether there is an abnormality in the driving transistor DT and the organic light emitting diode OLED. The pixel sensing circuit 147 may sense the current or voltage flowing through the driving transistor DT and the organic light emitting diode OLED.

[0065] The data driver 140 may convert the sensed value Vsen obtained by the pixel sensing circuit 147 into a digital value and transmit the converted value to the timing controller 120 (or a compensation circuit). The timing controller 120 may determine whether there is a change in the characteristics (threshold voltage, current mobility, etc.) of the elements included in the sub-pixel SP based on the sensed value Vsen converted into a digital value, and prepare a compensation value for compensating the sub-pixel SP according to the degree of the characteristic change.

[0066] The timing controller 120 may include a compensator 125 configured to prepare a compensation data signal Cdata based on a compensation value to compensate for the change in the characteristics of the elements included in the sub-pixel SP based on the sensed value Vsen.

[0067] In addition to the compensation value for compensating the change in the characteristics of the actually deteriorated elements based on the sensed value Vsen, the compensator 125 may also prepare a compensation value for compensating the change in the characteristics of the elements included in the unsensed sub-pixels. In this case, the compensator 125 may use an interpolation method or a deterioration prediction method based on the sensed value Vsen to compensate other unsensed sub-pixels in the surrounding area.

[0068] In addition, the timing controller 120 may obtain driving environment variables such as changes in current, voltage, and temperature (a method of predicting temperature change based on changes in current or voltage) based on the sensed value Vsen, and compensate (control) the display panel and the device for driving the display panel (e.g., data driver, scan driver, power supply, etc.) individually or jointly based on this.

[0069] On the other hand, in the above description, by way of example, the sensing circuit that obtains the sensed value by sensing the characteristics of the elements included in the sensing sub-pixel SP and the compensation circuit that prepares the compensation value based on the sensed value are respectively included in the data driver 140 and the timing controller 120. However, this is merely an example, and the sensing circuit that obtains the sensed value by sensing the characteristics of the elements included in the sensing sub-pixel SP and the compensation circuit that prepares the compensation value based on the sensed value can be defined as a single compensation circuit and integrated into one circuit. However, hereinafter, for ease of description, an example in which the sensing circuit and the compensation circuit are separated from each other as Figure 6 shown will be described.

[0070] As Figure 7 shown, the pixel sensing circuit 147 can be implemented as a voltage sensing circuit, which includes a voltage output switch SWP, a voltage source VREF, a sampling switch SWS, an analog-to-digital converter ADC, etc.

[0071] The voltage output switch SWP can have a first electrode connected to the first sensing channel SCH1, a second electrode connected to the voltage source VREF, and a control electrode connected to the voltage output switch control line PRE. When outputting the voltage generated from the voltage source VREF through the first sensing channel SCH1, the voltage output switch SWP can be turned on. Depending on the purpose of use, driving method, and driving time, the voltage source VREF can be configured to output a single-level voltage or different voltages from the first-level voltage to the N-level voltage.

[0072] The sampling switch SWS can have a first electrode connected to the first sensing channel SCH1, a second electrode connected to the input terminal of the analog-to-digital converter ADC, and a control electrode connected to the sampling switch control line SAM. When sensing the elements included in the sub-pixel SP through the first sensing channel SCH1, the sampling switch SWS can be turned on. The analog-to-digital converter ADC can also include a sampling and holding circuit capable of sampling and holding the voltage.

[0073] As Figure 8 shown, the pixel sensing circuit 147 can initialize (or charge) the low-potential voltage line EVSS of the sub-pixel SP with a preset reference voltage Vref before performing the sensing operation. To this end, the voltage output switch SWP can be turned on in response to the on-voltage applied through the voltage output switch control line PRE. At the same time, the pixel sensing circuit 147 can change the reference voltage Vref so that different levels are formed for each sub-pixel. In this case, the sampling switch SWS can be turned off.

[0074] As Figure 9As shown, the pixel sensing circuit 147 may sense the low potential voltage line EVSS of the sub-pixel SP and obtain a sensed value Vsen to perform a sensing operation. To this end, the sampling switch SWS may be turned on in response to a conduction voltage applied through the sampling switch control line SAM. In this case, the voltage output switch SWP may be turned off.

[0075] Hereinafter, a display module implemented based on the above configuration will be described.

[0076] Figure 10 It is a diagram showing a display module according to an experimental example.

[0077] As Figure 10 shown, the display module 100 according to the experimental example may include a display panel 150, first to fourth flexible circuit boards 141a to 141d on which first to fourth data drivers 140a to 140d are respectively mounted, a printed circuit board 145, and the like.

[0078] The display panel 150 may include a plurality of pixels PIX and a plurality of low potential voltage lines EVSS1 to EVSSn. The plurality of pixels PIX may be provided in the active area AA. Each pixel PIX may include a red sub-pixel SPR, a white sub-pixel SPW, a blue sub-pixel SPB, and a green sub-pixel SPG. As an example, the red sub-pixel SPR, the white sub-pixel SPW, the blue sub-pixel SPB, and the green sub-pixel SPG are arranged in the horizontal direction. However, the present disclosure is not limited thereto. For example, the red sub-pixel SPR, the white sub-pixel SPW, the blue sub-pixel SPB, and the green sub-pixel SPG may be arranged in the vertical direction.

[0079] The plurality of low potential voltage lines EVSS1 to EVSSn may be provided inside and outside the active area AA. The plurality of low potential voltage lines EVSS1 to EVSSn may be arranged in the vertical direction and may be spaced apart from each other by a certain distance. As an example, for each data driver, two of the plurality of low potential voltage lines EVSS1 to EVSSn are spaced apart and arranged. However, the present disclosure is not limited thereto. For example, the low potential voltage lines may be further provided according to the number of pixels PIX between the first low potential voltage line EVSS1 and the second low potential voltage line EVSS2 connected to the first data driver 140a.

[0080] Multiple low-potential voltage lines EVSS1 to EVSSn are voltage lines that transmit low-potential voltage to multiple pixels PIX. However, the multiple low-potential voltage lines EVSS1 to EVSSn can be used as sensing lines. The multiple low-potential voltage lines EVSS1 to EVSSn can transmit low-potential voltage during the image display period of the display panel 150 and can not transmit low-potential voltage during the component sensing period of the display panel 150.

[0081] During the sensing period, the power supply may not output low-potential voltage through the multiple low-potential voltage lines EVSS1 to EVSSn. In this case, the multiple low-potential voltage lines EVSS1 to EVSSn may be temporarily floating or may form a specific voltage by a voltage source ( Figure 7 VREF) included in each of the first data driver 140a to the fourth data driver 140d, etc.

[0082] The display module 100 according to the experimental example can sense components included in the sub-pixels of the pixel PIX based on the first data driver 140a to the fourth data driver 140d connected to the multiple low-potential voltage lines EVSS1 to EVSSn. For this purpose, in the display module 100 according to the experimental example, the first data driver 140a to the fourth data driver 140d can be implemented in the form described in Figure 6 and Figure 7 . In addition, in order to operate the display module 100 according to the experimental example as shown in Figure 8 and Figure 9 , under the control of the timing controller, the first data driver 140a to the fourth data driver 140d and the scan driver can be linked. In addition, the display module 100 according to the experimental example can sense components included in the sub-pixels of all pixels PIX or some pixels PIX of the display panel 150 and provide a compensation value according to the degree of characteristic change.

[0083] Figure 11 is a diagram showing a display module according to the first embodiment, Figures 12 to 15 is a diagram describing the display module according to the first embodiment for each driving period, Figure 16 and Figure 17 is a diagram describing the sensing process of sub-pixels connected to one low-potential voltage line according to the first embodiment.

[0084] As Figure 11 shown, the display module 100 according to the first embodiment may include a display panel 150, first flexible circuit boards 141a to 141d respectively mounted with the first data driver 140a to the fourth data driver 140d, and a printed circuit board 145.

[0085] The display panel 150 may include a plurality of pixels PIX and a plurality of low-potential voltage lines EVSS1 to EVSSn. The plurality of pixels PIX may be disposed in the active area AA. Each pixel PIX may include a red sub-pixel SPR, a white sub-pixel SPW, a blue sub-pixel SPB, and a green sub-pixel SPG.

[0086] The plurality of low-potential voltage lines EVSS1 to EVSSn may be disposed inside and outside the active area AA. The plurality of low-potential voltage lines EVSS1 to EVSSn may be disposed in the vertical direction and may be spaced apart from each other by a certain distance.

[0087] The display module 100 according to the first embodiment is similar to the display module of the experimental example. However, the difference lies in that a plurality of switches SW1 to SW7 are disposed between the plurality of low-potential voltage lines EVSS1 to EVSSn, and the difference lies in the operation of the plurality of switches. The description is as follows.

[0088] The plurality of switches SW1 to SW7 may be respectively disposed between the plurality of low-potential voltage lines EVSS1 to EVSSn that are spaced apart from each other on the display panel 150. The plurality of switches SW1 to SW7 may be controlled such that the plurality of low-potential voltage lines EVSS1 to EVSSn that are spaced apart from each other on the display panel 150 are electrically (physically) connected to each other or are not electrically (physically) connected to each other. For example, the first switch SW1 may have a first electrode connected to the first low-potential voltage line EVSS1, a second electrode connected to the second low-potential voltage line EVSS2, and a control electrode connected to the first switch control line S1. The second switch SW2 may have a first electrode connected to the second low-potential voltage line EVSS2, a second electrode connected to the third low-potential voltage line EVSS3, and a control electrode connected to the second switch control line S2. The remaining third switch SW3 to seventh switch SW7 may be connected in the same manner as described above.

[0089] The plurality of switches SW1 to SW7 may be turned on during the image display period of the display panel 150, and may be turned off during the element sensing period of the display panel 150. The driving period operation of the display module 100 according to the first embodiment will be described below.

[0090] As Figure 12 and Figure 13 shown, the display module 100 according to the first embodiment may have a display period for displaying an image on the display panel 150. During the display period, the plurality of switches SW1 to SW7 may all be in an on state. To this end, a conduction voltage (for example, a high voltage) may be applied to each of the plurality of switch control lines S1 to S7.

[0091] When all of the plurality of switches SW1 to SW7 are turned on, the plurality of low potential voltage lines EVSS1 to EVSSn can be electrically (physically) connected to each other. In this case, the plurality of low potential voltage lines EVSS1 to EVSSn can transmit the low potential voltage or the corresponding current uniformly and stably. As a result, the stability and uniformity of the low potential voltage or the corresponding current applied to the entire area of the display panel 150 can be improved. In addition, the sensing accuracy and sensing reliability of the elements included in the sub-pixels can be improved.

[0092] As Figure 14 and Figure 15 shown, the display module 100 according to the first embodiment may include a sensing period for sensing the elements included in the sub-pixels of all pixels PIX or some pixels PIX. During the sensing period, all of the plurality of switches SW1 to SW7 may be in an off state. To this end, a turn-off voltage (e.g., a low voltage) may be applied to each of the plurality of switch control lines S1 to S7.

[0093] When all of the plurality of switches SW1 to SW7 are turned off, the plurality of low potential voltage lines EVSS1 to EVSSn can be electrically (physically) disconnected from each other (separated state). In this case, the plurality of low potential voltage lines EVSS1 to EVSSn can be separated (divided) by line (by position or area). As a result, the sensing accuracy of the elements included in all pixels PIX or some pixels PIX of the display panel 150 can be improved.

[0094] As Figure 16 and Figure 17 shown, depending on the number of gate lines provided in the horizontal direction, a plurality of sub-pixels may be connected to a first low potential voltage line EVSS1 provided in the vertical direction. Hereinafter, an example in which two sub-pixels SP1 and SP2 are connected to the first low potential voltage line EVSS1 will be described.

[0095] As Figure 16As shown, in order to sense the first sub-pixel SP1 connected to the first gate line GL1, a condition of not sensing the second sub-pixel SP2 connected to the second gate line GL2 can be set (for example, DT for not driving SP2). To this end, a sensing data voltage Data_sen for promoting element sensing can be applied to the first sub-pixel SP1. However, in order to set the condition of not sensing the second sub-pixel SP2, a black data voltage (a voltage for forming a non-sensing condition) can be applied to the second sub-pixel SP2 instead of applying the sensing data voltage Data_sen. An example thereof is a case where a turn-on voltage scan signal (a scan signal capable of turning on a switching transistor) is sequentially applied through the first gate line GL1 and the second gate line GL2. However, when scan signals are simultaneously applied through the first gate line GL1 and the second gate line GL2, a turn-on voltage scan signal can be applied to the first gate line GL1 and a turn-off voltage scan signal (a scan signal capable of turning off a switching transistor) can be applied to the second gate line GL2, or a method of omitting (not applying) the output of the scan signal can be used.

[0096] As Figure 17 shown, in order to sense the second sub-pixel SP2 connected to the second gate line GL2, a condition of not sensing the first sub-pixel SP1 connected to the first gate line GL1 can be set (for example, DT for not driving SP1). To this end, a sensing data voltage Data_sen for promoting element sensing can be applied to the second gate line GL2. The condition of not sensing the first gate line GL1 can be obtained by referring to the above method. However, the present disclosure is not limited thereto.

[0097] Figure 18 and Figure 19 is a diagram showing a connection relationship between a sub-pixel included in a display module and a low-potential voltage line.

[0098] As Figure 18 shown, the red sub-pixel SPR, the white sub-pixel SPW, the blue sub-pixel SPB, and the green sub-pixel SPG included in one pixel PIX can have a connection relationship of sharing the first low-potential voltage line EVSS1. In this case, the first switch SW1 can be connected between the first low-potential voltage line EVSS1 and the second low-potential voltage line.

[0099] As Figure 19As shown, the red sub-pixel SPR, white sub-pixel SPW, blue sub-pixel SPB, and green sub-pixel SPG included in one pixel PIX may include the 1-1st to 1-4th low-potential voltage lines EVSS1-1 to EVSS1-4 each having a separate connection relationship. In this case, the first switch SW1 to the third switch SW3 may be respectively connected between the 1-1st to 1-4th low-potential voltage lines EVSS1-1 to EVSS1-4.

[0100] In the structure described in the reference Figure 18 Four sub-pixels (or three sub-pixels) share one low-potential voltage line, so one of the four sub-pixels can be independently sensed during the sensing period.

[0101] In contrast, in the structure described in the reference Figure 19 Four sub-pixels (or three sub-pixels) are respectively connected to four separate low-potential voltage lines, so the four sub-pixels can be sensed simultaneously during the sensing period. Additionally, in the structure described in the reference Figure 19 Four sub-pixels (or three sub-pixels) are each assigned a low-potential voltage line, so the stability and consistency of the low-potential voltage or the corresponding current can be improved.

[0102] Meanwhile, in the first embodiment, by way of example, a plurality of switches are shown and described as being provided in the active area of the display panel. However, the plurality of switches may be provided in the non-active area of the display panel or on the flexible circuit board where the data driver is installed. Additionally, in the first embodiment, by way of example, a plurality of switches are shown and described as being all turned off during the sensing period. However, depending on the sensing area, sensing method, etc., the plurality of switches may be turned off sequentially (in reverse order) or selectively (randomly) individually.

[0103] Figure 20 and Figure 21 are diagrams illustrating the reference voltage variable operation of the pixel sensing circuit according to the second embodiment, Figure 22 and Figure 23 are diagrams illustrating the advantages of the second embodiment.

[0104] As Figure 20 and Figure 21As shown, during the display period, the pixel sensing circuit 147 according to the second embodiment may output a voltage equal to the low potential voltage Evss, or may float without being electrically connected to the first low potential voltage line EVSS1. Further, during the sensing period, a reference voltage Vref having a voltage level higher than the voltage level of the low potential voltage Evss (for example, Vref is a voltage higher than Evss and may have a ΔV exceeding 0V and less than or equal to 3.0V) may be output to the first low potential voltage line EVSS1.

[0105] As Figure 22 and Figure 23 shown, even when a black data voltage Data_blk (for example, 0.5V) is applied to the first sub-pixel SP1 and a sensing data voltage Data_sen (for example, 4.5V) is applied to the second sub-pixel SP2 to sense the second sub-pixel SP2, there may be a minute leakage through the driving transistor DT included in the first sub-pixel SP1.

[0106] When there is a minute leakage, the pixel sensing circuit 147 acquires Vsen1 + Vsen2 including the sensed value Vsen1 of the first sub-pixel SP1 and the sensed value Vsen2 of the second sub-pixel SP2. That is, the minute leakage acts as a noise current during the sensing.

[0107] Thus, when the sensing operation for sensing the second sub-pixel SP2 includes a noise current caused by the first sub-pixel SP1, it may be difficult for the pixel sensing circuit 147 to accurately sense the elements included in the second sub-pixel SP2.

[0108] However, when the reference voltage Vref higher than the low potential voltage Evss is output during the sensing period, the off-state characteristics of the driving transistor DT included in the first sub-pixel SP1 can be improved. For example, the reference voltage Vref may be set to have a voltage level (for example, ∼3.0V) higher than the voltage level (for example, -2.5V) of the gate-source voltage of the driving transistor included in the non-sensing sub-pixel.

[0109] Therefore, the second embodiment has the same configuration and operation as the first embodiment. However, the reference voltage Vref may be configured under conditions where minute leakage from the non-sensing sub-pixel is prevented or the generation of the noise current can be minimized. That is, the second embodiment can improve the sensing accuracy and sensing reliability of the elements included in the sub-pixel.

[0110] Meanwhile, according to the second embodiment, the level of the sensed data voltage Data_sen may need to increase in response to an increase in the level of the reference voltage Vref. For example, when the reference voltage Vref is increased to 3.0V to address a minor leakage that occurs when applying a sensed data voltage Data_sen of 4.5V, the sensed data voltage Data_sen may increase to 7V in response to the increase in the reference voltage Vref.

[0111] Figure 24 FIG. is a diagram showing a display module according to a third embodiment. Figures 25 to 28 FIG. is a diagram describing the display module according to the third embodiment for each driving period.

[0112] As Figure 24 shown, the display module 100 according to the third embodiment may include a display panel 150, first to fourth flexible printed circuits 141a to 141d respectively mounting first to fourth data drivers 140a to 140d, and a printed circuit board 145.

[0113] The display panel 150 may include a plurality of pixels PIX, a plurality of low-potential voltage lines EVSS1 to EVSSn, a plurality of switches SW1 to SW4, and a plurality of short-circuit bars SB1 to SB3. The plurality of pixels PIX may be disposed in an active area AA. Each pixel PIX may include a red sub-pixel SPR, a white sub-pixel SPW, a blue sub-pixel SPB, and a green sub-pixel SPG.

[0114] The plurality of low-potential voltage lines EVSS1 to EVSSn may be disposed inside and outside the active area AA. The plurality of low-potential voltage lines EVSS1 to EVSSn may be disposed in a vertical direction and may be spaced apart from each other by a certain distance.

[0115] The display module 100 according to the third embodiment is similar to the first or second embodiment. However, the difference is that a plurality of short-circuit bars SB1 to SB3 are disposed between the plurality of switches SW1 to SW4, thereby providing a switch arrangement area and a short-circuit bar arrangement area, which are described as follows.

[0116] A plurality of switches SW1 to SW4 can be selectively disposed between a plurality of low-potential voltage lines EVSS1 to EVSSn that are spaced apart from each other on the display panel 150. The plurality of switches SW1 to SW4 can be controlled such that a low-potential voltage line selected from the plurality of low-potential voltage lines EVSS1 to EVSSn that are spaced apart from each other on the display panel 150 is electrically (physically) connected or not electrically (physically) connected. For example, the first switch SW1 can have a first electrode connected to the second low-potential voltage line EVSS2, a second electrode connected to the third low-potential voltage line EVSS3, and a control electrode connected to the first switch control line S1. The second switch SW2 can have a first electrode connected to the third low-potential voltage line EVSS3, a second electrode connected to the fourth low-potential voltage line EVSS4, and a control electrode connected to the second switch control line S2. The remaining third switch SW3 and fourth switch SW4 can be connected adjacent to each other in the same manner as described above.

[0117] A plurality of short-circuit bars SB1 to SB3 can be selectively disposed between a plurality of low-potential voltage lines EVSS1 to EVSSn that are spaced apart from each other on the display panel 150. The plurality of short-circuit bars SB1 to SB3 can be disposed such that a low-potential voltage line selected from the plurality of low-potential voltage lines EVSS1 to EVSSn that are spaced apart from each other on the display panel 150 remains in an electrically (physically) connected state. For example, the first short-circuit bar SB1 can have one end connected to the first low-potential voltage line EVSS1 and the other end connected to the second low-potential voltage line EVSS2. The second short-circuit bar SB2 can have one end connected to the fourth low-potential voltage line EVSS4 and the other end connected to the fifth low-potential voltage line EVSS5.

[0118] The plurality of switches SW1 to SW4 can be turned on during an image display period of the display panel 150, and can be turned off during an element sensing period of the display panel 150. The driving period operation of the display module 100 according to the third embodiment will be described below.

[0119] As Figure 25 and Figure 26 shown, the display module 100 according to the third embodiment can include a display period for displaying an image on the display panel 150. During the display period, the plurality of switches SW1 to SW4 can all be in an on state. To this end, a conduction voltage (e.g., a high voltage) can be applied to each of the plurality of switch control lines S1 to S4.

[0120] When all of the plurality of switches SW1 to SW4 are turned on, the plurality of low-potential voltage lines EVSS1 to EVSSn can be electrically (physically) connected. In this case, the plurality of low-potential voltage lines EVSS1 to EVSSn can transmit the low-potential voltage or the corresponding current uniformly and stably. As a result, the stability and uniformity of the low-potential voltage or the corresponding current applied to the entire area of the display panel 150 can be improved.

[0121] As Figure 27 and Figure 28 shown, the display module 100 according to the third embodiment may include a sensing period for sensing elements included in sub-pixels of some pixels PIX in the display panel 150. During the sensing period, all of the plurality of switches SW1 to SW4 may be in an off state. To this end, a turn-off voltage (e.g., a low voltage) may be applied to each of the plurality of switch control lines S1 to S4.

[0122] When all of the plurality of switches SW1 to SW4 are turned off, the plurality of low-potential voltage lines EVSS1 to EVSSn can be electrically (physically) disconnected (separated state). In this case, the plurality of low-potential voltage lines EVSS1 to EVSSn can be separated (divided) by line (by position or area). As a result, the sensing accuracy of elements included in sub-pixels of some pixels PIX in the display panel 150 can be improved.

[0123] Meanwhile, in the third embodiment, as Figure 28 shown, an example in which there are two sensing-available lines (the third low-potential voltage line EVSS3 and the (n-1)th low-potential voltage line EVSSn-1) is shown. The reason therefor is described as follows.

[0124] The first switch SW1 is disposed on the left side of the third low-potential voltage line EVSS3, and the second switch SW2 is disposed on the right side of the third low-potential voltage line EVSS3. In addition, the third switch SW3 is disposed on the left side of the (n-1)th low-potential voltage line EVSSn-1, and the fourth switch SW4 is disposed on the right side of the (n-1)th low-potential voltage line EVSSn-1. When the first switch SW1 to the fourth switch SW4 are turned on, unlike the other low-potential voltage lines, the third low-potential voltage line EVSS3 and the (n-1)th low-potential voltage line EVSSn-1 can be in an independent state.

[0125] In this case, the second data driver 140b may sense the elements included in the sub-pixels of the pixel PIX connected to the third low potential voltage line EVSS3, and the fourth data driver 140d may sense the elements included in the sub-pixels of the pixel PIX connected to the (n-1)th low potential voltage line EVSSn-1. Accordingly, the switches may be set adjacent to the low potential voltage line connected to the pixel PIX to be sensed, and the shorting bars may be set adjacent to the low potential voltage line connected to the non-sensed pixel PIX.

[0126] Meanwhile, in the third embodiment, an example in which a plurality of switches SW1 to SW4 are provided in the active area AA of the display panel 150 is illustrated and described. However, the plurality of switches SW1 to SW4 may be provided in the non-active area or on the flexible printed circuit boards 141a to 141d on which the data drivers 140a to 140d are mounted. Additionally, in the third embodiment, an example in which all of the plurality of switches SW1 to SW4 are turned off during the sensing period is illustrated and described. However, depending on the sensing area, sensing method, etc., the plurality of switches SW1 to SW4 may be individually turned off sequentially (in reverse order) or selectively (randomly).

[0127] As described above, the effects of the present disclosure are that it is possible to sense the elements included in the sub-pixels through the low potential voltage lines, determine whether there are changes in the characteristics (threshold voltage, current mobility, etc.) of the elements, and compensate the sub-pixels according to the degree of change in the characteristics to improve the display quality and lifespan. Additionally, the effects of the present disclosure are that it is possible to improve the sensing accuracy and sensing reliability of the elements included in the sub-pixels. Additionally, the effects of the present disclosure are that it is possible to selectively sense the elements included in the sub-pixels located in the entire area or a partial area of the display panel based on the arrangement structure of the switches or the switches and shorting bars connected between the low potential voltage lines, and compensate the non-sensed sub-pixels based on this.

[0128] It will be apparent to those skilled in the art that various modifications and variations can be made in the present disclosure without departing from the spirit or scope of the disclosure. Accordingly, the present disclosure is intended to cover modifications and variations of the present disclosure as long as they fall within the scope of the appended claims and their equivalents.

Claims

1. A display device, comprising: a display panel, the display panel including a plurality of sub-pixels connected to a high-potential voltage line and a plurality of low-potential voltage lines; a driver configured to drive the display panel; and a circuit configured to sense and compensate for characteristics of a sub-pixel selected from the plurality of sub-pixels through the plurality of low-potential voltage lines.

2. The display device according to claim 1, wherein, The plurality of low-potential voltage lines are parallel to data lines on the display panel and are spaced apart.

3. The display device according to claim 2, wherein, The display panel includes a plurality of switches, each switch electrically connecting two adjacent low-potential voltage lines among the plurality of low-potential voltage lines.

4. The display device according to claim 3, wherein: during a display period of displaying an image based on the plurality of sub-pixels, the plurality of switches are turned on, during a sensing period of sensing characteristics of a sub-pixel selected from the plurality of sub-pixels, at least one of the plurality of switches is turned off.

5. The display device according to claim 4, wherein, During the sensing period, the circuit uses at least one of the plurality of low-potential voltage lines as a sensing line to sense characteristics of a sub-pixel selected from the plurality of sub-pixels.

6. The display device according to claim 3, wherein, The plurality of switches are selectively disposed in one of an active area and a non-active area of the display panel.

7. The display device according to claim 5, wherein, During the sensing period, a reference voltage is applied to at least one of the low-potential voltage lines used as the sensing line, and the reference voltage is higher than the low-potential voltage applied during the display period.

8. The display device according to claim 3, wherein: the display panel further includes a plurality of short-circuit bars, each short-circuit bar electrically connecting two adjacent low-potential voltage lines among the plurality of low-potential voltage lines, the display panel includes a switch arrangement area where the plurality of switches are disposed and a short-circuit bar arrangement area where the plurality of short-circuit bars are disposed.

9. A method of driving a display device, the display device including a display panel, a driver, a circuit, and a plurality of switches, the display panel including a plurality of sub-pixels connected to a high-potential voltage line and a plurality of low-potential voltage lines, the driver being configured to drive the display panel, the circuit being configured to sense and compensate for characteristics of a sub-pixel selected from the plurality of sub-pixels through the plurality of low-potential voltage lines, each switch electrically connecting two adjacent low-potential voltage lines among the plurality of low-potential voltage lines, the method comprising: a display step of turning on the plurality of switches to display an image based on the plurality of sub-pixels; a sensing step of turning off at least one of the plurality of switches to sense characteristics of a sub-pixel selected from the plurality of sub-pixels; and a compensation step of preparing a compensation value based on a sensed value obtained from the selected sub-pixel to compensate the selected sub-pixel.

10. The method according to claim 9, wherein: the display panel further includes a plurality of short-circuit bars, each short-circuit bar electrically connecting two adjacent low-potential voltage lines among the plurality of low-potential voltage lines, the display panel includes a switch arrangement area where the plurality of switches are disposed and a short-circuit bar arrangement area where the plurality of short-circuit bars are disposed.

11. The method according to claim 9, wherein, During the sensing step, at least one of the plurality of low potential voltage lines serves as a sensing line.

12. The method according to claim 11, wherein, During the sensing step, a reference voltage is applied to at least one of the low potential voltage lines serving as the sensing line, and the reference voltage is higher than the low potential voltage applied during the display step.

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