Display device, display driving device and driving method

Abstract

The invention provides a display device, a display driving device and a driving method. The display driving device comprises an interface circuit and a control circuit. The interface circuit extracts a display data frame from a data stream provided by the processor to the control circuit. In the full panel display mode, the display data frame contains first resolution display data corresponding to all display areas of the display panel, and the control circuit drives a plurality of data lines of the display panel based on the first resolution display data. In the partial panel display mode, the display data frame contains second resolution display data corresponding to a first partial display area of the display panel (but does not contain display data corresponding to other display areas except the first partial display area in the display panel); and the control circuit drives the data lines based on the second resolution display data.

Description

Technical Field

[0001] The present invention relates to an electronic device, and more particularly to a display device, a display driving device, and a driving method. Background Art

[0002] Display panels have been widely used in various types of electronic devices. A display panel may need to operate in different display modes in different operating scenarios. For example, the display panel may selectively operate in either a full-panel display mode or a partial-panel display mode. In the full-panel display mode, all display areas of the display panel are used to display various types of information. In the partial-panel display mode, a part of the display area (normal active area) of the display panel is used to display various types of information, while another part of the display area (inactive area) of the display panel is used to display any unconcerned image (such as a black screen). Generally, regardless of which display mode the display panel operates in, an application processor (AP) will transmit full-frame display data (high-resolution display data) corresponding to all display areas of the display panel to the display driving device. That is, the display driving device will perform various image processing operations on the full-frame display data corresponding to all display areas, and then drive multiple data lines of the display panel based on the processed display data. Based on the actual design, the image processing operations performed by the display driving device on the display data may include logical operations, image enhancement, or other processing, such as: defect elimination (De-mura), burn-in elimination (Deburn-in), color enhancement (colorenhancement), etc.

[0003] In the partial-panel display mode, the display data (unconcerned image, such as a black screen) corresponding to the inactive area of the display panel will occupy the transmission bandwidth. Furthermore, the display driving device will perform various image processing operations on the display data of the inactive area, but performing various image processing operations on the unconcerned image (such as a black screen) of the inactive area will consume / waste the computing resources and power consumption of the display driving device, and will occupy a large amount of storage resources of the display driving device. Summary of the Invention

[0004] The present invention provides a display device, a display driving device, and a driving method, which can selectively operate in either a full-panel display mode or a partial-panel display mode.

[0005] In an embodiment according to the present invention, the above-mentioned display driving device is used to drive a display panel. The display driving device includes an interface circuit and a control circuit. The interface circuit receives a data stream from a processor, where the data stream includes display data frames and vertical synchronization information. The control circuit is coupled to the interface circuit to receive the vertical synchronization information and the display data frames. In response to the display panel operating in the full-panel display mode, the display data frames received by the control circuit from the interface circuit contain first-resolution display data corresponding to all the display areas of the display panel, and the control circuit drives a plurality of data lines of the display panel based on the first-resolution display data. In response to the display panel operating in the first partial-panel display mode, the display data frames received by the control circuit from the interface circuit contain second-resolution display data corresponding to the first partial display area of the display panel (but do not contain the display data corresponding to the other display areas of the display panel except for the first partial display area), and the control circuit drives these data lines based on the second-resolution display data. Wherein, the resolution of the second-resolution display data is lower than the resolution of the first-resolution display data.

[0006] In an embodiment according to the present invention, the above-mentioned driving method includes: receiving, by the interface circuit of the display driving device, a data stream from a processor, where the data stream includes display data frames and vertical synchronization information; in response to the display panel operating in the full-panel display mode, receiving, by the control circuit of the display driving device, a display data frame containing first-resolution display data corresponding to all the display areas of the display panel from the interface circuit, and driving, by the control circuit, a plurality of data lines of the display panel based on the first-resolution display data; and in response to the display panel operating in the first partial-panel display mode, receiving, by the control circuit, a display data frame containing second-resolution display data corresponding to the first partial display area of the display panel (but not containing the display data corresponding to the other display areas of the display panel except for the first partial display area) from the interface circuit, and driving, by the control circuit, these data lines based on the second-resolution display data. Wherein, the resolution of the second-resolution display data is lower than the resolution of the first-resolution display data.

[0007] In an embodiment according to the present invention, the above display device includes a processor, a display panel, and a display driving device. The display driving device is used to drive the display panel. The display driving device is coupled to the processor to receive a data stream, where the data stream includes display data frames and vertical synchronization information. In response to the display panel operating in a full-panel display mode, the display data frames received by the display driving device from the processor contain first-resolution display data corresponding to all display areas of the display panel, and the display driving device drives a plurality of data lines of the display panel based on the first-resolution display data. In response to the display panel operating in a first partial-panel display mode, the display data frames received by the display driving device from the processor contain second-resolution display data corresponding to a first partial display area of the display panel (but not including display data corresponding to other display areas of the display panel except the first partial display area), and the display driving device drives these data lines based on the second-resolution display data. Among them, the resolution of the second-resolution display data is lower than the resolution of the first-resolution display data.

[0008] Based on the above, the display device described in the embodiments of the present invention can selectively operate in either a full-panel display mode or a partial-panel display mode. When the display panel operates in the first partial-panel display mode, the display data frames received by the display driving device from the processor do not contain display data corresponding to other display areas (inactive areas) except the first partial display area (normal active area). Therefore, the amount of data transmitted between the processor and the display driving device and the amount of data transmitted between the display driving device and the display panel can both be effectively reduced. Furthermore, because the display data frames do not contain display data for the inactive areas, the display driving device does not need to perform various image processing operations on the display data for the inactive areas, thereby avoiding the consumption / waste of computing resources and power consumption. Description of the Drawings

[0009] Figure 1 is a schematic diagram of a circuit block of a display device according to an embodiment of the present invention.

[0010] Figure 2 is a schematic diagram of a circuit block of a display driving device according to an embodiment of the present invention.

[0011] Figure 3 is a schematic flowchart of a driving method of a display driving device according to an embodiment of the present invention.

[0012] Figure 4 is a schematic diagram of a scenario of a display panel operating in a full-panel display mode as illustrated in an embodiment of the present invention.

[0013] Figure 5It is a signal timing diagram of a display driving device operating in a full panel display mode, as illustrated according to an embodiment of the present invention.

[0014] Figure 6 It is a schematic diagram of the scenario of a display panel operating in a partial panel display mode, as illustrated according to an embodiment of the present invention.

[0015] Figure 7 It is a signal timing diagram of a display driving device operating in a partial panel display mode, as illustrated according to an embodiment of the present invention.

[0016] Figure 8 It is a signal timing diagram of a display driving device operating in a partial panel display mode, as illustrated according to another embodiment of the present invention.

[0017] Figure 9 It is a schematic diagram of the scenario of a display panel operating in another partial panel display mode, as illustrated according to an embodiment of the present invention.

[0018] Figure 10 It is a signal timing diagram of a display driving device operating in another partial panel display mode, as illustrated according to an embodiment of the present invention.

[0019] Figure 11 It is a signal timing diagram of a display driving device operating in another partial panel display mode, as illustrated according to still another embodiment of the present invention.

[0020] Description of Reference Numerals

[0021] 100: Display device

[0022] 110: Processor

[0023] 120: Display driving device

[0024] 121: Interface circuit

[0025] 122: Control circuit

[0026] 130: Display panel

[0027] DS: Data stream

[0028] DZ11, DZ12: Partial display areas

[0029] EC2: Transmitting signal control circuit

[0030] EM_STV1, EM_STV2: Transmitting start pulse signals

[0031] F51, F71, F81, F82, F101, F110, F111: Frame periods

[0032] F51_1, F51_2, F71_1, F71_2, F81_1, F82_1, F101_1, F101_2, F110_1, F111_1: During sub-frame scanning

[0033] GC2: Gate signal control circuit

[0034] GOA11, GOA12: Gate scanning circuit

[0035] GOA13, GOA14: Emitter scanning circuit

[0036] IP2: Processing circuit

[0037] S310, S320, S330, S340, S350, S360: Steps

[0038] SC2: Source signal control circuit

[0039] SD: Display data frame

[0040] STV1, STV2: Gate start pulse signal

[0041] TM2: Timing circuit

[0042] VBP: Vertical back porch

[0043] VFP: Vertical front porch

[0044] VS: Vertical synchronization information Detailed implementation manners

[0045] Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals will be used in the drawings and the description to refer to the same or like parts.

[0046] As used throughout this specification (including the claims), the term "coupled (or connected)" may refer to any direct or indirect means of connection. For example, if it is described in the text that the first device is coupled (or connected) to the second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be indirectly connected to the second device through other devices or some means of connection. The terms "first", "second", etc. mentioned throughout this specification (including the claims) are used to name components (elements), or to distinguish different embodiments or scopes, rather than to limit the upper or lower limits of the number of components, nor to limit the order of the components. Additionally, whenever possible, components / elements / steps with the same reference numerals in the drawings and embodiments represent the same or similar parts. Components / elements / steps with the same reference numerals or the same terms used in different embodiments can be referred to each other's relevant descriptions.

[0047] Figure 1 It is a schematic diagram of a circuit block of a display device 100 according to an embodiment of the present invention. Figure 1 The illustrated display device 100 includes a processor 110, a display driving device 120, and a display panel 130. The specific implementation manner of the display panel 130 is not limited in this embodiment. According to the actual design, the display panel 130 may be an organic light-emitting diode (OLED) display panel or other display panels. The display panel 130 includes a partial display area DZ11 and a partial display area DZ12.

[0048] A gate scan circuit GOA11, a gate scan circuit GOA12, an emission scan circuit GOA13, and an emission scan circuit GOA14 are arranged on the display panel 130. According to the actual design, the gate scan circuit GOA11, the gate scan circuit GOA12, the emission scan circuit GOA13, and / or the emission scan circuit GOA14 may include a gate driver-on-array (GOA) or other scan circuits on the array. The gate scan circuit GOA11 is coupled to a plurality of gate lines (gate scan lines) in the partial display area DZ11, and the gate scan circuit GOA12 is coupled to a plurality of gate lines (gate scan lines) in the partial display area DZ12. The emission scan circuit GOA13 is coupled to a plurality of emission scan lines in the partial display area DZ11, and the emission scan circuit GOA14 is coupled to a plurality of emission scan lines in the partial display area DZ12.

[0049] This embodiment does not limit the specific implementation of the processor 110. According to the actual design, the processor 110 may include an application processor (AP) or other processors. The display driving device 120 is coupled to the processor 110 to receive the data stream DS. For example (but not limited to this), the processor 110 may output the data stream DS to the display driving device 120 through the mobile industry processor interface (MIPI). The display driving device 120 may extract the display data frame and the vertical synchronization information from the data stream DS provided by the processor 110. The display driving device 120 may drive the display panel 130 based on the display data frame to display an image. According to different designs, in some embodiments, the implementation of the display driving device 120 may be a hardware circuit. In other embodiments, the implementation of the display driving device 120 may be a combination of hardware, firmware, and software (i.e., programs).

[0050] In terms of the hardware form, the above-mentioned display driving device 120 may be implemented as a logic circuit on an integrated circuit. For example, the related functions of the display driving device 120 may be implemented in various logic blocks, modules, and circuits of one or more controllers, microcontrollers, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), central processing units (CPUs), and / or other processing units. The related functions of the display driving device 120 may be implemented as a hardware circuit, such as various logic blocks, modules, and circuits in an integrated circuit, by using a hardware description language (such as Verilog HDL or VHDL) or other suitable programming languages.

[0051] In terms of software form and / or firmware form, the relevant functions of the above display driving device 120 can be implemented as programming codes. For example, the display driving device 120 is implemented using general programming languages (such as C, C++ or assembly language) or other suitable programming languages. The programming codes can be recorded / stored in a "non-transitory machine-readable storage medium". In some embodiments, the non-transitory machine-readable storage medium includes, for example, semiconductor memory and / or storage devices. An electronic device (such as a CPU, a controller, a microcontroller or a microprocessor) can read and execute the programming codes from the non-transitory machine-readable storage medium, thereby implementing the relevant functions of the display driving device 120.

[0052] The display driving device 120 is coupled to a plurality of data lines of the display panel 130. In response to the display panel 130 operating in the full panel display mode, the display data frame received by the display driving device 120 from the processor 110 contains high-resolution display data (first-resolution display data) corresponding to all the display areas of the display panel 130. At this time, the display driving device 120 can drive the data lines of the display panel 130 based on the first-resolution display data.

[0053] In response to the display panel 130 operating in the partial panel display mode (for example, the first partial panel display mode), the display data frame received by the display driving device 120 from the processor 110 contains low-resolution display data (second-resolution display data, the resolution of the second-resolution display data is lower than the resolution of the first-resolution display data) corresponding to a partial display area (normal active area, such as the first partial display area) of the display panel 130, but does not contain the display data corresponding to other display areas (inactive areas) of the display panel 130 except the first partial display area. At this time, the display driving device 120 can drive the data lines of the display panel 130 based on the second-resolution display data.

[0054] In response to the display panel 130 operating in another partial panel display mode (e.g., the second partial panel display mode), the display data frame received by the display driving device 120 from the processor 110 contains low-resolution display data (third-resolution display data, the resolution of the third-resolution display data being lower than that of the first-resolution display data) corresponding to another partial display area (normal active area, e.g., the second partial display area) of the display panel 130, but does not contain display data corresponding to other display areas (inactive areas) of the display panel 130 except for the second partial display area. At this time, the display driving device 120 can drive the data lines of the display panel 130 based on the third-resolution display data.

[0055] For example, when the display panel 130 operates in a certain "partial panel display mode", the partial display area DZ11 is the normal active area and the partial display area DZ12 is the inactive area. Therefore, the display data frame received by the display driving device 120 from the processor 110 contains low-resolution display data corresponding to the partial display area DZ11 (but does not contain display data corresponding to the partial display area DZ12). At this time, the display driving device 120 can drive the data lines of the display panel 130 based on the low-resolution display data corresponding to the partial display area DZ11. When the display panel 130 operates in another "partial panel display mode", the partial display area DZ12 is the normal active area and the partial display area DZ11 is the inactive area. Therefore, the display data frame received by the display driving device 120 from the processor 110 contains low-resolution display data corresponding to the partial display area DZ12 (but does not contain display data corresponding to the partial display area DZ11). At this time, the display driving device 120 can drive the data lines of the display panel 130 based on the low-resolution display data corresponding to the partial display area DZ12.

[0056] In summary, the display device 100 can selectively operate in either the full-panel display mode or the partial panel display mode. When the display panel 130 operates in the first partial panel display mode, the display data frame received by the display driving device 120 from the processor 110 does not contain display data corresponding to other display areas (inactive areas) except for the normal active area. Therefore, the amount of data transmitted between the processor 110 and the display driving device 120 and the amount of data transmitted between the display driving device 120 and the display panel 130 can both be effectively reduced. Furthermore, since the display data frame does not contain display data for the inactive area, the display driving device 120 does not need to perform various image processing operations on the display data for the inactive area, thereby avoiding the consumption / waste of computing resources and power consumption.

[0057] Figure 2 It is a schematic block diagram of a display driving device 120 according to an embodiment of the present invention.Figure 2 The display device 100, the processor 110, the display driving device 120 and the display panel 130 shown in FIG. Figure 1 The display device 100, the processor 110, the display driver 120 and the display panel 130 are shown in FIG. Figure 2 In the illustrated embodiment, the display driver 120 includes an interface circuit 121 and a control circuit 122 . The interface circuit 121 is coupled to the processor 110 to receive the data stream DS. The interface circuit 121 is also coupled to the control circuit 122 .

[0058] Figure 3 FIG is a flow chart of a driving method of a display driving device 120 according to an embodiment of the present invention. Figure 2 and Figure 3 In step S310, the interface circuit 121 receives a data stream DS from the processor 110, wherein the data stream DS includes a display data frame and vertical synchronization information. The interface circuit 121 extracts the display data frame and vertical synchronization information from the data stream DS and transmits them to the control circuit 122. In response to the display panel 130 operating in full-panel display mode (i.e., the determination result of step S320 is "full-panel display mode"), the control circuit 122 receives a display data frame containing high-resolution display data (first-resolution display data) corresponding to the entire display area of the display panel 130 from the interface circuit 121 (step S330).

[0059] Figure 4 FIG. 1 is a schematic diagram illustrating a display panel 130 operating in a full-panel display mode according to an embodiment of the present invention. Figure 2 and Figure 4 When the display panel 130 operates in full-panel display mode, the partial display areas DZ11 and DZ12 of the display driver 120 are both normally active areas. The control circuit 122 receives a display data frame containing first-resolution display data corresponding to the entire display area of the display panel 130 (the partial display areas DZ11 and DZ12) from the interface circuit 121. In step S340, the control circuit 122 drives the multiple data lines of the display panel 130 based on the first-resolution display data. Consequently, both the partial display areas DZ11 and DZ12 perform normal display operations.

[0060] Figure 5 FIG. 1 is a signal timing diagram of the display driving device 120 operating in the full panel display mode according to an embodiment of the present invention. Figure 5 The horizontal axis represents time. Figure 1 、 Figure 2 、 Figure 4 and Figure 5, the interface circuit 121 can extract the display data frame SD and the vertical synchronization information VS from the data stream DS provided by the processor 110 and supply them to the control circuit 122. The vertical synchronization information VS defines the frame period, for example Figure 5 the frame period F51 shown. The frame period F51 corresponding to the display data frame SD includes a porch period and an active data period (scanning period), where the porch period includes a vertical front porch VFP and a vertical back porch VBP. In the full-panel display mode, the active data period (scanning period) includes a sub-frame scanning period F51_1 corresponding to a partial display area DZ11 and a sub-frame scanning period F51_2 corresponding to a partial display area DZ12.

[0061] The control circuit 122 supplies Figure 5 the gate start pulse signal STV1 shown to the gate scanning circuit GOA11 corresponding to the partial display area DZ11 to trigger the gate scanning circuit GOA11 to perform a gate scan on the partial display area DZ11 during the sub-frame scanning period F51_1. The control circuit 122 supplies the emission start pulse signal EM_STV1 to the emission scanning circuit GOA13 corresponding to the partial display area DZ11 to trigger the emission scanning circuit GOA13 to perform an emission scan on the partial display area DZ11 during the sub-frame scanning period F51_1. Therefore, the partial display area DZ11 can perform normal display operations in the full-panel display mode.

[0062] The control circuit 122 supplies Figure 5 the gate start pulse signal STV2 shown to the gate scanning circuit GOA12 corresponding to the partial display area DZ12 to trigger the gate scanning circuit GOA12 to perform a gate scan on the partial display area DZ12 during the sub-frame scanning period F51_2. The control circuit 122 supplies the emission start pulse signal EM_STV2 to the emission scanning circuit GOA14 corresponding to the partial display area DZ12 to trigger the emission scanning circuit GOA14 to perform an emission scan on the partial display area DZ12 during the sub-frame scanning period F51_2. Therefore, the partial display area DZ12 can perform normal display operations in the full-panel display mode.

[0063] Please refer to Figure 2 and Figure 3, in response to the display panel 130 operating in the partial panel display mode (i.e., the determination result in step S320 is "partial panel display mode"), the display data frame received by the control circuit 122 from the interface circuit 121 contains the low-resolution display data (second-resolution display data) corresponding to the first partial display area (normal active area) of the display panel 130, but does not contain the display data corresponding to other display areas (inactive areas) of the display panel 130 except the first partial display area (step S350). Among them, the resolution of the second-resolution display data is lower than the resolution of the first-resolution display data.

[0064] For example, in a certain partial panel display mode (such as the first partial panel display mode), the display data frame received by the control circuit 122 contains the low-resolution display data corresponding to the partial display area DZ11, but does not contain the display data corresponding to the partial display area DZ12. In another partial panel display mode (such as the second partial panel display mode), the display data frame received by the control circuit 122 contains the low-resolution display data corresponding to the partial display area DZ12, but does not contain the display data corresponding to the partial display area DZ11. In step S360, the control circuit 122 drives multiple data lines of the display panel 130 based on the second-resolution display data.

[0065] Figure 6 is a schematic diagram of the scenario of the display panel 130 operating in a certain partial panel display mode (such as the first partial panel display mode) according to an embodiment of the present invention. Please refer to Figure 2 and Figure 6 , when the display panel 130 operates in the partial panel display mode, the partial display area DZ11 of the display driving device 120 is the normal active area, and the partial display area DZ12 of the display driving device 120 is the inactive area. The control circuit 122 receives a display data frame containing the low-resolution display data corresponding to the partial display area DZ11 from the interface circuit 121. The control circuit 122 drives multiple data lines of the display panel 130 based on the low-resolution display data. Therefore, the partial display area DZ11 can perform normal display operations.

[0066] Figure 7 is a schematic diagram of the signal timing of the display driving device 120 operating in the partial panel display mode according to an embodiment of the present invention. Figure 7 The horizontal axis of Figure 1 , Figure 2 , Figure 6 and Figure 7, the interface circuit 121 can extract the display data frame SD and the vertical synchronization information VS from the data stream DS provided by the processor 110 and supply them to the control circuit 122. The vertical synchronization information VS defines a frame period, for example Figure 7 the frame period F71 shown. The frame period F71 corresponding to the display data frame SD includes a porch period and a scan period. In a partial panel display mode, the scan period includes a sub-frame scan period F71_1 corresponding to a partial display area DZ11 and a sub-frame scan period F71_2 corresponding to a partial display area DZ12.

[0067] The control circuit 122 supplies Figure 7 the gate start pulse signal STV1 shown to the gate scan circuit GOA11 corresponding to the partial display area DZ11 to trigger the gate scan circuit GOA11 to perform a gate scan on the partial display area DZ11 during the sub-frame scan period F71_1. The control circuit 122 drives a plurality of data lines of the display panel 130 based on the low-resolution display data corresponding to the partial display area DZ11 during the sub-frame scan period F71_1. The control circuit 122 supplies an emission start pulse signal EM_STV1 to the emission scan circuit GOA13 corresponding to the partial display area DZ11 to trigger the emission scan circuit GOA13 to perform an emission scan on the partial display area DZ11 during the sub-frame scan period F71_1. By supplying the emission start pulse signal EM_STV1, the entire partial display area DZ11 of the display panel 130 can operate in a normal display state during the frame period F71. Therefore, the partial display area DZ11 can Figure 6 perform normal display operations in the partial panel display mode shown.

[0068] Since the control circuit 122 has no display data corresponding to the partial display area DZ12, a plurality of data lines of the display panel 130 are maintained in a steady state during the sub-frame scan period F71_2. For example, the control circuit 122 can output a common voltage (or other fixed voltage) to a plurality of data lines of the display panel 130 during the sub-frame scan period F71_2. The control circuit 122 cancels the gate start pulse signal STV2 to the gate scan circuit GOA12 to disable the gate scan circuit GOA12 from performing a gate scan on the partial display area DZ12 during the sub-frame scan period F71_2. The control circuit 122 also cancels the emission start pulse signal EM_STV2 to the emission scan circuit GOA14 to disable the emission scan circuit GOA14 from performing an emission scan on the partial display area DZ12 during the sub-frame scan period F71_2. By canceling the emission start pulse signal EM_STV2, the entire partial display area DZ12 of the display panel 130 operates in a non-display state during the frame period F71. Therefore, the partial display area DZ12 in Figure 6There is no display operation in the partial panel display mode shown.

[0069] Figure 8 It is shown according to another embodiment of the present invention, and it is a schematic diagram of the signal timing of the display driving device 120 operating in the partial panel display mode. Figure 8 The horizontal axis of represents time. Please refer to Figure 1 , Figure 2 , Figure 6 and Figure 8 , the interface circuit 121 can extract the display data frame SD and the vertical synchronization information VS from the data stream DS provided by the processor 110 and supply them to the control circuit 122. The vertical synchronization information VS defines the frame period, such as Figure 8 the frame periods F81 and F82 shown. The frame period F81 includes the porch period and the scan period (the sub-frame scan period F81_1 corresponding to the partial display area DZ11). The frame period F82 includes the porch period and the scan period (the sub-frame scan period F82_1 corresponding to the partial display area DZ11).

[0070] For comparison, Figure 7 the frame period F71 shown is also depicted in Figure 8 . Compared with the frame period F71, Figure 8 the frame period F81 shown does not have the sub-frame scan period F71_2 corresponding to the partial display area DZ12. Figure 8 The frame period F82 shown can refer to the relevant description of the frame period F81 and be analogized.

[0071] The control circuit 122 supplies Figure 8 the gate start pulse signal STV1 shown to the gate scan circuit GOA11 corresponding to the partial display area DZ11 to trigger the gate scan circuit GOA11 to perform a gate scan on the partial display area DZ11 during the sub-frame scan period F81_1. The control circuit 122 drives multiple data lines of the display panel 130 based on the low-resolution display data corresponding to the partial display area DZ11 during the sub-frame scan period F81_1. The control circuit 122 supplies the emission start pulse signal EM_STV1 to the emission scan circuit GOA13 corresponding to the partial display area DZ11 to trigger the emission scan circuit GOA13 to perform an emission scan on the partial display area DZ11 during the sub-frame scan period F81_1. By supplying the emission start pulse signal EM_STV1, all operations of the partial display area DZ11 of the display panel 130 during the frame period F81 are in the normal display state. Therefore, the partial display area DZ11 can perform normal display operations in Figure 6 the partial panel display mode shown.

[0072] The control circuit 122 cancels the gate start pulse signal STV2 given to the gate scanning circuit GOA12 to disable the gate scanning of the gate scanning circuit GOA12 for a partial display area DZ12. The control circuit 122 also cancels the emission start pulse signal EM_STV2 given to the emission scanning circuit GOA14 to disable the emission scanning of the emission scanning circuit GOA14 for the partial display area DZ12. By canceling the emission start pulse signal EM_STV2, all operations of the partial display area DZ12 of the display panel 130 during the frame period F81 are in a non-display state. Therefore, the partial display area DZ12 is in Figure 6 the non-display operation in the partial panel display mode shown.

[0073] Figure 9 FIG. is a schematic diagram of a display panel 130 operating in another partial panel display mode (e.g., the second partial panel display mode) according to an embodiment of the present invention. Please refer to Figure 2 and Figure 9 , when the display panel 130 operates in the partial panel display mode, the partial display area DZ12 of the display driving device 120 is a normal active area, while the partial display area DZ11 of the display driving device 120 is an inactive area. The control circuit 122 receives a display data frame containing low-resolution display data (e.g., third-resolution display data) corresponding to the partial display area DZ12 from the interface circuit 121. The control circuit 122 drives a plurality of data lines of the display panel 130 based on the low-resolution display data. Therefore, the partial display area DZ12 can perform normal display operations.

[0074] Figure 10 FIG. is a schematic diagram of signal timings of the display driving device 120 operating in the partial panel display mode according to another embodiment of the present invention. Figure 10 The horizontal axis of FIG. represents time. Please refer to Figure 1 , Figure 2 , Figure 9 and Figure 10 , the interface circuit 121 can extract the display data frame SD and the vertical synchronization information VS from the data stream DS provided by the processor 110 to the control circuit 122. The vertical synchronization information VS defines the frame period, e.g., Figure 10 the frame period F101 shown in FIG. The frame period F101 corresponding to the display data frame SD includes a porch period and a scanning period. In the partial panel display mode, the scanning period includes a sub-frame scanning period F101_1 corresponding to the partial display area DZ11 and a sub-frame scanning period F101_2 corresponding to the partial display area DZ12.

[0075] Since the control circuit 122 does not have the display data corresponding to the partial display area DZ11, a plurality of data lines of the display panel 130 are maintained in a steady state during the sub-frame scan period F101_1. For example, the control circuit 122 can output a common voltage (or other fixed voltage) to a plurality of data lines of the display panel 130 during the sub-frame scan period F101_1. The control circuit 122 cancels the gate start pulse signal STV1 given to the gate driving circuit GOA11 to disable the gate driving circuit GOA11 from performing gate scanning on the partial display area DZ11 during the sub-frame scan period F101_1. The control circuit 122 also cancels the emission start pulse signal EM_STV1 given to the emission driving circuit GOA13 to disable the emission driving circuit GOA13 from performing emission scanning on the partial display area DZ11 during the sub-frame scan period Fx01_1. By canceling the emission start pulse signal EM_STV1, all operations of the partial display area DZ11 of the display panel 130 are in a non-display state during the frame period F101. Therefore, the partial display area DZ11 has no display operation in the Figure 9 partial panel display mode shown.

[0076] The control circuit 122 provides Figure 10 the shown gate start pulse signal STV2 to the gate driving circuit GOA1x corresponding to the partial display area DZ12 to trigger the gate driving circuit GOA12 to perform gate scanning on the partial display area DZ12 during the sub-frame scan period F101_2. The control circuit 122 drives a plurality of data lines of the display panel 130 based on the low-resolution display data corresponding to the partial display area DZ12 during the sub-frame scan period F101_2. The control circuit 122 provides the emission start pulse signal EM_STV2 to the emission driving circuit GOA14 corresponding to the partial display area DZ12 to trigger the emission driving circuit GOA14 to perform emission scanning on the partial display area DZ12 during the sub-frame scan period F101_2. By providing the emission start pulse signal EM_STV2, all of the partial display area DZ12 of the display panel 130 can operate in a normal display state during the frame period F101. Therefore, the partial display area DZ12 can perform normal display operations in the Figure 9 partial panel display mode shown.

[0077] Figure 11 is a signal timing diagram of the display driving device 120 operating in the partial panel display mode according to another embodiment of the present invention. Figure 11 The horizontal axis of represents time. Please refer to Figure 1 、 Figure 2 、 Figure 9 and Figure 11, the interface circuit 121 can extract the display data frame SD and the vertical synchronization information VS from the data stream DS provided by the processor 110 and supply them to the control circuit 122. The vertical synchronization information VS defines the frame period, for example Figure 11 the frame periods F110 and F111 shown. The frame period F110 includes a porch period and a scan period (the sub-frame scan period F110_1 corresponding to a partial display area DZ12). The frame period F111 includes a porch period and a scan period (the sub-frame scan period F111_1 corresponding to a partial display area DZ12).

[0078] For comparison, Figure 10 the frame period F101 shown is also depicted in Figure 11 . Compared with the frame period F101, Figure 11 the frame period F111 shown does not have the sub-frame scan period F101_1 corresponding to the partial display area DZ11. Figure 11 The frame period F110 shown can refer to the relevant description of the frame period F111 and be analogized accordingly.

[0079] The control circuit 122 cancels the gate start pulse signal STV1 supplied to the gate scan circuit GOA11 to disable the gate scan of the partial display area DZ11 by the gate scan circuit GOA11. The control circuit 122 also cancels the emission start pulse signal EM_STV1 supplied to the emission scan circuit GOA13 to disable the emission scan of the partial display area DZ11 by the emission scan circuit GOA13. By canceling the emission start pulse signal EM_STV1, all operations of the partial display area DZ11 of the display panel 130 are in a non-display state during the frame period F111. Therefore, the partial display area DZ11 has no display operation in Figure 9 the partial panel display mode shown.

[0080] The control circuit 122 supplies Figure 11 the gate start pulse signal STV2 shown to the gate scan circuit GOA12 corresponding to the partial display area DZ12 to trigger the gate scan of the partial display area DZ12 by the gate scan circuit GOA12 during the sub-frame scan period F111_1. The control circuit 122 drives a plurality of data lines of the display panel 130 based on the low-resolution display data corresponding to the partial display area DZ12 during the sub-frame scan period F111_1. The control circuit 122 supplies the emission start pulse signal EM_STV2 to the emission scan circuit GOA14 corresponding to the partial display area DZ12 to trigger the emission scan of the partial display area DZ12 by the emission scan circuit GOA14 during the sub-frame scan period F111_1. By supplying the emission start pulse signal EM_STV2, all operations of the partial display area DZ12 of the display panel 130 are in a normal display state during the frame period F111. Therefore, the partial display area DZ12 can be inFigure 9 Perform normal display operations in the partial panel display mode shown.

[0081] In Figure 2 In the embodiment shown, the control circuit 122 includes a processing circuit IP2, a timing circuit TM2, a gate signal control circuit GC2, a transmit signal control circuit EC2, and a source signal control circuit SC2. The number of processing circuits IP2 can be one or more. The processing circuit IP2 is coupled to the interface circuit 121 to receive a display data frame. The processing circuit IP2 can perform at least one image processing on the display data frame to generate a processed data frame. Based on the actual design, in some embodiments, the image processing performed by the processing circuit IP2 on the display data frame may include logical operations, image enhancement, or other processing, such as: defect elimination (De-mura), burn-in elimination (Deburn-in), color enhancement, etc.

[0082] The timing circuit TM2 is coupled to the processing circuit IP2 to receive the processed data frame. The timing circuit TM2 controls the operation timing of the control circuit 122 based on the vertical synchronization information VS (not shown in Figure 2 ). The gate signal control circuit GC2 and the transmit signal control circuit EC2 are coupled to the timing circuit TM2. The timing circuit TM2 can control the operation timing of the gate signal control circuit GC2 and the transmit signal control circuit EC2. The source signal control circuit SC2 is also coupled to the timing circuit TM2 to receive the processed data frame. Based on the timing control of the timing circuit TM2, the source signal control circuit SC2 can drive the data lines of the display panel 130 in coordination with the scanning timing of the scanning circuit.

[0083] In the full-panel display mode, the processed data frame received by the source signal control circuit SC2 from the timing circuit TM2 contains first-resolution display data (high-resolution display data corresponding to the entire display area of the display panel 130). The source signal control circuit SC2 drives the data lines of the display panel 130 based on the first-resolution display data. Based on the timing control of the timing circuit TM2, the gate signal control circuit GC2 provides a gate start pulse signal STV1 to the gate scan circuit GOA11 corresponding to the partial display area DZ11 to trigger the gate scan of the partial display area DZ11 by the gate scan circuit GOA11 during the first sub-frame scan, and the gate signal control circuit GC2 provides a gate start pulse signal STV2 to the gate scan circuit GOA12 corresponding to the partial display area DZ12 to trigger the gate scan of the partial display area DZ12 by the gate scan circuit GOA12 during the second sub-frame scan. In addition, based on the timing control of the timing circuit TM2, the emission signal control circuit EC2 provides an emission start pulse signal EM_STV1 to the emission scan circuit GOA13 corresponding to the partial display area DZ11 to trigger the emission scan of the partial display area DZ11 by the emission scan circuit GOA13 during the first sub-frame scan, and the emission signal control circuit EC2 provides an emission start pulse signal EM_STV2 to the emission scan circuit GOA14 corresponding to the partial display area DZ12 to trigger the emission scan of the partial display area DZ12 by the emission scan circuit GOA14 during the second sub-frame scan. The operation of the control circuit 122 in the full-panel display mode can be referred to Figure 3 , Figure 4 and Figure 5 for the relevant descriptions, so they will not be elaborated here.

[0084] Please refer to Figure 1 , Figure 2 , Figure 6 and Figure 7, in the first partial panel display mode, the processed data frame received by the source signal control circuit SC2 from the timing circuit TM2 contains the display data of the second resolution corresponding to the partial display area DZ11 (but does not contain the display data corresponding to other display areas except the partial display area DZ11), and the source signal control circuit SC2 drives the data lines of the display panel 130 based on the display data of the second resolution. The gate signal control circuit GC2 provides the gate start pulse signal STV1 to the gate scanning circuit GOA11 based on the timing control of the timing circuit TM2 to trigger the gate scanning circuit GOA11 to perform gate scanning on the partial display area DZ11 during the sub-frame scan period F71_1. The source signal control circuit SC2 drives the data lines of the display panel 130 based on the display data of the second resolution during the sub-frame scan period F71_1. The gate signal control circuit GC2 cancels the gate start pulse signal STV2 to disable the gate scanning circuit GOA12 from performing gate scanning on the partial display area DZ12 during the sub-frame scan period F71_2. The source signal control circuit SC2 keeps the data lines of the display panel 130 in a steady state (fixed voltage) during the sub-frame scan period F71_2 because there is no display data corresponding to the partial display area DZ12. Based on the timing control of the timing circuit TM2, the emission signal control circuit EC2 provides the first emission start pulse signal EM_STV1 to the emission scanning circuit GOA13 to trigger the emission scanning circuit GOA13 to perform emission scanning on the partial display area DZ11 during the sub-frame scan period F71_1, and the emission signal control circuit EC2 cancels the emission start pulse signal EM_STV2 to disable the emission scanning circuit GOA14 from performing emission scanning on the partial display area DZ12 during the sub-frame scan period F71_2.

[0085] Please refer to Figure 1 , Figure 2 , Figure 6 and Figure 8, in the first partial panel display mode, the gate signal control circuit GC2 provides a gate start pulse signal STV1 to the gate scanning circuit GOA11 corresponding to the partial display area DZ11 based on the timing control of the timing circuit TM2 to trigger the gate scanning circuit GOA11 to perform gate scanning on the partial display area DZ11 during the sub-frame scan period F81_1. The source signal control circuit drives the data lines of the display panel 130 during the sub-frame scan period F81_1 based on the second-resolution display data corresponding to the partial display area DZ11. The gate signal control circuit GC2 cancels the gate start pulse signal STV2 for the gate scanning circuit GOA12 to disable the gate scanning of the partial display area DZ12 by the gate scanning circuit GOA12. Based on the timing control of the timing circuit TM2, the emission signal control circuit EC2 provides a first emission start pulse signal EM_STV1 to the emission scanning circuit GOA13 corresponding to the first partial display area DZ11 to trigger the emission scanning circuit GOA13 to perform emission scanning on the partial display area DZ11 during the sub-frame scan period F81_1, and the emission signal control circuit EC2 cancels the emission start pulse signal EM_STV2 for the emission scanning circuit GOA14 to disable the emission scanning of the partial display area DZ12 by the emission scanning circuit GOA14.

[0086] In summary, the control circuit 122 can selectively operate in either the full-panel display mode or the partial-panel display mode. When the display panel 130 operates in the first partial panel display mode, there is no display data corresponding to other display areas (inactive areas) except for the normal active area in the display data frame. Therefore, the amount of transmission data of the transmission channel can be effectively reduced. Moreover, since there is no display data for the inactive area in the display data frame, the processing circuit IP2 does not need to perform various image processing operations on the display data of the inactive area, thereby avoiding the consumption / waste of computing resources and power consumption.

[0087] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display driving device for driving a display panel, characterized in that, The display driving device includes: an interface circuit that receives a data stream from a processor, where the data stream includes display data frames and vertical synchronization information; and a control circuit coupled to the interface circuit to receive the vertical synchronization information and the display data frames, where in response to the display panel operating in a full-panel display mode, the display data frames received by the control circuit from the interface circuit contain first-resolution display data corresponding to all display areas of the display panel, and the control circuit drives a plurality of data lines of the display panel based on the first-resolution display data; and in response to the display panel operating in a first partial-panel display mode, the display data frames received by the control circuit from the interface circuit contain second-resolution display data corresponding to a first partial display area of the display panel but do not contain display data corresponding to other display areas of the display panel except the first partial display area, and the control circuit drives the plurality of data lines based on the second-resolution display data, where the resolution of the second-resolution display data is lower than the resolution of the first-resolution display data.

2. The display driving device according to claim 1, wherein in response to the display panel operating in a second partial-panel display mode, the display data frames received by the control circuit from the interface circuit contain third-resolution display data corresponding to a second partial display area of the display panel but do not contain display data corresponding to other display areas of the display panel except the second partial display area, and the control circuit drives the plurality of data lines based on the third-resolution display data, where the resolution of the third-resolution display data is lower than the resolution of the first-resolution display data, and the second partial display area is different from the first partial display area.

3. The display driving device according to claim 1, wherein In the full-panel display mode: the vertical synchronization information defines a frame period, and the frame period corresponding to the display data frames includes a porch period, a first sub-frame scan period corresponding to the first partial display area, and a second sub-frame scan period corresponding to a second partial display area of the display panel, where the second partial display area is different from the first partial display area; the control circuit provides a first gate start pulse signal to a first gate scan circuit corresponding to the first partial display area to trigger the first gate scan circuit to perform a gate scan on the first partial display area of the display panel during the first sub-frame scan period; and the control circuit provides a second gate start pulse signal to a second gate scan circuit corresponding to the second partial display area to trigger the second gate scan circuit to perform a gate scan on the second partial display area of the display panel during the second sub-frame scan period.

4. The display driving device according to claim 3, wherein In the full-panel display mode: The control circuit provides a first emission start pulse signal to the first emission scanning circuit corresponding to the first partial display area, so as to trigger the first emission scanning circuit to perform emission scanning on the first partial display area of the display panel during the first sub-frame scan; And The control circuit provides a second emission start pulse signal to the second emission scanning circuit corresponding to the second partial display area, so as to trigger the second emission scanning circuit to perform emission scanning on the second partial display area of the display panel during the second sub-frame scan.

5. The display driving device according to claim 1, wherein In the first partial panel display mode: During the frame period defined by the vertical synchronization information, the frame period corresponding to the display data frame includes the first sub-frame scan period corresponding to the first partial display area and the second sub-frame scan period corresponding to the second partial display area of the display panel, wherein the second partial display area is different from the first partial display area; The control circuit provides a first gate start pulse signal to the first gate scanning circuit corresponding to the first partial display area, so as to trigger the first gate scanning circuit to perform gate scanning on the first partial display area of the display panel during the first sub-frame scan; The control circuit drives the plurality of data lines during the first sub-frame scan based on the second-resolution display data; The control circuit maintains the plurality of data lines in a steady state during the second sub-frame scan due to the absence of display data corresponding to the second partial display area; And The control circuit cancels the second gate start pulse signal to the second gate scanning circuit to disable the second gate scanning circuit from performing gate scanning on the second partial display area during the second sub-frame scan.

6. The display driving device according to claim 5, characterized in that, In the first partial panel display mode: The control circuit provides a first emission start pulse signal to the first emission scanning circuit corresponding to the first partial display area, so as to trigger the first emission scanning circuit to perform emission scanning on the first partial display area of the display panel during the first sub-frame scan; And The control circuit cancels the second emission start pulse signal to the second emission scanning circuit to disable the second emission scanning circuit from performing emission scanning on the second partial display area during the second sub-frame scan.

7. The display driving device according to claim 6, wherein In the first partial panel display mode: By providing the first emission start pulse signal, all operations of the first partial display area of the display panel during the frame period are in the normal display state; And By canceling the second emission start pulse signal, all operations of the second partial display area of the display panel during the frame period are in the non-display state.

8. The display driving device according to claim 1, wherein In the first partial panel display mode: During the frame period defined by the vertical synchronization information, the frame period corresponding to the display data frame includes the porch period and the first sub-frame scan period corresponding to the first partial display area, wherein there is no scan period corresponding to the second partial display area of the display panel during the frame period, and the first partial display area is different from the second partial display area; The control circuit provides a first gate start pulse signal to a first gate scanning circuit corresponding to the first partial display area, so as to trigger the first gate scanning circuit to perform gate scanning on the first partial display area of the display panel during the first sub-frame scan; The control circuit drives the plurality of data lines based on the second-resolution display data during the first sub-frame scan; and The control circuit cancels the second gate start pulse signal to the second gate scanning circuit, so as to disable the gate scanning of the second gate scanning circuit on the second partial display area.

9. The display driving device according to claim 8, wherein, In the first partial panel display mode: The control circuit provides a first emission start pulse signal to a first emission scanning circuit corresponding to the first partial display area, so as to trigger the first emission scanning circuit to perform emission scanning on the first partial display area of the display panel during the first sub-frame scan; And The control circuit cancels the second emission start pulse signal to the second emission scanning circuit, so as to disable the emission scanning of the second emission scanning circuit on the second partial display area.

10. The display driving device according to claim 9, wherein In the first partial panel display mode: By providing the first emission start pulse signal, all operations of the first partial display area of the display panel during the frame are in the normal display state; And By canceling the second emission start pulse signal, all operations of the second partial display area of the display panel during the frame are in the non-display state.

11. The display driving device according to claim 1, wherein The control circuit includes: At least one processing circuit, coupled to the interface circuit to receive the display data frame, wherein the at least one processing circuit performs at least one image processing on the display data frame to generate a processed data frame; A timing circuit, coupled to the at least one processing circuit to receive the processed data frame, wherein the timing circuit controls the operation timing of the control circuit based on the vertical synchronization information; and A source signal control circuit, coupled to the timing circuit to receive the processed data frame, wherein, In the full-panel display mode, the processed data frame received by the source signal control circuit from the timing circuit contains the first-resolution display data, and the source signal control circuit drives the plurality of data lines based on the first-resolution display data; and In the first partial panel display mode, the processed data frame received by the source signal control circuit from the timing circuit contains the second-resolution display data but does not contain the display data corresponding to other display areas except the first partial display area, and the source signal control circuit drives the plurality of data lines based on the second-resolution display data.

12. The display driving device according to claim 11, wherein The vertical synchronization information defines a frame period, and the frame period corresponding to the display data frame includes a porch period, a first sub-frame scan period corresponding to the first partial display area, and a second sub-frame scan period corresponding to the second partial display area of the display panel. The control circuit further includes: A gate signal control circuit, coupled to the timing circuit, wherein, In the full-panel display mode, the gate signal control circuit, based on the timing control of the timing circuit, provides a first gate start pulse signal to the first gate scanning circuit corresponding to the first partial display area to trigger the first gate scanning circuit to perform gate scanning on the first partial display area during the first sub-frame scan, and provides a second gate start pulse signal to the second gate scanning circuit corresponding to the second partial display area to trigger the second gate scanning circuit to perform gate scanning on the second partial display area during the second sub-frame scan; and In the first partial-panel display mode, the gate signal control circuit provides the first gate start pulse signal to the first gate scanning circuit based on the timing control of the timing circuit to trigger the first gate scanning circuit to perform gate scanning on the first partial display area during the first sub-frame scan, the source signal control circuit drives the plurality of data lines during the first sub-frame scan based on the second-resolution display data, the gate signal control circuit cancels the second gate start pulse signal to disable the second gate scanning circuit from performing gate scanning on the second partial display area during the second sub-frame scan, and the source signal control circuit maintains the plurality of data lines in a steady state during the second sub-frame scan due to the absence of display data corresponding to the second partial display area.

13. The display driving device according to claim 12, wherein The control circuit further includes: A transmit signal control circuit, coupled to the timing circuit, wherein in the full-panel display mode, the transmit signal control circuit, based on the timing control of the timing circuit, provides a first transmit start pulse signal to the first transmit scanning circuit corresponding to the first partial display area to trigger the first transmit scanning circuit to perform transmit scanning on the first partial display area during the first sub-frame scan, and provides a second transmit start pulse signal to the second transmit scanning circuit corresponding to the second partial display area to trigger the second transmit scanning circuit to perform transmit scanning on the second partial display area during the second sub-frame scan; and in the first partial-panel display mode, the transmit signal control circuit, based on the timing control of the timing circuit, provides the first transmit start pulse signal to the first transmit scanning circuit to trigger the first transmit scanning circuit to perform transmit scanning on the first partial display area during the first sub-frame scan, and cancels the second transmit start pulse signal to disable the second transmit scanning circuit from performing transmit scanning on the second partial display area during the second sub-frame scan.

14. The display driving device according to claim 11, wherein During the period defined by the vertical synchronization information frame, the control circuit further includes: A gate signal control circuit, coupled to the timing circuit, wherein In the first partial panel display mode, the frame period corresponding to the display data frame includes a porch period and a first sub-frame scanning period corresponding to the first partial display area, but does not include a scanning period corresponding to the second partial display area of the display panel. The gate signal control circuit provides a first gate start pulse signal to the first gate scanning circuit corresponding to the first partial display area based on the timing control of the timing circuit to trigger the first gate scanning circuit to perform gate scanning on the first partial display area during the first sub-frame scanning period. The source signal control circuit drives the plurality of data lines during the first sub-frame scanning period based on the second-resolution display data, and the gate signal control circuit cancels the second gate start pulse signal to the second gate scanning circuit to disable the gate scanning of the second partial display area by the second gate scanning circuit.

15. The display driving device according to claim 14, wherein The control circuit further includes: A transmission signal control circuit, coupled to the timing circuit, wherein, In the first partial panel display mode, the transmission signal control circuit provides a first transmission start pulse signal to the first transmission scanning circuit corresponding to the first partial display area based on the timing control of the timing circuit to trigger the first transmission scanning circuit to perform transmission scanning on the first partial display area during the first sub-frame scanning period, and cancels the second transmission start pulse signal to the second transmission scanning circuit to disable the transmission scanning of the second partial display area by the second transmission scanning circuit.

16. A driving method for a display driving device, characterized in that, The driving method includes: Receiving a data stream from a processor by an interface circuit of the display driving device, wherein the data stream includes a display data frame and a vertical synchronization information; In response to the display panel operating in a full panel display mode, receiving, by the control circuit of the display driving device, the display data frame containing the first-resolution display data corresponding to all display areas of the display panel from the interface circuit, and driving, by the control circuit, the plurality of data lines of the display panel based on the first-resolution display data; and In response to the display panel operating in a first partial panel display mode, receiving, by the control circuit, the display data frame containing the second-resolution display data corresponding to the first partial display area of the display panel but not containing the display data corresponding to other display areas of the display panel except the first partial display area from the interface circuit, and driving, by the control circuit, the plurality of data lines based on the second-resolution display data, wherein the resolution of the second-resolution display data is lower than the resolution of the first-resolution display data.

17. The driving method according to claim 16, wherein The driving method further includes: In response to the display panel operating in the second partial panel display mode, the control circuit receives, from the interface circuit, the display data frame containing the display data corresponding to the second partial display area of the display panel but not containing the display data corresponding to other display areas of the display panel except the second partial display area, and the control circuit drives the plurality of data lines based on the third-resolution display data, where the resolution of the third-resolution display data is lower than the resolution of the first-resolution display data, and the second partial display area is different from the first partial display area.

18. The driving method according to claim 16, wherein In the full-panel display mode, during the frame period defined by the vertical synchronization information, the frame period corresponding to the display data frame includes a porch period, a first sub-frame scanning period corresponding to the first partial display area, and a second sub-frame scanning period corresponding to the second partial display area of the display panel, the second partial display area being different from the first partial display area, and the driving method further includes: In the full-panel display mode, the control circuit provides a first gate start pulse signal to the first gate scanning circuit corresponding to the first partial display area to trigger the first gate scanning circuit to perform gate scanning on the first partial display area of the display panel during the first sub-frame scanning period; and In the full-panel display mode, the control circuit provides a second gate start pulse signal to the second gate scanning circuit corresponding to the second partial display area to trigger the second gate scanning circuit to perform gate scanning on the second partial display area of the display panel during the second sub-frame scanning period.

19. The driving method according to claim 18, characterized in that, The driving method further includes: In the full-panel display mode, the control circuit provides a first emission start pulse signal to the first emission scanning circuit corresponding to the first partial display area to trigger the first emission scanning circuit to perform emission scanning on the first partial display area of the display panel during the first sub-frame scanning period; and In the full-panel display mode, the control circuit provides a second emission start pulse signal to the second emission scanning circuit corresponding to the second partial display area to trigger the second emission scanning circuit to perform emission scanning on the second partial display area of the display panel during the second sub-frame scanning period.

20. The driving method according to claim 16, characterized in that, In the first partial panel display mode, during the frame period defined by the vertical synchronization information, the frame period corresponding to the display data frame includes a first sub-frame scanning period corresponding to the first partial display area and a second sub-frame scanning period corresponding to the second partial display area of the display panel, the second partial display area being different from the first partial display area, and the driving method further includes: In the first partial panel display mode, the control circuit provides a first gate start pulse signal to the first gate scanning circuit corresponding to the first partial display area to trigger the first gate scanning circuit to perform gate scanning on the first partial display area of the display panel during the first sub-frame scanning period; The control circuit drives the plurality of data lines during the first sub-frame scan based on the second-resolution display data; In the first partial panel display mode, the control circuit causes the plurality of data lines to be maintained in a steady state during the second sub-frame scan due to the absence of display data corresponding to the second partial display area; and In the first partial panel display mode, the control circuit cancels the second gate start pulse signal to the second gate scan circuit to disable the second gate scan circuit from scanning the second partial display area during the second sub-frame scan.

21. The driving method according to claim 20, wherein, The driving method further includes: In the first partial panel display mode, the control circuit provides a first emission start pulse signal to the first emission scan circuit corresponding to the first partial display area to trigger the first emission scan circuit to scan the first partial display area of the display panel during the first sub-frame scan; and In the first partial panel display mode, the control circuit cancels the second emission start pulse signal to the second emission scan circuit to disable the second emission scan circuit from scanning the second partial display area during the second sub-frame scan.

22. The driving method according to claim 21, characterized in that, The driving method further includes: In the first partial panel display mode, by providing the first emission start pulse signal, all operations of the first partial display area of the display panel during the frame are in a normal display state; and In the first partial panel display mode, by canceling the second emission start pulse signal, all operations of the second partial display area of the display panel during the frame are in a non-display state.

23. The driving method according to claim 16, wherein In the first partial panel display mode, the vertical synchronization information defines the frame period. The frame period corresponding to the display data frame includes a porch period and the first sub-frame scan period corresponding to the first partial display area. There is no scan period corresponding to the second partial display area of the display panel during the frame period. The first partial display area is different from the second partial display area, and the driving method further includes: In the first partial panel display mode, the control circuit provides a first gate start pulse signal to the first gate scan circuit corresponding to the first partial display area to trigger the first gate scan circuit to scan the first partial display area of the display panel during the first sub-frame scan; The control circuit drives the plurality of data lines during the first sub-frame scan based on the second-resolution display data; and In the first partial panel display mode, the control circuit cancels the second gate start pulse signal to the second gate scan circuit to disable the second gate scan circuit from scanning the second partial display area.

24. The driving method according to claim 23, wherein The driving method further includes: In the first partial panel display mode, the control circuit provides a first emission start pulse signal to a first emission scanning circuit corresponding to the first partial display area, so as to trigger the first emission scanning circuit to perform emission scanning on the first partial display area of the display panel during the first sub-frame scan; and In the first partial panel display mode, the control circuit cancels the second emission start pulse signal to the second emission scanning circuit, so as to disable the emission scanning of the second emission scanning circuit on the second partial display area.

25. The driving method according to claim 24, wherein The driving method further includes: In the first partial panel display mode, by providing the first emission start pulse signal, all operations of the first partial display area of the display panel during the frame are in the normal display state; and In the first partial panel display mode, by canceling the second emission start pulse signal, all operations of the second partial display area of the display panel during the frame are in the non-display state.

26. A display device, characterized in that, The display device includes: a processor; a display panel; and a display driving device for driving the display panel, wherein the display driving device is coupled to the processor to receive a data stream, and the data stream includes a display data frame and vertical synchronization information, In response to the display panel operating in the full panel display mode, the display data frame received by the display driving device from the processor contains first resolution display data corresponding to all display areas of the display panel, and the display driving device drives a plurality of data lines of the display panel based on the first resolution display data; and In response to the display panel operating in the first partial panel display mode, the display data frame received by the display driving device from the processor contains second resolution display data corresponding to the first partial display area of the display panel but does not contain display data corresponding to other display areas of the display panel except the first partial display area, and the display driving device drives the plurality of data lines based on the second resolution display data, wherein the resolution of the second resolution display data is lower than the resolution of the first resolution display data.

27. The display device according to claim 26, wherein The display driving device includes: a control circuit; and an interface circuit that receives the data stream from the processor, wherein the interface circuit is coupled to the control circuit to provide the display data frame and the vertical synchronization information of the data stream to the control circuit, In response to the display panel operating in the full panel display mode, the display data frame received by the control circuit from the interface circuit contains the first resolution display data, and the control circuit drives the plurality of data lines of the display panel based on the first resolution display data; and In response to the display panel operating in the first partial panel display mode, the display data frame received by the control circuit from the interface circuit contains the display data of the second resolution but does not contain the display data corresponding to other display areas of the display panel except the first partial display area, and the control circuit drives the plurality of data lines based on the display data of the second resolution.

28. The display device according to claim 27, wherein in response to the display panel operating in the second partial panel display mode, the display data frame received by the control circuit from the interface circuit contains the display data of the third resolution corresponding to the second partial display area of the display panel but does not contain the display data corresponding to other display areas of the display panel except the second partial display area, and the control circuit drives the plurality of data lines based on the display data of the third resolution, wherein the resolution of the display data of the third resolution is lower than the resolution of the display data of the first resolution, and the second partial display area is different from the first partial display area.

29. The display device according to claim 27, wherein In the full panel display mode: during the frame period defined by the vertical synchronization information, the frame period corresponding to the display data frame includes a porch period, a first sub-frame scanning period corresponding to the first partial display area, and a second sub-frame scanning period corresponding to the second partial display area of the display panel, wherein the second partial display area is different from the first partial display area; the control circuit provides a first gate start pulse signal to the first gate scanning circuit corresponding to the first partial display area to trigger the first gate scanning circuit to perform a gate scan on the first partial display area of the display panel during the first sub-frame scanning period; and the control circuit provides a second gate start pulse signal to the second gate scanning circuit corresponding to the second partial display area to trigger the second gate scanning circuit to perform a gate scan on the second partial display area of the display panel during the second sub-frame scanning period.

30. The display device according to claim 29, characterized in that, In the full panel display mode: the control circuit provides a first emission start pulse signal to the first emission scanning circuit corresponding to the first partial display area to trigger the first emission scanning circuit to perform an emission scan on the first partial display area of the display panel during the first sub-frame scanning period; and the control circuit provides a second emission start pulse signal to the second emission scanning circuit corresponding to the second partial display area to trigger the second emission scanning circuit to perform an emission scan on the second partial display area of the display panel during the second sub-frame scanning period.

31. The display device according to claim 27, wherein In the first partial panel display mode: during the frame period defined by the vertical synchronization information, the frame period corresponding to the display data frame includes a first sub-frame scanning period corresponding to the first partial display area and a second sub-frame scanning period corresponding to the second partial display area of the display panel, wherein the second partial display area is different from the first partial display area; The control circuit provides a first gate start pulse signal to a first gate scan circuit corresponding to the first partial display area, to trigger the first gate scan circuit to perform a gate scan on the first partial display area of the display panel during the first sub-frame scan; The control circuit drives the plurality of data lines based on the second-resolution display data during the first sub-frame scan; The control circuit causes the plurality of data lines to be maintained in a steady state during the second sub-frame scan due to the absence of display data corresponding to the second partial display area; And The control circuit cancels the second gate start pulse signal to the second gate scan circuit, to disable the second gate scan circuit from performing a gate scan on the second partial display area during the second sub-frame scan.

32. The display device according to claim 31, wherein, In the first partial panel display mode: The control circuit provides a first emission start pulse signal to a first emission scan circuit corresponding to the first partial display area, to trigger the first emission scan circuit to perform an emission scan on the first partial display area of the display panel during the first sub-frame scan; And The control circuit cancels the second emission start pulse signal to the second emission scan circuit, to disable the second emission scan circuit from performing an emission scan on the second partial display area during the second sub-frame scan.

33. The display device according to claim 32, wherein In the first partial panel display mode: By providing the first emission start pulse signal, all operations of the first partial display area of the display panel during the frame are in a normal display state; And By canceling the second emission start pulse signal, all operations of the second partial display area of the display panel during the frame are in a non-display state.

34. The display device according to claim 27, wherein In the first partial panel display mode: The vertical synchronization information defines a frame period, the frame period corresponding to the display data frame includes a porch period and a first sub-frame scan period corresponding to the first partial display area, wherein there is no scan period corresponding to the second partial display area of the display panel during the frame period, and the first partial display area is different from the second partial display area; The control circuit provides a first gate start pulse signal to a first gate scan circuit corresponding to the first partial display area, to trigger the first gate scan circuit to perform a gate scan on the first partial display area of the display panel during the first sub-frame scan; The control circuit drives the plurality of data lines based on the second-resolution display data during the first sub-frame scan; and The control circuit cancels the second gate start pulse signal to the second gate scan circuit, to disable the second gate scan circuit from performing a gate scan on the second partial display area.

35. The display device according to claim 34, wherein In the first partial panel display mode: The control circuit provides a first emission start pulse signal to a first emission scan circuit corresponding to the first partial display area, to trigger the first emission scan circuit to perform an emission scan on the first partial display area of the display panel during the first sub-frame scan; And The control circuit cancels the second emission start pulse signal given to the second emission scanning circuit to disable the emission scanning of the second emission scanning circuit for the second partial display area.

36. The display device according to claim 35, characterized in that, In the first partial panel display mode: By providing the first emission start pulse signal, all operations of the first partial display area of the display panel during the frame are in the normal display state; And By canceling the second emission start pulse signal, all operations of the second partial display area of the display panel during the frame are in the non-display state.

37. The display device according to claim 27, characterized in that, The control circuit includes: At least one processing circuit, coupled to the interface circuit to receive the display data frame, wherein the at least one processing circuit performs at least one image processing on the display data frame to generate a processed data frame; A timing circuit, coupled to the at least one processing circuit to receive the processed data frame, wherein the timing circuit controls the operation timing of the control circuit based on the vertical synchronization information; and A source signal control circuit, coupled to the timing circuit to receive the processed data frame, wherein, In the full panel display mode, the processed data frame received by the source signal control circuit from the timing circuit contains the first resolution display data, and the source signal control circuit drives the plurality of data lines based on the first resolution display data; and In the first partial panel display mode, the processed data frame received by the source signal control circuit from the timing circuit contains the second resolution display data but does not contain the display data corresponding to other display areas except the first partial display area, and the source signal control circuit drives the plurality of data lines based on the second resolution display data.

38. The display device according to claim 37, wherein The vertical synchronization information defines a frame period. The frame period corresponding to the display data frame includes a porch period, a first sub-frame scanning period corresponding to the first partial display area, and a second sub-frame scanning period corresponding to the second partial display area of the display panel. The control circuit further includes: A gate signal control circuit, coupled to the timing circuit, wherein, In the full panel display mode, the gate signal control circuit, based on the timing control of the timing circuit, provides a first gate start pulse signal to the first gate scanning circuit corresponding to the first partial display area to trigger the first gate scanning circuit to perform a gate scan on the first partial display area during the first sub-frame scanning period, and provides a second gate start pulse signal to the second gate scanning circuit corresponding to the second partial display area to trigger the second gate scanning circuit to perform a gate scan on the second partial display area during the second sub-frame scanning period; and In the first partial panel display mode, the gate signal control circuit provides the first gate start pulse signal to the first gate scanning circuit based on the timing control of the timing circuit to trigger the first gate scanning circuit to perform gate scanning on the first partial display area during the first sub-frame scan. The source signal control circuit drives the plurality of data lines during the first sub-frame scan based on the second resolution display data. The gate signal control circuit cancels the second gate start pulse signal to disable the second gate scanning circuit from performing gate scanning on the second partial display area during the second sub-frame scan. And the source signal control circuit keeps the plurality of data lines in a steady state during the second sub-frame scan because there is no display data corresponding to the second partial display area.

39. The display device according to claim 38, wherein The control circuit further includes: A transmission signal control circuit, coupled to the timing circuit, wherein, In the full panel display mode, the transmission signal control circuit provides a first transmission start pulse signal to the first transmission scanning circuit corresponding to the first partial display area based on the timing control of the timing circuit to trigger the first transmission scanning circuit to perform transmission scanning on the first partial display area during the first sub-frame scan, and provides a second transmission start pulse signal to the second transmission scanning circuit corresponding to the second partial display area to trigger the second transmission scanning circuit to perform transmission scanning on the second partial display area during the second sub-frame scan; and In the first partial panel display mode, the transmission signal control circuit provides the first transmission start pulse signal to the first transmission scanning circuit based on the timing control of the timing circuit to trigger the first transmission scanning circuit to perform transmission scanning on the first partial display area during the first sub-frame scan, and cancels the second transmission start pulse signal to disable the second transmission scanning circuit from performing transmission scanning on the second partial display area during the second sub-frame scan.

40. The display device according to claim 37, wherein During the period defined by the vertical synchronization information frame, the control circuit further includes: A gate signal control circuit, coupled to the timing circuit, wherein, In the first partial panel display mode, the period of the frame corresponding to the display data frame includes a porch period and the first sub-frame scan period corresponding to the first partial display area but does not include the scan period corresponding to the second partial display area of the display panel. The gate signal control circuit provides a first gate start pulse signal to the first gate scanning circuit corresponding to the first partial display area based on the timing control of the timing circuit to trigger the first gate scanning circuit to perform gate scanning on the first partial display area during the first sub-frame scan. The source signal control circuit drives the plurality of data lines during the first sub-frame scan based on the second resolution display data. And the gate signal control circuit cancels the second gate start pulse signal for the second gate scanning circuit to disable the second gate scanning circuit from performing gate scanning on the second partial display area.

41. The display device according to claim 40, characterized in that, The control circuit further includes: A transmission signal control circuit is coupled to the timing circuit, wherein, in the first partial panel display mode, the transmission signal control circuit, based on the timing control of the timing circuit, provides a first transmission start pulse signal to a first transmission scanning circuit corresponding to the first partial display area to trigger the first transmission scanning circuit to perform transmission scanning on the first partial display area during the first sub-frame scanning, and cancels the second transmission start pulse signal to the second transmission scanning circuit to disable the second transmission scanning circuit from performing transmission scanning on the second partial display area.

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