Gate driving circuit, array substrate, display panel and display device

Abstract

The present invention provides a gate driving circuit, an array substrate, a display panel and a display device. The gate driving circuit includes a plurality of gate driving units. Among them, odd-numbered gate driving units are respectively connected to the first m1 gate driving units, the last n1 gate driving units, the first n1 gate driving units and the last m1 gate driving units, and even-numbered gate driving units are respectively connected to the first m2 gate driving units, the last n2 gate driving units, the first n2 gate driving units and the last m2 gate driving units, so as to achieve the cascade charging, resetting and output of each gate driving unit. And m1 < m2, and / or n1 > n2, which reduces the charging rate of pixel units connected to odd-numbered gate driving units and / or increases the charging rate of pixel units connected to even-numbered gate driving units, ultimately making the brightness of pixel units in odd rows and even rows consistent and weakening the bright and dark lines.

Description

Technical Field

[0001] The present invention belongs to the technical field of display devices, and in particular relates to a gate drive circuit, an array substrate, a display panel and a display device. Background Art

[0002] A liquid crystal display panel is usually composed of a color film substrate, a liquid crystal layer and an array substrate. The array substrate is provided with a display area and a non-display area. The display area is provided with corresponding data lines, scan lines and a pixel array. The pixel array is composed of pixel units arranged in an array. The pixel units are connected to the data lines and scan lines respectively. The scan lines are used to input row scan signals line by line, and the data lines are used to input data signals. The pixel units display according to the received row scan signals and data signals.

[0003] Due to the row-by-row output of the row scan signal, the pixel units connected to the odd-numbered scan lines will be coupled with the row scan signal once, while the pixel units connected to the even-numbered scan lines will be coupled downward once during the charging process due to the cutoff of the row scan signal of the previous odd-numbered row. Therefore, they are coupled with the row scan signal twice, resulting in the charging efficiency of the pixel units connected to the even-numbered scan lines being lower than the charging efficiency of the pixel units connected to the odd-numbered scan lines, causing bright and dark lines in the horizontal or vertical direction.

[0004] Among them, the pixel units can be connected to the data lines and scan lines in different architectures, for example, connected to the data lines and scan lines in a DRG arrangement architecture. In the DRG architecture, two scan lines are arranged between the pixel units in adjacent rows, and the pixel units in each even column are a group, for example, 12 columns of pixel units are a group, wherein the pixel units in the first half of each pixel unit group are connected to the scan lines of the odd rows, and the pixel units in the second half are connected to the pixel units in the even rows, and the two columns of pixel units separated by 6 columns in each group are connected to the same data line. When the pixel units are arranged in a DRG architecture, due to the different charging rates of the odd rows and the even rows, vertical bright and dark lines will appear in the column direction of the pixel unit group. Summary of the Invention

[0005] The present invention aims to provide a gate driving circuit to solve the problem of bright and dark lines in traditional display panels.

[0006] A first aspect of an embodiment of the present invention provides a gate drive circuit, including:

[0007] a plurality of gate driving units, wherein the plurality of gate driving units are sequentially connected to the plurality of scanning lines of the display panel and are used to output row scanning signals row by row;

[0008] Among them, the input end of the (2i - 1)-th gate driving unit is connected to the output end of the (2i - 1 - m1)-th gate driving unit and performs pre-charging when receiving the row scanning signal of the (2i - 1 - m1)-th level. The reset end of the (2i - 1)-th gate driving unit is connected to the output end of the (2i - 1 + n1)-th gate driving unit and performs discharge reset when receiving the row scanning signal of the (2i - 1 + n1)-th level. The output end of the (2i - 1)-th gate driving unit is respectively connected to the reset end of the (2i - 1 - n1)-th gate driving unit and the input end of the (2i - 1 + m1)-th gate driving unit and is used to input the row scanning signal of this level;

[0009] The input end of the 2i-th gate driving unit is connected to the output end of the (2i - m2)-th gate driving unit and performs pre-charging when receiving the row scanning signal of the (2i - m2)-th level. The reset end of the 2i-th gate driving unit is connected to the output end of the (2i + n2)-th gate driving unit and performs discharge reset when receiving the row scanning signal of the (2i + n2)-th level. The output end of the 2i-th gate driving unit is respectively connected to the reset end of the (2i - n2)-th gate driving unit and the input end of the (2i + m2)-th gate driving unit and is used to input the row scanning signal of this level, where i, m1, n1, m2, n2 are positive integers;

[0010] i > 1, m1 < m2, and / or n1 > n2.

[0011] Optionally, m2 - m1 = m3, n1 - n2 = n3, and m3 and n3 are even numbers.

[0012] Optionally, n1 = m2 = 4, m1 = n2 = 2.

[0013] Optionally, the input ends from the first gate driving unit to the m1-th gate driving unit are used to input the frame start signal and perform pre-charging;

[0014] The input ends of the 2i-th gate driving unit among the m1-th gate driving unit to the m2-th gate driving unit are used to input the frame start signal and perform pre-charging.

[0015] Optionally, clock signals are respectively input to the clock ends of each gate driving unit, and the clock signals input to each gate driving unit differ by a preset phase in sequence.

[0016] Optionally, the gate driving unit at least includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, and a capacitor;

[0017] The control terminal and the first terminal of the first thin film transistor constitute an input terminal of the gate driving unit, the second terminal of the first thin film transistor, the first terminal of the capacitor, the first terminal of the fourth thin film transistor, and the control terminal of the second thin film transistor are connected, the first terminal of the second thin film transistor constitutes a clock terminal of the gate driving unit, the second terminal of the second thin film transistor, the first terminal of the third thin film transistor, and the second terminal of the capacitor are connected to constitute an output terminal of the gate driving unit, the second terminal of the third thin film transistor and the second terminal of the fourth thin film transistor are used to input a low-level signal, and the control terminal of the third thin film transistor and the control terminal of the fourth thin film transistor are connected to constitute a reset terminal of the gate driving unit;

[0018] The width-to-length ratio of the first thin film transistor of the 2i-1th gate driving unit is smaller than the width-to-length ratio of the first thin film transistor of the 2ith gate driving unit;

[0019] and / or, the width-to-length ratio of the third thin film transistor of the 2i-1th gate driving unit is greater than the width-to-length ratio of the third thin film transistor of the 2ith gate driving unit;

[0020] The width-to-length ratio of the fourth thin film transistor of the 2i-1th gate driving unit is greater than the width-to-length ratio of the fourth thin film transistor of the 2ith gate driving unit.

[0021] A second aspect of an embodiment of the present invention proposes an array substrate, comprising a display area and a non-display area, wherein the non-display area is bonded with the gate drive circuit as described above, and the display area comprises data lines, scan lines and a pixel array, wherein the data lines are used to input data signals of corresponding polarities, and the scan lines are used to input row scan signals row by row, and the pixel array comprises pixel units arranged in an array, and the gate drive circuit is correspondingly connected to a plurality of the scan lines.

[0022] Optionally, every 2k1 columns of pixel units constitute a pixel unit group, and the pixel units in the jth column and the pixel units in the j+k1th column in the k2th pixel unit group are connected to the (k2-1)*k1+j1th column of data lines;

[0023] Two scan lines are set between the pixel units in adjacent rows, the pixel units in the first k1 columns of the pixel unit group in the k3th row are connected to the 2k3-1th scan line, and the pixel units in the last k1 columns of the pixel unit group in the k3th row are connected to the 2k3th scan line, and k1, k2, k3, and j are positive integers.

[0024] A third aspect of the embodiments of the present invention provides a display panel, including a color filter substrate, a liquid crystal layer, and the array substrate as described above, wherein the liquid crystal layer is located between the color filter substrate and the array substrate.

[0025] A fourth aspect of the embodiments of the present invention provides a display device, including a backlight module, a driving circuit of a display panel, and the display panel as described above. The display panel driving circuit is correspondingly connected to the display panel, and the backlight module is disposed opposite to the display panel.

[0026] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: The above-mentioned gate driving circuit includes multiple gate driving units. Among them, the (2i - 1)-th gate driving unit is respectively connected to the output terminal of the (2i - 1 - m1)-th gate driving unit, the output terminal of the (2i - 1 + n1)-th gate driving unit, the reset terminal of the (2i - 1 - n1)-th gate driving unit, and the input terminal of the (2i - 1 + m1)-th gate driving unit to achieve stage transfer pre-charging and resetting. The 2i-th gate driving unit is respectively connected to the output terminal of the (2i - m2)-th gate driving unit, the output terminal of the (2i + n2)-th gate driving unit, the reset terminal of the (2i - n2)-th gate driving unit, and the input terminal of the (2i + m2)-th gate driving unit to achieve stage transfer charging and resetting, and m1 < m2, and / or n1 > n2, which reduces the charging rate of pixel units connected to the gate driving units of odd rows and / or increases the charging rate of pixel units connected to the gate driving units of even rows, ultimately making the brightness of pixel units in odd rows and even rows consistent and weakening the bright and dark lines. Description of the Drawings

[0027] Figure 1 It is a schematic structural diagram of a gate driving circuit of a traditional architecture;

[0028] Figure 2 It is a schematic waveform diagram of a row scanning signal output by a traditional gate driving circuit;

[0029] Figure 3 It is a schematic waveform diagram of a driving signal received by a traditional pixel unit;

[0030] Figure 4 It is a first schematic structural diagram of a gate driving circuit provided in Embodiment One of the present invention;

[0031] Figure 5 It is a second schematic structural diagram of a gate driving circuit provided in Embodiment One of the present invention;

[0032] Figure 6 It is a schematic waveform diagram of a row scanning signal output by a gate driving circuit provided in Embodiment One of the present invention;

[0033] Figure 7 It is a schematic waveform diagram of a driving signal received by a pixel unit provided in Embodiment One of the present invention;

[0034] Figure 8A first circuit diagram of a gate driving unit provided in the second embodiment of the present invention;

[0035] Figure 9 A second circuit diagram of a gate driving unit provided in the second embodiment of the present invention;

[0036] Figure 10 A schematic structural diagram of an array substrate provided in a third embodiment of the present invention;

[0037] Figure 11 A schematic structural diagram of a pixel array provided in a third embodiment of the present invention;

[0038] Figure 12 A schematic structural diagram of a display panel provided in a fourth embodiment of the present invention;

[0039] Figure 13 This is a structural diagram of a display device provided in Example 5 of the present invention.

[0040] Among them, the reference numerals in the figures are:

[0041] 100, display panel; 200, display panel drive circuit, 300, backlight module; 1, array substrate; 2, color filter substrate; 3, liquid crystal layer; 110, display area; 111, pixel array; 120, non-display area; 10, gate drive circuit; 11, gate drive unit; 101, pixel unit; 102, scan line; 103, data line;

[0042] T1, first thin film transistor; T2, second thin film transistor; T3, third thin film transistor; T4, fourth thin film transistor; C, capacitor; G, row scan signal; Tr, precharge time; Tf, discharge time; CK, clock signal; STV, start signal. DETAILED DESCRIPTION

[0043] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0044] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0045] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present invention.

[0046] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0047] Example 1

[0048] A first aspect of an embodiment of the present invention provides a gate drive circuit 10, such as Figure 1 and Figure 2 As shown, the gate driving circuit 10 includes a plurality of gate driving units 11, which are sequentially connected to a plurality of scanning lines 102 of the display panel 100 and are used to output high-level row scanning signals G row by row. The multiple row scanning signals G are output to the display panel 100 and turn on each row of pixel units 101 row by row.

[0049] The gate driving unit 11 may be composed of a plurality of thin film transistors and capacitors. The gate driving units 11 may be cascaded in sequence or cascaded at intervals, for example Figure 1 As shown, each gate driving unit 11 is respectively connected to four gate driving units 11 apart. For example, the fifth gate driving unit 11 is respectively connected to the first gate driving unit 11 and the ninth gate driving unit 11, and the sixth gate driving unit 11 is respectively connected to the second gate driving unit 11 and the tenth gate driving unit 11. Taking the fifth gate driving unit 11 as an example, the gate driving unit 11 generally includes a pre-charging period, an output period, and a discharge reset period. The fifth gate driving unit 11 receives the high-level row scanning signal G output by the first gate driving unit 11 and performs pre-charging. When the clock signal CK of this stage arrives, the high-level row scanning signal G of this stage is output to the scan line 102 of the fifth row. At the same time, the row scanning signal G output by this stage is output to the first gate driving unit 11 as a reset signal for reset discharge and is input to the ninth gate driving unit 11 as an input signal for pre-charging. At the same time, this stage also receives the high-level row scanning signal G of the ninth gate driving unit 11 for reset discharge. Each gate driving unit 11 performs pre-charging, output, and discharge reset operations in sequence.

[0050] Among them, as Figure 3 shown, due to the progressive output of the line scanning signal G, the pixel unit 101 connected to the odd-numbered line scanning line 102 will be coupled by the line scanning signal G once. And during the charging process of the pixel unit 101 connected to the even-numbered line scanning line 102, due to the fall of the line scanning signal G of the previous odd-numbered line, the pixel unit 101 connected to the even-numbered line scanning line 102 will be coupled downward once during the charging process. Therefore, it is coupled by the line scanning signal G twice before and after, resulting in the charging efficiency of the pixel unit 101 connected to the even-numbered line scanning line 102 being lower than that of the pixel unit 101 connected to the odd-numbered line scanning line 102, causing bright and dark lines in the horizontal or vertical direction.

[0051] To solve the problem of bright and dark lines, in this embodiment, as Figure 4 shown, the input end of the (2i - 1)-th gate driving unit 11 is connected to the output end of the (2i - 1 - m1)-th gate driving unit 11 and performs pre-charging when receiving the line scanning signal G of the (2i - 1 - m1)-th stage. The reset end of the (2i - 1)-th gate driving unit 11 is connected to the output end of the (2i - 1 + n1)-th gate driving unit 11 and performs discharge reset when receiving the line scanning signal G of the (2i - 1 + n1)-th stage. The output end of the (2i - 1)-th gate driving unit 11 is respectively connected to the reset end of the (2i - 1 - n1)-th gate driving unit 11 and the input end of the (2i - 1 + m1)-th gate driving unit 11 and is used to input the line scanning signal G of this stage;

[0052] The input end of the (zhi 2i)-th gate driving unit 11 is connected to the output end of the (2i - m2)-th gate driving unit 11 and performs pre-charging when receiving the line scanning signal G of the (2i - m2)-th stage. The reset end of the (2i)-th gate driving unit 11 is connected to the output end of the (2i + n2)-th gate driving unit 11 and performs discharge reset when receiving the line scanning signal G of the (2i + n2)-th stage. The output end of the (2i)-th gate driving unit 11 is respectively connected to the reset end of the (2i - n2)-th gate driving unit 11 and the input end of the (2i + m2)-th gate driving unit 11 and is used to input the line scanning signal G of this stage, where i, m1, n1, m2, n2 are positive integers;

[0053] i > 1, m1 < m2, and / or n1 > n2.

[0054] In this embodiment, the conventional stage transmission method of the gate driving unit 11 is changed. Among them, the stage transmission method of the gate driving unit 11 for odd-numbered lines is changed to 2i - 1 - m1 and 2i - 1 + n1, and the stage transmission method of the gate driving unit 11 for even-numbered lines is changed to 2i - m2 and 2i + n2.

[0055] That is, the input end of the 2i-1th gate driving unit 11 receives the high-level row scanning signal G output by the 2i-1-m1th gate driving unit 11 for pre-charging, and the reset end receives the high-level row scanning signal G output by the 2i-1+n1th gate driving unit 11 for discharge reset, and outputs the high-level row scanning signal G of this level when the clock signal CK of this level arrives, and the row scanning signal G of this level is output to the reset end of the 2i-1-n1th gate driving unit 11 as a reset signal to discharge and reset the 2i-1-n1th gate driving unit 11. At the same time, the row scanning signal G of this level is output to the input end of the 2i-1+m1th gate driving unit 11 as an input signal to pre-charge the 2i-1+m1th gate driving unit 11, wherein m1 and n1 are not equal.

[0056] The input end of the 2i-th gate driving unit 11 receives the high-level row scanning signal G output by the 2i-m2 gate driving unit 11 for pre-charging, and the reset end receives the high-level row scanning signal G output by the 2i+n2 gate driving unit 11 for discharge and reset, and outputs the high-level row scanning signal G of this stage when the clock signal CK of this stage arrives. The row scanning signal G of this stage is output to the reset end of the 2i-n2 gate driving unit 11 as a reset signal to discharge and reset the 2i-n2 gate driving unit 11. At the same time, the row scanning signal G of this stage is output to the input end of the 2i+m2 gate driving unit 11 as an input signal to pre-charge the 2i+m2 gate driving unit 11, wherein m2 and n2 are not equal.

[0057] like Figure 4 As shown, assuming that m1=2 and n1=4, taking the fifth gate driving unit 11 as an example, the fifth gate driving unit 11 receives the high-level row scanning signal G of the third gate driving unit 11 for pre-charging, and then, when the clock signal CK of the current stage arrives, the fifth gate driving unit 11 outputs the current-stage row scanning signal G to the corresponding connected fifth row scanning line 102 and outputs it to the connected pixel unit 101 through the odd-numbered row scanning lines 102. At the same time, the current-stage row scanning signal G is also output to the reset end of the first gate driving unit 11, and the first gate driving unit 11 is discharged and reset. The row scanning signal G of the first gate driving unit 11 gradually decreases from a high level to a low level. At the same time, the output row scanning signal G is output to the input end of the seventh gate driving unit 11, and the seventh gate driving unit 11 is pre-charged. Then, the row scanning signal G of the ninth gate driving unit 11 is received for discharge and reset.

[0058] like Figure 4As shown, assuming that m2=4 and n1=2, taking the sixth gate driving unit 11 as an example, the sixth gate driving unit 11 receives the high-level row scanning signal G of the second gate driving unit 11 for pre-charging, and then, when the clock signal CK of the current stage arrives, the sixth gate driving unit 11 outputs the current-stage row scanning signal G to the corresponding connected sixth row scanning line 102 and outputs it to the connected pixel unit 101 through the even-numbered row scanning line 102. At the same time, the current-stage row scanning signal G is also output to the reset end of the fourth gate driving unit 11, and the fourth gate driving unit 11 is discharged and reset. The row scanning signal G of the fourth gate driving unit 11 gradually decreases from a high level to a low level. At the same time, the output row scanning signal G is output to the input end of the tenth gate driving unit 11, and the tenth gate driving unit 11 is pre-charged, and then receives the row scanning signal G of the eighth gate driving unit 11 for discharge and reset.

[0059] In order to achieve the same charging rate and brightness of the pixel units 101 connected to the gate driving units 11 of odd rows and the pixel units 101 connected to the gate driving units 11 of even rows, m1 is set to be smaller than m2, for example, m1=2, m2=4, as shown in FIG. Figure 6 and Figure 7 As shown, when so configured, the gate driving units 11 of the odd rows receive the row scanning signals G of the previous gate driving units 11 that differ by two levels for pre-charging, and the gate driving units 11 of the even rows receive the row scanning signals G of the previous gate driving units 11 that differ by four levels for pre-charging. The pre-charging time Tr of the gate driving units 11 of the odd rows is greater than the pre-charging time Tr of the gate driving units 11 of the even rows, and the pre-charging rate of the gate driving units 11 of the odd rows is less than the pre-charging rate of the gate driving units 11 of the even rows. The overall output of the gate driving units 11 of the odd rows is reduced. Correspondingly, the charging rates of the several pixel units 101 connected to the gate driving units 11 of the odd rows through the corresponding scanning lines 102 are relatively reduced, and the charging rates of the several pixel units 101 connected to the gate driving units 11 of the even rows through the corresponding scanning lines 102 are relatively increased. Ultimately, the charging rates and brightness of the pixel units 101 in different rows or columns are made the same, thereby eliminating bright and dark lines and improving the display effect.

[0060] And / or, set n1 greater than n2, for example, n1=4, n2=2, as Figure 6 and Figure 7As shown, when so configured, the gate driving units 11 of the odd rows receive the row scanning signals G of the gate driving units 11 four levels behind to perform reset discharge, and the gate driving units 11 of the even rows receive the row scanning signals G of the gate driving units 11 two levels behind to perform reset discharge, wherein the sizes of the areas a and b in the figure represent the charging rates, the discharge time Tf of the gate driving units 11 of the odd rows is less than the discharge time Tf of the gate driving units 11 of the even rows, and the overall output of the gate driving units 11 of the even rows increases, and correspondingly, the charging rates of the several pixel units 101 connected to the gate driving units 11 of the odd rows through the corresponding scanning lines 102 are relatively reduced, and the charging rates of the several pixel units 101 connected to the gate driving units 11 of the even rows through the corresponding scanning lines 102 are relatively increased, ultimately making the charging rates and brightness of the pixel units 101 in different rows or columns the same, eliminating bright and dark lines, and improving the display effect.

[0061] Among them, m1 and n2 can be equal or unequal, and n1 and m2 can be equal or unequal, for example Figure 5 As shown, assuming that m1=1, m2=3, n1=4, and n2=2, taking the fourth gate driving unit 11 and the fifth gate driving unit 11 as an example, for the fifth gate driving unit 11 of the odd row, it receives the high-level row scanning signal G of the fourth gate driving unit 11 for pre-charging, and then, when the clock signal CK of the current stage arrives, the fifth gate driving unit 11 outputs the current stage row scanning signal G to the corresponding connected fifth row scan line 102 and outputs it to the connected pixel unit 101 through the odd row scan line 102. At the same time, the current stage row scanning signal G is also output to the reset end of the first gate driving unit 11, and the first gate driving unit 11 is discharged and reset. The row scanning signal G of the first gate driving unit 11 gradually decreases from a high level to a low level. At the same time, the output row scanning signal G is output to the input end of the eighth gate driving unit 11, and the eighth gate driving unit 11 is pre-charged. Then, the row scanning signal G of the ninth gate driving unit 11 is received for discharge and reset.

[0062] For the fourth gate driving unit 11 of the even row, it receives the high-level row scanning signal G of the th gate driving unit 11 for pre-charging. Then, when the clock signal CK of the current stage arrives, the fourth gate driving unit 11 outputs the current stage row scanning signal G to the corresponding connected fourth row scanning line 102 and outputs it to the connected pixel unit 101 through the odd row scanning line 102. At the same time, the current stage row scanning signal G is also output to the reset end of the second gate driving unit 11, and the second gate driving unit 11 is discharged and reset. The row scanning signal G of the second gate driving unit 11 gradually decreases from a high level to a low level. At the same time, the output row scanning signal G is output to the input end of the fifth gate driving unit 11, and the fifth gate driving unit 11 is pre-charged. Then, the row scanning signal G of the sixth gate driving unit 11 is received for discharge and reset.

[0063] The gate drive units 11 of the odd rows receive the row scanning signal G of the gate drive units 11 that are one level ahead for pre-charging, and the gate drive units 11 of the even rows receive the row scanning signal G of the gate drive units 11 that are three levels ahead for pre-charging. The pre-charging time Tr of the gate drive units 11 of the odd rows is greater than the pre-charging time Tr of the gate drive units 11 of the even rows, and the pre-charging rate of the gate drive units 11 of the odd rows is less than the pre-charging rate of the gate drive units 11 of the even rows. Ultimately, the pixel units 101 in different rows or columns have the same charging rate and brightness, thereby eliminating bright and dark lines and improving the display effect.

[0064] The gate driving units 11 of the odd rows receive the row scanning signal G of the gate driving units 11 with a difference of four levels behind them to perform reset discharge, and the gate driving units 11 of the even rows receive the row scanning signal G of the gate driving units 11 with a difference of two levels behind them to perform reset discharge. The charging rates of the several pixel units 101 connected to the gate driving units 11 of the odd rows through the corresponding scanning lines 102 are relatively reduced, and the charging rates of the several pixel units 101 connected to the gate driving units 11 of the even rows through the corresponding scanning lines 102 are relatively increased, ultimately making the charging rates and brightness of the pixel units 101 in different rows or columns the same, eliminating bright and dark lines, and improving the display effect.

[0065] For example, when the pixel units 101 in the same row are connected to the same scan line 102, by changing the level transmission mode of the gate driving unit 11, the brightness of the pixel units 101 in odd and even rows can be made consistent, thereby eliminating horizontal bright and dark lines and improving the display effect.

[0066] Alternatively, when multiple pixel units 101 in the same column are staggeredly connected to two adjacent scan lines 102, for example, in the first row, the odd-numbered pixel units 101 are connected to the first scan line 102, and the even-numbered pixel units 101 are connected to the second scan line 102, by changing the level transmission mode of the gate driving unit 11, the brightness of the pixel units 101 in the odd columns and the pixel units 101 in the even columns can be made consistent, vertical bright and dark lines can be eliminated, and the display effect can be improved.

[0067] Among them, m1, m2, n1, and n2 can be set accordingly according to the size limitation rules specified above, and the specific size is not limited.

[0068] Among them, since the gate driving units 11 of adjacent odd rows and the gate driving units 11 of even rows themselves differ by one level, if the two gate driving units 11 connected to the input ends of the gate driving units 11 of adjacent odd rows and the gate driving units 11 of even rows differ by an odd level, the input ends of the gate driving units 11 of adjacent odd rows and the gate driving units 11 of even rows will be connected to the gate driving units 11 of the same level in front, resulting in individual gate driving units 11 having no reset signal input and causing abnormal operation, or, if the two gate driving units 11 connected to the output ends of the gate driving units 11 of adjacent odd rows and the gate driving units 11 of even rows differ by an odd level, the output ends of the gate driving units 11 of adjacent odd rows and the gate driving units 11 of even rows will be connected to the gate driving units 11 of the same level in the back, resulting in individual gate driving units 11 having no input signal input, pre-charging failure and abnormal operation.

[0069] For example, when m1=1, m2=4, n1=3, and n2=2, when so set, taking the fifth gate driving unit 11 and the sixth gate driving unit 11 as an example, the fifth gate driving unit 11 receives the high-level row scanning signal G of the fourth gate driving unit 11 for pre-charging, and then, when the clock signal CK of the current stage arrives, the fifth gate driving unit 11 outputs the current-stage row scanning signal G to the corresponding connected fifth row scanning line 102 and outputs it to the connected pixel unit 101 through the odd-numbered row scanning lines 102. At the same time, the current-stage row scanning signal G is also output to the reset end of the first gate driving unit 11, and the first gate driving unit 11 is discharged and reset. The row scanning signal G of the first gate driving unit 11 gradually decreases from a high level to a low level. At the same time, the output row scanning signal G is output to the input end of the sixth gate driving unit 11, and the sixth gate driving unit 11 is pre-charged. Then, the fifth gate driving unit 11 receives the row scanning signal G of the eighth gate driving unit 11 for discharge and reset.

[0070] The sixth gate driving unit 11 receives the high-level row scanning signal G of the second gate driving unit 11 for pre-charging. Then, when the clock signal CK of the current stage arrives, the sixth gate driving unit 11 outputs the current-stage row scanning signal G to the corresponding connected sixth row scanning line 102 and outputs it to the connected pixel unit 101 through the even-numbered row scanning line 102. At the same time, the current-stage row scanning signal G is also output to the reset end of the fourth gate driving unit 11, and the fourth gate driving unit 11 is discharged and reset. The row scanning signal G of the fourth gate driving unit 11 gradually decreases from a high level to a low level. At the same time, the output row scanning signal G is output to the input end of the tenth gate driving unit 11, and the tenth gate driving unit 11 is pre-charged. Then, the row scanning signal G of the eighth gate driving unit 11 is received for discharge and reset.

[0071] When such a setting is made, the third gate driving unit 11 and other gate driving units 11 may not have input signals or reset signals, causing abnormal operation of individual gate driving units 11. Therefore, in an optional embodiment, m2-m1=m3, n1-n2=n3, m3 and n3 are even numbers, n1=m2, m1=n2, for example, m1=1, n1=3, then m2=3, n2=1, m3=2, n3=2. With such a setting, still taking the fifth gate driving unit 11 and the sixth gate driving unit 11 as an example, the fifth gate driving unit 11 receives the high-level row scanning signal G of the fourth gate driving unit 11 for pre-charging, and then the fifth gate driving unit 11 is pre-charged. When the clock signal CK of this stage arrives, the element 11 outputs the row scan signal G of this stage to the corresponding connected fifth row scan line 102 and outputs it to the connected pixel unit 101 through the odd row scan lines 102. At the same time, the row scan signal G of this stage is also output to the reset end of the first gate driving unit 11, and the first gate driving unit 11 is discharged and reset. The row scan signal G of the first gate driving unit 11 gradually decreases from a high level to a low level. At the same time, the output row scan signal G is output to the input end of the sixth gate driving unit 11, and the sixth gate driving unit 11 is pre-charged. Then, the row scan signal G of the eighth gate driving unit 11 is received for discharge and reset.

[0072] The sixth gate driving unit 11 receives the high-level row scanning signal G of the third gate driving unit 11 for pre-charging. Then, when the clock signal CK of the current stage arrives, the sixth gate driving unit 11 outputs the current-stage row scanning signal G to the corresponding connected sixth row scanning line 102 and outputs it to the connected pixel unit 101 through the even-numbered row scanning line 102. At the same time, the current-stage row scanning signal G is also output to the reset end of the fifth gate driving unit 11, and the fifth gate driving unit 11 is discharged and reset. The row scanning signal G of the fifth gate driving unit 11 gradually decreases from a high level to a low level. At the same time, the output row scanning signal G is output to the input end of the ninth gate driving unit 11, and the ninth gate driving unit 11 is pre-charged. Then, the row scanning signal G of the seventh gate driving unit 11 is received for discharge and reset.

[0073] By such a configuration, each gate driving unit 11 can receive the input signal and the reset signal normally to perform pre-charging and discharge reset, thereby improving the display reliability of the pixel unit 101. In an optional embodiment, in order to realize interconnection and signal level transmission between the gate driving units 11 in odd rows, and to realize interconnection and signal level transmission between the gate driving units 11 in even rows, in an optional embodiment, m1, m2, n1, and n2 are even numbers. In an optional embodiment, as Figure 4 As shown, m1=n2=2, m2=n1=4.

[0074] That is, the gate driving unit 11 of the odd row receives the high-level row scanning signal G of the previous gate driving unit 11 with a difference of two levels for pre-charging, and then, when the clock signal CK of the current level arrives, the gate driving unit 11 of the odd row outputs the row scanning signal G of the current level to the corresponding connected odd row scanning line 102 and outputs it to the connected pixel unit 101 through the odd row scanning line 102. At the same time, the row scanning signal G of the current level is also output to the reset end of the previous gate driving unit 11 with a difference of four levels and discharges and resets it. At the same time, the output row scanning signal G is output to the input end of the next gate driving unit 11 with a difference of two levels and pre-charges it, and then receives the row scanning signal G of the next gate driving unit 11 with a difference of four levels for discharge and reset.

[0075] The gate driving unit 11 of the even row receives the high-level row scanning signal G of the previous gate driving unit 11 with a difference of four levels for pre-charging. Then, when the clock signal CK of the current level arrives, the gate driving unit 11 of the even row outputs the row scanning signal G of the current level to the corresponding connected scan line 102 of the even row and outputs it to the connected pixel unit 101 through the scan line 102 of the even row. At the same time, the row scanning signal G of the current level is also output to the reset end of the previous gate driving unit 11 with a difference of two levels and discharges and resets it. At the same time, the output row scanning signal G is output to the input end of the subsequent gate driving unit 11 with a difference of four levels and pre-charges it, and then receives the row scanning signal G of the subsequent gate driving unit 11 with a difference of two levels for discharge and reset.

[0076] Through such a setting, the gate driving units 11 of the odd rows can be interconnected and signal-level transmitted with the gate driving units 11 of the previous and next odd rows, and the gate driving units 11 of the even rows can be interconnected and signal-level transmitted with the gate driving units 11 of the previous and next even rows. Each gate driving unit 11 can normally receive the input signal and reset signal for pre-charging and discharge-resetting, complete the pre-charging, discharging and reset operations, and realize the normal driving operation of the display panel, thereby improving the display effect.

[0077] Correspondingly, since each gate driving unit 11 needs to receive the row scanning signal G output by the gate driving unit 11 of the previous stage as an input signal to achieve precharging, and the first gate driving unit 11 to the m2-th gate driving unit 11 have no corresponding gate driving unit 11 connected to the previous stage to achieve precharging, in order to ensure that each gate driving unit 11 achieves precharging, output and discharge reset, in an optional embodiment, the input end of the first gate driving unit 11 to the input end of the m1-th gate driving unit 11 are used to input the frame start signal and perform precharging;

[0078] The input end of the 2i-th gate driving unit 11 among the m1-th gate driving unit 11 to the m2-th gate driving unit 11 is used for inputting a frame start signal and performing pre-charging.

[0079] For example Figure 4 As shown, when m1=2 and m2=1, the input ends of the first gate driving unit 11 and the second gate driving unit 11 are used to input the frame start signal and perform precharging, and the fourth gate driving unit 11 uses the frame start signal STV as an input signal to perform precharging.

[0080] Furthermore, in order to ensure that each gate driving unit 11 normally outputs the row scanning signal G of the current stage, Figure 4As shown, in an optional embodiment, a clock signal CK is further input to the clock terminal of each gate driving unit 11 respectively. The clock signals CK input to each gate driving unit 11 differ by a preset phase in sequence. When each gate driving unit 11 receives the clock signal CK of its own stage, it turns on the switching transistor serving as the output unit inside and outputs the row scanning signal G of its own stage. The clock signals CK differ by a preset phase in sequence. Correspondingly, as Figure 6 shown, the row scanning signals G output by each gate driving unit 11 differ by a preset phase in sequence and are output to each row scanning line 102 and the pixel unit 101 of the corresponding row one by one.

[0081] The gate driving unit 11 can be composed of multiple thin film transistors and capacitors. For example, it can adopt a 4T1C architecture, an 8T1C architecture, etc. The specific structure is not limited.

[0082] The beneficial effects of the embodiment of the present invention compared with the prior art are as follows: The above-mentioned gate driving circuit 10 includes multiple gate driving units 11. Among them, the (2i - 1)-th gate driving unit 11 is respectively connected to the output terminal of the (2i - 1 - m1)-th gate driving unit 11, the output terminal of the (2i - 1 + n1)-th gate driving unit 11, the reset terminal of the (2i - 1 - n1)-th gate driving unit 11, and the input terminal of the (2i - 1 + m1)-th gate driving unit 11 to achieve stage transmission pre-charging and resetting. The 2i-th gate driving unit 11 is respectively connected to the output terminal of the (2i - m2)-th gate driving unit 11, the output terminal of the (2i + n2)-th gate driving unit 11, the reset terminal of the (2i - n2)-th gate driving unit 11, and the input terminal of the (2i + m2)-th gate driving unit 11 to achieve stage transmission charging and resetting. And m1 < m2, and / or n1 > n2, which reduces the charging rate of the pixel unit 101 connected to the gate driving unit 11 of odd rows and / or increases the charging rate of the pixel unit 101 connected to the gate driving unit 11 of even rows, and finally makes the brightness of the pixel units 101 of odd rows and even rows consistent and weakens the bright and dark lines.

[0083] Embodiment Two

[0084] As Figure 8 and Figure 9 shown, the gate driving unit 11 at least includes a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, and a capacitor C;

[0085] The control end and the first end of the first thin film transistor T1 constitute the input end of the gate driving unit 11. The second end of the first thin film transistor T1, the first end of the capacitor C, the first end of the fourth thin film transistor T4, and the control end of the second thin film transistor T2 are connected. The first end of the second thin film transistor T2 constitutes the clock end of the gate driving unit 11. The second end of the second thin film transistor T2, the first end of the third thin film transistor T3, and the second end of the capacitor C are connected to constitute the output end of the gate driving unit 11. The second end of the third thin film transistor T3 and the second end of the fourth thin film transistor T4 are used to input a low-level signal. The control end of the third thin film transistor T3 and the control end of the fourth thin film transistor T4 are connected to constitute the reset end of the gate driving unit 11.

[0086] In this embodiment, the first thin film transistor T1 constitutes a charging unit, the third thin film transistor T3 and the fourth thin film transistor T4 constitute a reset unit, and the second thin film transistor T2 constitutes an output unit. When the corresponding connected previous-stage gate driving unit 11 outputs the row scanning signal G, the first thin film transistor T1 is turned on and charges the capacitor C, the potential of the PU point rises, and the second thin film transistor T2 is in the on state. However, since the clock terminal linked to the second thin film transistor T2 does not input the clock signal CK of this stage at this time, the output of the gate driving unit 11 is a low level.

[0087] Then, when the clock signal CK is input, a capacitor C coupling is generated between the control end and the first end of the second thin-film transistor T2, and the potential of the PU point is synchronously pulled up. When the potential of the PU point increases, the conduction capability of the second thin-film transistor T2 increases, so that the gate drive unit 11 outputs a high-potential row scanning signal G.

[0088] Then, when receiving the row scan signal G from the gate driving unit 11 connected to the subsequent stage, the third thin film transistor T3 and the fourth thin film transistor T4 are turned on, so that the capacitor C is discharged and reset, and the second thin film transistor T2 is turned off, cutting off the output of the row scan signal G.

[0089] In order to further achieve uniform brightness of the pixel units 101 connected to the gate driving units 11 of odd rows and the pixel units 101 connected to the gate driving units 11 of even rows, in an optional embodiment, the width-to-length ratio of the first thin film transistor T1 of the 2i-1th gate driving unit 11 is smaller than the width-to-length ratio of the first thin film transistor T1 of the 2ith gate driving unit 11;

[0090] and / or, the width-to-length ratio of the third thin film transistor T3 of the 2i-1th gate driving unit 11 is greater than the width-to-length ratio of the third thin film transistor T3 of the 2ith gate driving unit 11;

[0091] The width-to-length ratio of the fourth thin film transistor T4 of the 2i-1th gate driving unit 11 is greater than the width-to-length ratio of the fourth thin film transistor T4 of the 2ith gate driving unit 11 .

[0092] In this embodiment, the width-to-length ratio of the first thin film transistor T1 of the gate driving unit 11 of the odd rows is relatively reduced, the pre-charging time Tr of the gate driving unit 11 of the odd rows is greater than the pre-charging time Tr of the gate driving unit 11 of the even rows, the pre-charging rate of the gate driving unit 11 of the odd rows is less than the pre-charging rate of the gate driving unit 11 of the even rows, and the overall output of the gate driving unit 11 of the odd rows is reduced. Correspondingly, the charging rate of the several pixel units 101 connected to the gate driving unit 11 of the odd rows through the corresponding scan lines 102 is relatively reduced, and the charging rate of the several pixel units 101 connected to the gate driving unit 11 of the even rows through the corresponding scan lines 102 is relatively increased, ultimately making the charging rate and brightness of the pixel units 101 in different rows or columns the same, eliminating bright and dark lines, and improving the display effect.

[0093] And / or, the width-to-length ratio of the third thin-film transistor T3 and the fourth thin-film transistor T4 of the gate driving unit 11 of the even-numbered rows is relatively reduced, the discharge time Tf of the gate driving unit 11 of the odd-numbered rows is shorter than the discharge time Tf of the gate driving unit 11 of the even-numbered rows, and the overall output of the gate driving unit 11 of the even-numbered rows is increased. Correspondingly, the charging rate of the several pixel units 101 connected to the gate driving unit 11 of the odd-numbered rows through the corresponding scan lines 102 is relatively reduced, and the charging rate of the several pixel units 101 connected to the gate driving unit 11 of the even-numbered rows through the corresponding scan lines 102 is relatively increased. Ultimately, the charging rate and brightness of the pixel units 101 in different rows or columns are made the same, bright and dark lines are eliminated, and the display effect is improved.

[0094] Example 3

[0095] The second aspect of the embodiment of the present invention provides an array substrate 1, such as Figure 10 As shown, the array substrate 1 includes a display area 110 and a non-display area 120. The non-display area 120 is bonded with a gate drive circuit 10. The specific structure of the gate drive circuit 10 is similar to the above-mentioned embodiments. Since the array substrate 1 adopts all the technical solutions of all the above-mentioned embodiments, it has at least all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, which will not be described in detail here. Among them, the display area 110 includes data lines 103, scan lines 102 and a pixel array 111. The data lines 103 are used to input data signals of corresponding polarity, and the scan lines 102 are used to input row scan signals G row by row. The pixel array 111 includes pixel units 101 arranged in an array. The gate drive circuit 10 is correspondingly connected to multiple scan lines 102.

[0096] A display area 110 and a non-display area 120 are provided on the array substrate 1. The display area 110 is provided with corresponding data lines 103, scan lines 102 and a pixel array 111. The pixel array 111 is composed of pixel units 101 arranged in an array. The pixel units 101 are connected to the data lines 103 and the scan lines 102 respectively. The scan lines 102 are used to input row scan signals G row by row, and the data lines 103 are used to input data signals. The pixel units 101 display according to the received row scan signals G and data signals. The multiple gate driving units 11 of the gate driving circuit 10 are sequentially bonded to the non-display area 120. The multiple gate driving units 11 are sequentially connected to the multiple scan lines 102 of the display panel 100 and are used to output high-level row scan signals G row by row. The multiple row scan signals G are output to the display panel 100 and turn on the pixel units 101 of each row row by row.

[0097] By adopting the gate driving unit 11 of the above-mentioned stage transmission method, it is possible to achieve uniform brightness of the pixel units 101 corresponding to odd rows and even rows or to achieve uniform brightness of the pixel units 101 corresponding to odd columns and even columns.

[0098] In an optional embodiment, the pixel array 111 is connected to the data line 103 and the scan line 102 using a DRG arrangement structure. In the DRG structure, every 2k1 columns of pixel units 101 constitute a pixel unit 101 group, and the j-th column of pixel units 101 and the j+k1-th column of pixel units 101 in the k2-th pixel unit 101 group are connected to the (k2-1)*k1+j1-th column of data line 103.

[0099] Two scan lines 102 are set between the pixel units 101 in adjacent rows, the first k1 columns of pixel units 101 in the k3-th row of pixel units 101 are connected to the 2k3-1 scan line 102, and the last k1 columns of pixel units 101 in the k3-th row of pixel units 101 are connected to the 2k3-1 scan line 102, where k1, k2, k3, and j are positive integers.

[0100] In the DRG architecture, two scan lines 102 are provided between adjacent rows of pixel units 101, and each even-numbered column of pixel units 101 forms a group. Figure 11 As shown, assuming that k1 is 6, in the pixel array 111, 12 columns of pixel units 101 are grouped together. For example, in the first pixel unit 101 group in the first row, the first six pixel units 101 are connected to the scan lines 102 of the odd rows, and the last six pixel units 101 are connected to the pixel units 101 of the even rows, and the two columns of pixel units 101 separated by 6 columns in each group are connected to the same data line 103. When the pixel units 101 are arranged in a DRG architecture, due to the different charging rates of the odd rows and the even rows, vertical bright and dark lines will appear in the column direction of the pixel unit 101 group. Specifically, the first 6 columns are bright lines, and the next 6 columns are dark lines, and the bright and dark lines are staggered.

[0101] By changing the level transmission mode of the gate driving unit 11, the charging rate of the pixel units 101 connected to the gate driving units 11 of the odd rows and the pixel units 101 connected to the gate driving units 11 of the even rows are made consistent, showing the same brightness, eliminating vertical bright and dark lines, and improving the display effect.

[0102] Example 4

[0103] A third aspect of the embodiment of the present invention provides a display panel 100, such as Figure 12 As shown, the display panel 100 includes a color filter substrate 2, a liquid crystal layer 3, and an array substrate 1. The specific structure of the array substrate 1 is similar to that of the above-mentioned embodiments. Since the display panel 100 adopts all the technical solutions of all the above-mentioned embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above-mentioned embodiments, and will not be described in detail here. The liquid crystal layer 3 is located between the color filter substrate 2 and the array substrate 1.

[0104] In this embodiment, the color film substrate 2 includes an upper polarizer, a color filter, a common electrode layer and an upper alignment layer, and the array substrate 1 includes a lower alignment layer, a driving layer and a lower polarizer, wherein the driving layer is a thin film transistor driving layer, and the driving layer is used to cooperate with the common electrode layer to drive the liquid crystal molecules of the liquid crystal layer 3. The array substrate 1 is provided with corresponding data lines 103, scanning lines 102, pixel arrays 111, gate driving circuits 10, etc.

[0105] Example 5

[0106] A fourth aspect of the embodiments of the present invention provides a display device, such as Figure 13 As shown, the display device includes a backlight module 300, a display panel 100 driving circuit, and the display panel 100. The specific structure of the display panel 100 is similar to the above-mentioned embodiment. Since the present display device adopts all the technical solutions of all the above-mentioned embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above-mentioned embodiments, and will not be described in detail here. Among them, the display panel driving circuit 200 is connected to the display panel 100, and the backlight module 300 is arranged opposite to the display panel 100.

[0107] In this embodiment, the display panel driving circuit 200 may include a source driving circuit and a timing controller, and may also include a power management integrated circuit required for driving. The timing controller controls the source driving circuit and the gate driving circuit 10 to scan line by line. The common electrode voltage signal on the common electrode layer of the color film substrate 2 cooperates with the data driving signal output by the source driving circuit to drive the liquid crystal molecules and cooperates with the backlight module 300 to display the corresponding image information.

[0108] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention, and should all be included in the scope of protection of the present invention.

Claims

1. A gate drive circuit, characterized in that: Including: Multiple gate driving units, where the multiple gate driving units are sequentially connected to multiple scan lines of a display panel and are used to output row scan signals line by line; Among them, the input terminal of the (2i - 1)-th gate driving unit is connected to the output terminal of the (2i - 1 - m1)-th gate driving unit and performs pre-charging when receiving the row scan signal of the (2i - 1 - m1)-th level. The reset terminal of the (2i - 1)-th gate driving unit is connected to the output terminal of the (2i - 1 + n1)-th gate driving unit and performs discharge reset when receiving the row scan signal of the (2i - 1 + n1)-th level. The output terminal of the (2i - 1)-th gate driving unit is respectively connected to the reset terminal of the (2i - 1 - n1)-th gate driving unit and the input terminal of the (2i - 1 + m1)-th gate driving unit and is used to input the row scan signal of this level; The input terminal of the 2i-th gate driving unit is connected to the output terminal of the (2i - m2)-th gate driving unit and performs pre-charging when receiving the row scan signal of the (2i - m2)-th level. The reset terminal of the 2i-th gate driving unit is connected to the output terminal of the (2i + n2)-th gate driving unit and performs discharge reset when receiving the row scan signal of the (2i + n2)-th level. The output terminal of the 2i-th gate driving unit is respectively connected to the reset terminal of the (2i - n2)-th gate driving unit and the input terminal of the (2i + m2)-th gate driving unit and is used to input the row scan signal of this level, where i, m1, n1, m2, n2 are positive integers; i > 1, m1 < m2, and / or n1 > n2.

2. The gate drive circuit according to claim 1, wherein: m2 - m1 = m3, n1 - n2 = n3, and m3 and n3 are even numbers.

3. The gate drive circuit according to claim 2, wherein: n1 = m2 = 4, m1 = n2 = 2.

4. The gate drive circuit according to claim 2, wherein: The input terminals from the input terminal of the first gate driving unit to the input terminal of the m1-th gate driving unit are used to input a frame start signal and perform pre-charging; The input terminals of the 2i-th gate driving unit among the m1-th gate driving unit to the m2-th gate driving unit are used to input a frame start signal and perform pre-charging.

5. The gate driving circuit according to claim 4, wherein: Clock signals are respectively input to the clock terminals of each of the gate driving units, and the clock signals input to each of the gate driving units differ by a preset phase in sequence.

6. The gate driving circuit according to claim 5, wherein: The gate driving unit at least includes a first thin-film transistor, a second thin-film transistor, a third thin-film transistor, a fourth thin-film transistor, and a capacitor; The control terminal and the first terminal of the first thin film transistor constitute an input terminal of the gate driving unit, the second terminal of the first thin film transistor, the first terminal of the capacitor, the first terminal of the fourth thin film transistor, and the control terminal of the second thin film transistor are connected, the first terminal of the second thin film transistor constitutes a clock terminal of the gate driving unit, the second terminal of the second thin film transistor, the first terminal of the third thin film transistor, and the second terminal of the capacitor are connected to constitute an output terminal of the gate driving unit, the second terminal of the third thin film transistor and the second terminal of the fourth thin film transistor are used to input a low-level signal, and the control terminal of the third thin film transistor and the control terminal of the fourth thin film transistor are connected to constitute a reset terminal of the gate driving unit; The width-to-length ratio of the first thin film transistor of the 2i-1th gate driving unit is smaller than the width-to-length ratio of the first thin film transistor of the 2ith gate driving unit; and / or, the width-to-length ratio of the third thin film transistor of the 2i-1th gate driving unit is greater than the width-to-length ratio of the third thin film transistor of the 2ith gate driving unit; The width-to-length ratio of the fourth thin film transistor of the 2i-1th gate driving unit is greater than the width-to-length ratio of the fourth thin film transistor of the 2ith gate driving unit.

7. An array substrate, characterized in that: The invention comprises a display area and a non-display area, wherein the non-display area is bonded with a gate drive circuit according to any one of claims 1 to 6, the display area comprises data lines, scan lines and a pixel array, the data lines are used to input data signals of corresponding polarities, the scan lines are used to input row scan signals row by row, the pixel array comprises pixel units arranged in an array, and the gate drive circuit is correspondingly connected to a plurality of the scan lines.

8. The array substrate according to claim 7, wherein: Every 2k1 columns of pixel units constitute a pixel unit group, and the pixel units in the jth column and the pixel units in the j+k1th column in the k2th pixel unit group are connected to the (k2-1)*k1+j1th column of data lines; Two scan lines are set between the pixel units in adjacent rows, the pixel units in the first k1 columns of the pixel unit group in the k3th row are connected to the 2k3-1th scan line, and the pixel units in the last k1 columns of the pixel unit group in the k3th row are connected to the 2k3th scan line, and k1, k2, k3, and j are positive integers.

9. A display panel, characterized in that: The method comprises a color filter substrate, a liquid crystal layer and the array substrate according to any one of claims 7 or 8, wherein the liquid crystal layer is located between the color filter substrate and the array substrate.

10. A display device, characterized in that: The device comprises a backlight module, a display panel driving circuit and the display panel as claimed in claim 9, wherein the display panel driving circuit is connected to the display panel correspondingly, and the backlight module is arranged opposite to the display panel.

Images