A horizontally polarized electromagnetic pulse simulation device

Abstract

This application belongs to the field of electromagnetic pulse simulation technology and specifically discloses a horizontally polarized electromagnetic pulse simulation device, which includes: a pulse forming unit, a steepening unit, a trigger control unit, and an antenna transmitting unit. The pulse forming unit is used to convert the energy of a DC power supply into a high-frequency oscillating current and form a pulse voltage; the steepening unit is used to control the discharge path of the energy storage capacitor and achieve steep discharge of the pulse voltage; the trigger control unit is used to generate a pulse trigger signal to control the triggering and protection of the steepening unit; and the antenna transmitting unit is used to convert the pulse voltage into a spatially radiated electromagnetic wave and radiate and transmit the electromagnetic wave. This application can eliminate the steepening phenomenon in the waveform generated by existing pulse simulation devices.

Description

Technical Field

[0001] The present application belongs to the technical field of electromagnetic pulse simulation, and specifically relates to a horizontally polarized electromagnetic pulse simulation device. Background Art

[0002] With the increasing demand for high-frequency, intense pulsed electromagnetic waves in electronic devices, the research and application of electromagnetic pulse (EMP) simulators has garnered widespread attention. Traditional EMP simulators typically rely on mechanical switches and analog circuits to generate and modulate pulses. However, these devices often suffer from slow response, high power consumption, and poor stability, resulting in a steepening waveform.

[0003] Therefore, it is necessary to develop a new electromagnetic pulse simulation device to eliminate the steepening problem in the waveform generated by the existing device. Summary of the Invention

[0004] In view of the deficiencies in the prior art, the purpose of this application is to provide a horizontally polarized electromagnetic pulse simulation device, which aims to overcome the steepening phenomenon in the waveform generated by the existing pulse simulation device.

[0005] To achieve the above objectives, this application provides the following technical solutions:

[0006] A horizontally polarized electromagnetic pulse simulation device comprises: a pulse forming unit, a steepening unit, a trigger control unit, and an antenna transmitting unit, wherein the pulse forming unit is used to convert the energy of a DC power supply into a high-frequency oscillating current and form a pulse voltage; the steepening unit is used to control the discharge path of an energy storage capacitor and achieve steep discharge of the pulse voltage; the trigger control unit is used to generate a pulse trigger signal to control the triggering and protection of the steepening unit; and the antenna transmitting unit is used to convert the pulse voltage into a spatially radiated electromagnetic wave and radiate and transmit the electromagnetic wave.

[0007] Optionally, the pulse forming unit includes: a primary circuit and a secondary circuit, wherein the primary circuit is used to convert the DC power supply energy into a high-frequency oscillating current; the secondary circuit is used to sense the high-frequency oscillating current generated by the primary circuit and perform rectification, energy storage and protection.

[0008] Optionally, the primary circuit includes: a first SIC MOSFET switch, a primary coil, a first resonant capacitor, a current limiting resistor, and a first power relay, wherein the drain of the first SIC MOSFET switch is connected to the positive electrode of the DC power supply via the first power relay and the current limiting resistor, and the source of the first SIC MOSFET switch is connected to the negative electrode of the DC power supply; the first end of the first resonant capacitor is connected to the source of the first SIC MOSFET switch, and the second end of the first resonant capacitor is connected to the first ground terminal; the first end of the primary coil is connected to the drain of the first SIC MOSFET switch, and the second end of the primary coil is connected to the first end of the first resonant capacitor; the gate of the first SIC MOSFET switch is connected to the positive electrode of the DC power supply via the first power relay and the current limiting resistor; The mosfet driver chip is connected to the PWM signal pin of the trigger control unit; the secondary circuit includes a secondary coil, a second resonant capacitor, a rectifier silicon stack, an energy storage capacitor and a varistor, wherein the secondary coil and the primary coil are coupled, the first end of the secondary coil is connected to the first end of the second resonant capacitor, and the second end of the second resonant capacitor is connected to the third ground end; the second end of the secondary coil is connected to the input end of the rectifier silicon stack, and the output end of the rectifier silicon stack is connected to the fourth ground end via the energy storage capacitor; the varistor is connected in parallel to the two ends of the energy storage capacitor.

[0009] Optionally, the steepening unit includes: an energy storage capacitor network and an intelligent matching network, wherein the energy storage capacitor network is used to store the pulse voltage generated by the pulse forming unit; and the intelligent matching network is used to automatically adjust impedance matching to maximize electromagnetic wave radiation efficiency and prevent energy reflection.

[0010] Optionally, the energy storage capacitor network includes: a first energy storage capacitor, a second energy storage capacitor, a first capacitor switching control relay, a second capacitor switching control relay and a steepening switch, wherein the positive electrode of the first energy storage capacitor is connected to a high-voltage power supply, the negative electrode of the first energy storage capacitor is connected to the input end of the first capacitor switching control relay to form a node, and the input end of the second capacitor switching control relay is connected to the node; the output end of the second capacitor switching control relay is connected to the positive electrode of the second energy storage capacitor, the output end of the first capacitor switching control relay is connected to the negative electrode of the second energy storage capacitor, and the positive electrode of the second energy storage capacitor is connected to the input end of the intelligent matching network through the steepening switch.

[0011] Optionally, the intelligent matching network includes: a fifth resistor, a sixth resistor, a seventh resistor, a second SIC MOSFET switch, a third SIC MOSFET switch and a fourth SIC MOSFET switch, wherein the first ends of the fifth resistor, the sixth resistor and the seventh resistor are simultaneously connected to the output end of the steepening switch; the second end of the fifth resistor is connected to the source of the second SIC MOSFET switch, and the gate of the second SIC MOSFET switch is connected to the first control end of the trigger control unit; the second end of the sixth resistor is connected to the source of the third SIC MOSFET switch, and the gate of the third SIC MOSFET is connected to the second control end of the trigger control unit; the second end of the seventh resistor is connected to the source of the fourth SIC MOSFET switch, and the gate of the fourth SIC MOSFET is connected to the third control end of the trigger control unit; the drain of the second SIC MOSFET, the drain of the third SIC MOSFET and the drain of the fourth SIC MOSFET are simultaneously connected to the input end of the antenna transmitting unit.

[0012] Optionally, the antenna transmitting unit includes: an antenna, an adaptive matching network, a surge protection unit and a high-voltage charge balancing unit, wherein the adaptive matching network is used to automatically adjust the impedance matching under different load or frequency conditions to maximize the electromagnetic wave radiation efficiency and prevent energy reflection; the surge protection unit is used to suppress transient overvoltage and protect the safe operation of the antenna; the high-voltage charge balancing unit is used to release or balance the residual high-voltage charge that may accumulate at the antenna port to prevent the accumulated charge from causing corona discharge or insulation breakdown.

[0013] Optionally, the adaptive matching network includes: a first branch and a second branch, the first branch includes: a fourth diode, a second power relay, a ninth resistor and a first inductor; the second branch includes: a fifth diode, a third power relay, a tenth resistor and a second inductor; wherein, the anode of the fourth diode is connected to the fourth control terminal of the trigger control unit through the ninth resistor, and the cathode of the fourth diode is connected to the +5V power supply; the control terminal of the second power relay is connected to the anode of the fourth diode, and the normally open contact of the second power relay is connected to the first end of the first inductor; the anode of the fifth diode is connected to the fifth control terminal of the trigger control unit through the tenth resistor, and the cathode of the fifth diode is connected to the -5V power supply; the control terminal of the third power relay is connected to the anode of the fifth diode, and the normally open contact of the third power relay is connected to the first end of the second inductor; the second end of the second inductor and the second end of the first inductor are commonly connected to the input end of the surge protection unit.

[0014] Optionally, the surge protection unit includes: a gas discharge tube, a transient suppression diode, a high-voltage bypass capacitor and a current limiting resistor, wherein the first end of the current limiting resistor serves as the input end of the surge protection unit, and the second end of the current limiting resistor is simultaneously connected to the first ends of the gas discharge tube, the transient suppression diode and the high-voltage bypass capacitor; the second ends of the gas discharge tube, the transient suppression diode and the high-voltage bypass capacitor are jointly connected to the input end of the high-voltage charge balancing unit.

[0015] Optionally, the high-voltage charge balancing unit includes: a first branch and a second branch arranged in parallel, the first branch including: a twelfth resistor, a fifth inductor, a varactor diode and a third TVS diode connected in series; the second branch including: a thirteenth resistor, a sixth inductor and a voltage suppression diode connected in series, wherein the first ends of the twelfth resistor and the thirteenth resistor jointly serve as the input end of the high-voltage charge balancing unit, and the second end of the twelfth resistor is connected to the anode of the varactor diode through the fifth inductor; the anode of the third TVS diode is connected to the connection between the fifth inductor and the varactor diode, and the cathode of the third TVS diode is connected to the seventh ground end; the second end of the thirteenth resistor is connected to the cathode of the voltage suppression diode, the anode of the voltage suppression diode is connected to the first end of the sixth inductor, the second end of the sixth inductor is connected to the cathode of the varactor diode and is connected to the antenna as the output end of the high-voltage charge balancing unit.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] This application introduces innovative designs such as a pulse forming unit and a steepening unit to effectively improve the response speed, stability, and energy efficiency of electromagnetic pulse simulation devices. Furthermore, by precisely controlling the pulse waveform, dynamically adjusting voltage and capacity, and optimizing impedance matching, this application significantly improves the radiation efficiency of electromagnetic waves and reduces energy reflection, thereby achieving more efficient electromagnetic wave simulation. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a schematic structural diagram of a horizontally polarized electromagnetic pulse simulation device provided by one embodiment of the present application;

[0019] Figure 2 is a circuit structure diagram of a pulse forming unit provided in another embodiment of the present application;

[0020] Figure 3 is a schematic diagram of the circuit structure of an energy storage capacitor network provided by another embodiment of the present application;

[0021] Figure 4 is a circuit structure diagram of an intelligent matching network provided by another embodiment of the present application;

[0022] Figure 5is a schematic diagram of the circuit structure of a primary drive module provided in another embodiment of the present application;

[0023] Figure 6 is a schematic diagram of the circuit structure of an adaptive matching network provided by another embodiment of the present application;

[0024] Figure 7 is a schematic diagram of the circuit structure of a surge protection unit provided in another embodiment of the present application;

[0025] Figure 8 is a schematic diagram of the circuit structure of a high-voltage charge balancing unit provided in another embodiment of the present application;

[0026] Figure 9 This is a schematic diagram of the field strength waveform of an existing pulse simulation device;

[0027] Figure 10 This is a schematic diagram of a field strength waveform provided by another embodiment of the present application;

[0028] Figure 11 Another embodiment of the present application provides a waveform diagram obtained by measuring at a voltage of 1.5 kV;

[0029] Figure 12 Another embodiment of the present application provides a waveform diagram obtained by measuring at a voltage of 1.65 kV;

[0030] Figure 13 Another embodiment of the present application provides a waveform diagram obtained by measuring at a voltage of 1.7 kV. DETAILED DESCRIPTION

[0031] Specific embodiments of the present application will be described in detail below with reference to the accompanying drawings. Although specific embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0032] It should be noted that certain words are used in the specification and claims to refer to specific components. Those skilled in the art should understand that technicians may use different nouns to refer to the same component. This specification and claims do not use the difference in nouns as a way to distinguish components, but use the difference in the functions of the components as the criterion for distinction. As mentioned throughout the specification and claims, "including" or "comprising" is an open term, so it should be interpreted as "including but not limited to". The subsequent description of the specification is a preferred embodiment of the present application, but the description is based on the general principles of the specification and is not intended to limit the scope of the present application. The scope of protection of this application shall be as defined by the attached claims.

[0033] To facilitate understanding of the embodiments of the present application, further explanation will be given below using specific embodiments as examples in conjunction with the accompanying drawings, and the various drawings do not constitute a limitation on the embodiments of the present application.

[0034] Figure 1 FIG. 1 is a schematic structural diagram of a horizontally polarized electromagnetic pulse simulation device provided by an exemplary embodiment of the present application. Figure 1 As shown, the device includes: a pulse forming unit, a steepening unit, a trigger control unit and an antenna transmitting unit, wherein the pulse forming unit is used to convert the energy of the DC power supply into a high-frequency oscillating current and form a pulse voltage; the steepening unit is used to control the discharge path of the energy storage capacitor and realize the steepening discharge of the pulse voltage; the trigger control unit is used to generate a pulse trigger signal to control the triggering and protection of the pulse forming unit, the steepening unit and the antenna transmitting unit; the antenna transmitting unit is used to convert the pulse voltage into a space-radiated electromagnetic wave, and radiate and transmit the electromagnetic wave.

[0035] In another exemplary embodiment, the pulse forming unit includes: a primary circuit and a secondary circuit, wherein the primary circuit is used to convert DC power supply energy into high-frequency oscillating current; and the secondary circuit is used to sense the high-frequency oscillating current generated by the primary circuit and perform rectification, energy storage and protection.

[0036] In another exemplary embodiment, Figure 2As shown, the primary circuit includes a first SIC MOSFET switch Q1, a primary coil L1, a first resonant capacitor C1, a current limiting resistor R1, and a first power relay K1, wherein the drain of the first SIC MOSFET switch Q1 is connected to the positive electrode of the DC power supply via the first power relay K1 and the current limiting resistor R1, the source of the first SIC MOSFET switch Q1 is connected to the negative electrode of the DC power supply, the first end of the first resonant capacitor C1 is connected to the source of the first SIC MOSFET switch Q1, the second end of the first resonant capacitor C1 is connected to the first ground terminal GND1, the first end of the primary coil L1 is connected to the drain of the first SIC MOSFET switch Q1, and the second end of the primary coil L1 is connected to the first end of the first resonant capacitor C1; the gate of the first SIC MOSFET switch Q1 is connected through an optocoupler isolator U1 (such as ACPL-P346) and a SIC MOSFET driver chip U2 (such as TI UCC21750) is connected to the PWM signal pin of the trigger control unit; the secondary circuit includes a secondary coil L2, a second resonant capacitor C3, a rectifier silicon stack D2, an energy storage capacitor C4 and a varistor R3, wherein the secondary coil L2 and the primary coil L1 are coupled, the first end of the secondary coil L2 is connected to the first end of the second resonant capacitor C3, and the second end of the second resonant capacitor C3 is connected to the third ground terminal GND3; the second end of the secondary coil L2 is connected to the input end of the rectifier silicon stack D2, and the output end of the rectifier silicon stack D2 is connected to the fourth ground terminal GND4 via the energy storage capacitor C4; the varistor R3 is connected in parallel to the two ends of the energy storage capacitor C4.

[0037] In this embodiment, the operating principle of the primary circuit is mainly to control the flow of current through the first SIC MOSFET switch Q1 to achieve the generation of pulse voltage. First, the source of the first SIC MOSFET switch Q1 is connected to the negative terminal of the DC power supply, and the drain is connected to the positive terminal of the DC power supply through the first power relay K1 and the current-limiting resistor R1, thereby forming a complete current loop. The gate of the first SIC MOSFET switch Q1 is connected to the PWM signal pin of the trigger control unit through the optocoupler isolator U1 and the SIC MOSFET driver chip U2. The PWM signal generated by the trigger control unit controls the switching state of the first SIC MOSFET switch Q1. When the first SIC MOSFET switch Q1 is turned on, the primary coil L1 forms a resonant circuit with the power supply through the first resonant capacitor C1, converting electrical energy into a high-frequency oscillating current. The function of the primary coil L1 is to form an oscillating current by coupling with the first resonant capacitor C1, and converting the current into a pulse voltage to supply the secondary circuit. At the same time, the two ends of the first resonant capacitor C1 are connected to the first sic mosfet switch Q1 and the ground terminal to achieve storage and release of voltage and energy and ensure current stability.

[0038] In summary, the primary circuit converts the energy from the DC power supply into a high-frequency pulse voltage, which then forms a stable oscillating current through the primary coil L1 and the first resonant capacitor C1. This provides a stable and efficient pulse voltage for the subsequent secondary circuit, facilitating the transmission of pulse signals and energy storage.

[0039] In another exemplary embodiment, the primary circuit further includes an absorption protection network, please continue to refer to Figure 2 The absorption protection network includes an absorption resistor R2 and an absorption capacitor C2 connected in parallel, one end of the absorption resistor R2 and the absorption capacitor C2 are commonly connected to the drain of the first SIC MOSFET switch Q1, and the other end is commonly connected to the source of the first SIC MOSFET switch Q1.

[0040] In this embodiment, the absorption protection network is primarily used to protect the first SIC MOSFET switch Q1 from voltage spikes, ensuring the stability and safety of the primary circuit. The absorption protection network includes an absorption resistor R2 and an absorption capacitor C2 connected in parallel, one end of which is commonly connected to the drain of the first SIC MOSFET switch Q1 and the other end is commonly connected to its source. This design is intended to absorb and dissipate voltage spikes or overvoltages caused by the rapid switching action of the first SIC MOSFET switch Q1 during switching. When the first SIC MOSFET switch Q1 switches on and off, overvoltages or voltage spikes are generated due to sudden changes in current. The absorption resistor R2 and the absorption capacitor C2 are connected in parallel to absorb these overvoltages. The absorption capacitor C2 acts as an energy storage device, while the absorption resistor R2 dissipates the stored energy as heat, effectively reducing the impact on the first SIC MOSFET switch Q1 and preventing damage caused by voltage spikes.

[0041] In another exemplary embodiment, the absorption protection network further includes a first TVS diode D1 , a cathode of which is connected to the drain of the first SIC MOSFET switch Q1 , and an anode of which is connected to the second ground terminal GND2 .

[0042] In this embodiment, by providing a first TVS diode D1, the first sic mosfet switch Q1 can be protected from overvoltage. When the voltage in the system exceeds a preset threshold, the first TVS diode D1 will quickly turn on and clamp the excessive voltage to a safe range. Specifically, the cathode of the first TVS diode D1 is connected to the drain of the first sic mosfet switch Q1, and the anode is connected to the second ground terminal GND2. Then, when the voltage rises to the breakdown voltage of the first TVS diode D1, it will provide a low-impedance path to guide the overvoltage into the ground line, thereby effectively limiting the voltage peak and preventing the overvoltage from damaging the first sic mosfet switch Q1 and the entire circuit. In this way, the first TVS diode D1 can provide rapid overvoltage protection for the primary circuit, thereby improving the stability and reliability of the primary circuit.

[0043] In another exemplary embodiment, the steepening unit includes an energy storage capacitor network and an intelligent matching network, wherein the energy storage capacitor network is used to store the pulse voltage generated by the pulse forming unit; and the intelligent matching network is used to automatically adjust impedance matching to maximize electromagnetic wave radiation efficiency and prevent energy reflection.

[0044] In another exemplary embodiment, Figure 3 As shown, the energy storage capacitor network includes a first energy storage capacitor CE1, a second energy storage capacitor CE2, a first capacitor switching control relay Kp, a second capacitor switching control relay Ks and a steepening switch S1, wherein the positive electrode of the first energy storage capacitor CE1 is connected to the high-voltage power supply HV, the negative electrode of the first energy storage capacitor CE1 is connected to the input end of the first capacitor switching control relay Kp to form a node N1, and the input end of the second capacitor switching control relay Ks is connected to the node N1; the output end of the second capacitor switching control relay Ks is connected to the positive electrode of the second energy storage capacitor CE2, the output end of the first capacitor switching control relay Kp is connected to the negative electrode of the second energy storage capacitor CE2, and the positive electrode of the second energy storage capacitor CE2 is connected to the input end of the intelligent matching network through the steepening switch S1.

[0045] In this embodiment, the control ends of the first capacitor switching control relay Kp and the second capacitor switching control relay Ks are respectively connected to the GPIO pin GPIO_Kp and GPIO pin GPIO_Ks of the main controller FPGA. The main controller FPGA adjusts the connection mode of the first energy storage capacitor CE1 and the second energy storage capacitor CE2 by controlling the state of these two relays, thereby achieving precise adjustment of the output voltage and capacitance. When the main controller controls the first capacitor switching control relay Kp to be conductive and the second capacitor switching control relay Ks to be disconnected, the first energy storage capacitor CE1 and the second energy storage capacitor CE2 are output in parallel, forming a larger total capacitance, thereby providing a larger energy storage capacity. When the main controller controls the first capacitor switching control relay Kp to be disconnected and the second capacitor switching control relay Ks to be conductive, the first energy storage capacitor CE1 and the second energy storage capacitor CE2 are output in series. At this time, the total voltage capability of the capacitors is increased, while the total capacitance is correspondingly reduced.

[0046] In summary, the above dual regulation mechanism can flexibly adjust the connection mode of the capacitor by triggering the precise control of the control unit, thereby adjusting the output voltage and capacity according to different working requirements, ensuring that the system can adapt to different power output requirements while optimizing the system's performance and efficiency.

[0047] In another exemplary embodiment, the energy storage capacitor network further includes a protection and buffer module, which includes a first TVS diode D2, a fourth resistor R4, a fifth capacitor C5 and an absorption inductor Ls, wherein the first end of the first TVS diode D2 is connected to the output end of the steepening switch S1, and the second end of the TVS diode is connected to the fifth ground terminal GND5; the first end of the fourth resistor R4 is connected to the output end of the steepening switch S1, and the second end of the fourth resistor R4 is connected to the sixth ground terminal GND6 via the fifth capacitor C5; the absorption inductor Ls is connected in series between the steepening switch S1 and the smart matching network.

[0048] In this embodiment, the first TVS diode D2 is connected between the output terminal of the steepening switch S1 and the fifth ground terminal GND5. When the voltage exceeds the set threshold, the first TVS diode D2 can quickly turn on, clamping the excessive voltage within a safe range to prevent damage to other components in the circuit. The fourth resistor R4 and the fifth capacitor C5 form a filter. The fourth resistor R4 is used to limit the current and reduce the impact of voltage spikes on the circuit, while the fifth capacitor C5 helps absorb high-frequency signals, stabilize the voltage, and reduce noise. The absorption inductor Ls is connected in series between the steepening switch S1 and the intelligent matching network, acting as a filter and current buffer. It can absorb the high-frequency noise generated by the sudden change in current, avoid affecting the system, and ensure the stability and accuracy of signal transmission.

[0049] In summary, the protection and buffer module can ensure that the energy storage capacitor network can maintain stable operation under extreme working conditions through rapid overvoltage protection, noise filtering and current buffering, while improving the reliability and anti-interference capability of the energy storage capacitor network.

[0050] In another exemplary embodiment, the intelligent matching network includes a plurality of power matching resistors of different resistance values ​​and an electronic switching device connected in series therewith, wherein the electronic switching device may be a MOSFET array, a solid-state relay, or an electromagnetic relay; each group of resistors is connected in series with a switch to form a branch, and multiple branches are connected in parallel to form a matching selection matrix, which is connected between the output end of the pulse forming line and the load; the control end of each switch is connected to the main controller, which is used to select a suitable matching resistor input according to the reflection characteristics of the output pulse waveform to dynamically adjust the output impedance; illustratively, the intelligent matching network includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a second SIC MOSFET switch Q2, a third SIC MOSFET switch Q3, and a fourth SIC MOSFET switch Q4, wherein the first ends of the fifth resistor R5, the sixth resistor R6, and the seventh resistor R7 are simultaneously connected to the output end of the steepening switch S1 through the absorption inductor Ls, the second end of the fifth resistor R5 is connected to the source of the second SIC MOSFET switch Q2, and the second SIC The gate of the mosfet switch Q2 is connected to the first control end of the trigger control unit (i.e., the GPIO pin GPIO_Q2 of the main controller FPGA), the second end of the sixth resistor R6 is connected to the source of the third sic mosfet switch Q3, the gate of the third sic mosfet switch Q3 is connected to the second control end of the trigger control unit (i.e., the GPIO pin GPIO_Q3 of the main controller FPGA), the second end of the seventh resistor R7 is connected to the source of the fourth sic mosfet switch Q4, the gate of the fourth sic mosfet switch Q4 is connected to the third control end of the trigger control unit (i.e., the GPIO pin GPIO_Q4 of the main controller FPGA), and the drain of the second sic mosfet switch Q2, the drain of the third sic mosfet switch Q3, and the drain of the fourth sic mosfet switch Q4 are simultaneously connected to the input end of the antenna transmitting unit.

[0051] In this embodiment, in this network, the first ends of the fifth resistor R5, the sixth resistor R6, and the seventh resistor R7 are connected to the output end of the steepening switch S1 via an absorption inductor Ls. These resistors are responsible for absorbing high-frequency noise during current changes to reduce electromagnetic interference and smooth current fluctuations. After the signal is output from the steepening switch S1, it passes through the fifth resistor R5, the sixth resistor R6, and the seventh resistor R7. These resistors are respectively connected to the gates of their respective SIC MOSFET switches via their second ends. The gate signals of these SIC MOSFET switches are controlled by the trigger control unit via GPIO pins. For example, the drain of the second SIC MOSFET switch Q2 is connected to the GPIO_Q2 pin of the main controller FPGA, the drain of the third SIC MOSFET switch Q3 is connected to the GPIO_Q3 pin of the main controller FPGA, and the drain of the fourth SIC MOSFET switch Q4 is connected to the GPIO_Q4 pin of the main controller FPGA. These connections enable the trigger control unit to precisely control the on and off states of the switches, thereby achieving dynamic adjustment for different impedance matching. When these SiC MOSFET switches are controlled, their sources (Q2, Q3, Q4) are simultaneously connected to the input of the antenna transmitting unit, so that the optimal load matching can be adjusted through the switch state control to ensure the maximum radiation efficiency of the electromagnetic wave.

[0052] In summary, the intelligent matching network can accurately control the switching state of each SiC MOSFET switch by triggering the control unit according to the reflection characteristics of the signal, select the appropriate resistor for input, and thus dynamically adjust the impedance matching of the system, thereby optimizing the electromagnetic wave radiation efficiency, reducing signal reflection, and ensuring that the antenna transmitting unit can obtain the best working state under different load or frequency conditions, thereby improving the reliability and efficiency of the system.

[0053] In another exemplary embodiment, the trigger control unit includes a main controller, a primary drive module, and a steepening switch trigger module, wherein the main controller (for example, an FPGA (such as Xilinx Kintex-7)) is used to generate a pulse trigger signal and receive feedback data and synchronize timing logic; the primary drive module is used to drive the second SIC MOSFET switch Q2, the third SIC MOSFET switch Q3, and the fourth SIC MOSFET switch Q4, and control the triggering of the steepening switch S1; and the steepening switch trigger module is used to trigger and control the steepening switch S1 to perform high-speed switching.

[0054] In another exemplary embodiment, Figure 5As shown, the primary driver module includes a sic mosfet driver IC (such as Cree CAS325M12HM2), a fifth sic mosfet switch Q5, a gate current limiting resistor R8, a second TVS diode D3, and an optical fiber isolator OP (such as ACPL-P346), wherein the transmitting end TX of the optical fiber isolator OP is connected to the trigger signal pin TRIG_OUT of the main controller FPGA, which outputs a pulse trigger signal and is transmitted through the optical fiber isolator, and the receiving end RX of the optical fiber isolator OP outputs a control signal and is connected to the input end of the sic mosfet driver IC, the positive output end OUT+ of the sic mosfet driver IC is connected to the gate of the fifth sic mosfet Q5 via the gate current limiting resistor R8, the negative output end OUT- of the sic mosfet driver IC is connected to the source of the fifth sic mosfet Q5, and the drain of the fifth sic mosfet Q5 is connected to the input end of the steepening unit, and the second TVS diode D3 is connected in parallel to the fifth sic mosfet. Between the gate and source of Q5 (the anode of the second TVS diode D3 is connected to the source, and the cathode of the second TVS diode D3 is connected to the gate).

[0055] In this embodiment, the primary driver module controls the switching state of the fifth SIC MOSFET switch Q5 through a SIC MOSFET driver IC, thereby driving the steepening unit. First, the transmit terminal (TX) of the optical fiber isolator OP is connected to the TRIG_OUT pin of the main controller FPGA. A pulse trigger signal generated by the main controller FPGA is transmitted through the optical fiber isolator to its receive terminal (RX), which then outputs a control signal to the input of the SIC MOSFET driver IC. The SIC MOSFET driver IC activates the gate of the fifth SIC MOSFET switch Q5 in response to the received control signal. Gate current-limiting resistor R8 controls the gate current, ensuring stable switching of the fifth SIC MOSFET switch Q5. The output terminal (OUT+) of the SIC MOSFET driver IC is connected to the gate of the fifth SIC MOSFET Q5, ensuring it is turned on. The negative output terminal (OUT-) of the SIC MOSFET driver IC is connected to the source of the fifth SIC MOSFET Q5, ensuring that the source of the fifth SIC MOSFET Q5 is grounded and begins conducting. The discharge process of the energy storage capacitor is controlled by controlling the gate of the fifth SIC MOSFET Q5, whose drain is connected to the input of the steepening unit. To protect the circuit from voltage spikes, a second TVS diode D3 is connected in parallel between the gate and source of the fifth SIC MOSFET Q5. When the voltage between the gate and source exceeds a set threshold, the second TVS diode D3 quickly turns on, preventing overvoltage damage to the fifth SIC MOSFET Q5.

[0056] In summary, the primary driver module controls the switching state of the fifth SiC MOSFET Q5 via a pulse trigger signal from the trigger control unit, thereby driving the steepening unit. This module utilizes a fiber optic isolator to isolate and transmit signals, ensuring the safe transfer of high-voltage signals. Furthermore, the gate current-limiting resistor and TVS diode ensure the stability and safety of the drive signal, thereby improving the reliability and anti-interference capabilities of the trigger control unit.

[0057] In another exemplary embodiment, the steepening switch module includes an ultraviolet laser, a laser driver (e.g., a high-voltage pulsed laser diode driver DEI PCX-7420), an optical fiber delay line, and an optical focusing lens, wherein the input end of the laser driver is connected to the PWM signal pin of the main controller, and the output end of the laser driver is connected to the steepening switch S1 via the ultraviolet laser, the optical fiber delay line, and the optical focusing lens in sequence.

[0058] In this embodiment, the laser driver first receives a trigger signal from a main controller. It then generates high-voltage electrical pulses through its internal energy storage and rapid discharge circuits, driving a UV laser (e.g., a pulsed laser with a wavelength of 266 nm or 355 nm) to emit short laser pulses according to a set timing sequence. The short laser pulses then enter a fiber delay line via a coupling interface. This fiber delay line precisely controls the delay of the short laser pulses during transmission, ensuring the timing accuracy of the subsequent steepening triggering process. After the delayed laser pulses are output from the end of the optical fiber, they are focused by an aligned optical focusing lens (e.g., a quartz aspheric lens) to achieve high spatial concentration of the laser energy. This energy is then directed to the light-triggering window of the steepening switch S1 (e.g., a light-controlled SiC MOSFET, a photothyristor, or a vacuum light-controlled switch), achieving rapid on-state control of the switch device and high-speed activation of the energy storage capacitor discharge path, thus forming the master switch link of the steepening unit. This design offers advantages such as fast response, strong electromagnetic interference resistance, and high isolation, making it suitable for high-voltage, fast-pulse systems requiring nanosecond-level triggering accuracy.

[0059] In another exemplary embodiment, the trigger control unit further includes a protection monitoring module, which includes a capacitive voltage divider, a high-speed comparator (such as ADI ADCMP605), a Rogowski coil, and an ultraviolet sensor (such as Hamamatsu C13572). The capacitive voltage divider is used to proportionally reduce the voltage of the energy storage capacitors CE1 and CE2. The upper end of the capacitive voltage divider is connected to the positive electrode or high-voltage bus node of the energy storage capacitors CE1 and CE2, and the lower end is grounded. The voltage divider signal is connected to the positive input terminal (+IN) of the high-speed comparator after being led out through the center tap, and the negative input terminal (−IN) of the high-speed comparator is connected to the reference voltage provided by the resistor divider or the DAC to set the overvoltage threshold. When the monitored voltage exceeds the set threshold, the high-speed comparator outputs a jump signal, which is transmitted to the GPIO pin of the main controller through its output pin, triggering a system protection response. Meanwhile, a Rogowski coil is placed around the discharge cable from the high-voltage energy storage capacitor to the steepening switch S1. Its inductive output signal is processed by an integrator circuit before being fed into the main controller's ADC channel, enabling non-contact monitoring of high-frequency pulse currents and determining the presence of abnormal discharges, inrush currents, and other issues. A UV sensor is mounted near the steepening switch or load area, facing locations where arcing or breakdown may occur. Its power supply is connected to +5V or +12V, its ground terminal to system ground, and its output is connected to the main controller's ADC or interrupt pin. Abnormal light radiation (such as UV flash or arcing) can be immediately reported, enabling multimodal real-time status perception and protective response.

[0060] In another exemplary embodiment, the antenna transmitting unit is used to convert the high-steepness voltage pulses output by the steepening switch module into space-radiated electromagnetic waves. The antenna transmitting unit includes an antenna, an adaptive matching network, a surge protection unit and a high-voltage charge balancing unit, wherein the adaptive matching network is used to automatically adjust the impedance matching under different load or frequency conditions to maximize the electromagnetic wave radiation efficiency and prevent energy reflection; the surge protection unit is used to suppress transient overvoltages and protect the safe operation of the antenna; the high-voltage charge balancing unit is used to release or balance the residual high-voltage charge that may accumulate at the antenna port to prevent the accumulated charge from causing corona discharge or insulation breakdown.

[0061] In another exemplary embodiment, Figure 6 As shown, the adaptive matching network includes a first branch and a second branch, the first branch includes a fourth diode D4, a second power relay K2, a ninth resistor R9 and a first inductor L3, and the second branch includes a fifth diode D5, a third power relay K3, a tenth resistor R10 and a second inductor L4, wherein the anode of the fourth diode D4 is connected to the fourth control terminal of the trigger control unit (i.e., the GPIO pin GPIO1 of the main controller FPGA) through the ninth resistor R9, the cathode of the fourth diode D4 is connected to the +5V power supply, the control terminal of the second power relay K2 is connected to the anode of the fourth diode D4, and the normally open contact of the second power relay K2 is connected to the first end of the first inductor L3; the anode of the fifth diode D5 is connected to the fifth control terminal of the trigger control unit (i.e., the GPIO pin GPIO1 of the main control FPGA) through the tenth resistor R10. Pin GPIO2), the cathode of the fifth diode D5 is connected to a -5V power supply, the control end of the third power relay K3 is connected to the anode of the fifth diode D5, and the normally open contact of the third power relay K3 is connected to the first end of the second inductor L4; the second end of the second inductor L4 and the second end of the first inductor L3 are commonly connected to the input end of the surge protection unit.

[0062] In this embodiment, in this network, the fourth diode D4 and the fifth diode D5 are responsible for detecting current direction and controlling the power relay, while the second power relay K2 and the third power relay K3 adjust the circuit's impedance matching by controlling the inductor connection. Specifically, in the first branch, the anode of the fourth diode D4 is connected to the GPIO pin GPIO_D4 of the main controller FPGA via the ninth resistor R9, receiving a control signal from the main controller FPGA. When the signal reaches a certain threshold, the fourth diode D4 turns on and controls the opening and closing of the second power relay K2 through its anode, thereby changing the connection state of the first inductor L3. The normally open contact of the second power relay K2 is connected to the input terminal of the first inductor L3, thereby adjusting the inductor connection or disconnection. In the second branch, the anode of the fifth diode D5 is connected to the GPIO pin GPIO_D5 of the main controller FPGA via the tenth resistor R10, for receiving another control signal. When the signal reaches a set value, the fifth diode D5 turns on, controlling the opening and closing of the third power relay K3, thereby adjusting the connection state of the second inductor L4. The normally open contact of the third power relay K3 is connected to the input of the second inductor L4, controlling its conduction. Ultimately, the second end of the second inductor L4 and the second end of the first inductor L3 are connected to the input of the surge protection unit, ensuring that current is transmitted through the appropriate inductor path under different load and frequency conditions, achieving optimal impedance matching.

[0063] In summary, the adaptive matching network can dynamically adjust the impedance matching according to the working state of the antenna transmitting unit. By controlling the switching state of the diode and the power relay, the impedance optimization under different load conditions can be achieved, thereby maximizing the radiation efficiency of electromagnetic waves and effectively protecting the system from damage by transient surge voltage.

[0064] In another exemplary embodiment, Figure 7 As shown, the surge protection unit includes: a gas discharge tube GDT, a transient suppression diode D6, a high-voltage bypass capacitor C6 and a current limiting resistor R11, wherein the first end of the current limiting resistor R11 serves as the input end of the surge protection unit, the second end of the current limiting resistor R11 is simultaneously connected to the first ends of the gas discharge tube GDT, the transient suppression diode D6 and the high-voltage bypass capacitor C6, and the second ends of the gas discharge tube GDT, the transient suppression diode D6 and the high-voltage bypass capacitor C6 are commonly connected to the input end of the high-voltage charge balancing unit.

[0065] In this embodiment, the input signal enters the main circuit in series through current-limiting resistor R11. Three key components are then connected in parallel between this node and ground: a gas discharge tube, a TVS diode array, and a high-voltage bypass capacitor. The gas discharge tube is connected directly between the signal line and ground. When the surge voltage exceeds a set breakdown threshold (e.g., 90V or higher), it automatically turns on, instantly discharging the peak current into the ground line. The TVS diode array is also connected in parallel between the signal line and ground, offering a fast response time and absorbing high-frequency surge energy within nanoseconds. The high-voltage bypass capacitor is connected to the same node to filter out high-frequency noise and rising spikes, providing high-frequency stability for the system voltage. Finally, this node continues to the right and connects to the antenna feed unit. The entire structure forms a π-shaped surge suppression network, effectively isolating high-energy interference and transient voltages without affecting the main signal transmission, ensuring stable system operation.

[0066] In another exemplary embodiment, Figure 8 As shown, the high-voltage charge balancing unit includes a first branch and a second branch connected in parallel. The first branch includes a twelfth resistor R12, a fifth inductor L5, a varactor diode D7, and a third TVS diode D8 connected in series. The second branch includes a thirteenth resistor R13, a sixth inductor L6, and a voltage suppression diode D9 connected in series. The first ends of the twelfth resistor R12 and the thirteenth resistor R13 jointly serve as an input end of the high-voltage charge balancing unit. The second end of the twelfth resistor R12 is connected to the anode of the varactor diode D7 via the fifth inductor L5. The anode of the third TVS diode D8 is connected to the connection between the fifth inductor L5 and the varactor diode D7. The cathode of the third TVS diode D8 is connected to the seventh ground terminal GND7. The second end of the thirteenth resistor R13 is connected to the cathode of the voltage suppression diode D9. The anode of the voltage suppression diode D9 is connected to the first end of the sixth inductor L6. The second end of the sixth inductor L6 is connected to the cathode of the varactor diode D7 and serves as the output end of the high-voltage charge balancing unit and is connected to the antenna.

[0067] In this embodiment, the high-voltage charge balancing unit achieves charge balancing and suppresses high-voltage fluctuations through two parallel branches to protect the antenna transmitting unit from high-voltage current or voltage spikes. This unit introduces current through the twelfth resistor R12 and the thirteenth resistor R13 and distributes the charge through their respective branches, thereby ensuring that the high-voltage current can flow evenly through the two branches and effectively balancing the charge. Specifically, in the first branch, the second end of the twelfth resistor R12 is connected to the anode of the varactor diode D7 through the fifth inductor L5, forming a filtering path. The function of the varactor diode D7 is to adjust the capacitance according to voltage changes, further balancing the charge distribution and optimizing the charge release process. The third TVS diode D8 is connected in parallel with the connection point of the varactor diode D7 and is responsible for quickly turning on when the voltage exceeds the set threshold, clamping the overvoltage and protecting the circuit from damage caused by high voltage. The cathode of the TVS diode D8 is connected to the ground terminal GND7 to ensure that the overvoltage can be quickly discharged to the ground line. In the second branch, the second end of the thirteenth resistor R13 is connected to the cathode of the voltage suppression diode D9, which suppresses sharp voltage increases and prevents voltage spikes from reaching sensitive components. Its anode is connected to the cathode of the varactor diode D7 via the sixth inductor L6, ensuring smooth current flow through this branch and preventing damage caused by voltage instability. Finally, the output of the high-voltage charge balancing unit is connected to the antenna via the varactor diode D7 and the sixth inductor L6, ensuring effective charge balancing at the antenna port and preventing electrical breakdown or corona discharge caused by high-voltage charge accumulation.

[0068] In summary, the high-voltage charge balancing unit can regulate and distribute charge and suppress voltage spikes through the design of two parallel branches. At the same time, it can provide effective charge balancing to prevent excessive voltage from damaging circuit components.

[0069] In summary, the present application can effectively eliminate the steepening phenomenon in the waveform generated by the existing analog device, mainly due to the precise control and optimized adjustment mechanism in the innovative design of the present application. First of all, the present application ensures the stable discharge of the pulse voltage through the precise design of the pulse forming unit and the steepening unit, and realizes fast and smooth waveform changes by dynamically adjusting the discharge path of the energy storage capacitor. Unlike traditional analog devices that rely on mechanical switches or imprecise circuit control, the present application adopts all-solid-state technology and intelligent matching networks to make the waveform formation and discharge process more controllable, avoiding the steepening of the waveform caused by too rapid voltage changes. In addition, the steepening unit optimizes the radiation efficiency of the electromagnetic wave and the smoothness of the waveform through precise impedance matching and capacitor switching control, ensuring that the steepening edge of the waveform remains continuous and without mutations, thereby eliminating the problem of over-steepening or under-steepening caused by imprecise control in traditional devices.

[0070] Figure 9 This is a schematic diagram of the field strength waveform of an existing pulse simulation device; Figure 10 is a schematic diagram of the field strength waveform of the pulse simulation device described in this application; Figure 9 The pulse simulation device designed in this application has a waveform that is closer to a standard double-exponential waveform, and no steepening or under-steepening occurs in the falling edge test. This means that the design of this application is more precise in waveform control, ensuring the stability and continuity of the electromagnetic pulse, thereby avoiding the problem of over-steepening or under-steepening that may occur in traditional designs, and further improving the performance of the pulse simulation device.

[0071] Furthermore, the present application conducted three waveform measurements on the electromagnetic pulse simulation device at voltages of 1.5 kV, 1.65 kV, and 1.7 kV. The measurement results are shown in Table 1:

[0072] Table 1

[0073]

[0074] As shown in Table 1, as the charging voltage increases, the peak value gradually increases from 25.47 kV / m at 1.50 kV to 25.62 kV / m at 1.70 kV, demonstrating the stability and high output capacity of the pulse simulation device designed in this application at different voltages. The electric field half-width remained at approximately 25.4 ns in all three tests, and the leading edge time also showed relatively consistent values ​​(between 2.44 ns and 2.55 ns), demonstrating the waveform control accuracy and consistency of this device at different voltages. These stable test results demonstrate that this application can ensure the reliability of the device under various voltage conditions, with higher performance and better adjustability.

[0075] Figure 11 、 Figure 12 and Figure 13 Schematic diagrams of the measurement waveforms of the pulse simulation device described in this application at voltages of 1.5kV, 1.65kV and 1.7kV are respectively shown. It can be seen from these figures that the test waveforms of the pulse simulation device designed in this application under three different voltage conditions all meet the waveform requirements of the GJB8848-2016 standard, and the waveforms measured each time maintain a high degree of stability and consistency. In addition, these test results show that the device realizes continuous voltage adjustment, and the test indicators show more stable and reliable characteristics. More importantly, there was no over-steepening fault during the three tests, which further verified the accuracy and stability of the pulse simulation device designed in this application in terms of waveform control, and successfully avoided the problems of over-steepening or under-steepening common in traditional pulse simulation devices.

[0076] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art may still modify the technical solutions described in the aforementioned embodiments or replace some of the technical features therein with equivalents. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A horizontally polarized electromagnetic pulse simulation device, characterized in that: The device comprises: A pulse forming unit, a steepening unit, a trigger control unit and an antenna transmitting unit, wherein: The pulse forming unit is used to convert the energy of the DC power supply into a high-frequency oscillating current and form a pulse voltage; The steepening unit is used to control the discharge path of the energy storage capacitor and realize the steepening discharge of the pulse voltage; The trigger control unit is used to generate a pulse trigger signal to control the triggering and protection of the steepening unit; The antenna transmitting unit is used to convert the pulse voltage into space-radiated electromagnetic waves, and radiate and transmit the electromagnetic waves; The steepening unit comprises: Energy storage capacitor network and intelligent matching network, where The energy storage capacitor network is used to store the pulse voltage generated by the pulse forming unit; Intelligent matching network is used to automatically adjust impedance matching to maximize electromagnetic wave radiation efficiency and prevent energy reflection; The energy storage capacitor network includes: A first energy storage capacitor, a second energy storage capacitor, a first capacitor switching control relay, a second capacitor switching control relay and a steepening switch, wherein: The positive electrode of the first energy storage capacitor is connected to the high voltage power supply, the negative electrode of the first energy storage capacitor is connected to the input end of the first capacitor switching control relay to form a node, and the input end of the second capacitor switching control relay is connected to the node; The output end of the second capacitor switching control relay is connected to the positive electrode of the second energy storage capacitor, the output end of the first capacitor switching control relay is connected to the negative electrode of the second energy storage capacitor, and the positive electrode of the second energy storage capacitor is connected to the input end of the intelligent matching network through the steepening switch; The intelligent matching network includes: a fifth resistor, a sixth resistor, a seventh resistor, a second sic mosfet switch, a third sic mosfet switch and a fourth sic mosfet switch, wherein: The first ends of the fifth resistor, the sixth resistor and the seventh resistor are connected to the output end of the steepening switch at the same time; The second end of the fifth resistor is connected to the source of the second SIC MOSFET switch, and the gate of the second SIC MOSFET switch is connected to the first control end of the trigger control unit; The second end of the sixth resistor is connected to the source of the third SIC MOSFET switch, and the gate of the third SIC MOSFET switch is connected to the second control end of the trigger control unit; The second end of the seventh resistor is connected to the source of the fourth SIC MOSFET switch, and the gate of the fourth SIC MOSFET switch is connected to the third control terminal of the trigger control unit; The drain of the second SIC MOSFET switch, the drain of the third SIC MOSFET switch and the drain of the fourth SIC MOSFET switch are simultaneously connected to the input end of the antenna transmitting unit.

2. The device according to claim 1, characterized in that The pulse forming unit comprises: primary circuit and secondary circuit, where The primary circuit is used to convert the DC power supply energy into a high-frequency oscillating current; The secondary circuit is used to sense the high-frequency oscillating current generated by the primary circuit and perform rectification, energy storage and protection.

3. The device according to claim 2, characterized in that The primary circuit comprises: A first sic mosfet switch, a primary coil, a first resonant capacitor, a current limiting resistor, and a first power relay, wherein: The drain of the first SIC MOSFET switch is connected to the positive electrode of the DC power supply via the first power relay and the current limiting resistor, and the source of the first SIC MOSFET switch is connected to the negative electrode of the DC power supply; A first end of the first resonant capacitor is connected to the source of the first sic mosfet switch, and a second end of the first resonant capacitor is connected to the first ground terminal; A first end of the primary coil is connected to the drain of the first sic mosfet switch, and a second end of the primary coil is connected to the first end of the first resonant capacitor; The gate of the first SIC MOSFET switch is connected to the PWM signal pin of the trigger control unit through an optocoupler isolator and a SIC MOSFET driver chip; The secondary circuit includes a secondary coil, a second resonant capacitor, a rectifier silicon stack, an energy storage capacitor and a varistor, wherein: The secondary coil is coupled to the primary coil, a first end of the secondary coil is connected to a first end of a second resonant capacitor, and a second end of the second resonant capacitor is connected to a third ground end; The second end of the secondary coil is connected to the input end of the rectifier silicon stack, and the output end of the rectifier silicon stack is connected to the fourth ground end via the energy storage capacitor; The varistor is connected in parallel to both ends of the energy storage capacitor.

4. The device according to claim 1, characterized in that The antenna transmitting unit includes: Antenna, adaptive matching network, surge protection unit and high voltage charge balancing unit, among which, Adaptive matching networks are used to automatically adjust impedance matching under different load or frequency conditions to maximize electromagnetic wave radiation efficiency and prevent energy reflection; The surge protection unit is used to suppress transient overvoltage and protect the safe operation of the antenna; The high-voltage charge equalization unit is used to release or equalize the residual high-voltage charge accumulated at the antenna port to prevent the accumulated charge from causing corona discharge or insulation breakdown.

5. The device according to claim 4, characterized in that The adaptive matching network comprises: The first and second branches, The first branch includes: a fourth diode, a second power relay, a ninth resistor, and a first inductor; The second branch includes: a fifth diode, a third power relay, a tenth resistor, and a second inductor; wherein, The anode of the fourth diode is connected to the fourth control terminal of the trigger control unit through the ninth resistor, and the cathode of the fourth diode is connected to the +5V power supply; The control end of the second power relay is connected to the anode of the fourth diode, and the normally open contact of the second power relay is connected to the first end of the first inductor; An anode of the fifth diode is connected to the fifth control terminal of the trigger control unit through a tenth resistor, and a cathode of the fifth diode is connected to a -5V power supply; The control end of the third power relay is connected to the anode of the fifth diode, and the normally open contact of the third power relay is connected to the first end of the second inductor; The second end of the second inductor and the second end of the first inductor are commonly connected to the input end of the surge protection unit.

6. The device according to claim 5, characterized in that The surge protection unit comprises: Gas discharge tube, transient suppression diode, high voltage bypass capacitor and current limiting resistor, among which, The first end of the current limiting resistor serves as the input end of the surge protection unit, and the second end of the current limiting resistor is simultaneously connected to the gas discharge tube, the transient suppression diode, and the first end of the high-voltage bypass capacitor; The second end of the gas discharge tube, the transient suppression diode and the high-voltage bypass capacitor are commonly connected to the input end of the high-voltage charge balancing unit.

7. The device according to claim 5, characterized in that The high-voltage charge balancing unit includes: The first branch and the second branch are connected in parallel. The first branch includes: a twelfth resistor, a fifth inductor, a varactor diode, and a third TVS diode connected in series; The second branch includes: A thirteenth resistor, a sixth inductor and a voltage suppression diode are connected in series, wherein: The first ends of the twelfth resistor and the thirteenth resistor serve together as the input end of the high-voltage charge balancing unit, and the second end of the twelfth resistor is connected to the anode of the varactor diode through the fifth inductor; An anode of a third TVS diode is connected to a connection point between the fifth inductor and the varactor diode, and a cathode of the third TVS diode is connected to a seventh ground terminal; The second end of the thirteenth resistor is connected to the cathode of the voltage suppression diode, the anode of the voltage suppression diode is connected to the first end of the sixth inductor, the second end of the sixth inductor is connected to the cathode of the varactor diode and is connected to the antenna as the output end of the high-voltage charge balancing unit.

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