Sampling hold circuit, chip and electronic equipment
By adding a sampling selection module to the sampling and holding circuit and selecting the sampling paths of the two selected signals in the same target signal group, the signal error problem caused by resistor network mismatch is solved, and the number of resistors and chip cost is reduced.
Patent Information
- Application Number
- CN202510425658.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-07
- Publication Date
- 2025-08-01
AI Technical Summary
In multi-channel signal sampling, due to mismatch in the resistor network during the production and manufacturing process, there are large errors in the signals sampled through different channels.
A sampling and holding circuit is adopted, including an input selection module, a resistor module, a sampling selection module, a sampling processing module and an output selection module. By adding the sampling selection module to select the sampling path of two target selected signals in the same target signal group, the resistor module can process two initial selected signals in the same initial signal group through two resistors.
Reduces the number of resistors used, reduces sampling errors, and reduces the area required for resistors, thereby reducing the cost of the chip.
Smart Images
Figure CN120415435A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the technical field of electronic circuits, and particularly to a sample-and-hold circuit, a chip, and an electronic device. Background Art
[0002] In multi-channel signal sampling, usually one channel corresponds to one sample-and-hold circuit, and each sample-and-hold circuit includes a resistor network composed of multiple resistors.
[0003] However, mismatches often occur in the production and manufacturing process of the resistor network, which may lead to large errors in the signals sampled through different channels. Summary of the Invention
[0004] In view of the above problems, embodiments of this application provide a sample-and-hold circuit, a chip, and an electronic device to solve the above technical problems.
[0005] In a first aspect, an embodiment of this application provides a sample-and-hold circuit, which includes an input selection module, a resistor module, a sampling selection module, a sampling processing module, and an output selection module. The input selection module is configured to select and output an input signal group from a plurality of input signal groups accessed as an initial signal group, and each initial signal group includes two initially selected signals. The resistor module is configured to process the two initially selected signals in the same initial signal group through two resistors respectively to generate a corresponding target signal group, and each target signal group includes two target selected signals. The sampling selection module is configured to select the sampling paths of the two target selected signals in the same target signal group. The sampling processing module is configured to sample the two target selected signals in the same target signal group to the same capacitor according to the sampling paths. The output selection module is configured to select and output the voltages at both ends of the same capacitor as a target output signal group.
[0006] In a second aspect, an embodiment of this application further provides a chip, which includes the above sample-and-hold circuit.
[0007] In a third aspect, an embodiment of this application further provides an electronic device, which includes a device main body and the above sample-and-hold circuit or chip provided on the device main body.
[0008] The sample-and-hold circuit, chip, and electronic device provided by the embodiments of the present application can enable the resistance module to process two initially selected signals in the same initial signal group through two resistors respectively by adding a sampling selection module for selecting the sampling paths of two target selected signals in the same target signal group between the resistance module and the sampling processing module. As a result, multiple channels can respectively multiplex two resistors. Compared with a resistor network that requires a larger number of resistors, the number of resistors used is reduced by two. This not only reduces the sampling error but also reduces the area occupied by the resistors, thereby reducing the cost of the chip.
[0009] These aspects or other aspects of the present application will be more clearly understood in the following description of the embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0010] To more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.
[0011] Figure 1 The principle block diagram of the sample-and-hold circuit provided by the embodiments of the present application is shown.
[0012] Figure 2 The circuit schematic diagram of the resistance module is shown.
[0013] Figure 3 The principle block diagram of the input selection module is shown.
[0014] Figure 4 The circuit schematic diagrams of the first input selection unit and the second input selection unit are shown.
[0015] Figure 5 The first principle block diagram of the sampling selection module is shown.
[0016] Figure 6 The first circuit schematic diagrams of the first sampling selection unit and the second sampling selection unit are shown.
[0017] Figure 7 The first circuit schematic diagram of the sampling processing module is shown.
[0018] Figure 8 The first principle block diagram of the output selection module is shown.
[0019] Figure 9 The first circuit schematic diagrams of the first output selection unit and the second output selection unit are shown.
[0020] Figure 10 The second principle block diagram of the sampling selection module is shown.
[0021] Figure 11 The second circuit schematic diagram of the first sampling selection unit and the second sampling selection unit is shown.
[0022] Figure 12 The second circuit schematic diagram of the sampling processing module is shown.
[0023] Figure 13 The second principle block diagram of the output selection module is shown.
[0024] Figure 14 The second circuit schematic diagram of the first output selection unit and the second output selection unit is shown.
[0025] Figure 15 The structural schematic diagram of the chip provided by the embodiment of the present application is shown.
[0026] Figure 16 The principle block diagram of the chip provided by the embodiment of the present application is shown.
[0027] Figure 17 The structural schematic diagram of the electronic device provided by the embodiment of the present application is shown. Detailed implementation manners
[0028] The following details the implementation manners of the present application. The examples of the implementation manners are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The implementation manners described below by referring to the accompanying drawings are exemplary only for explaining the present application and should not be construed as limiting the present application.
[0029] In order to enable those skilled in the art of the present technology to better understand the solution of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the scope of protection of the present application.
[0030] In the embodiments of the present application, it should be noted that in this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.
[0031] Moreover, the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, such that a process, method, article or apparatus comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or apparatus. Without further limitation, an element qualified by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element.
[0032] In the description of the embodiments of the present application, words such as "example" or "for example" are used to represent exemplification, illustration or description. Any embodiment or design solution described as "for example" or "for instance" in the embodiments of the present application is not construed as being more preferred or having more advantages than another embodiment or design solution. The use of words such as "example" or "for example" is intended to present relative concepts in a clear manner.
[0033] In addition, "a plurality of" in the embodiments of the present application means two or more. In view of this, "a plurality of" in the embodiments of the present application can also be understood as "at least two". "At least one" can be understood as one or more, for example, understood as one, two or more. For example, including at least one means including one, two or more, and does not limit which ones are included. For example, including at least one of A, B, and C, then what can be included are A, B, C, A and B, A and C, B and C, or A, B, and C.
[0034] It should be noted that "connection" in the embodiments of the present application can be understood as electrical connection, and the connection of two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.
[0035] In the embodiments of the present application, the first pole / first end of each transistor is one of the source and the drain, and the second pole / second end of each transistor is the other of the source and the drain. Since the source and the drain of a transistor can be symmetric in structure, there can be no difference in their structures. That is to say, the first pole / first end and the second pole / second end of the transistors in the embodiments of the present application can have no difference in structure. Exemplarily, when the transistor is a P-type transistor, the first pole / first end of the transistor is the source, and the second pole / second end is the drain; Exemplarily, when the transistor is an N-type transistor, the first pole / first end of the transistor is the drain, and the second pole / second end is the source.
[0036] The embodiments of the present application provide a sample and hold circuit 100, as Figure 1As shown, the sample and hold circuit 100 includes an input selection module 10, a resistor module 20, a sampling selection module 30, a sampling processing module 40, and an output selection module 50 connected in sequence. By adding the sampling selection module 30 for selecting the sampling paths of two target selected signals in the same target signal group between the resistor module 20 and the sampling processing module 40, the resistor module 20 can process two initial selected signals in the same initial signal group through two resistors respectively, so that multiple channels can respectively multiplex two resistors. Compared with the resistor network that requires a larger number of resistors, the number of resistors used is reduced by two. This not only reduces the sampling error, but also reduces the area occupied by the resistors, and thus can reduce the cost of the chip 200.
[0037] An embodiment of the present application provides a sample and hold circuit 100. Please refer to Figures 1 to 14 , as Figure 1 shown, the sample and hold circuit 100 includes an input selection module 10, a resistor module 20, a sampling selection module 30, a sampling processing module 40, and an output selection module 50. The input selection module 10 is configured to select and output an input signal group from a plurality of input signal groups connected thereto as an initial signal group, and each initial signal group includes two initial selected signals; the resistor module 20 is configured to process two initial selected signals in the same initial signal group through two resistors respectively to generate a corresponding target signal group, and each target signal group includes two target selected signals; the sampling selection module 30 is configured to select the sampling paths of two target selected signals in the same target signal group; the sampling processing module 40 is configured to sample two target selected signals in the same target signal group to the same corresponding capacitor according to the sampling paths; the output selection module 50 is configured to select and output the voltages at both ends of the same capacitor as a target output signal group.
[0038] It can be understood that for the sample and hold circuit 100 provided by the embodiment of the present application, by adding the sampling selection module 30 for selecting the sampling paths of two target selected signals in the same target signal group between the resistor module 20 and the sampling processing module 40, the resistor module 20 can process two initial selected signals in the same initial signal group through two resistors respectively, so that multiple channels can respectively multiplex two resistors. Compared with the resistor network that requires a larger number of resistors, the number of resistors used is reduced by two. This not only reduces the sampling error, but also reduces the area occupied by the resistors, and thus can reduce the cost of the chip 200.
[0039] It should be noted that each input signal group may include a first input signal (Vip) and a second input signal (Vin). The first input signal (Vip) is, for example, Vip1, Vip2... Vipn, and the second input signal (Vin) is, for example, Vin1, Vin2... Vinn. Among them, Vip1 and Vin1 can exemplarily be an input signal group, Vip2 and Vin2 can exemplarily be an input signal group, and so on. Vipn and Vinn can exemplarily be an input signal group. The target output signal group includes a first target output signal (Vop) and a second target output signal (Von), and the first target output signal (Vop) and the second target output signal (Von) can be a differential signal pair.
[0040] In some embodiments, as Figure 2 , Figure 10 shown, the resistor module 20 includes a first resistor R1 and a second resistor R2. The first end of the first resistor R1 is connected to the first output end of the input selection module 10, and the second end of the first resistor R1 is connected to the first input end of the sampling selection module 30. The first output end of the input selection module 10 is used to output the first input signal. The first end of the second resistor R2 is connected to the second output end of the input selection module 10, and the second end of the second resistor R2 is connected to the second input end of the sampling selection module 30. The second output end of the input selection module 10 is used to output the second input signal.
[0041] It should be noted that in this embodiment, the first input signal (Vip) can be processed by the first resistor R and then output as the first target output signal (Vop), and the second input signal (Vin) can be processed by the second resistor R2 and then output as the second target output signal (Von). This not only reduces the number of resistors used but also reduces the sampling error caused by using a larger number of resistors, thereby improving the pressure difference accuracy between the first target output signal (Vop) and the second target output signal (Von) in the target output signal group.
[0042] In some embodiments, as Figure 3 , Figure 10 shown, the input selection module 10 includes a first input selection unit 11 and a second input selection unit 12. The first input selection unit 11 is used to select and output a first input signal from multiple accessed first input signals. The second input selection unit 12 is used to select and output a second input signal from multiple accessed second input signals.
[0043] It should be noted that in this embodiment, a first input signal can be selected and output from multiple first input signals to the first resistor R1, and a second input signal can be selected and output from multiple second input signals to the second resistor R2, thereby realizing the sampling of different input signal groups.
[0044] In some of these embodiments, such as Figure 4 , Figure 10 shown, the first input selection unit 11 includes a plurality of first input selection switches. The first end of each first input selection switch is connected to a first input signal, and the second end of each first input selection switch is connected to the first end of a first resistor R1. The second input selection unit 12 includes a plurality of second input selection switches. The first end of each second input selection switch is connected to a second input signal, and the second end of each second input selection switch is connected to the first end of a second resistor R2. Among them, the second ends of the first input selection switches serve as the first output end of the input selection module 10, and the second ends of the first input selection switches serve as the second output end of the input selection module 10.
[0045] It should be noted that the plurality of first input selection switches are, for example, S11, S12... S1n, and the plurality of second input selection switches are, for example, S21, S22... S2n. When S11 and S21 are turned on synchronously, sampling of the input signal group of Vip1 and Vin1 can be achieved; when S12 and S22 are turned on synchronously, sampling of the input signal group of Vip2 and Vin2 can be achieved; and so on. When S1n and S2n are turned on synchronously, sampling of the input signal group of Vipn and Vinn can be achieved.
[0046] In some of these embodiments, such as Figure 5 shown, each target signal group includes a first target selected signal and a second target selected signal. The sampling selection module 30 includes a first sampling selection unit 31 and a second sampling selection unit 32. The first sampling selection unit 31 is used to select the sampling path of the first target selected signal; the second sampling selection unit 32 is used to select the sampling path of the second target selected signal.
[0047] It should be noted that the first target selected signal can be an initial selected signal processed by the first resistor R1, and the second target selected signal can be another initial selected signal processed by the second resistor R2.
[0048] In some of these embodiments, such as Figure 6As shown in the figure, the first sampling selection unit 31 includes a plurality of first sampling selection switches. The first end of each first sampling selection switch is connected to the second end of the first resistor R1, and the second end of each first sampling selection switch is respectively connected to different ends of the sampling processing module 40. The number of first sampling selection switches is equal to the number of first input selection switches. The second sampling selection unit 32 includes a plurality of second sampling selection switches. The first end of each second sampling selection switch is connected to the second end of the second resistor R2, and the second end of each second sampling selection switch is respectively connected to different ends of the sampling processing module 40. The number of second sampling selection switches is equal to the number of second input selection switches.
[0049] It should be noted that the plurality of first sampling selection switches are, for example, S31, S32... S3n, and the plurality of second sampling selection switches are, for example, S41, S42... S4n. When S31 and S41 are synchronously turned on, the first target selected signal and the second target selected signal in the same target signal group can be transmitted to both ends of a capacitor in the sampling processing module 40; when S32 and S42 are synchronously turned on, the first target selected signal and the second target selected signal in the same target signal group can be transmitted to both ends of another capacitor in the sampling processing module 40; and so on. When S3n and S4n are synchronously turned on, the first target selected signal and the second target selected signal in the same target signal group can be transmitted to both ends of yet another capacitor in the sampling processing module 40.
[0050] In some embodiments, as Figure 7 shown, the sampling processing module 40 includes a plurality of capacitors. The first end of each capacitor is connected to the second end of a first sampling selection switch, and the second end of each capacitor is connected to the second end of a second sampling selection switch.
[0051] It should be noted that the plurality of capacitors are, for example, C11, C12... C1n. When S31 and S41 are synchronously turned on, the first target selected signal and the second target selected signal in the same target signal group can be transmitted to both ends of C11; when S32 and S42 are synchronously turned on, the first target selected signal and the second target selected signal in the same target signal group can be transmitted to both ends of C12; and so on. When S3n and S4n are synchronously turned on, the first target selected signal and the second target selected signal in the same target signal group can be transmitted to both ends of C1n.
[0052] In some embodiments, as Figure 8 shown, the output selection module 50 includes a first output selection unit 51 and a second output selection unit 52. The first output selection unit 51 is used to select and output the voltage at the first end of a capacitor as the first target output signal; the second output selection unit 52 is used to select and output the voltage at the second end of the capacitor as the second target output signal.
[0053] It should be noted that in this embodiment, under the control of the first output selection unit 51 and the second output selection unit 52, the voltages at both ends of different capacitors can be selected as the first target output signal and the second target output signal.
[0054] In some embodiments, as Figure 9 shown, the first output selection unit 51 includes a plurality of first output selection switches. The first end of each first output selection switch is connected to the first end of a capacitor, and the second ends of each first output selection switch are connected to each other and output the first target output signal. The second output selection unit 52 includes a plurality of second output selection switches. The first end of each second output selection switch is connected to the second end of a capacitor, and the second ends of each second output selection switch are connected to each other and output the second target output signal.
[0055] It should be noted that the plurality of first output selection switches are, for example, S51, S52... S5n, and the plurality of second output selection switches are, for example, S61, S62... S6n. S51 and S61 are synchronously turned on, and the voltage across C11 can be output as Vop and Von; S52 and S62 are synchronously turned on, and the voltage across C12 can be output as Vop and Von; and so on. S5n and S6n are synchronously turned on, and the voltage across C1n can be output as Vop and Von.
[0056] In some embodiments, as Figure 10 shown, the sampling selection module 30 includes a first sampling selection unit 31 and a second sampling selection unit 32. The first sampling selection unit 31 is used to select the sampling path of the first target selected signal; the second sampling selection unit 32 is used to select the sampling path of the second target selected signal.
[0057] It should be noted that the first target selected signal can be an initial selected signal processed by the first resistor R1, and the second target selected signal can be another initial selected signal processed by the second resistor R2.
[0058] In some embodiments, as Figure 11As shown, the first sampling selection unit 31 includes a first switch S71 and a second switch S72. The first end of the first switch S71 is connected to the second end of the first resistor R1, and the second end of the first switch S71 is connected to the first end of the sampling processing module 40. The first end of the second switch S72 is connected to the second end of the first resistor R1, and the second end of the second switch S72 is connected to the second end of the sampling processing module 40. The second sampling selection unit 32 includes a third switch S73 and a fourth switch S74. The first end of the third switch S73 is connected to the second end of the second resistor R2, and the second end of the third switch S73 is connected to the third end of the sampling processing module 40. The first end of the fourth switch S74 is connected to the second end of the second resistor R2, and the second end of the fourth switch S74 is connected to the fourth end of the sampling processing module 40.
[0059] It should be noted that the first switch S71 and the third switch S73 are synchronously turned on, and the first target selected signal and the second target selected signal in the same target signal group can be transmitted to both ends of a capacitor in the sampling processing module 40. The second switch S72 and the fourth switch S74 are synchronously turned on, and the first target selected signal and the second target selected signal in the same target signal group can be transmitted to both ends of another capacitor in the sampling processing module 40. Compared with the foregoing embodiments, the present embodiment realizes the selection of the sampling path with a smaller number of switches, which not only reduces the occupied area of the switches, but also reduces the cost.
[0060] In some embodiments, as Figure 12 shown, the sampling processing module 40 includes a first capacitor C1 and a second capacitor C2. The first end of the first capacitor C1 is connected to the second end of the first switch S71, and the second end of the first capacitor C1 is connected to the second end of the third switch S73. The first end of the second capacitor C2 is connected to the second end of the second switch S72, and the second end of the second capacitor C2 is connected to the second end of the fourth switch S74.
[0061] It should be noted that the first switch S71 and the third switch S73 are synchronously turned on, and the first target selected signal and the second target selected signal in the same target signal group can be transmitted to both ends of the first capacitor C1. The second switch S72 and the fourth switch S74 are synchronously turned on, and the first target selected signal and the second target selected signal in the same target signal group can be transmitted to both ends of the second capacitor C2. Compared with the foregoing embodiments, the sampling processing module 40 constructed with a smaller number of capacitors in the present embodiment reduces the occupied area and cost of the capacitors by reducing the number of capacitors.
[0062] In some embodiments, as Figure 13As shown in the figure, the output selection module 50 includes a first output selection unit 51 and a second output selection unit 52. The first output selection unit 51 is configured to select and output the voltage at the first end of the first capacitor or the voltage at the first end of the second capacitor as the first target output signal; the second output selection unit 52 is configured to select and output the voltage at the second end of the first capacitor or the voltage at the second end of the second capacitor as the second target output signal.
[0063] It should be noted that, in this embodiment, under the control of the first output selection unit 51 and the second output selection unit 52, the voltages at both ends of different capacitors can be selected and output as the first target output signal and the second target output signal. Due to the reduction in the number of capacitors, it is beneficial to simplify the structures of the first output selection unit 51 and the second output selection unit 52 and reduce costs.
[0064] In some embodiments, as Figure 14 shown, the first output selection unit 51 includes a fifth switch S75 and a sixth switch S76. The first end of the fifth switch S75 is connected to the first end of the first capacitor C1, and the second end of the fifth switch S75 is used to output the first target output signal; the first end of the sixth switch S76 is connected to the first end of the second capacitor C2, and the second end of the sixth switch S76 is connected to the second end of the fifth switch S75. The second output selection unit 52 includes a seventh switch S77 and an eighth switch S78. The first end of the seventh switch S77 is connected to the second end of the first capacitor C1, and the second end of the seventh switch S77 is used to output the second target output signal; the first end of the eighth switch S78 is connected to the second end of the second capacitor C2, and the second end of the eighth switch S78 is connected to the second end of the seventh switch S77.
[0065] It should be noted that the fifth switch S75 and the seventh switch S77 are synchronously turned on, and the voltages at both ends of the first capacitor C1 can be output as Vop and Von; the sixth switch S76 and the eighth switch S78 are synchronously turned on, and the voltages at both ends of the second capacitor C2 can be output as Vop and Von. Compared with the foregoing embodiments, the first output selection unit 51 and the second output selection unit 52 constructed with a smaller number of switches in this embodiment reduce the occupied area and cost of the switches by reducing the number of switches.
[0066] The embodiment of the present application further provides a chip 200, as Figure 15 shown. The chip 200 includes the above-mentioned sample and hold circuit 100. The chip 200 is also referred to as an integrated circuit (IC). The chip 200 can be, but is not limited to, a system-on-chip (SOC) chip or a system-in-package (SIP) chip.
[0067] It can be understood that since the chip 200 provided by the embodiments of the present application includes the above-mentioned sample and hold circuit 100, and a sample selection module 30 for adding a sample path for selecting two target selected signals in the same target signal group can also be added between the resistor module 20 and the sample processing module 40, the resistor module 20 can process two initial selected signals in the same initial signal group through two resistors respectively, so that multiple channels can respectively multiplex two resistors. Compared with a resistor network that requires a larger number of resistors, the number of resistors used is reduced by two, which not only reduces the sampling error, but also reduces the area occupied by the resistors, and thus can reduce the cost of the chip 200.
[0068] In some embodiments, as Figure 16 shown, the chip 200 further includes an analog-to-digital converter 110. The input end of the analog-to-digital converter 110 is connected to the output end of the sample and hold circuit 100, and the target output signal group (Vop, Von) is used as the differential input signal of the analog-to-digital converter 110.
[0069] It should be noted that the analog-to-digital converter 110 can be, for example, a successive approximation analog-to-digital converter (SAR ADC), a Delta-Sigma ADC (Σ-Δ ADC), or a pipelined analog-to-digital converter, etc.
[0070] Optionally, the digital processing circuit 120 can be disposed in the chip 200 or outside the chip 200. The input end of the digital processing circuit 120 is connected to the output end of the analog-to-digital converter 110 to perform digital processing on the digital signal output by the analog-to-digital converter 110.
[0071] The embodiments of the present application also provide an electronic device 300, as Figure 17 shown, the electronic device 300 includes a device main body and the above-mentioned sample and hold circuit 100 or chip 200 disposed in the device main body. The electronic device 300 can be, but is not limited to, a weighing scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a vehicle charger, an adapter, a display, a USB (Universal Serial Bus) expansion dock, a stylus, a true wireless earphone, an in-vehicle display screen, a vehicle, a smart wearable device, a mobile terminal, a smart home device. The smart wearable device includes, but is not limited to, a smart watch, a smart bracelet, and a cervical massager. The mobile terminal includes, but is not limited to, a smart phone, a laptop computer, a tablet computer, and a POS (point of sales terminal) machine. The smart home device includes, but is not limited to, a smart socket, a smart rice cooker, a smart sweeper, and a smart light.
[0072] It can be understood that since the electronic device 300 provided in the embodiment of the present application includes the above-mentioned sample-and-hold circuit 100 or chip 200, a sample selection module 30 for selecting sampling paths of two target selected signals in the same target signal group can also be added between the resistor module 20 and the sampling processing module 40. This enables the resistor module 20 to process two initial selected signals in the same initial signal group through two resistors respectively, so that multiple channels can respectively multiplex two resistors. Compared with a resistor network that requires a larger number of resistors, the number of resistors used is reduced by two. This not only reduces the sampling error but also reduces the area occupied by the resistors, thereby reducing the cost of the chip 200.
[0073] The above are only the preferred embodiments of the present application and do not impose any form of limitation on the present application. Although the present application has been disclosed above with the preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to equivalent embodiments by using the technical content disclosed above without departing from the technical solution scope of the present application. However, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still fall within the scope of the technical solution of the present application.
Claims
1. A sample-and-hold circuit, characterized in that, The sample-and-hold circuit includes: An input selection module, which is configured to select and output one of the multiple input signal groups connected thereto as an initial signal group, and each initial signal group includes two initially selected signals; A resistor module, which is configured to process the two initially selected signals in the same initial signal group through two resistors respectively to generate a corresponding target signal group, and each target signal group includes two target selected signals; A sampling selection module, which is configured to select the sampling paths of the two target selected signals in the same target signal group; A sampling processing module, which is configured to sample the two target selected signals in the same target signal group to the same corresponding capacitor according to the sampling paths; An output selection module, which is configured to select and output the voltages at both ends of the same capacitor as a target output signal group.
2. The sample and hold circuit according to claim 1, wherein Each input signal group includes a first input signal and a second input signal, and the resistor module includes: A first resistor, the first end of which is connected to the first output end of the input selection module, the second end of which is connected to the first input end of the sampling selection module, and the first output end of the input selection module is configured to output the first input signal; A second resistor, the first end of which is connected to the second output end of the input selection module, the second end of which is connected to the second input end of the sampling selection module, and the second output end of the input selection module is configured to output the second input signal.
3. The sampling and holding circuit according to claim 2, wherein The input selection module includes: A first input selection unit, which is configured to select and output one of the multiple first input signals connected thereto; A second input selection unit, which is configured to select and output one of the multiple second input signals connected thereto.
4. The sampling and holding circuit according to claim 3, wherein The first input selection unit includes multiple first input selection switches, the first end of each first input selection switch is connected to a first input signal, the second end of each first input selection switch is connected to the first end of the first resistor, and the second ends of the first input selection switches serve as the first output end of the input selection module; The second input selection unit includes multiple second input selection switches, the first end of each second input selection switch is connected to a second input signal, the second end of each second input selection switch is connected to the first end of the second resistor, and the second ends of the second input selection switches serve as the second output end of the input selection module.
5. The sampling and holding circuit according to claim 1, wherein Each target signal group includes a first target selected signal and a second target selected signal, and the sampling selection module includes: A first sampling selection unit, which is configured to select the sampling path of the first target selected signal; A second sampling selection unit, which is configured to select the sampling path of the second target selected signal.
6. The sampling and holding circuit according to claim 5, wherein The first sampling selection unit includes a plurality of first sampling selection switches. The first end of each first sampling selection switch is connected to the first output end of the resistor module, and the second end of each first sampling selection switch is respectively connected to different ends of the sampling processing module. The number of the first sampling selection switches is equal to the number of the first input selection switches; The second sampling selection unit includes a plurality of second sampling selection switches. The first end of each second sampling selection switch is connected to the second output end of the resistor module, and the second end of each second sampling selection switch is respectively connected to different ends of the sampling processing module. The number of the second sampling selection switches is equal to the number of the second input selection switches.
7. The sampling and holding circuit according to claim 1, wherein The sampling processing module includes a plurality of capacitors. The first end of each capacitor is connected to a first output end of the sampling selection module, and the second end of each capacitor is connected to a second output end of the sampling selection module.
8. The sampling and holding circuit according to claim 1, wherein The target output signal group includes a first target output signal and a second target output signal. The output selection module includes: A first output selection unit configured to select and output the voltage at the first end of a capacitor in the sampling processing module as the first target output signal; A second output selection unit configured to select and output the voltage at the second end of the capacitor in the sampling processing module as the second target output signal.
9. The sampling and holding circuit according to claim 8, characterized in that, The first output selection unit includes a plurality of first output selection switches. The first end of each first output selection switch is connected to the first end of a capacitor, and the second ends of each first output selection switch are connected to each other and output the first target output signal; The second output selection unit includes a plurality of second output selection switches. The first end of each second output selection switch is connected to the second end of a capacitor, and the second ends of each second output selection switch are connected to each other and output the second target output signal.
10. The sampling and holding circuit according to any one of claims 1 to 4, characterized in that Each target signal group includes a first target selection signal and a second target selection signal. The sampling selection module includes: A first sampling selection unit configured to select the sampling path of the first target selection signal; A second sampling selection unit configured to select the sampling path of the second target selection signal; Wherein, the first sampling selection unit includes: A first switch, the first end of which is connected to the second end of the first resistor, and the second end of which is connected to the first end of the sampling processing module; A second switch, the first end of which is connected to the second end of the first resistor, and the second end of which is connected to the second end of the sampling processing module; The second sampling selection unit includes: A third switch, the first end of which is connected to the second end of the second resistor, and the second end of which is connected to the third end of the sampling processing module; A fourth switch, a first end of the fourth switch is connected to a second end of the second resistor, and a second end of the fourth switch is connected to a fourth end of the sampling and processing module.
11. The sampling and holding circuit according to claim 10, wherein The sampling and processing module includes: A first capacitor, a first end of the first capacitor is connected to a second end of the first switch, and a second end of the first capacitor is connected to a second end of the third switch; A second capacitor, a first end of the second capacitor is connected to a second end of the second switch, and a second end of the second capacitor is connected to a second end of the fourth switch.
12. The sample and hold circuit according to claim 11, wherein The target output signal group includes a first target output signal and a second target output signal, and the output selection module includes: A first output selection unit, the first output selection unit is configured to select and output a voltage at a first end of the first capacitor or a voltage at a first end of the second capacitor as the first target output signal; A second output selection unit, the second output selection unit is configured to select and output a voltage at a second end of the first capacitor or a voltage at a first end of the first capacitor as the second target output signal.
13. The sampling and holding circuit according to claim 12, wherein The first output selection unit includes: A fifth switch, a first end of the fifth switch is connected to a first end of the first capacitor, and a second end of the fifth switch is used to output the first target output signal; A sixth switch, a first end of the sixth switch is connected to a first end of the second capacitor, and a second end of the sixth switch is connected to a second end of the fifth switch; The second output selection unit includes: A seventh switch, a first end of the seventh switch is connected to a second end of the first capacitor, and a second end of the seventh switch is used to output the second target output signal; An eighth switch, a first end of the eighth switch is connected to a second end of the second capacitor, and a second end of the eighth switch is connected to a second end of the seventh switch.
14. A chip, characterized in that, The chip includes the sampling and holding circuit according to any one of claims 1 to 13.
15. The chip according to claim 14, characterized in that, The chip further includes an analog-to-digital converter, and the target output signal group is used as a differential input signal of the analog-to-digital converter.
16. An electronic device, characterized in that, The electronic device includes a device main body and the chip according to claim 14 or 15 provided on the device main body.