An ultra-wideband receiver with multi-channel amplitude and phase calibration

Abstract

The present invention discloses a multi-channel amplitude and phase calibrated ultra-wideband receiver, comprising a first signal acquisition module, a second signal acquisition module, and an FPGA. The first signal acquisition module comprises a first selection switch, a second selection switch, a third selection switch, and a first mixer, a first intermediate frequency filter, a first amplifier, a first digitally controlled attenuator, a second intermediate frequency filter, a first automatic gate controller (AGC), and a first analog-to-digital converter (AD converter) connected in sequence. The second signal acquisition module comprises an eight-select-one switch selection array and a second mixer, a third intermediate frequency filter, a second amplifier, a second digitally controlled attenuator, a fourth intermediate frequency filter, a second AGC, and a second AD converter connected in sequence. The present invention utilizes two frequency conversion channels to achieve frequency conversion acquisition and signal amplitude and phase calibration. The receiver features a small number of components, a compact size, ease of integration, and low cost.

Description

Technical Field

[0001] The present invention relates to the field of receivers, and in particular to an ultra-wideband receiver with multi-channel amplitude and phase calibration. Background Art

[0002] Receivers are a crucial component of technical reconnaissance, space, and communications technologies. Frequency conversion and calibration of frequency signals are widely used in communications, radar, electronic countermeasures, instrumentation, and other fields. To cope with today's increasingly complex electronic environments, receivers must possess ultra-wideband, multi-channel, low spurious emissions, and a wide dynamic range. Therefore, designing an ultra-wideband, multi-channel, low-spurious receiver is crucial for frequency, amplitude, and phase calibration.

[0003] The current industry's main disadvantages of ultra-wideband receivers are large size, heavy weight, and inconvenience in product integration and miniaturization. The popular technical solution is to use RF preselection, image frequency suppression, secondary mixing or multiple mixing, intermediate frequency filtering, signal amplification, and A / D sampling at the input front end. This has the characteristics of complex implementation, multiple components, large size, and high cost. Figure 1 As shown in the figure, the RF signal passes through the RF preselector group, effectively suppressing harmonics and images, reducing intermodulation products and spurious signals. The amplifier compensates for signal amplitude loss and improves gain. After mixing, the first intermediate signal is generated. Passing through IF filter 1, it effectively suppresses out-of-band signals and improves the IF rejection ratio. The signal is mixed again to obtain the second intermediate signal. Passing through IF filter 2, it further suppresses out-of-band signals and effectively prevents the entry of spurious signals. The signal is then sampled by A / D and sent to the FPGA for processing.

[0004] Due to the ultra-wide frequency band (1M-50GHz), this technical solution has redundant RF preselector groups, two mixing (or multiple times), two intermediate frequency filtering and related amplification; there are more devices, larger size and higher cost; the eight-channel solution has more devices, larger size, higher cost, difficult to integrate and miniaturize, and has less market competitiveness. Summary of the Invention

[0005] The purpose of the present invention is to overcome the shortcomings of the existing technology and provide an ultra-wideband receiver with multi-channel amplitude and phase calibration, which realizes frequency conversion acquisition by two frequency conversion channels and realizes signal amplitude and phase calibration; it has the advantages of few components, small size, easy integration and low cost.

[0006] The object of the present invention is achieved through the following technical solutions: A multi-channel amplitude and phase calibrated ultra-wideband receiver, comprising a first signal acquisition module, a second signal acquisition module and an FPGA;

[0007] The first signal acquisition module includes a first strobe switch, a second strobe switch, a third strobe switch, and a first mixer, a first intermediate frequency filter, a first amplifier, a first digitally controlled attenuator, a second intermediate frequency filter, a first AGC, and a first AD converter connected in sequence; a first input end of the first strobe switch is connected to the CH_1 channel, and a second input end is grounded via a first resistor; an output end of the first strobe switch is connected to a first input end of the second strobe switch, and a second input end of the second strobe switch is grounded via a second resistor; an output end of the second strobe switch is connected to a first input end of the third strobe switch, and a second input end of the third strobe switch is grounded via a third resistor, and an output end of the third strobe switch is connected to a signal input end of the first mixer; and an output end of the first AD converter is connected to an FPGA;

[0008] The second signal acquisition module includes an eight-selective switch array, and a second mixer, a third intermediate frequency filter, a second amplifier, a second digitally controlled attenuator, a fourth intermediate frequency filter, a second AGC, and a second AD converter connected in sequence; a first input end of the switch array is connected to ground via a second resistor, and the remaining seven input ends are connected to channels CH_2, CH_3, CH_4, CH_5, CH_6, CH_7, and CH_8, respectively; an output end of the switch array is connected to a signal input end of the second mixer, and an output end of the second AD converter is connected to an FPGA;

[0009] The FPGA identifies the phase and amplitude of the signal output by the first signal acquisition module to form standard sample data; and when the switch selection array selects CH2, CH_3, CH_4, CH_5, CH_6, CH_7, and CH_8 channels respectively, it calculates the amplitude and phase sample data of each channel and compares them with the standard sample data. If an error occurs that does not meet the conditions with the sample data of CH_1, a request for amplitude and phase adjustment of CH_2, CH_3, CH_4, CH_5, CH_6, CH_7, and CH_8 is sent to the host computer connected to the FPGA.

[0010] The FPGA converts the input data to baseband through digital down-conversion, filters the fixed-frequency signal through CIC+FIR filters, and performs orthogonal demodulation to decompose it into in-phase I and quadrature Q components, filter out-of-band noise and sample extraction; then uses the CORDIC algorithm module and inverse tangent operation to obtain phase and amplitude:

[0011] In vector mode, ensure I and Q data synchronization to avoid phase error and perform vector amplitude and phase calculations as follows:

[0012] Amplitude =

[0013] Phase = arctan(Q / I).

[0014] The beneficial effects of the present invention are as follows: the present invention realizes frequency conversion acquisition of multi-channel ultra-wideband signals by two frequency conversion channels, and realizes signal amplitude and phase calibration; it has the characteristics of few components, small size, easy integration, low cost, etc., and is an ideal choice for multi-channel frequency conversion to perform amplitude and phase calibration. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a schematic diagram of the principle of an existing ultra-wideband receiver;

[0016] Figure 2 It is a schematic diagram of the principle of the present invention;

[0017] Figure 3 Schematic diagram of FPGA data processing;

[0018] Figure 4 This is a schematic diagram of the principle of the local oscillator module. DETAILED DESCRIPTION

[0019] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings, but the protection scope of the present invention is not limited to the following.

[0020] like Figure 2 As shown, a multi-channel amplitude and phase calibrated ultra-wideband receiver includes a first signal acquisition module, a second signal acquisition module and an FPGA 18;

[0021] The first signal acquisition module includes a first gate switch 1, a second gate switch 2, a third gate switch 22, and a first mixer 3, a first intermediate frequency filter 4, a first amplifier 5, a first digitally controlled attenuator 6, a second intermediate frequency filter 7, a first AGC 8 and a first AD converter 9 connected in sequence; the first input end of the first gate switch 1 is connected to the CH_1 channel, and the second input end is grounded through a first resistor; the output end of the first gate switch is connected to the first input end of the second gate switch 2, and the second input end of the second gate switch 2 is grounded through a second resistor; the output end of the second gate switch 2 is connected to the first input end of the third gate switch 22, and the second input end of the third gate switch 22 is grounded through a third resistor, and the output end of the third gate switch 22 is connected to the signal input end of the first mixer 3; the output end of the first AD converter 9 is connected to the FPGA 18;

[0022] The second signal acquisition module includes an eight-selective switch gating array, and a second mixer 11, a third intermediate frequency filter 12, a second amplifier 13, a second digitally controlled attenuator 14, a fourth intermediate frequency filter 15, a second AGC 16, and a second AD converter 17 connected in sequence; the first input end of the switch gating array is connected to ground through a second resistor, and the remaining seven input ends are respectively connected to the CH_2, CH_3, CH_4, CH_5, CH_6, CH_7, and CH_8 channels; the output end of the switch gating switch is connected to the signal input end of the second mixer 11, and the output end of the second AD converter 17 is connected to the FPGA 18;

[0023] The FPGA18 identifies the phase and amplitude of the signal output by the first signal acquisition module to form standard sample data; and when the switch selection array selects CH_2, CH_3, CH_4, CH_5, CH_6, CH_7, and CH_8 channels respectively, it calculates the amplitude and phase sample data of each channel respectively, and compares them with the standard sample data. If an error occurs that does not meet the conditions with the sample data of CH_1, a request for amplitude and phase adjustment of the non-compliant channel is sent to the host computer connected to the FPGA. After receiving the instruction, the host computer will adjust the amplitude and phase of the non-compliant channel.

[0024] Acquisition of standard signals: The RF signal enters the CH_1 channel and is selected by a two-choice switch. It is converted to an intermediate frequency signal by a mixer and enters an intermediate frequency filter to filter out out-of-band spurious signals to ensure signal purity. It is amplified by an amplifier to compensate for frequency conversion loss and then attenuated by a digitally controlled attenuator (controlling signal gain to match the signal level range of the A / D sampling). It then enters an intermediate frequency filter for secondary filtering and is amplified by an AGC (programmable gain amplifier) ​​(link loss varies at different frequencies on the link, with higher high-frequency loss. The AGC gain is adjusted through program control to compensate for high-frequency loss to match the level range of the A / D sampling). It is then converted into a digital signal by A / D sampling. The FPGA identifies the phase and amplitude to form standard sample data.

[0025] The sampling principle of CH_2, CH_3, CH_4, CH_5, CH_6, CH_7, and CH_8 channels is the same as that of CH_1. The channel signal sample data collected by CH_2, CH_3, CH_4, CH_5, CH_6, CH_7, and CH_8 are compared with the sample data of CH_1. If there is an error that does not meet the conditions with the sample data of CH_1, the host computer will adjust the frequency, phase, and amplitude of the input signals of CH_2, CH_3, CH_4, CH_5, CH_6, CH_7, and CH_8.

[0026] Before frequency conversion, the two frequency conversion channels, CH_1, CH_2, CH_3, CH_4, CH_5, CH_6, CH_7, and CH_8, have the same number of two-choice switches, a symmetrical layout, and equal trace lengths. This same number of two-choice switches and trace lengths ensures the same link loss for the eight input signals and consistent signal gain for each channel. Identical trace lengths ensure the same link signal delay, thus ensuring the same signal phase on the link. After frequency conversion, the two channels also maintain symmetrical device distribution and equal trace lengths, minimizing amplitude and phase errors generated by the link.

[0027] The transmission loss and conversion loss of the output signal levels of CH_1, CH_2, CH_3, CH_4, CH_5, CH_6, CH_7, and CH_8 (e.g., signal dynamic range: -90dBm to +8dBm) on the link are related to the ADC (SFDR: 90dBc,

[0028] If the sampling level of the 2.7 Vp-p analog-to-digital converter (ADC) does not meet the sampling level range, the output signal levels of CH_1, CH_2, CH_3, CH_4, CH_5, CH_6, CH_7, and CH_8 cannot be calibrated, resulting in inaccurate output levels. The FPGA must set the sampling level range. If the actual signal level is outside this range, the FPGA automatically activates the AGC and digitally controlled attenuator control programs to adjust the gain of the frequency conversion channel to bring the input signal level within the ADC sampling level range. This ensures a wide dynamic range and high accuracy for the output signal levels of CH_1, CH_2, CH_3, CH_4, CH_5, CH_6, CH_7, and CH_8. Different frequency signals experience different transmission losses on the transmission link. Lower frequency signals experience less loss, while higher (millimeter wave) frequency signals experience greater loss on the same transmission link. The calibration program automatically activates the AGC and digitally controlled attenuator control programs based on the signal level on the link to ensure that the signal level meets the ADC sampling requirements.

[0029] like Figure 3 As shown, the sampling data of the AD converter is sent to the FPGA to convert the RF signal to baseband through digital down conversion (DDC). The fixed frequency signal after frequency conversion is filtered by CIC+FIR filter (signal bandwidth is 100kHz / 10kHz), and orthogonal demodulation is performed to decompose it into in-phase (I) and quadrature (Q) components, filter out-of-band noise and perform sample extraction; then the algorithm of the CORDIC algorithm module and the inverse tangent operation are used to obtain the phase and amplitude. In vector mode, the I and Q channel data are synchronized to avoid phase error, and the vector amplitude and phase calculation are performed, as shown in the following formula:

[0030] Amplitude =

[0031] Phase = arctan(Q / I)

[0032] If the amplitude and phase fluctuate, the AGC gain module (or digitally controlled attenuator) can be adjusted to adjust the link gain, ensuring it operates within the appropriate power range. The aforementioned digital function modules process the sampled data from the ADC, resulting in a lower resolution for digital signals sampled at smaller bandwidths, less signal jitter, and higher phase and amplitude consistency. This provides an accurate basis for the host computer to issue phase and amplitude adjustments to the multiple signal sources (CH_2, CH_3, CH_4, CH_5, CH_6, CH_7, and CH_8), ensuring consistent amplitude and phase of the signal outputs.

[0033] like Figure 4 As shown, in the embodiment of the present application, the local oscillator module includes a PLL circuit 28, a third amplifier 29, an eleventh selection switch 30, a frequency multiplier 31, a first filter group 32, a twelfth selection switch 33, a fourth amplifier 34, a third digitally controlled attenuator 35, a fifth amplifier 36, a DDS module 37, a second filter group 38 and a third filter group 39;

[0034] The output end of the PLL circuit 28 is respectively connected to the third amplifier 29 and the DDS module 37, the output end of the third amplifier 29 is connected to the eleventh selection switch 30, the output end of the eleventh selection switch 30 is respectively connected to the frequency multiplier 31 and the second filter group 38, the output end of the frequency multiplier 31 is connected to the first filter group 32, the output end of the DDS module 37 is connected to the third filter group 39, the output ends of the first filter group 32, the second filter group 38 and the third filter group 39 are all connected to the twelfth selection switch 33; the output end of the twelfth selection switch 33 is connected to the power divider 27 through the fourth amplifier 34, the third digitally controlled attenuator 35 and the fifth amplifier 36. The frequency signal generated by the PLL (frequency synthesizer) suppresses harmonics through the filter group, is amplified by the amplifier to the power level required by the mixer, and then is divided by the power divider and mixed with the mixer and the signals input by CH_1, CH_2, CH_3, CH_4, CH_5, CH_6, CH_7, and CH_8 to form an intermediate frequency signal; due to the wide frequency of this invention, the PLL cannot directly generate a sufficiently high or low frequency signal, and the higher frequency signal is filtered and amplified by frequency multiplication and then mixed with the mixer and CH_1, CH_2, CH_3, CH_8. The CH_4, CH_5, CH_6, CH_7, and CH_8 signals are mixed into intermediate frequency signals. Lower frequency signals are generated by the DDS and filtered and amplified before being mixed with the CH_1, CH_2, CH_3, CH_4, CH_5, CH_6, CH_7, and CH_8 signals by the mixer to form intermediate frequency signals. The digitally controlled attenuator is used to attenuate large link signals to the power level required by the mixer for mixing with the CH_1, CH_2, CH_3, CH_4, CH_5, CH_6, CH_7, and CH_8 signals.

[0035] The foregoing description is a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the form disclosed herein and should not be construed as excluding other embodiments. Instead, the present invention can be used in other combinations, modifications, and environments and can be modified within the scope of the concept described herein through the above teachings or techniques or knowledge in the relevant field. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention are intended to be protected by the appended claims.

Claims

1. A multi-channel amplitude and phase calibrated ultra-wideband receiver, characterized by: It includes a first signal acquisition module, a second signal acquisition module and an FPGA (18); The first signal acquisition module comprises a first selection switch (1), a second selection switch (2), a third selection switch (22), and a first mixer (3), a first intermediate frequency filter (4), a first amplifier (5), a first digitally controlled attenuator (6), a second intermediate frequency filter (7), a first AGC (8) and a first AD converter (9) connected in sequence; the first input end of the first selection switch (1) is connected to the CH_1 channel, and the second input end is grounded through a first resistor; the output end of the first selection switch is connected to the first input end of the second selection switch (2), and the second input end of the second selection switch (2) is grounded through a second resistor; the output end of the second selection switch (2) is connected to the first input end of the third selection switch (22), and the second input end of the third selection switch (22) is grounded through a third resistor, and the output end of the third selection switch (22) is connected to the signal input end of the first mixer (3); the output end of the first AD converter (9) is connected to the FPGA (18); The second signal acquisition module includes an eight-select switch array, and a second mixer (11), a third intermediate frequency filter (12), a second amplifier (13), a second digitally controlled attenuator (14), a fourth intermediate frequency filter (15), a second AGC (16) and a second AD converter (17) connected in sequence; the first input end of the switch array is connected to the ground through a second resistor, and the remaining seven input ends are connected to the CH_2, CH_3, CH_4, CH_5, CH_6, CH_7 and CH_8 channels respectively; the output end of the switch array is connected to the signal input end of the second mixer (11), and the output end of the second AD converter (17) is connected to the FPGA (18); The FPGA (18) identifies the phase and amplitude of the signal output by the first signal acquisition module to form standard sample data; and when the switch selection array selects the CH_2, CH_3, CH_4, CH_5, CH_6, CH_7, and CH_8 channels respectively, calculates the amplitude and phase sample data of each channel respectively, and compares them with the standard sample data; if an error occurs that does not meet the conditions with the sample data of CH_1, a request for amplitude and phase adjustment of the channel that does not meet the conditions is sent to a host computer connected to the FPGA; The number of two-choice switches before frequency conversion for channels CH_1, CH_2, CH_3, CH_4, CH_5, CH_6, CH_7, and CH_8 is the same, their layout and routing are symmetrical, and their routing lengths are equal; The FPGA needs to set the sampling level range. If the actual signal level is not within the range, the FPGA automatically starts the control program of the AGC and digitally controlled attenuator, and adjusts the gain of the frequency conversion channel to make the input signal level within the sampling level range of the ADC analog-to-digital converter.

2. The multi-channel amplitude and phase calibrated ultra-wideband receiver according to claim 1, wherein: The switch gating array comprises a fourth gating switch to a tenth gating switch, wherein the first input end of the fourth gating switch (19) is grounded through a fourth resistor, and the second input end is connected to the CH_2 channel; the input ends of the fifth gating switch (23), the sixth gating switch (24), and the seventh gating switch (25) are respectively connected to the CH_3, CH_4, CH_5, CH_6, CH_7, and CH_8 channels; the input end of the eighth gating switch (20) is respectively connected to the output ends of the fourth gating switch (19) and the fifth gating switch (23); the input end of the ninth gating switch (26) is respectively connected to the output ends of the sixth gating switch (24) and the seventh gating switch (25); the input end of the tenth gating switch (21) is respectively connected to the output ends of the eighth gating switch (20) and the ninth gating switch (26), and the output end of the tenth gating switch (21) is connected to the signal input end of the second mixer (11).

3. The multi-channel amplitude and phase calibrated ultra-wideband receiver according to claim 2, wherein: The first to tenth selection switches are all two-selection switches.

4. The multi-channel amplitude and phase calibrated ultra-wideband receiver according to claim 1, wherein: The resistance values ​​of the first to fourth resistors are all 50 ohms.

5. The multi-channel amplitude and phase calibrated ultra-wideband receiver according to claim 1, wherein: The ultra-wideband receiver further comprises a local oscillator module (10) and a power divider (27), wherein the output end of the local oscillator module (10) is connected to the power divider (27), and the output end of the power divider (27) is respectively connected to the local oscillator input ends of the first mixer (3) and the second mixer (11).

6. The multi-channel amplitude and phase calibrated ultra-wideband receiver according to claim 1, wherein: The FPGA converts the input data to baseband through digital down-conversion, and then filters and demodulates the fixed-frequency signal through CIC+FIR filters, decomposing it into in-phase I and quadrature Q components, filtering out out-of-band noise and sample extraction. The CORDIC algorithm module and inverse tangent operation are then used to obtain the phase and amplitude: In vector mode, ensure I and Q data synchronization to avoid phase error and perform vector amplitude and phase calculations as follows: Amplitude = Phase = arctan(Q / I).

7. The multi-channel amplitude and phase calibrated ultra-wideband receiver according to claim 1, wherein: When the amplitude and phase fluctuate, the FPGA adjusts the link gain by adjusting the first AGC, the second AGC, the first digitally controlled attenuator, or the second digitally controlled attenuator.

8. The multi-channel amplitude and phase calibrated ultra-wideband receiver according to claim 5, characterized in that: The local oscillator module includes a PLL circuit (28), a third amplifier (29), an eleventh selection switch (30), a frequency multiplier (31), a first filter group (32), a twelfth selection switch (33), a fourth amplifier (34), a third digitally controlled attenuator (35), a fifth amplifier (36), a DDS module (37), a second filter group (38) and a third filter group (39); The output end of the PLL circuit (28) is connected to the third amplifier (29) and the DDS module (37) respectively. The output end of the third amplifier (29) is connected to the eleventh selection switch (30). The output end of the eleventh selection switch (30) is connected to the frequency multiplier (31) and the second filter group (38) respectively. The output end of the frequency multiplier (31) is connected to the first filter group (32). The output end of the DDS module (37) is connected to the third filter group (39). The output ends of the first filter group (32), the second filter group (38) and the third filter group (39) are all connected to the twelfth selection switch (33). The output end of the twelfth selection switch (33) is connected to the power divider (27) through the fourth amplifier (34), the third digitally controlled attenuator (35) and the fifth amplifier (36) in sequence.

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