Satellite communication high-speed data transmission method and system

Abstract

The invention discloses a satellite communication high-speed data transmission method and system, and the method comprises the steps: providing a basis for refined operation through separating cache data content and length information; when a decision is transmitted, a predictive decision arbitration module based on opportunity cost is introduced, and when the length and the time threshold are triggered at the same time to generate decision conflicts, the weighting cost is calculated according to the service quality level and the system configuration weight, and the optimal transmission is selected; when a data batch is constructed, a stateful predictive byte splicing module is activated, an elastic piggybacking or byte splicing operation is intelligently executed according to the overflow amount, and state updating is performed on the remaining length of a data packet after splicing. According to the invention, through intelligent arbitration and adaptive batch generation, the bus utilization rate and the system throughput rate are improved, and the real-time performance and reliability of data transmission are considered at the same time.

Description

Technical Field

[0001] The present invention belongs to the field of data transmission, and in particular, to a method and system for high-speed data transmission in satellite communication. Background Art

[0002] With the rapid evolution of information technology, the demand for data communication in human society has been continuously increasing. As the forefront of modern satellite communication technology, High Throughput Satellite (HTS), with its core advantages of wide coverage, high bandwidth, high speed, and low latency, has become a key infrastructure for building a global seamless connection network and bridging the digital divide. From providing high-speed Internet access in remote areas, to supporting real-time cross-border video conferencing, remote high-definition medical diagnosis, and then to serving the data backhaul of a large number of Internet of Things (IoT) terminals, high throughput satellites are profoundly changing all aspects of social production and life. Driven by these application scenarios, the load of satellite communication systems is increasing day by day, and the data processing capacity is facing severe challenges. In the entire link, the baseband processing system in the ground station or user terminal is the core bottleneck to ensure efficient and reliable data transmission. In such a system, the data exchange efficiency inside the System on Chip (SoC) directly determines the performance of the whole machine. The AXI (Advanced eXtensible Interface) bus protocol, especially its AXI4-STREAM protocol for stream data transmission, has become the de facto standard for data exchange in such systems due to its high performance, high bandwidth, and low latency characteristics. Combining with the AXI Multi-Channel Direct Memory Access (AXI MCDMA) technology, the system can build a high-speed data channel between the baseband processing unit and the protocol processor. Therefore, how to design and implement a data transmission control method that can adapt to high-throughput and high-dynamic service flows under this technical framework to maximize the hardware performance and ensure the ultimate efficiency and reliability of data transmission has crucial theoretical research significance and great practical application value.

[0003] Currently, in the SoC data transmission design based on AXI4-STREAM and AXI MCDMA, the industry has formed a relatively mature implementation solution. At the hardware level, a First-In-First-Out (FIFO) queue is usually used as a data caching mechanism to build a data content buffer and a data length buffer respectively, for temporarily storing baseband data frames and their metadata with different lengths sent from the upstream demodulation module. At the flow control logic level, in order to balance the DMA transmission efficiency and data real-time performance, a batch transmission strategy based on dual-threshold triggering is generally adopted. This strategy mainly includes two triggering mechanisms: The first is length accumulation triggering. The system will continuously accumulate the total length of the data packets in the cache. When the reception of the nth data packet causes the cumulative total length to exceed the preset maximum transmission byte count (Max length), a DMA transfer is triggered once. To ensure that the downstream DMA driver buffer does not overflow, this transfer usually only includes the first to the n - 1th complete data packets. The second is timeout waiting trigger. If the data stream is relatively sparse, within the preset maximum waiting time (Max waittime ), the cumulative length still does not reach Max length threshold, the system will also trigger a DMA transfer to send all the data packets in the current buffer at once to ensure data real-time and avoid indefinite delay of individual data packets. After the data is read out, it is encapsulated by a standard AXI4-STREAM protocol module to generate a protocol data stream containing timing signals such as TVALID and TLAST, and finally sent to AXI MCDMA for processing.

[0004] However, although the above conventional technical solutions can work effectively in most scenarios, in the complex environment of high dynamic, high load and huge differences in quality of service (QoS) unique to high-throughput satellite communication, their inherent and deep-seated design defects will be fully exposed and trigger a series of difficult-to-solve technical problems, including: in complex scenarios where both the length and time thresholds are triggered simultaneously, the decision-making mechanism of the existing methods is rigid and will fall into a decision-making conflict dilemma of being unable to balance throughput and delay, resulting in the inability to optimize the overall performance of the system. And when processing transmissions triggered by length overrun, the existing methods cannot refine the processing of the last data packet that causes the overflow, resulting in low batch construction efficiency. Summary of the Invention

[0005] The object of the invention is to provide a satellite communication high-speed data transmission method and system, hoping to solve at least one technical problem existing in the prior art.

[0006] Technical solution, a satellite communication high-speed data transmission method, wherein the data from the baseband frame is stored in the first buffer, and the length information of the data is stored in the second buffer, including:

[0007] Real-time calculate the cumulative length of the data in the first buffer and the waiting time since the last transmission;

[0008] When the cumulative length exceeds the length threshold or the waiting time reaches the time threshold, generate a transmission instruction;

[0009] According to the transmission instruction, extract the data and length information from the first buffer and the second buffer to construct a data block to be sent;

[0010] Encapsulate the data block to be sent into an AXI4-STREAM protocol data stream and send it.

[0011] A satellite communication high-speed data transmission system, including:

[0012] A data caching module, configured to obtain an input baseband frame, store data from the baseband frame into a first cache, and store the length information of the data into a second cache;

[0013] A status parameter calculation module, connected to the data caching module, configured to calculate in real time the cumulative length of the data in the first cache and the waiting time since the last transmission;

[0014] A transmission decision module, connected to the status parameter calculation module, configured to generate a transmission instruction when the cumulative length exceeds a length threshold or the waiting time reaches a time threshold;

[0015] A data batch generation module, connected to the data caching module and the transmission decision module, configured to extract data and length information from the first cache and the second cache according to the transmission instruction to construct a data block to be sent;

[0016] A protocol encapsulation and sending module, connected to the data batch generation module, configured to encapsulate the data block to be sent into an AXI4-STREAM protocol data stream and send it.

[0017] Advantageous effects: Through intelligent arbitration and adaptive batch generation, the present invention makes the system resource allocation more reasonable, effectively reduces the load of the protocol processor at high data rates, improves the bus utilization rate and system throughput rate, and takes into account the real-time performance and reliability of data transmission. Description of the Drawings

[0018] Figure 1 It is a step flow chart of a satellite communication high-speed data transmission method provided by an embodiment of the present application.

[0019] Figure 2 It is a step flow chart of generating a transmission instruction provided by an embodiment of the present application.

[0020] Figure 3 It is a step flow chart of calculating time-priority cost and length-priority cost provided by an embodiment of the present application.

[0021] Figure 4 It is a step flow chart of constructing a data block to be sent provided by an embodiment of the present application. Detailed Embodiments

[0022] To enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0023] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above accompanying drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0024] It has been found in the research that the decision-making mechanism of the existing method is too rigid and lacks the intelligent arbitration ability under complex constraints. When the rate and burst characteristics of the data stream cause the length threshold and time threshold to be triggered simultaneously, the system will fall into the dilemma of decision-making conflicts. It is unable to dynamically select the optimal transmission strategy according to the quality of service level (QoS) of the service and the current system state. Conventional designs usually can only make a decision based on a fixed priority (for example, time priority), and this one-size-fits-all strategy is blind. It ignores the opportunity cost of making different decisions: forcing transmission by time may seriously reduce the bus utilization rate and throughput due to too small data volume; while forcing transmission by length may unnecessarily hold a newly arrived high-priority, low-latency packet (such as a VoIP voice packet) in the next transmission window, thus damaging its quality of service. This decision-making mechanism that cannot dynamically balance throughput and latency and cannot perceive the QoS of data is unable to cope when facing a mixed traffic flow and cannot achieve the optimization of the overall system performance.

[0025] In addition, when dealing with scenarios triggered by length, existing methods suffer from low batch construction efficiency and implicit head-of-line blocking problems. They do not have the ability to splice bytes, and thus cannot maximize the utilization of the current transmission bandwidth. The resulting head-of-line blocking and bandwidth waste will seriously affect the efficiency and real-time performance of data transmission under high load. When the nth data packet causes a length overflow, simply discarding the packet and sending the first n - 1 packets is a crude and inefficient strategy. On the one hand, if the overflow amount is extremely small (for example, only a few bytes), this processing method will abandon sending an almost complete large data packet in order to abide by the rigid length limit, resulting in an obvious throughput loss and fragmentation of subsequent processing. On the other hand, this method does not have the refined operation ability for partial processing. It cannot precisely borrow a part of the bytes from the nth data packet to perfectly fill the current batch to achieve the maximum transmission efficiency allowed by Max length The defects of being unable to splice data packets, unable to remember the status of partially sent packets and continue processing not only lead to waste of bus bandwidth, but also make the delayed nth data packet form a de facto head-of-line blocking, increasing the jitter and uncertainty of data processing and severely restricting the ultimate performance of the system under high-speed and heavy-load conditions.

[0026] As Figure 1 shown, a high-speed data transmission method for satellite communication is proposed, including the following steps:

[0027] Data from the baseband frame is stored in the first buffer, and the length information of the data is stored in the second buffer;

[0028] In this embodiment, the original baseband frame data stream passed in by the upstream module and its corresponding enable signal are obtained. During the valid period of the enable signal, the actual length (unit: byte) of the original baseband frame is calculated by a counter. The data frame of the original baseband frame is written into the data content buffer (the first-in-first-out queue FIFO of the data content) in the form of a byte stream as the first buffer; at the moment when each data frame is written, the data length of the frame is written into the data length buffer (data length FIFO, which may be a dual-port RAM supporting updates in hardware) as the second buffer. This cache architecture that separates data from metadata is the basis for subsequent implementation of complex decision-making and batch generation.

[0029] Calculate the cumulative length of the data in the first buffer and the waiting time since the last transmission in real time;

[0030] In this embodiment, every time new length information is written into the data length buffer, the status parameter calculation module is immediately triggered to use the length information of the data and the metadata from the baseband frame to update or calculate in real time the set of aggregated status parameters for decision-making. This parameter set is stored in a set of hardware registers, which at least includes the total number of data packets n currently cached in the data length buffer, the cumulative total data length (cumulative total number of bytes) S of the n packets currently cached n , the waiting time since the last transmission (the counted clock cycles elapsed), and the quality of service level of the currently latest incoming nth data packet (parsed from the baseband frame metadata). The calculation process is as follows: Read the current value of the total packet count n register, add 1 to it through an adder to obtain the updated total packet count n; Read the current cumulative total length S n register value, add it to the aligned data length through an adder to obtain the updated cumulative total length S n ; Check the transmission completion flag. If the flag is high (indicating that a transmission was just completed in the previous cycle), then clear the waiting time time cnt register; Otherwise, increment its count value by 1 to obtain the updated waiting time time cnt ; Parse the quality of service level from the metadata field of the original baseband frame and store it in the service level QoS of the currently latest packet n register.

[0031] When the cumulative length exceeds the length threshold or the waiting time reaches the time threshold, a transmission instruction is generated;

[0032] In this embodiment, the transmission decision module continuously monitors the set of aggregated status parameters in each clock cycle. When any preset trigger condition is met (cumulative total length S n > maximum transmission byte count Max length or waiting time time cnt ≥ longest waiting time Max waittime ), it enters the decision arbitration stage. If only a single condition is triggered, a clear single-trigger instruction is generated; If both conditions are triggered simultaneously (decision conflict), then call the predictive decision arbitration module based on opportunity cost to calculate the set of aggregated status parameters and the system configuration weights (such as delay weight W lat , throughput weight W thr ), and obtain the optimal post-arbitration transmission instruction, outputting a unique and unambiguous final transmission decision instruction. This embodiment solves the decision conflict and optimizes the selection.

[0033] According to the transmission instruction, extract the data and length information from the first buffer and the second buffer to construct the data block to be sent;

[0034] In this embodiment, according to the final transmission decision instruction, data batches to be sent are extracted from the data content buffer and the data length buffer and generated. If the instruction requires transmission based on Max waittime transmission, a data block to be sent containing all current n data packets is generated. If the instruction requires transmission based on Max length transmission, the stateful predictive byte stitching module is activated, and elastic piggybacking or hardware byte stitching operations are performed according to the overflow amount to generate an optimized data block to be sent, and an entry in the data length buffer is updated when necessary. The processed data block to be sent and its final transmission length are output. This embodiment solves the head-of-line blocking problem that may be caused by Max length triggering.

[0035] The data block to be sent is encapsulated into an AXI4-STREAM protocol data stream and sent.

[0036] In this embodiment, the data block to be sent and the final transmission length are read, the sending logic is started, the data block to be sent is sent to the sending buffer, and the data in the data block to be sent (4 bytes at a time) is assigned to the transmission data (TDATA) signal in each clock cycle, preparing for serialization and output to the TDATA bus. The transmission valid (TVALID) signal is set to high during the data valid period or as long as there is data in the sending buffer. Through a counter, count from 0 to the final transmission length / 4 - 1. When and only when the counter value reaches the maximum value, the transmission last (TLAST) signal is set to high to mark the end of the data block. Specifically, the value of (final transmission length / 4) - 1 is loaded into the TLAST target count register; the successful transmission beat counter increments by one in each clock cycle when both TVALID and TREADY (transmission ready, from downstream) are high; the hardware comparator continuously compares the values of the successful transmission beat counter and the TLAST target count register; when the two values are equal, the TLAST signal is set to high and maintained for one clock cycle. All generated signals such as TDATA, TVALID, and TLAST are combined to generate an AXI4-STREAM protocol data stream according to the AXI4-STREAM protocol specification and sent to the downstream AXI MCDMA module through a physical interface.

[0037] As Figure 2 shown, according to one aspect of the present application, a transmission instruction is generated, including:

[0038] When the cumulative length and the waiting time both exceed their respective corresponding thresholds, it is determined as a decision conflict;

[0039] In this embodiment, in each clock cycle, the aggregated state parameter set is read and compared with the preset system configuration parameters (including Max length 、Maxwaittime ), compare them, and generate two boolean signals of length trigger condition and time trigger condition in real time. The specific judgment conditions are as follows: Length trigger condition (Trigger_L): When S n > Max length it is true; Time trigger condition (Trigger_T): When time cnt ≥Max waittime it is true. Judge the trigger status through combinational logic. If only one of the two trigger conditions is true, generate a single trigger instruction containing the corresponding action (LENGTH_FIRST or TIME_FIRST); if both conditions are true, it is determined as a decision conflict. Specifically: If!Trigger_L and!Trigger_T, no instruction is generated and continue to wait; if Trigger_L and!Trigger_T, generate a single trigger instruction, and the instruction content is {Action: LENGTH_FIRST, Count: n - 1}; if!Trigger_L and Trigger_T, generate a single trigger instruction, and the instruction content is {Action: TIME_FIRST, Count: n}; if Trigger_L and Trigger_T, it is determined as a decision conflict. Where! is the logical NOT operator, and!Trigger_L means Trigger_L is false; Action represents the behavior taken in the trigger instruction, and Count is the counting parameter value related to the instruction.

[0040] To solve the decision conflict, start the arbitration module for predictive decision-making;

[0041] The arbitration module generates a transmission instruction that can maximize the transmission benefit by calculating and comparing the time-first cost and the length-first cost.

[0042] As Figure 3 shown, in an alternative embodiment, calculating the time-first cost and the length-first cost includes:

[0043] Calculate the time-first cost based on the quality of service level of the latest data packet in the current cache, the preset delay weight and throughput weight, and the cumulative length of all data packets in the current cache;

[0044] Optionally, the calculation of the time-first cost includes:

[0045] Determine the delay penalty value through a delay evaluation function based on the quality of service level of the latest data packet;

[0046] Determine the throughput score based on the cumulative length of all data packets;

[0047] Using the delay weight and throughput weight, perform a weighted sum of the delay penalty value and the throughput score to obtain the time - priority cost.

[0048] According to the quality - of - service level of the latest data packet, the delay weight and the throughput weight, as well as the cumulative length of other data packets except the latest data packet, calculate the length - priority cost.

[0049] In this embodiment, start the predictive - decision arbitration module based on opportunity cost to resolve decision conflicts. Obtain the aggregated state parameter set (S n , n, QoS n ) and the system - configuration weight (W lat , W thr ). Calculate the costs of two decision branches in parallel: Calculate the time - priority cost (Cost TimeFirst ): Use QoS n as the address to query the delay - penalty lookup table (LUT) to obtain the penalty value P lat ; Use the hardware reciprocal operation unit to calculate the throughput score S n from S thr_n = 1 / S n ; Calculate W lat * P lat and W thr * S thr_n in parallel through two hardware multipliers; Add the above two products through an adder to obtain the final Cost TimeFirst : Cost TimeFirst =W lat ×f lat (QoS n )+W thr ×1 / S n ; Where f lat (QoS n ) is a function to evaluate the delay penalty according to the service level QoS n , and a high - priority QoS n will result in an extremely high delay - penalty value. Calculate the length - priority cost (Cost LengthFirst ): Use QoS n to query the delay - benefit lookup table (LUT) to obtain a very small delay cost P lat_next ; Similarly, calculate the cumulative total number of bytes S n of the first n - 1 data packets except the latest data packet from S n-1 and the length of the nth packet, and calculate the throughput score S thr_n-1 = 1 / S n-1 ; Similarly, obtain the final Cost LengthFirst through multipliers and adders: Cost LengthFirst =Wlat ×f lat_next (QoS n )+W thr ×1 / S n-1 ; where the delay opportunity cost evaluation function f lat_next (QoS n ) evaluates the benefit (a very small value) of leaving high-priority packets for the next nearly zero-delay transmission. Compare Cost TimeFirst and Cost LengthFirst using a hardware comparator. If Cost TimeFirst <= Cost LengthFirst , then select time priority; otherwise, select length priority. Based on the comparison result, generate an arbitration-based transmission instruction containing the optimal action (TIME_FIRST or LENGTH_FIRST), which has the same format as the single-trigger instruction. Through a selector, select to output the single-trigger instruction or the arbitration-based transmission instruction as the final and only final transmission decision instruction.

[0050] In another embodiment of the present application, the transmission decision module continuously monitors the aggregated state parameter set provided by the state parameter calculation module. When it is detected that the cumulative total length S n of the current cached data has exceeded the preset Max length , and the waiting time time cnt since the last transmission has also reached Max waittime , it is determined that the system has entered a decision conflict state, and the predictive decision arbitration process is immediately started. After the decision conflict is determined, the arbitration module will parallelly start two independent hardware cost calculation units to calculate the opportunity costs of selecting different decision paths respectively. Specifically: Calculate the time priority cost Cost TimeFirst : This cost aims to quantify the comprehensive benefit of immediately sending all current n packets. Its calculation inputs include: the service level QoS n of the current latest packet, the cumulative length S n of all packets, and the delay weight W lat and throughput rate weight W thr configured in the system. In this embodiment, QoS n is mapped to a delay penalty value f lat (QoS n ) through a preset delay penalty lookup table (LUT). A high-priority QoS will correspond to a very large penalty value. The final cost is calculated by the formula Cost TimeFirst =W lat ×f lat (QoS n )+W thr ×1 / S n . Calculate the length priority cost Cost LengthFirst: This cost aims to quantify the comprehensive benefit of only sending the first n - 1 packets to preferentially meet the length limit. Its calculation input is similar, but the data length is S n-1 . In addition, its delay cost item f lat_next (QoS n ) evaluates the opportunity cost of postponing a high-priority packet to the next transmission opportunity. If this packet is a high-priority packet, this cost value will be very high. The final cost is calculated by the formula Cost LengthFirst = W lat × f lat_next (QoS n ) + W thr × 1 / S n-1 . Input the two cost values Cost TimeFirst and Cost LengthFirst into the hardware comparator. If Cost TimeFirst <= Cost LengthFirst , it indicates that the comprehensive benefit of immediate transmission is higher (or the opportunity cost is lower), and the system will generate an arbitration transmission instruction with the content {Action: TIME_FIRST, Count: n}. Otherwise, an instruction with the content {Action: LENGTH_FIRST, Count: n - 1} will be generated. This instruction, as the final transmission decision instruction, is sent to the downstream data batch generation module.

[0051] For example, in a specific application, Max length = 32000 bytes, Max waittime = 50000 clock cycles, the weight W lat = 0.7, W thr = 0.3. When S n = 33000 bytes (consisting of 22 1500-byte packets), time cnt = 50000, and the QoS n of the latest packet is of the highest priority, f lat (QoS n ) looks up a very small value in the table (such as 0.1, representing a high benefit), while f lat_next (QoS n ) is a very large value (such as 100, representing a high cost). It is calculated that Cost TimeFirst is much smaller than Cost LengthFirst , so the system will decide to immediately send all 22 packets, ensuring low latency for high-priority services. Through the above steps, this embodiment transforms the fuzzy decision conflict point into a quantifiable optimization problem, realizing the intelligent and dynamic trade-off between throughput and latency under complex constraints.

[0052] In this embodiment, by introducing a predictive decision arbitration module based on opportunity cost, the problem of sub-optimal system performance caused by rigid decision logic when the dual thresholds of length and time are triggered in the prior art is solved. In a satellite communication hybrid service scenario, for example, when service data packets of interactive video streams (requiring low latency) and large file downloads (requiring high throughput) coexist and cause decision conflicts, this embodiment can make a smart trade-off: by assigning an extremely high latency opportunity cost to data packets of high QoS levels, the system will preferentially choose to send immediately, ensuring that the user experience of video conferencing does not degrade; conversely, for batch data without special latency requirements, it will preferentially choose to meet the length threshold to maximize the single DMA transfer efficiency. This makes the system resource allocation more reasonable and achieves Pareto optimality of the overall performance under complex service loads.

[0053] As Figure 4 shown, according to one aspect of the present application, constructing a data block to be sent includes:

[0054] Determine whether the generation of the transmission instruction is due to the cumulative length exceeding the length threshold or the waiting time reaching the time threshold;

[0055] When it is determined that the transmission instruction is generated because the cumulative length exceeds the length threshold, the stateful predictive byte splicing module is activated, and it is responsible for generating the data block to be sent.

[0056] In this embodiment, obtain the final transmission decision instruction, and prepare to read data from the data content buffer and the data length buffer. If the instruction is {Action: TIME_FIRST, Count: n}, execute the standard process: read all n length values from the data length buffer, each read length value is sent to the accumulator, and after n cycles, the value in the accumulator is the final transmission length; divide the final transmission length by 4 and load it into the countdown counter, which will precisely control the read enable signal of the data content buffer to form a complete data block to be sent. If the instruction is {Action: LENGTH_FIRST, Count: n - 1}, then activate the stateful predictive byte splicing module and output the finally generated data block to be sent.

[0057] According to one aspect of the present application, the stateful predictive byte splicing module generates a data block to be sent, including:

[0058] Calculate the overflow amount that exceeds the length threshold due to the addition of the latest data packet in the first buffer;

[0059] Judge whether the overflow amount is greater than zero and does not exceed the preset elastic margin; if so, construct all the current cached data packets including the latest data packet together as the data block to be sent;

[0060] If the overflow amount is greater than a preset elastic margin, then: calculate the number of bytes to be spliced, where the number of bytes to be spliced is the difference between the length threshold and the cumulative length of other cached data packets except the latest data packet; based on the number of bytes to be spliced, merge all cached data packets except the latest data packet and the partial data content intercepted from the latest data packet to construct a data block to be sent.

[0061] Where the calculation is the number of bytes to be read from the latest data packet to make the total length of the data block reach the length threshold. In other words, the number of bytes to be spliced is the number of bytes to be read from the latest data packet to make the total length of the data block reach the length threshold. It can also be said that: calculate the difference between the length threshold and the cumulative length of other cached data packets except the latest data packet, and determine this difference as the number of bytes to be spliced; merge all cached data packets except the latest data packet and the data content corresponding to the number of bytes to be spliced read from the latest data packet to jointly construct a data block to be sent.

[0062] In this embodiment, read the length Size of the nth data packet n , calculate the overflow amount Overflow = (S n-1 + Size n ) - Max length . Obtain the elastic margin Margin_E configured by the system. If 0 < Overflow ≤ Margin_E, then perform piggybacking: read the lengths and contents of all n packets from the cache, and generate a data block to be sent with a total length of S n and a final transmission length S n ; if Overflow > Margin_E, then perform byte splicing: read the lengths of the first n - 1 packets from the data length buffer, and calculate S n-1 ; calculate the number of bytes Bytes To_Splice to be spliced from the nth packet = Max length - S n-1 ; start a special read control state machine, first read the first n - 1 complete data packets and their lengths from the data content buffer, then the state machine enters the partial read state, and read the first Bytes To_Splice bytes of the nth data packet, and merge the first n - 1 complete packets and the header data of the nth packet to form a data block to be sent with a total length of Max length , and its final transmission length is Max length .

[0063] According to one aspect of the present application, after merging and constructing the data block to be sent, it further includes:

[0064] Calculate the remaining length of the latest data packet after intercepting part of its data content;

[0065] Perform an update operation on the second cache, and modify the length information corresponding to the latest data packet therein to the remaining length.

[0066] In this embodiment, perform a read-modify-write operation on the data length buffer: change the length entry of the nth packet therein from Size n to the remaining length New Size_n = Size n - Bytes To_Splice . The state machine issues an update instruction to the data length buffer (the hardware is a dual-port RAM), including the address to be updated (the position of the nth packet) and the new length value, to complete the modification of the length of this entry. The output of this operation is the updated data length buffer, ensuring the correctness of the next decision.

[0067] In another embodiment of the present application, after receiving the length-first instruction, read the number of packets (n - 1) included in the instruction, and obtain the length Size of the nth packet from the second cache n . Calculate the overflow amount Overflow=(S n-1 +Size n )-Max length . Compare Overflow with the system-predefined elasticity margin Margin_E to decide whether to enter the elastic piggyback mode or the byte stitching mode. If the determination result is 0 < Overflow ≤ Margin_E, activate the first path: In this embodiment, Margin_E can be set to, for example, 256 bytes. The operation of the first path is very straightforward: the module will generate an instruction to read n data packets, and read the data content and length information of all n packets from the first cache and the second cache, jointly constituting a data block to be sent with a total length of S n . At the cost of an acceptable and tiny overlength at one time, higher single-transmission efficiency is obtained, and unnecessary packet splitting operations are avoided. If it is determined that Overflow > Margin_E, activate the second path: The second path aims to construct a data block with a length strictly equal to Max length . Specifically, calculate the number of bytes to be intercepted from the nth packet, that is, the stitched bytes. The calculation method is: Bytes To_Splice =Max length -S n-1 ; the module controls to continuously read the first n - 1 complete data packets from the first cache, and then immediately read Bytes from the starting position of the nth data packet To_SpliceThe data content of [X] bytes. These two parts of data are merged to form the final data block to be sent. After constructing the data block, the module immediately performs an update operation on the second cache (whose hardware is a dual-port RAM supporting read-modify-write). Specifically, calculate the remaining length New of the nth packet Size_n =Size n -Bytes To_Splice ; For the corresponding entry in the second cache that stores the length of the nth packet, change its value from Size n to New Size_n .

[0068] For example, in another specific application, Max length = 32000 bytes, S n-1 = 31500 bytes, Size n = 2000 bytes. Overflow is 1500 bytes, which is much larger than Margin_E. The module will calculate Bytes To_Splice = 32000 - 31500 = 500 bytes. Generate a data block with a length of 32000 bytes, whose content is the first n - 1 complete packets plus the first 500 bytes of the nth packet. Calculate New Size_n = 2000 - 500 = 1500 bytes, and update the length entry of the nth packet in the second cache to 1500. Through the above steps, the head-of-line blocking problem caused by length triggering is solved, the bus utilization rate is maximized, and the state consistency and data integrity of the data stream during multiple transmissions are ensured.

[0069] This embodiment improves the transmission efficiency loss and unnecessary processing overhead caused by strictly adhering to the length threshold in the prior art. It is achieved by introducing a configurable parameter of elastic margin and performing larger-batch DMA transmissions including the oversized data packets when it is determined that the overflow amount does not exceed this margin. In an actual satellite communication scenario, the packet lengths of upper-layer protocols (such as TCP / IP) are often large, for example, 1500 bytes. If Max lengthIt is 32000 bytes. When the 22nd packet (with a total length of 33000 bytes) arrives, the conventional method will only send the first 21 packets (31500 bytes), resulting in 500 bytes of idle bandwidth. In this embodiment, under the condition that Overflow (1000 bytes) is less than Margin_E (such as 2048 bytes), it will choose to send all 33000 bytes at once. The transmission task that originally required two DMA interrupts and two interactions with the protocol processor is merged into one, reducing the CPU processing overhead per unit of data volume, effectively reducing the load on the protocol processor at high data rates, and enhancing the overall stability and throughput capacity of the system. It also solves the head-of-line blocking and bus bandwidth waste problems caused by the inability to finely process overflow packets in the prior art. By precisely calculating Bytes To_Splice , and intercepting part of the content from the latest packet that causes the overflow to construct a data block that is perfectly filled and has a length strictly equal to Max length . In the satellite communication link where bandwidth resources are extremely precious, it improves the bus utilization rate of each DMA transmission triggered by length, avoiding byte waste. By modifying the length information of the packet in the second cache, the system retains the memory of the remaining data fragments, ensuring the absolute integrity of the data stream, enabling the next transmission decision to be made based on the correctly updated system state, and achieving seamless and lossless continuation of data between multiple transmission batches, so that even under the most extreme load conditions, data transmission can still maintain the highest efficiency and the highest reliability.

[0070] According to one aspect of the present application, the first cache is a first-in-first-out queue; the second cache is an updatable buffer area that supports modifying the stored length information in the middle of the queue.

[0071] According to one aspect of the present application, before storing the data in the first cache and storing the length information in the second cache, it further includes data alignment preprocessing:

[0072] Calculate the original length of the baseband frame;

[0073] According to the numerical characteristics of the original length, query the preset padding data comparison table to determine the number of bytes to be filled;

[0074] Append the padding data corresponding to the number of bytes to be filled after the baseband frame to form a byte-aligned data frame, where the byte-aligned data frame is the data to be stored in the first cache.

[0075] Optionally, before appending the padding data to the baseband frame, perform synchronous delay processing on the baseband frame and its corresponding frame valid signal; use the baseband frame after synchronous delay processing to splice with the padding data.

[0076] In this embodiment, according to the AXI4-STREAM bus width requirement (e.g., 4 bytes), data padding processing is performed on the original baseband frame to obtain a byte-aligned aligned data frame and its corresponding aligned data length. Specifically, start the byte counter i data_en_cnt , and in each clock cycle when the enable signal i data_en is at a high level, this counter increments by one. When the falling edge of the enable signal i data_en is detected, the final count value of the counter i data_en_cnt is locked into a register to obtain the stable original baseband frame length Count_A. Use the lowest two bits of the actual length Count_A value of the original baseband frame as the address to query a preset padding data number look-up table (LUT) or read-only memory (ROM) to obtain the number of 0 bytes Count_B that need to be filled to achieve 4-byte alignment within a single clock cycle. For example, if the lowest two bits of Count_A in binary are 01, it can be known from the table that 3 0 bytes need to be filled. To solve the problem of subsequent signal timing misalignment caused by the single-clock-cycle delay introduced by calculating Count_B, an input synchronization delay method is used for processing. Synchronously delay the input original baseband frame (i data ) and its enable signal i data_en by one clock cycle to obtain the i data_delay and i data_en_delay with synchronized timing. Specifically: Connect the original baseband frame data stream i data to the input end of a group of D flip-flops; Connect the frame valid signal i data_en to the input end of another D flip-flop; Use a unified system clock to drive all the above flip-flops, and at the rising edge of the next clock edge, obtain the data i data_delay and the enable signal i data_en_delay that are delayed by one cycle and have synchronized timing. A data selector (MUX) is used to merge the data streams. During the valid period of i data_en_delay , select i data_delay as the output data; During the valid period of the extended enable signal determined by Count_B (e.g., a countdown counter loaded with the value of Count_B), select a constant 0 level as the output; The outputs of the above two stages are spliced to obtain the complete aligned data frame. At the same time, an adder calculates the aligned data frame with a total length of Count_A + Count_B and its corresponding aligned data length. Through the above steps, not only the 4-byte alignment processing of baseband frames of any length is completed, but also through the synchronous delay design, the potential timing competition risk is removed at the hardware level, ensuring the stability and reliability of data preprocessing.

[0077] This embodiment solves the problem of internal timing competition that may be caused by inconsistent hardware pipeline processing delays, ensuring the stability and reliability of the data preprocessing stage. In the high-speed digital circuit design of FPGA or ASIC, calculating the filled byte count requires one or more clock cycles of lookup and operation, and the output timing of the result will lag behind the end timing of the original data stream. Without processing, the timing misalignment will cause metastability or data sampling errors at the moment of data stitching, resulting in difficult-to-debug and occasional data corruption. By synchronously inserting a delay equal to the calculation delay into the two faster paths of the original data stream and its enable signal, all signals participating in the final data stitching can be precisely aligned at the same clock edge. Each data bit delivered to the core processing module is correct, avoiding upper-layer (such as TCP) error detection and retransmission caused by underlying data corruption, and ensuring the macroscopic performance of the entire satellite communication link and the stability of the user experience.

[0078] According to one aspect of the present application, a satellite communication high-speed data transmission method includes: obtaining a plurality of input baseband frames, separating the data content and their respective corresponding length information included in the plurality of baseband frames, and writing them into a data content buffer and a data length buffer respectively.

[0079] Specifically, the data content buffer (preferably, a hardware FIFO) is used to temporarily store the data content of the byte-aligned data frames in byte order. At the same time, an independent data length buffer (preferably, another FIFO) is used to store the total length of each data frame as an independent entry.

[0080] Based on the current states of the data content buffer and the data length buffer, the aggregated state parameter set is updated in real time, where the aggregated state parameter set at least includes the total number of currently cached data packets, the cumulative total data length of all cached data packets, and the waiting time since the last transmission.

[0081] Specifically, whenever a new length information is written into the data length buffer, the state parameter calculation module will be immediately triggered to update in real time a set of aggregated state parameter sets for global decision-making. This parameter set is stored in hardware registers and at least includes: the total number of currently cached data packets n; the cumulative total number of bytes S of all cached data packets n ; and the number of clock cycles time elapsed since the last successful DMA batch transmission cnt 。

[0082] Continuously monitor the aggregated state parameter set. When the cumulative total data length exceeds a preset length threshold or the waiting time reaches a preset time threshold, it is determined that the trigger condition is established and a final transmission decision instruction is generated.

[0083] Specifically, the transmission decision module continuously monitors the aggregation state parameter set in each clock cycle. The module makes judgments based on two preset thresholds: length threshold Max length and time threshold Max waittime When S n > Max length or time cnt ≥ Max waittime When any of the conditions are met, the module generates the final transmission decision instruction. Optionally, in the case of a decision conflict scenario where both conditions are met at the same time, a more advanced arbitration module can be activated to generate the optimal instruction.

[0084] In response to the final transmission decision instruction, corresponding data is extracted from the data content buffer and the data length buffer to construct a data block to be sent and its corresponding final transmission length.

[0085] Specifically, the data batch generation module extracts data from the first and second buffers in response to the decision instruction. If the instruction is triggered by time, the module reads all n packets in the current buffer to form the data block to be sent. If the instruction is triggered by length, the module reads the first n-1 packets. Preferably, a more advanced byte splicing module can be activated when the length is triggered to maximize efficiency. The module then outputs the finalized data block to be sent and the final transmission length.

[0086] The data block to be sent and the final transmission length are encapsulated into an AXI4-STREAM protocol data stream and sent to the downstream module.

[0087] Specifically, the protocol encapsulation and transmission module obtains the data block to be sent and the final transmission length. The data block contents are assigned to the TDATA signal on a clock-by-clock basis. The TVALID signal is pulled high during the data validity period, and the TLAST signal is set high when the last data beat is transmitted. All these signals together constitute the standard AXI4-STREAM protocol data stream, which is sent to the downstream AXI MCDMA controller. Through these steps, a complete closed-loop data processing process of caching, monitoring, deciding, building, and transmitting is established. This process converts unordered, arbitrary-length data streams into regular, efficient DMA transmission batches, providing a foundation for high-speed, reliable satellite communications.

[0088] According to one aspect of the present application, a satellite communication high-speed data transmission system is characterized by comprising:

[0089] a data buffer module configured to obtain an input baseband frame, store data from the baseband frame into a first buffer, and store length information of the data into a second buffer;

[0090] A status parameter calculation module, connected to the data cache module, is configured to calculate in real time the cumulative length of the data in the first cache and the waiting time since the last transmission;

[0091] A transmission decision module, connected to the status parameter calculation module, is configured to generate a transmission instruction when the cumulative length exceeds a length threshold or the waiting time reaches a time threshold;

[0092] A data batch generation module, connected to the data cache module and the transmission decision module, is configured to extract data and length information from the first cache and the second cache according to the transmission instruction to construct a data block to be sent;

[0093] A protocol encapsulation and sending module, connected to the data batch generation module, is configured to encapsulate the data block to be sent into an AXI4-STREAM protocol data stream and send it.

[0094] In a specific embodiment of the present application, aiming at the problem of packet loss of the DMA controller caused by untimely interruption handling of the protocol processor, based on the AXI4-STREAM protocol, a high-speed data transmission method for satellite communication is provided. Mainly by reducing the data sending interval and increasing the amount of data transmitted in one DMA transmission without reducing the rate to meet the interruption handling time requirement of the protocol processor. On the one hand, set the maximum amount of data transmitted in one DMA data transmission to ensure that the data cache in the DMA driver will not overflow during high-speed communication and improve the reliability of data transmission; on the other hand, set the maximum interval of data transmission to ensure that during low-speed communication, the data delay and jitter will not increase and improve the real-time performance of data transmission. This embodiment is developed based on the FPGA platform, and the whole data processing process is as follows: the demodulated baseband frame data is sent to the data alignment module, and the data alignment module fills different lengths of data 0 according to the baseband frame length, so that the total length after adding the length of the filled data 0 to the baseband frame length is a multiple of 4; the 4-byte aligned data is sent to the data cache module, the aligned data is stored in the data content cache area, and the aligned data length is stored in the data length cache area; when there is data in the data content cache area, the flow control module starts to work and judges whether the total data length written into the data length cache area is greater than Max length (set the maximum number of bytes sent to the AXI MCDMA each time), if after the nth packet of data is written, the total data length in the data length cache area exceeds Max length , then the data from the 1st packet to the (n - 1)th packet is read out from the data content cache area at one time; if from the writing of the 1st packet of data to the writing of the nth packet of data, the total data length in the data length cache area is less than Max length , but the time taken has reached Max waittimeIf the maximum waiting time sent to AXI MCDMA each time is set, then the first packet of data to the nth packet of complete data is read out from the data buffer at one time; the data read from the data content buffer passes through flow control and finally passes through the AXI4-STREAM protocol module, and corresponding data signals are generated according to the AXI4-STREAM protocol.

[0095] Among them, the data alignment module is mainly used to align the baseband frame data in 4-byte units, preparing for the AXI-STREAM protocol module to transmit 4-byte data in a single clock cycle. Setting to transmit 4-byte data in a single clock cycle according to the AXI4-STREAM protocol, the reasons are as follows: modern applications have high requirements for data transmission bandwidth, and transmitting 4-byte data in a single clock cycle can significantly improve the bus efficiency and meet the high-bandwidth requirements; 4 bytes (32 bits) is a common data alignment unit, and many processors and memories use 32 bits as the basic operation unit, which simplifies data alignment and transmission; increasing the clock frequency will increase power consumption and the complexity of the design. Transmitting 4-byte data in a single clock cycle can achieve high bandwidth at a lower frequency and reduce problems caused by high-frequency clocks; the AXI-STREAM bus supports multiple data widths, and 4 bytes is one of its common configurations. Flexibility is considered in the design to cope with different usage scenarios.

[0096] The implementation process of the data alignment module is as follows: during the period when the baseband frame enable i data_en is at a high level, a 16-bit counter i data_en_cnt is used for counting. When the baseband frame enable falls, the value of the counter is latched. The latched counter value is recorded as Count_A and the counter value is cleared to 0. Determine the number of 0s to be filled according to the lower two bits of the counter value Count_A. The number of 0s to be filled is recorded as Count_B, as follows: when Count_A [1:0] is 0, Count_B is 0; when Count_A [1:0] is 1, Count_B is 3; when Count_A [1:0] is 2, Count_B is 2; when Count_A [1:0] is 3, Count_B is 1. Determine the number of clock cycles of the extended signal Delay_A of the baseband frame enable according to the number of 0s to be filled Count_B. Numerically, Delay_A = Count_B. Since the number of 0s to be filled Count_B lags one clock cycle behind the output of the counter latch value Count_A, the output of the Delay_A signal lags one clock cycle, resulting in the misalignment of the end of the baseband frame enable signal i data_en and the start time of the extended signal Delay_A, as well as the misalignment of the end of the baseband frame data i data and the start time of the filled 0s. Therefore, the baseband frame enable signal i data_en and the baseband frame data signal idata Delay one clock cycle simultaneously, i data_en The signal after delaying one clock cycle is denoted as i data_en_delay , i data The signal after delaying one clock cycle is denoted as i data_delay , to solve the timing alignment problem of the data alignment module in generating the output enable o data_en and the data o data . The output data enable o data_en consists of two parts. One is the baseband frame enable signal i data_delay , and the other is the extended signal Delay_A. The clock cycle with o data_en continuously high level is Count_A + Count_B. The output data signal o data also consists of two parts. When the baseband frame enable signal is high, the baseband frame data i data_delay is output. When the Delay_A signal is high, the data 0 is output.

[0097] The data cache module mainly stores the data length and data output by the data alignment module. The implementation process is as follows: Two FIFO (First In First Out) IP cores are used to cache the data length and data respectively. For the FIFO cache of the data length, its FIFO write enable is the falling edge of the data enable o data_en output by the data alignment module, and the data input of the data length FIFO cache is Count_A + Count_B. The read enable is generated by the flow control module, and the bit width of the read data is the same as the bit width of the input data. For the FIFO cache of the data, its FIFO write enable is the data enable o data_neg data_en output by the data filling module, and the data input of the data FIFO cache is o data . The read enable is generated by the flow control module. Since the FIFO data is input in 1 byte and output in 4 bytes, the read data bit width is 1 / 4 of the input data bit width.

[0098] The implementation process of the flow control module is as follows: When data is written into the data cache module, the number of input data packets is counted, denoted as Cnt n and the data packet lengths are accumulated. The accumulated result is S n . When the data packet count Cnt n is n and at this time the data packet length S n is greater than Max length , a data length FIFO read enable signal is generated. The signal duration is n - 1 clock cycles, that is, the respective lengths of the first n - 1 packets of data are read out. Each time a length information is read, it is accumulated to calculate the total length of the n - 1 packets of data, denoted as S n-1 ​After the calculation is completed, a data content cache read enable signal is generated, and the signal duration is S n-1 / 4 clock cycles, that is, the first n - 1 packets of data content are read. 4 bytes of data are read in a single clock cycle, and the read data content is sent to the AXI STREAM protocol module. The next data transfer will start with the nth packet of data. The following is an example to illustrate the total data transfer control logic:

[0099] Case 1: Assume that the length of each packet of data is 1500 Byte, and Max length value is 32000 Byte. When n = 21, S21 = 31500 Byte, which is less than Max length ; when n = 22, S22 = 33000 Byte, which is greater than Max length , triggering the mechanism of the data cache module. Read the length of 21 packets of data from the data length cache module and calculate that the total length of 21 packets of data S21 is 31500 Byte. Read the data content cache, and the read enable signal data rd_en lasts for 31500 / 4 = 7875 clock cycles, and 4 bytes of data are output in a single clock cycle. When data is written to the data cache module, the number of input data packets is counted as Cnt n and the packet lengths are accumulated, and the accumulated result is S n . When the packet count Cnt n is n and at this time the packet length S n is less than Max length but the time time cnt since the last data transmission = Max waittime , a data length FIFO read enable signal is generated, and the signal duration is n clock cycles. Each time a length information is read, it is accumulated to calculate the total length of n packets of data. After the calculation is completed, a data cache read enable signal is generated, and the signal duration is S n / 4 clock cycles, that is, the first n packets of data content are read. 4 bytes of data are read in a single clock cycle. The read data content is sent to the AXI STREAM protocol module.

[0100] Case 2: Assume that the length of each packet of data is 1500 Byte, and Max length value is 32000 Byte, and the interval between every two packets of data transmission (the interval between the rising edges of every two packets of data enable) is 5000 clock cycles, and Max waittime value is 52000. When starting from the rising edge of the first packet of data, after Max waittime clock cycles (time cnt = Max waittimeAt this time, a total of 10 packets of complete data are stored in the data cache module. Read the lengths of 10 packets of data from the data length cache module and calculate the total length S10 of the 10 packets of data to be 15000 Byte. Read the data content cache, and the read enable signal data rd_en The duration is 3750 clock cycles, and 4 bytes of data are output per clock cycle.

[0101] The implementation process of the AXI4-STREAM protocol module is as follows: The AXI4-STREAM interface is divided into a master device (Source) and a slave device (Sink). The main signals are as follows: When the main signal is TVALID, the direction is from the master to the slave, issued by the master device, indicating that the current data (TDATA, etc.) is valid; when the main signal is TREADY, the direction is from the slave to the master, issued by the slave device, indicating that data can be received. For data transmission, both TVALID and TREADY need to be high; when the main signal is TDATA[n:0], the direction is from the master to the slave, and it is the actually transmitted data with a configurable bit width; when the main signal is TLAST, the direction is from the master to the slave, marking the last data of the data packet; when the main signal is TKEEP[n:0], the direction is from the master to the slave, indicating the bytes in TDATA that need to be retained (for padding when data reduction occurs); when the main signal is TDEST[p:0], the direction is from the master to the slave, and it is the destination identifier for multi-destination routing. The data transmission mechanism is as follows: Handshake condition: When TVALID and TREADY are both high at the rising edge of the clock, the data (TDATA, etc.) is successfully transmitted; Timing example: The master device sets TVALID = 1. If the slave device is ready, it sets TREADY = 1. If the slave device is not ready (TREADY = 0), the master device needs to keep TVALID and TDATA unchanged until the transmission is completed; Flow control: Backpressure is achieved through TREADY, and the slave device can pause the data stream to prevent overflow. AXI4-STREAM protocol conversion: Generation of the TVALID signal: The data read enable signal data generated in the flow control module rd_en Can be used as the TVALID signal when TREADY is high; Since the output of the data content data cache FIFO is delayed by two clock cycles, the data read enable data rd_en Needs to be delayed by two clock cycles to align with the data output; The data after being delayed by two clock cycles rd_en_delay2 can be used as the TVALID signal. Generation of the TDATA signal: The 4-byte data output from the data content buffer FIFO can be used as the TDATA signal. Note the definition of the endianness of the master and slave devices, which may involve byte order conversion. Generation of the TKEEP signal: Since it is set to transfer 4-byte data in a single clock cycle, the bit width of the TKEEP signal is 4. Additionally, the data alignment module aligns the 4-byte data, that is, the filled data 0 is also sent to the AXI MCDMA as valid data, and the TKEEP value is fixed at 15. Generation of the TDEST signal: The TDEST signal can specify the data transfer channel. The AXI MCDMA supports a maximum of 16 channels, so the bit width of the TDEST is 4. The data transfer channel needs to be agreed upon with the slave device. Generation of the TLAST signal: The data read enable signal data generated in the flow control module rd_en has a duration of S n / 4 clock cycles. When the count of the read enable signal data rd_encnt is S n / 4 - 1, the TLAST signal becomes high; when the count of the read enable signal data rd_encnt is S n / 4, the TLAST signal becomes low. After the generation of the AXI4-STREAM protocol signals is completed, the data will be sent to the AXI MCDMA.

[0102] The present invention solves the decision conflict problem by introducing a predictive decision arbitration module based on opportunity cost. In the prior art, when both the length and time thresholds are triggered simultaneously, the system can only make a blind decision based on a preset fixed priority. The present invention makes this decision-making process intelligent and quantitative. Once a decision conflict is detected, the arbitration module calculates the costs of the two options in parallel. By comparing these two precisely quantified opportunity costs, it makes a decision that truly optimizes the current interests, transforming the passive and rigid decision-making point into an active, dynamic, and data-driven optimization process, solving the decision conflict problem and achieving the optimization of the overall system performance. A set of combined refined solutions are provided through the stateful predictive byte splicing module. By introducing an elastic piggyback mechanism, the throughput loss caused by abandoning a large data packet due to a minor overflow is avoided, enhancing the flexibility and efficiency of batch construction. Byte splicing enables the present invention to no longer directly abandon the last data packet as in the prior art, but precisely calculates the number of bytes required to fill the current batch to the length threshold, intercepts this part of the data from the head of the last data packet, and merges it with the previous complete data packets to construct the most efficiently utilized data block with the maximized length. After the splicing is completed, an update operation is performed on the second cache storing the length information to modify the length of the partially transmitted data packet to its remaining length. This ensures that the system does not lose track of data fragments, completely solves the head-of-line blocking problem, and enables the processing of the entire data stream to have both extreme efficiency and 100% integrity.

[0103] The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present invention, various equivalent transformations can be made to the technical solutions of the present invention, and these equivalent transformations all fall within the protection scope of the present invention.

Claims

1. A satellite communication high-speed data transmission method, wherein, Data from the baseband frame is stored in the first buffer, and the length information of the data is stored in the second buffer. It is characterized in that it includes: Calculate the cumulative length of the data in the first buffer and the waiting time since the last transmission in real time; When the cumulative length exceeds the length threshold or the waiting time reaches the time threshold, generate a transmission instruction; According to the transmission instruction, extract the data and length information from the first buffer and the second buffer, and construct a data block to be sent; Encapsulate the data block to be sent into an AXI4-STREAM protocol data stream and send it.

2. The method according to claim 1, wherein Generating a transmission instruction includes: When the cumulative length and the waiting time both exceed their respective corresponding thresholds, it is determined as a decision conflict; To resolve the decision conflict, start the arbitration module for predictive decision-making; The arbitration module generates a transmission instruction that can maximize the transmission benefit by calculating and comparing the time-priority cost and the length-priority cost.

3. The method according to claim 2, characterized in that, Calculating the time-priority cost and the length-priority cost includes: Calculate the time-priority cost according to the quality-of-service level of the latest data packet in the current buffer, the preset delay weight and throughput rate weight, and the cumulative length of all data packets in the current buffer; Calculate the length-priority cost according to the quality-of-service level of the latest data packet, the delay weight and throughput rate weight, and the cumulative length of other data packets except the latest data packet.

4. The method according to claim 3, characterized in that, The calculation of the time-priority cost includes: Determine the delay penalty value according to the quality-of-service level of the latest data packet through a delay evaluation function; Determine the throughput rate score according to the cumulative length of all data packets; Use the delay weight and throughput rate weight to perform weighted summation on the delay penalty value and the throughput rate score to obtain the time-priority cost.

5. The method according to claim 1, characterized in that, Constructing the data block to be sent includes: Determine whether the generation of the transmission instruction is due to the cumulative length exceeding the length threshold or the waiting time reaching the time threshold; When it is determined that the transmission instruction is generated because the cumulative length exceeds the length threshold, activate the stateful predictive byte stitching module, and it is responsible for generating the data block to be sent.

6. The method according to claim 5, characterized in that, The stateful predictive byte stitching module generates the data block to be sent, including: Calculate the overflow amount that exceeds the length threshold due to the addition of the latest data packet in the first buffer; Judge whether the overflow amount is greater than zero and does not exceed the preset elastic margin; if so, jointly construct all the current buffer data packets including the latest data packet into the data block to be sent.

7. The method according to claim 5, wherein The stateful predictive byte stitching module generating the data block to be sent also includes: Calculate the overflow amount that exceeds the length threshold due to the addition of the latest data packet in the first buffer; If the overflow amount is greater than the preset elastic margin, then: Calculate the number of stitching bytes, where the number of stitching bytes is the difference between the length threshold and the cumulative length of other buffer data packets except the latest data packet; According to the number of stitching bytes, merge all buffer data packets except the latest data packet and the partial data content intercepted from the latest data packet to construct the data block to be sent.

8. The method according to claim 7, wherein After merging and constructing the data block to be sent, it also includes: Calculate the remaining length of the latest data packet after intercepting part of the data content; Perform an update operation on the second buffer, and modify the length information corresponding to the latest data packet in it to the remaining length.

9. The method according to claim 1, wherein: The first cache is a first-in, first-out queue; The second cache is an updatable buffer, supporting modification of the stored length information in the middle of the queue.

10. A satellite communication high-speed data transmission system, characterized in that, It includes: A data caching module, configured to obtain the input baseband frame, store the data from the baseband frame in the first cache, and store the length information of the data in the second cache; A status parameter calculation module, connected to the data caching module, configured to calculate in real time the cumulative length of the data in the first cache and the waiting time since the last transmission; A transmission decision module, connected to the status parameter calculation module, configured to generate a transmission instruction when the cumulative length exceeds the length threshold or the waiting time reaches the time threshold; A data batch generation module, connected to the data caching module and the transmission decision module, configured to extract the data and length information from the first cache and the second cache according to the transmission instruction to construct a data block to be sent; A protocol encapsulation and sending module, connected to the data batch generation module, configured to encapsulate the data block to be sent into an AXI4-STREAM protocol data stream and send it.

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