An automatic gain control test circuit for infrared receiving chip

Abstract

The present application discloses an automatic gain control test circuit for an infrared receiver chip, which relates to the field of electronic technology and includes a charge pump circuit and a charge and discharge logic control circuit. The charge pump circuit includes a fast charge control circuit, a first current mirror circuit, a charge pump charge and discharge switch circuit, a second current mirror circuit, and a capacitor charge and discharge circuit. The fast charge control circuit includes an OR gate and a PMOS switch, and the charge and discharge logic control circuit includes a startup circuit, a discharge logic control circuit, and a charge logic control circuit. By improving the fast charge control circuit, the capacitor charge and discharge circuit, the discharge logic control circuit, and the charge logic control circuit, the improved automatic gain control circuit can quickly test the AGC circuit after tape-out through two modes: current acceleration and capacitor acceleration, greatly reducing test time and cost, and reducing test difficulty.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to an automatic gain control test circuit for an infrared receiving chip. Background Art

[0002] In modern infrared communication technology, infrared receiver chips, as core components for signal reception and processing, have a direct impact on the stability and reliability of the entire system. As infrared communication applications continue to expand, from simple remote control devices to complex industrial automation and IoT systems, the performance requirements for infrared receiver chips are becoming increasingly stringent. Especially in complex environmental conditions, the strength of the received signal can fluctuate significantly due to variations in transmission distance, interference, and transmitter power. Automatic gain control (AGC) technology is crucial to ensuring stable output from infrared receiver chips under varying signal strengths. AGC monitors the strength of the received signal in real time and automatically adjusts the gain to maintain an optimal output signal.

[0003] See also Figure 1 Existing infrared receiver chip systems include an automatic gain control (AGC) circuit, a variable gain amplifier (VGA) circuit, a bandpass filter (BPF) circuit, and a DEM (demodulation and modulation) peak detection circuit. The BPF filters the pre-amplified input signal from the VGA before transmitting it to the peak detection circuit. If the signal amplitude exceeds the upper threshold, the AGC triggers a charge function, increasing the AGC output voltage and reducing the VGA gain to achieve the purpose of reducing the amplitude, thus achieving automatic gain control. If the signal continues to decrease and falls below the minimum threshold, the AGC triggers a discharge function, decreasing the AGC output voltage and increasing the VGA gain, causing the signal to exceed the lower threshold, thus achieving automatic gain control.

[0004] Automatic gain control (AGC) circuits primarily have two architectures: feedforward and feedback. The system response time of the feedforward architecture primarily depends on the time it takes for the peak modulation detection circuit (DEM) to detect the input signal. Because the detection circuit's detection range must match the input dynamic range of the variable gain amplifier (VGA), this results in a complex detection circuit structure and high power consumption. In contrast, the feedback AGC loop does not require a complex detection circuit, but it does have the following issues: the detection circuit and the variable gain amplifier (VGA) operate asynchronously, resulting in a longer AGC loop stabilization time and higher testing costs. Furthermore, the initial state of the charge pump's rapid charge and discharge path is affected by the signal amplitude, making testing more difficult.

[0005] See also Figure 2 and Figure 3Existing automatic gain control (AGC) circuits operate in two modes: charging and discharging. In the discharge mode, if the signal is low and ird is high, the AGC enters the hysteretic discharge mode, connecting the charge pump's internal charging and discharging capacitors C2, C4, and C5 to the circuit. P7 charges capacitor C3, causing the voltage at node -pok to rise, turning on INV1 and turning pok low, enabling the circuit. Capacitors C1 and C2 are charged to maintain a constant voltage at out, increasing the VGA op amp's gain to a certain value and maintaining the output amplitude. Because the circuit current is low, if the path signal suddenly disappears or decreases, P8 and P9 charge capacitors C4 and C5, causing the top plate voltage of capacitor C4 to rise at a rate of 103V / s. Until the voltage reaches the 1.5V Schmitt trigger turn-on voltage, the Schmitt trigger output state remains unchanged, and the AGC circuit output voltage amplitude remains constant for a certain period of 15ms. The hysteresis effect of capacitors C3 and C4 delays the switching time of the charge pump charge and discharge switches. During the hysteresis time, it can prevent sudden signal triggering of the DEM detection circuit in a short time, and resist the interference of transient signal mutations on the overall AGC loop. After capacitor C4 is fully charged, -vnc is high, -dchg is low, dchg is high, -chg is high, chg is low, the charge pump discharge switch N4 is turned on, capacitors C1 and C2 are discharged, and the vout output voltage decreases. Similarly, because the circuit current is small, capacitors C1 and C2 are large, and the discharge time is long, at a rate of 15V / s, the VGA gain increases, and the channel signal amplitude increases again.

[0006] If the signal is large enough to make the BPF output signal higher than the maximum threshold of the DEM detection circuit, the AGC's fast charging mode is triggered. As the power supply VDD increases, P7 charges capacitor C3, and the voltage at node -pok rises, turning on INV1. With pok at a low level, the circuit starts. ird is at a low level, and the P10 switch turns on, charging C1 and C2, causing the output voltage out to rise rapidly at 70V / s. The VGA gain decreases to achieve the purpose of reducing the signal amplitude. After the fast path is turned on and stabilized, P9 charges capacitor C5, which is 4 times that of capacitor C4. Therefore, the voltage on the upper plate of capacitor C4 rises at a rate of 27V / s. The Schmitt output does not change within 60ms, which also ensures that the signal amplitude will not decay again within one cycle.

[0007] While the aforementioned AGC loop performs automatic gain control, the AGC module lacks a test mode after chip fabrication (tapeout). Adding a test mode to the AGC module would still present issues such as long circuit stabilization time and high testing costs. Furthermore, the fast-charging path's heavy reliance on the input signal amplitude complicates setting the AGC's initial output voltage (out), increasing testing complexity. Summary of the Invention

[0008] To this end, the present application provides an automatic gain control test circuit for an infrared receiving chip to solve the problems of high post-tapeline testing cost and difficulty in testing of the AGC circuit in the prior art.

[0009] In order to achieve the above objectives, this application provides the following technical solutions:

[0010] An automatic gain control test circuit for an infrared receiving chip, comprising a charge pump circuit and a charge and discharge logic control circuit, wherein the charge pump circuit comprises a fast charging control circuit, a first current mirror circuit, a charge pump charge and discharge switch circuit, a second current mirror circuit, and a capacitor charge and discharge circuit;

[0011] The fast charge control circuit includes an OR gate and a PMOS switch, wherein the two input terminals of the OR gate are respectively input with a fast charge channel voltage and a test voltage, the output terminal of the OR gate is electrically connected to the gate of the PMOS switch, the source of the PMOS switch is electrically connected to the first output terminal of the first current mirror circuit, the drain of the PMOS switch is connected to the capacitor charge and discharge circuit and the charge pump charge and discharge switch circuit, the second output terminal of the first current mirror circuit is electrically connected to one terminal of the second current mirror circuit, the third output terminal of the first current mirror circuit is electrically connected to the charge pump charge and discharge switch circuit, and the charge pump charge and discharge switch circuit is electrically connected to the other terminal of the second current mirror circuit;

[0012] The charge and discharge logic control circuit includes a start-up circuit, a discharge logic control circuit and a charge logic control circuit; the start-up circuit, the discharge logic control circuit and the charge logic control circuit are connected in parallel, the discharge logic control circuit is electrically connected to the charge pump charge and discharge switch circuit and the capacitor charge and discharge circuit, and the charge logic control circuit is electrically connected to the charge pump charge and discharge switch circuit and the fast charging control circuit.

[0013] Optionally, the capacitor charging and discharging circuit includes a first NMOS switch, a second NMOS switch, a first capacitor, and a second capacitor. The drain of the first NMOS switch, the drain of the second NMOS switch, and one end of the first capacitor are connected together and electrically connected to an external initial bias voltage. The source of the first NMOS switch, the source of the second NMOS switch, and the other end of the first capacitor are connected together and electrically connected to the drain of the PMOS switch and the charge pump charging and discharging switch circuit. The second capacitor is connected in series to the source of the second NMOS switch.

[0014] Optionally, the startup circuit includes a first inverter, a fifth PMOS switch, a seventh PMOS switch and a third capacitor. The source of the fifth PMOS switch is connected to the source of the seventh PMOS switch and then electrically connected to the connection point of the discharge logic control circuit and the charging logic control circuit in parallel. The first inverter is connected in series between the drain and the gate of the fifth PMOS switch. The drain of the fifth PMOS switch is also electrically connected to the drain of the seventh PMOS switch and one end of the third capacitor. The other end of the third capacitor is electrically connected to the connection point of the discharge logic control circuit and the charging logic control circuit in parallel. The gate of the seventh PMOS switch is electrically connected to the discharge logic control circuit and the charging logic control circuit.

[0015] Optionally, the discharge logic control circuit includes a sixth PMOS switch, an eighth PMOS switch, a twelfth PMOS switch, a thirteenth PMOS switch, a first Schmitt trigger, a second inverter, a fourth capacitor, a seventh NMOS switch and an eighth NMOS switch, the source of the sixth PMOS switch, the source of the eighth PMOS switch and the source of the twelfth PMOS switch are connected together and electrically connected to the startup circuit and the charging logic control circuit, the drain of the twelfth PMOS switch is electrically connected to the source of the thirteenth PMOS switch, the gate of the twelfth PMOS switch is used to input a current test voltage, and the drain of the sixth PMOS switch, the drain of the eighth PMOS switch and the drain of the thirteenth PMOS switch are connected together and connected to the input end and the first Schmitt trigger. The drain of the seventh NMOS switch is electrically connected, the gate and source of the sixth PMOS switch are connected, the gate of the eighth PMOS switch and the gate of the thirteenth PMOS switch are electrically connected to the startup circuit and the charging logic control circuit, the output of the first Schmitt trigger is electrically connected to the input of the second inverter, the output of the second inverter is electrically connected to the charge pump charge and discharge switch circuit, the gate of the seventh NMOS switch is used to input a noise threshold voltage, the source of the seventh NMOS switch and the source of the eighth NMOS switch are connected together and then grounded, the gate of the eighth NMOS switch is electrically connected to the capacitor charge and discharge circuit, the drain of the eighth NMOS switch is electrically connected to the drain of the seventh NMOS switch, and the fourth capacitor is connected in series with the drain of the eighth NMOS switch.

[0016] Optionally, the charging logic control circuit includes a ninth PMOS switch, a fourteenth PMOS switch, a fifteenth PMOS switch, a second Schmitt trigger, a third inverter, a NAND gate, a fourth inverter, a fifth capacitor, a ninth NMOS switch, a tenth NMOS switch and a fifth inverter, the gate of the fourteenth PMOS switch is used to input a current test voltage, the drain of the fourteenth PMOS switch is electrically connected to the source of the fifteenth PMOS switch, the source of the ninth PMOS switch is connected to the source of the fourteenth PMOS switch and then electrically connected to the discharge logic control circuit, the drain of the ninth PMOS switch is connected to the drain of the fifteenth PMOS switch and then electrically connected to the drain of the fifteenth PMOS switch. The input end of the second Schmitt trigger is electrically connected to the drain of the ninth NMOS switch, the second Schmitt trigger, the third inverter, the NAND gate and the fourth inverter are connected in series in sequence, the output end of the fourth inverter is electrically connected to the charge pump charge and discharge switch circuit, the input end of the fifth inverter is electrically connected to the fast charging control circuit, the output end of the fifth inverter is electrically connected to the gate of the tenth NMOS switch, the source of the tenth NMOS switch is connected to the source of the ninth NMOS switch and then to ground, the fifth capacitor is connected in series to the drain of the tenth NMOS switch, and the drain of the tenth NMOS switch is electrically connected to the drain of the ninth NMOS switch.

[0017] Optionally, the first current mirror circuit includes a first PMOS switch, a second PMOS switch and a tenth PMOS switch, the source of the first PMOS switch, the source of the second PMOS switch and the source of the tenth PMOS switch are connected together, the gate of the first PMOS switch, the gate of the second PMOS switch and the gate of the tenth PMOS switch are connected together, the drain of the first PMOS switch is electrically connected to one end of the second current mirror circuit, the drain of the second PMOS switch is electrically connected to the charge pump charge and discharge switch circuit, and the drain of the tenth PMOS switch is electrically connected to the source of the PMOS switch.

[0018] Optionally, the charge pump charge and discharge switch circuit includes a charge control switch, a discharge control switch and a buffer amplifier, and the buffer amplifier is used to clamp the voltage so that the input terminal voltage of the buffer amplifier is equal to the output terminal voltage, that is, the output voltage out is equal to the voltage of vr.

[0019] Optionally, the charge control switch is composed of two PMOS switches, and the discharge control switch is composed of two NMOS switches.

[0020] Optionally, the second current mirror circuit includes a fifth NMOS switch and a sixth NMOS switch, the gate of the fifth NMOS switch and the gate of the sixth NMOS switch are connected together, the source of the fifth NMOS switch and the source of the sixth NMOS switch are connected together, the drain of the fifth NMOS switch is electrically connected to the second output end of the first current mirror circuit, and the drain of the sixth NMOS switch is electrically connected to the charge pump charge and discharge switch circuit.

[0021] Compared with the prior art, this application has at least the following beneficial effects:

[0022] The present application provides an automatic gain control test circuit for an infrared receiver chip, including a charge pump circuit and a charge-discharge logic control circuit. The charge pump circuit includes a fast charge control circuit, a first current mirror circuit, a charge pump charge-discharge switch circuit, a second current mirror circuit, and a capacitor charge-discharge circuit. The charge-discharge logic control circuit includes a startup circuit, a discharge logic control circuit, and a charge logic control circuit. By improving the fast charge control circuit, the capacitor charge-discharge circuit, the discharge logic control circuit, and the charge logic control circuit, the improved automatic gain control circuit can quickly test the AGC circuit after tape-out through two modes: current acceleration and capacitor acceleration, greatly reducing test time and cost, and reducing test difficulty. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] To more intuitively illustrate the prior art and the present application, exemplary drawings are provided below. It should be understood that the specific shapes and structures shown in the drawings should not generally be considered as limiting conditions for implementing the present application. For example, based on the technical concepts disclosed in this application and the exemplary drawings, those skilled in the art are capable of easily making routine adjustments or further optimizations to the addition / reduction / attribution division of certain units (components), the specific shapes, positional relationships, connection methods, and dimensional ratios.

[0024] Figure 1 This is a schematic diagram of the existing infrared receiving chip system structure;

[0025] Figure 2 The following is a schematic diagram of a charge pump circuit of an existing automatic gain control circuit;

[0026] Figure 3 It is a schematic diagram of the charge and discharge logic control circuit of the existing automatic gain control circuit;

[0027] Figure 4 A schematic diagram of a charge pump circuit for the automatic gain control circuit provided in this application;

[0028] Figure 5 This is a schematic diagram of the charge and discharge logic control circuit of the automatic gain control circuit provided in this application.

[0029] Description of reference numerals:

[0030] 1. Charge pump circuit; 101. Fast charging control circuit; 102. First current mirror circuit; 103. Charge pump charge and discharge switch circuit; 104. Second current mirror circuit; 105. Capacitor charge and discharge circuit; 2. Charge and discharge logic control circuit; 201. Startup circuit; 202. Discharge logic control circuit; 203. Charge logic control circuit. DETAILED DESCRIPTION

[0031] The present application will be further described below in detail through specific embodiments in conjunction with the accompanying drawings.

[0032] In the description of this application: unless otherwise specified, "plurality" means two or more. The terms "first," "second," "third," etc. in this application are intended to distinguish the objects referred to and do not have any special technical connotations (for example, they should not be understood as emphasizing importance or order). Expressions such as "including," "comprising," and "having" also mean "not limited to" (certain units, components, materials, steps, etc.).

[0033] The terms such as "upper", "lower", "left", "right", "middle", etc. cited in this application are usually used to indicate the general relative position relationship for the convenience of intuitive understanding by referring to the drawings, and are not absolute limitations on the position relationship in the actual product.

[0034] See also Figure 4 and Figure 5 The present application provides an automatic gain control test circuit for an infrared receiving chip, including a charge pump circuit 1 and a charge and discharge logic control circuit 2. The charge pump circuit 1 includes a fast charging control circuit 101, a first current mirror circuit 102, a charge pump charge and discharge switch circuit 103, a second current mirror circuit 104 and a capacitor charge and discharge circuit 105.

[0035] In which, the fast charging control circuit 101 includes an OR gate OR and a PMOS switch P11, the two input ends of the OR gate OR respectively input the fast charging channel voltage ird and the test voltage m2, the output end of the OR gate OR is electrically connected to the gate of the PMOS switch P11, the source of the PMOS switch P11 is electrically connected to the first output end of the first current mirror circuit 102, the drain of the PMOS switch P11 is electrically connected to the capacitor charging and discharging circuit 105 and the charge pump charging and discharging switch circuit 103, the second output end of the first current mirror circuit 102 is electrically connected to one end of the second current mirror circuit 104, the third output end of the first current mirror circuit 102 is electrically connected to the charge pump charging and discharging switch circuit 103, and the charge pump charging and discharging switch circuit 103 is electrically connected to the other end of the second current mirror circuit 104.

[0036] The charge and discharge logic control circuit 2 includes a start-up circuit 201, a discharge logic control circuit 202 and a charge logic control circuit 203; the start-up circuit 201, the discharge logic control circuit 202 and the charge logic control circuit 203 are connected in parallel, the discharge logic control circuit 202 is electrically connected to the charge pump charge and discharge switch circuit 103 and the capacitor charge and discharge circuit 105, and the charge logic control circuit 203 is electrically connected to the charge pump charge and discharge switch circuit 103 and the fast charge control circuit 101.

[0037] Specifically, the first current mirror circuit 102 includes a first PMOS switch P1, a second PMOS switch P2, and a tenth PMOS switch P10. The source of the first PMOS switch P1, the source of the second PMOS switch P2, and the source of the tenth PMOS switch P10 are connected together, the gate of the first PMOS switch P1, the gate of the second PMOS switch P2, and the gate of the tenth PMOS switch P10 are connected together, the drain of the first PMOS switch P1 is electrically connected to one end of the second current mirror circuit 104, the drain of the second PMOS switch P2 is electrically connected to the charge pump charge and discharge switch circuit 103, and the drain of the tenth PMOS switch P10 is electrically connected to the source of the PMOS switch P11.

[0038] Specifically, the charge pump charge-discharge switch circuit 103 includes a charge control switch, a discharge control switch, and a buffer amplifier. The buffer amplifier is used to clamp the voltage so that the voltage at the buffer amplifier's input terminal is equal to the voltage at the output terminal. That is, the output voltage out is equal to the voltage vr. The charge control switch is composed of two PMOS switches (P3 and P4), and the discharge control switch is composed of two NMOS switches (N3 and N4).

[0039] Specifically, the second current mirror circuit 104 includes a fifth NMOS switch N5 and a sixth NMOS switch N6. The gate of the fifth NMOS switch N5 and the gate of the sixth NMOS switch N6 are connected together, the source of the fifth NMOS switch N5 and the source of the sixth NMOS switch N6 are connected together, the drain of the fifth NMOS switch N5 is electrically connected to the second output end of the first current mirror circuit 102, and the drain of the sixth NMOS switch N6 is electrically connected to the charge pump charge and discharge switch circuit 103.

[0040] Specifically, the capacitor charging and discharging circuit 105 includes a first NMOS switch N1, a second NMOS switch N2, a first capacitor C1, and a second capacitor C2. The drain of the first NMOS switch N1, the drain of the second NMOS switch N2, and one end of the first capacitor C1 are connected together and electrically connected to an external initial bias voltage. The source of the first NMOS switch N1, the source of the second NMOS switch N2, and the other end of the first capacitor C1 are connected together and electrically connected to the drain of the PMOS switch P11 and the charge pump charging and discharging switch circuit 103. The second capacitor C2 is connected in series with the source of the second NMOS switch N2.

[0041] Specifically, the startup circuit 201 includes a first inverter INV1, a fifth PMOS switch P5, a seventh PMOS switch P7, and a third capacitor C3. The source of the fifth PMOS switch P5 is connected to the source of the seventh PMOS switch P7, and then electrically connected to the connection point of the discharge logic control circuit 202 and the charge logic control circuit 203 in parallel. The first inverter INV1 is connected in series between the drain and the gate of the fifth PMOS switch P5. The drain of the fifth PMOS switch P5 is also electrically connected to the drain of the seventh PMOS switch P7 and one end of the third capacitor C3. The other end of the third capacitor C3 is electrically connected to the connection point of the discharge logic control circuit 202 and the charge logic control circuit 203 in parallel. The gate of the seventh PMOS switch P7 is electrically connected to the discharge logic control circuit 202 and the charge logic control circuit 203.

[0042] Specifically, the discharge logic control circuit 202 includes a sixth PMOS switch P6, an eighth PMOS switch P8, a twelfth PMOS switch P12, a thirteenth PMOS switch P13, a first Schmitt trigger INT1, a second inverter INV2, a fourth capacitor C4, a seventh NMOS switch N7, and an eighth NMOS switch N8. The source of the sixth PMOS switch P6, the source of the eighth PMOS switch P8, and the source of the twelfth PMOS switch P12 are connected together and electrically connected to the startup circuit 201 and the charging logic control circuit 203. The drain of the twelfth PMOS switch P12 is electrically connected to the source of the thirteenth PMOS switch P13. The gate of the twelfth PMOS switch P12 is used to input a current test voltage. The drain of the sixth PMOS switch P6, the drain of the eighth PMOS switch P8, and the drain of the thirteenth PMOS switch P13 are connected together and electrically connected to the first Schmitt trigger INT1. An input terminal of the trigger INT1 is electrically connected to the drain of the seventh NMOS switch N7, a gate and source of the sixth PMOS switch P6 are connected, a gate of the eighth PMOS switch P8 and a gate of the thirteenth PMOS switch P13 are electrically connected to the startup circuit 201 and the charging logic control circuit 203, an output terminal of the first Schmitt trigger INT1 is electrically connected to the input terminal of the second inverter INV2, an output terminal of the second inverter INV2 is electrically connected to the charge pump charge and discharge switch circuit 103, a gate of the seventh NMOS switch N7 is used to input a noise threshold voltage, a source of the seventh NMOS switch N7 and a source of the eighth NMOS switch N8 are connected together and then grounded, a gate of the eighth NMOS switch N8 is electrically connected to the capacitor charge and discharge circuit 105, a drain of the eighth NMOS switch N8 is electrically connected to the drain of the seventh NMOS switch, and a fourth capacitor C4 is connected in series with the drain of the eighth NMOS switch N8.

[0043] Specifically, the charging logic control circuit 203 includes a ninth PMOS switch P9, a fourteenth PMOS switch P14, a fifteenth PMOS switch P15, a second Schmitt trigger INT2, a third inverter INV3, a NAND gate NAND, a fourth inverter INV4, a fifth capacitor C5, a ninth NMOS switch N9, a tenth NMOS switch N10, and a fifth inverter INV5. The gate of the fourteenth PMOS switch P14 is used to input a current test voltage, the drain of the fourteenth PMOS switch P14 is electrically connected to the source of the fifteenth PMOS switch P15, the source of the ninth PMOS switch P9 and the source of the fourteenth PMOS switch P14 are connected together and then electrically connected to the discharge logic control circuit 202, the drain of the ninth PMOS switch P9 and the fifteenth PMOS The drain of the switch P15 is connected together and then electrically connected to the input end of the second Schmitt trigger INT2 and the drain of the ninth NMOS switch N9. The second Schmitt trigger INT2, the third inverter INV3, the NAND gate NAND, and the fourth inverter INV4 are connected in series in sequence. The output end of the fourth inverter INV4 is electrically connected to the charge pump charge and discharge switch circuit 103. The input end of the fifth inverter INV5 is electrically connected to the fast charging control circuit 101. The output end of the fifth inverter INV5 is electrically connected to the gate of the tenth NMOS switch N10. The source of the tenth NMOS switch N10 is connected to the source of the ninth NMOS switch N9 and then to ground. The fifth capacitor C5 is connected in series with the drain of the tenth NMOS switch, and the drain of the tenth NMOS switch is electrically connected to the drain of the ninth NMOS switch.

[0044] This application provides an automatic gain control test circuit for an infrared receiver chip. By improving the fast charging control circuit (adding an OR gate), the capacitor charging and discharging circuit (adding N2), the discharge logic control circuit (adding P12, P13, and N8), and the charging logic control circuit (adding P14, P15, N10, and INV5), the improved automatic gain control (AGC) circuit can quickly test the AGC circuit after tape-out in two modes: current acceleration and capacitor acceleration. The working principles are as follows:

[0045] When the m2 port is at a high level, the capacitor acceleration test mode is started:

[0046] Please continue reading Figure 4 and Figure 5In capacitor acceleration test mode, the AGC circuit operates in two modes: charging and discharging. In discharge mode, if the signal is small, m2 is high, turning off P11. The circuit shuts down the fast charging channel, and the AGC's initial output voltage is no longer affected by the initial signal amplitude. m2b is low, disconnecting capacitors C2, C4, and C5 from the circuit and activating the hysteresis discharge mode. P7 charges capacitor C3, causing the voltage at node -pok to rise, turning on INV1. With pok low, the circuit starts. Capacitors C1 and C2 are charged, maintaining a certain voltage at out, increasing the gain of the VGA op amp to a certain value and maintaining the output amplitude. Because the circuit current remains unchanged, if the path signal suddenly disappears or becomes smaller, P8 and P9 charge capacitors C4 and C5. The voltage on the top plate of capacitor C4 rises at a rate of 1100V / s. Before the voltage reaches the 1.5V Schmitt trigger turn-on voltage, the Schmitt trigger output state remains unchanged, and the amplitude of the AGC circuit output voltage remains unchanged within 1.4ms. After C4 is charged, -vnc is high, -dchg is low, dchg is high, -chg is high, chg is low, the charge pump discharge switch N4 is turned on, capacitor C1 is discharged, and the vout output voltage decreases. Similarly, because the circuit current remains unchanged, the capacitance decreases, the voltage drops at a rate of 75V / s, the VGA gain increases, and the channel signal amplitude increases again.

[0047] If the signal is large enough to cause the BPF output signal to exceed the maximum threshold of the DEM detection circuit, the AGC charging mode is triggered. As power supply VDD increases, P7 charges capacitor C3, causing the voltage at node -pok to rise, turning on INV1. With pok at a low level, the circuit starts. m2 is high, turning off P11, and the circuit shuts down the fast charging channel. vnc is high, -vnc is flat, -dchg is high, dchg is low, -chg is high, and chg is low. P9 charges capacitor C5, and the voltage on the top plate of capacitor C5 rises at a rate of 455.88V / s. The Schmitt trigger output remains unchanged within 3ms. The Schmitt trigger output state remains unchanged until the voltage reaches the 1.5V Schmitt trigger turn-on voltage. The amplitude of the AGC circuit output voltage remains unchanged within 3ms. After C5 is charged, -chg is low and chg is high, P3 is turned on to charge C1, causing the out voltage to increase at a rate of 14V / s, the VGA gain to decrease, and the signal amplitude to decrease.

[0048] When the M2 port is at a high level and the M1 port is at a low level, connect P12 and P14 to the circuit and start the current acceleration test mode:

[0049] Please continue reading Figure 4 and Figure 5The working principle of the current acceleration test mode is the same as that of the capacitor acceleration mode. The difference is that this mode increases the current of P9 charging C4 by 2 times, so that the charging current of the upper plate of C4 and the upper plate of C5 increases by 2 times, thus shortening the charging time by another 2 times. In this mode, the current size is inversely proportional to the charging time, which can be expressed as the following formula:

[0050] ,

[0051] Integrating both sides of the formula we can get:

[0052] ,

[0053] ,

[0054] Where C is the capacitance of C5 and C4, Vth is the conduction threshold of the Schmitt trigger, and I is the current of P9 and P10 during charging.

[0055] The above formula shows that by adjusting the values ​​of C and I, the size of the noise detection time window can be adjusted. The time should be neither too short nor too long. If it is too short, the out voltage cannot effectively adjust the VGA. If it is too long, the AGC will be in a process of constantly adjusting the gain of the VGA during normal infrared communication. It needs to be adjusted according to the actual situation.

[0056] This application conducted simulation experiments on the charging and discharging output voltages of the AGC circuit before and after improvement, and the charging of the AGC circuit hysteresis capacitors C4 and C5. According to the simulation results, it can be seen that the detection time and rate after improvement are significantly faster than those of the circuit before improvement.

[0057] The automatic gain control test circuit for an infrared receiver chip provided in this application has the following outstanding advantages:

[0058] (1) It accelerates the charging and discharging speed of the charge pump and shortens the hysteresis time. During the test process, the circuit function can be tested in a shorter time, which greatly reduces the test time and cost;

[0059] (2) The initial output voltage of the AGC is no longer affected by the amplitude of the input signal, which reduces the difficulty of testing.

[0060] In summary, the automatic gain control test circuit of an infrared receiving chip provided in this application can test the circuit function in a relatively short time during the test process, greatly reducing the test cost and test difficulty, and solving the problems of the existing AGC loop such as long stabilization time, high detection cost, and high test difficulty.

[0061] The technical features of the above embodiments can be combined arbitrarily (as long as there is no contradiction in the combination of these technical features). In order to make the description concise, not all possible combinations of the technical features in the above embodiments are described; these embodiments that are not explicitly written should also be considered to be within the scope of this specification.

Claims

1. An automatic gain control test circuit for an infrared receiving chip, characterized in that: It includes a charge pump circuit and a charge and discharge logic control circuit, wherein the charge pump circuit includes a fast charging control circuit, a first current mirror circuit, a charge pump charge and discharge switch circuit, a second current mirror circuit and a capacitor charge and discharge circuit; The fast charge control circuit includes an OR gate and a PMOS switch, wherein the two input terminals of the OR gate are respectively input with a fast charge channel voltage and a test voltage, wherein the test voltage is at a high level, the output terminal of the OR gate is electrically connected to the gate of the PMOS switch, the source of the PMOS switch is electrically connected to the first output terminal of the first current mirror circuit, the drain of the PMOS switch is electrically connected to the capacitor charge and discharge circuit and the charge pump charge and discharge switch circuit, the second output terminal of the first current mirror circuit is electrically connected to one terminal of the second current mirror circuit, the third output terminal of the first current mirror circuit is electrically connected to the charge pump charge and discharge switch circuit, and the charge pump charge and discharge switch circuit is electrically connected to the other terminal of the second current mirror circuit; The charge and discharge logic control circuit includes a start-up circuit, a discharge logic control circuit and a charge logic control circuit; the start-up circuit, the discharge logic control circuit and the charge logic control circuit are connected in parallel, the discharge logic control circuit is electrically connected to the charge pump charge and discharge switch circuit and the capacitor charge and discharge circuit, and the charge logic control circuit is electrically connected to the charge pump charge and discharge switch circuit and the fast charging control circuit.

2. The automatic gain control test circuit of the infrared receiving chip according to claim 1, characterized in that: The capacitor charging and discharging circuit includes a first NMOS switch, a second NMOS switch, a first capacitor, and a second capacitor. The drain of the first NMOS switch, the drain of the second NMOS switch, and one end of the first capacitor are connected together and electrically connected to an external initial bias voltage. The source of the second NMOS switch is connected to one end of the second capacitor. The source of the first NMOS switch, the other end of the second capacitor, and the other end of the first capacitor are connected together and connected to the drain of the PMOS switch and the charge pump charging and discharging switch circuit.

3. The automatic gain control test circuit of the infrared receiving chip according to claim 1, characterized in that: The startup circuit includes a first inverter, a fifth PMOS switch, a seventh PMOS switch and a third capacitor. The source of the fifth PMOS switch is connected to the source of the seventh PMOS switch and then electrically connected to the connection point of the discharge logic control circuit and the charging logic control circuit in parallel. The first inverter is connected in series between the drain and the gate of the fifth PMOS switch. The drain of the fifth PMOS switch is also electrically connected to the drain of the seventh PMOS switch and one end of the third capacitor. The other end of the third capacitor is electrically connected to another connection point of the discharge logic control circuit and the charging logic control circuit in parallel. The gate of the seventh PMOS switch is electrically connected to the discharge logic control circuit and the charging logic control circuit.

4. The automatic gain control test circuit of the infrared receiving chip according to claim 1, characterized in that: The discharge logic control circuit includes a sixth PMOS switch, an eighth PMOS switch, a twelfth PMOS switch, a thirteenth PMOS switch, a first Schmitt trigger, a second inverter, a fourth capacitor, a seventh NMOS switch, and an eighth NMOS switch. The source of the sixth PMOS switch, the source of the eighth PMOS switch, and the source of the twelfth PMOS switch are connected together and electrically connected to the startup circuit and the charging logic control circuit. The drain of the twelfth PMOS switch is electrically connected to the source of the thirteenth PMOS switch. The gate of the twelfth PMOS switch is used to input a current test voltage. The drain of the sixth PMOS switch, the drain of the eighth PMOS switch, and the drain of the thirteenth PMOS switch are connected together and connected to the input end of the first Schmitt trigger and the The drain of the seventh NMOS switch is electrically connected, the gate and source of the sixth PMOS switch are connected, the gate of the eighth PMOS switch and the gate of the thirteenth PMOS switch are electrically connected to the startup circuit and the charging logic control circuit, the output of the first Schmitt trigger is electrically connected to the input of the second inverter, the output of the second inverter is connected to the charge pump charge and discharge switch circuit, the gate of the seventh NMOS switch is used to input a noise threshold voltage, the source of the seventh NMOS switch and the source of the eighth NMOS switch are connected together and then grounded, the gate of the eighth NMOS switch is electrically connected to the capacitor charge and discharge circuit, the drain of the eighth NMOS switch is electrically connected to one end of the fourth capacitor, and the other end of the fourth capacitor is electrically connected to the drain of the seventh NMOS switch.

5. The automatic gain control test circuit of the infrared receiving chip according to claim 1, characterized in that: The charging logic control circuit includes a ninth PMOS switch, a fourteenth PMOS switch, a fifteenth PMOS switch, a second Schmitt trigger, a third inverter, a NAND gate, a fourth inverter, a fifth capacitor, a ninth NMOS switch, a tenth NMOS switch and a fifth inverter. The gate of the fourteenth PMOS switch is used to input a current test voltage. The drain of the fourteenth PMOS switch is electrically connected to the source of the fifteenth PMOS switch. The source of the ninth PMOS switch and the source of the fourteenth PMOS switch are connected together and then electrically connected to the discharge logic control circuit. The drain of the ninth PMOS switch and the drain of the fifteenth PMOS switch are connected together and then electrically connected to the second Schmitt trigger. An input end of the trigger is electrically connected to the drain of the ninth NMOS switch, the second Schmitt trigger, the third inverter, the NAND gate and the fourth inverter are connected in series in sequence, the output end of the fourth inverter is electrically connected to the charge pump charge and discharge switch circuit, the input end of the fifth inverter is electrically connected to the fast charging control circuit, the output end of the fifth inverter is electrically connected to the gate of the tenth NMOS switch, the source of the tenth NMOS switch is connected to the source of the ninth NMOS switch and then to ground, the fifth capacitor is connected in series with the drain of the tenth NMOS switch and is electrically connected to one end of the fifth capacitor, and the other end of the fifth capacitor is electrically connected to the drain of the ninth NMOS switch.

6. The automatic gain control test circuit for an infrared receiving chip according to claim 1, characterized in that: The first current mirror circuit includes a first PMOS switch, a second PMOS switch, and a tenth PMOS switch. The source of the first PMOS switch, the source of the second PMOS switch, and the source of the tenth PMOS switch are connected together, and the gate of the first PMOS switch, the gate of the second PMOS switch, and the gate of the tenth PMOS switch are connected together. The drain of the first PMOS switch is electrically connected to one end of the second current mirror circuit, the drain of the second PMOS switch is electrically connected to the charge pump charge and discharge switch circuit, and the drain of the tenth PMOS switch is electrically connected to the source of the PMOS switch.

7. The automatic gain control test circuit for an infrared receiving chip according to claim 1, characterized in that: The charge pump charge and discharge switch circuit includes a charge control switch, a discharge control switch and a buffer amplifier. The buffer amplifier is used to clamp the voltage so that the input terminal voltage of the buffer amplifier is equal to the output terminal voltage.

8. The automatic gain control test circuit for an infrared receiving chip according to claim 7, characterized in that: The charge control switch is composed of two PMOS switches, and the discharge control switch is composed of two NMOS switches.

9. The automatic gain control test circuit for an infrared receiving chip according to claim 1, characterized in that: The second current mirror circuit includes a fifth NMOS switch and a sixth NMOS switch, wherein the gate of the fifth NMOS switch and the gate of the sixth NMOS switch are connected together, the source of the fifth NMOS switch and the source of the sixth NMOS switch are connected together, the drain of the fifth NMOS switch is electrically connected to the second output end of the first current mirror circuit, and the drain of the sixth NMOS switch is connected to the charge pump charge and discharge switch circuit.

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