Data verification method and device, electronic equipment, storage medium and chip

Abstract

The invention provides a data verification method and device, electronic equipment, a storage medium and a chip, and the method comprises the steps: after generating a frame header of to-be-transmitted data, controlling the parallel execution of the transmission of a data frame, and verifying the frame header verification information in the frame header; the frame header comprises frame header verification information, the frame header verification information is determined according to a frame header keyword and a dynamic variable, and when a frame tail keyword of a frame tail is detected, frame tail verification information is acquired for verification; the frame tail comprises frame tail verification information, the frame tail verification information is determined according to the data frame, and whether the to-be-transmitted data is abnormal or not during transmission is determined according to a verification result of the frame tail verification information. Through a mode of parallel execution of data frame transmission and verification, to-be-transmitted data does not need to be modified, the transmission efficiency of the to-be-transmitted data is not affected, when data verification is performed, frame header verification information is determined according to frame header keywords and dynamic variables, frame tail verification information is determined according to data frames, real-time effective data can be obtained, and the data verification efficiency is improved. And the reliability of data inspection is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of data processing, and in particular, to a method, apparatus, electronic device, storage medium, and chip for data verification. Background Art

[0002] Currently, when data is transmitted wirelessly or wiredly, the reliability of the data during the data transmission process cannot be fully ensured. Therefore, it is necessary to verify the data in the data transmission path to improve the robustness. Summary of the Invention

[0003] The present disclosure provides a method and apparatus, an electronic device, a storage medium, and a chip for data verification to solve the problems in the related art.

[0004] The first aspect embodiment of the present disclosure proposes a method for data verification, the method including:

[0005] After generating a frame header of the data to be transmitted, controlling the parallel execution of the transmission of the data frame and the verification of the frame header verification information in the frame header; the data to be transmitted includes at least the frame header, the data frame, and the frame tail, the frame header contains frame header verification information, and the frame header verification information is determined according to the frame header keyword and the dynamic variable;

[0006] When detecting the frame tail keyword of the frame tail, obtaining the frame tail verification information for verification; the frame tail includes frame tail verification information, and the frame tail verification information is determined according to the data frame;

[0007] Determining whether there is an abnormality in the transmission of the data to be transmitted according to the verification result of the frame tail verification information.

[0008] In some embodiments of the present disclosure, the execution of the transmission of the data frame includes:

[0009] Executing the transmission of the data to be transmitted through a data transmission path, where the data transmission path includes a source channel and a destination channel, and the number of the source channels is the same as or different from the number of the destination channels.

[0010] In some embodiments of the present disclosure, the execution of the transmission of the data to be transmitted through the data transmission path includes:

[0011] Controlling the data to be transmitted to be written into the source channel and updating the write pointer of the source channel;

[0012] In response to the update of the write pointer of the source channel, reading the data to be transmitted from the source channel to the destination channel and updating the write pointer of the source channel pointing to the destination channel;

[0013] After detecting that the data to be transmitted in the destination channel is read, updating the read pointer of the destination channel.

[0014] In some embodiments of the present disclosure, the method further includes:

[0015] After all data frames of the data to be transmitted are transmitted via the source channel, update the read pointer of the source channel pointing to the source of the data to be transmitted.

[0016] In some embodiments of the present disclosure, the reading of the data to be transmitted from the source channel to the destination channel includes:

[0017] When it is determined that the number of source channels is different from the number of destination channels, determine the corresponding destination channel through a preset connection routing table;

[0018] Read the data to be transmitted from the source channel to the corresponding destination channel.

[0019] In some embodiments of the present disclosure, the verification of the frame header check information in the frame header includes:

[0020] Verify the frame header check information in the frame header through an auxiliary bypass, the auxiliary bypass is independent of the data transmission path, and the auxiliary bypass has the permission to read the frame header check information and the frame tail check information.

[0021] In some embodiments of the present disclosure, the generation of the frame header of the data to be transmitted includes:

[0022] Determine the frame header check code according to the frame header keyword and the timestamp of initiating the data to be transmitted;

[0023] Fill the frame header check code into the frame header check information.

[0024] In some embodiments of the present disclosure, before obtaining the frame tail check information for verification, the method further includes:

[0025] [[ID=3�]]Select a preset number of target data frames from all data frames of the data to be transmitted according to a preset granularity;

[0026] Determine the frame tail check code according to the frame tail keyword and the target data frame;

[0027] Fill the frame tail check code into the frame tail check information.

[0028] In some embodiments of the present disclosure, the obtaining of the frame tail check information for verification includes:

[0029] Redetermine the check code to be verified according to the frame tail keyword and the target data frame;

[0030] If the verification code to be verified is consistent with the frame tail verification code in the frame tail verification information, it is determined that the verification is passed.

[0031] The second aspect of the present disclosure provides an apparatus for verifying data, the apparatus includes:

[0032] A control unit, configured to generate a frame header of data to be transmitted, control the parallel transmission of a data frame, and verify the frame header verification information in the frame header; the data to be transmitted at least includes the frame header, the data frame, and the frame tail, the frame header contains frame header verification information, and the frame header verification information is determined according to a frame header keyword and a dynamic variable;

[0033] An acquisition unit, configured to acquire frame tail verification information for verification when detecting a frame tail keyword of the frame tail; the frame tail includes frame tail verification information, and the frame tail verification information is determined according to the data frame;

[0034] A verification unit, configured to determine whether there is an abnormality in the data to be transmitted during transmission according to the verification result of the frame tail verification information.

[0035] In some embodiments of the present disclosure, the control unit controls the transmission of the data frame, including:

[0036] Performing the transmission of the data to be transmitted through a data transmission path, where the data transmission path includes a source channel and a destination channel, and the number of source channels is the same as or different from the number of destination channels.

[0037] In some embodiments of the present disclosure, the control unit controls the transmission of the data frame, including:

[0038] A control module, configured to control the data to be transmitted to be written into the source channel;

[0039] A first update module, configured to update the write pointer of the source channel;

[0040] A reading module, configured to read the data to be transmitted from the source channel to the destination channel in response to the update of the write pointer of the source channel;

[0041] A second update module, configured to update the write pointer of the source channel pointing to the destination channel;

[0042] A third update module, configured to update the read pointer of the destination channel after detecting that the data to be transmitted in the destination channel is read.

[0043] In some embodiments of the present disclosure, the control unit controlling the transmission of the data frame further includes:

[0044] A fourth update module, configured to update a read pointer of the source channel pointing to a source of the data to be transmitted after all data frames of the data to be transmitted are transmitted via the source channel.

[0045] In some embodiments of the present disclosure, the reading module is further configured to:

[0046] When it is determined that the number of source channels is different from the number of destination channels, determine corresponding destination channels through a preset connection routing table;

[0047] Read the data to be transmitted from the source channel to the corresponding destination channel.

[0048] In some embodiments of the present disclosure, the verification by the control unit of the frame header check information in the frame header includes:

[0049] Verify the frame header check information in the frame header through an auxiliary bypass, where the auxiliary bypass is independent of the data transmission path, and the auxiliary bypass has the permission to read the frame header check information and the frame tail check information.

[0050] In some embodiments of the present disclosure, the device further includes a generation unit, configured to:

[0051] Determine a frame header check code according to the frame header keyword and the timestamp when the data to be transmitted is initiated;

[0052] Fill the frame header check code into the frame header check information.

[0053] In some embodiments of the present disclosure, the device further includes:

[0054] A selection unit, configured to select a preset number of target data frames from all data frames of the data to be transmitted according to a preset granularity before the acquisition unit acquires the frame tail check information for verification;

[0055] A determination unit, configured to determine the frame tail check code according to the frame tail keyword and the target data frames;

[0056] A filling unit, configured to fill the frame tail check code into the frame tail check information.

[0057] In some embodiments of the present disclosure, the verification unit is further configured to:

[0058] Redetermine the check code to be verified according to the frame tail keyword and the target data frames;

[0059] If the check code to be verified is consistent with the frame tail check code in the frame tail check information, it is determined that the verification is passed.

[0060] A third aspect embodiment of the present disclosure provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and when the instructions are executed by the at least one processor, the at least one processor is enabled to execute the method described in the first aspect embodiment of the present disclosure.

[0061] A fourth aspect embodiment of the present disclosure provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to execute the method described in the first aspect embodiment of the present disclosure.

[0062] A fifth aspect embodiment of the present disclosure provides a chip, including one or more interface circuits and one or more processors; the interface circuit is configured to receive a signal and send the signal to the processor, and the signal includes computer instructions; when the processor executes the computer instructions, an electronic device is caused to execute the method described in the first aspect embodiment of the present disclosure.

[0063] In summary, according to the data verification method proposed by the present disclosure, the method includes generating a frame header of data to be transmitted, controlling the parallel execution of the transmission of a data frame, and verifying the frame header verification information in the frame header; the data to be transmitted includes at least a frame header, a data frame, and a frame tail, the frame header contains frame header verification information, and the frame header verification information is determined according to a frame header keyword and a dynamic variable. When a frame tail keyword of the frame tail is detected, frame tail verification information is obtained for verification; the frame tail includes frame tail verification information, and the frame tail verification information is determined according to the data frame. Whether there is an abnormality in the data to be transmitted during transmission is determined according to the verification result of the frame tail verification information. The solution of the present disclosure can parallelly execute data frame transmission and verification without modifying the data to be transmitted, and will not affect the transmission efficiency of the data to be transmitted. In addition, when performing data verification, based on the fact that the frame header verification information is determined according to the frame header keyword and the dynamic variable, and the frame tail verification information is determined according to the data frame, real-time and effective data can be obtained, improving the reliability of data verification.

[0064] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] The accompanying drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure and do not constitute an improper limitation of the present disclosure.

[0066] Figure 1 It is a flowchart of a data verification method provided by an embodiment of the present disclosure;

[0067] Figure 2A schematic diagram of a data transmission architecture provided by an embodiment of the present disclosure;

[0068] Figure 3 A schematic diagram of the composition of data to be transmitted provided by an embodiment of the present disclosure;

[0069] Figure 4 A schematic diagram of multi-channel data transmission provided by an embodiment of the present disclosure;

[0070] Figure 5 A flowchart of a data verification method provided by an embodiment of the present disclosure;

[0071] Figure 6 A schematic diagram of the interaction of a data transmission channel provided by an embodiment of the present disclosure;

[0072] Figure 7 A flowchart of a data verification method provided by an embodiment of the present disclosure;

[0073] Figure 8 A flowchart of a data verification method provided by an embodiment of the present disclosure;

[0074] Figure 9 A schematic diagram of the structure of a data verification device provided by an embodiment of the present disclosure;

[0075] Figure 10 A schematic diagram of the structure of a data verification device provided by an embodiment of the present disclosure;

[0076] Figure 11 A schematic diagram of the structure of an electronic device provided by an embodiment of the present disclosure;

[0077] Figure 12 A schematic diagram of the structure of a chip provided by an embodiment of the present disclosure. Detailed implementation manners

[0078] The embodiments of the present disclosure will be described in detail below. The examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions from beginning to end. The embodiments described below by referring to the accompanying drawings are exemplary and are intended to explain the present disclosure, but should not be construed as a limitation to the present disclosure.

[0079] In the related art, in order to achieve the accuracy of data transmission, frame delimiters are inserted at the head and tail of the data frame. For example, the frame delimiter is specified as binary 01111110. When data consistent with the frame delimiter appears inside the data frame, the zero-bit stuffing method is used to expand the frame to prevent misdetecting the real data as the frame delimiter. During frame parsing, if data consistent with the frame delimiter is parsed, then the 1 binary 0 after the frame delimiter should be removed to restore the original data.

[0080] Although the above solution can verify the data security in the data transmission path to a certain extent, the frame expansion verification scheme will add invalid data to the data frame, resulting in the expansion of the data frame length and thus affecting the efficiency of the transmitted data.

[0081] Therefore, to solve the problems existing in the related art, the present disclosure proposes a data verification method. According to the data verification method proposed by the present disclosure, the method includes generating a frame header of the data to be transmitted, controlling the parallel execution of the transmission of the data frame, and verifying the frame header verification information in the frame header; the data to be transmitted at least includes the frame header, the data frame, and the frame tail, the frame header contains frame header verification information, the frame header verification information is determined according to the frame header keyword and the dynamic variable, and when the frame tail keyword of the frame tail is detected, the frame tail verification information is obtained for verification; the frame tail includes frame tail verification information, the frame tail verification information is determined according to the data frame, and whether there is an abnormality in the data to be transmitted during transmission is determined according to the verification result of the frame tail verification information.

[0082] This solution can execute the data frame transmission and verification in parallel, that is, it does not need to modify the data to be transmitted and does not affect the transmission of the data to be transmitted. In addition, when performing data verification, based on the frame header verification information determined according to the frame header keyword and the dynamic variable, and determining the frame tail verification information according to the data frame, real-time and effective data can be obtained, improving the reliability of data verification.

[0083] The embodiments of the present disclosure are not exhaustive, but only schematic of some embodiments, and do not constitute a specific limitation on the protection scope of the present disclosure. Without contradiction, each step in a certain embodiment can be implemented as an independent embodiment, and the steps can be combined arbitrarily. For example, the solution after removing some steps in a certain embodiment can also be implemented as an independent embodiment, and the order of the steps in a certain embodiment can be exchanged arbitrarily. In addition, the optional implementation methods in a certain embodiment can be combined arbitrarily; in addition, the embodiments can be combined arbitrarily. For example, some or all of the steps of different embodiments can be combined arbitrarily, and a certain embodiment can be combined arbitrarily with the optional implementation methods of other embodiments.

[0084] In each embodiment of the present disclosure, if there is no special description and logical conflict, the terms and / or descriptions between the embodiments are consistent and can be referenced to each other. The technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationships.

[0085] The terms used in the embodiments of the present disclosure are only for the purpose of describing specific embodiments, and are not intended to limit the present disclosure.

[0086] In the embodiments of the present disclosure, unless otherwise specified, elements expressed in the singular form, such as "a", "an", "the", "above-mentioned", "said", "aforementioned", "this", etc., may mean "one and only one", or may also mean "one or more", "at least one", etc. For example, in the case of using articles such as "a", "an", "the" in English translation, the noun after the article can be understood as a singular expression form or a plural expression form.

[0087] In some embodiments, terms such as "in response to...", "in response to determining...", "in the case of...", "when...", "while...", "if...", "in the event that..." can be used interchangeably.

[0088] In some embodiments, terms such as "greater than", "greater than or equal to", "not less than", "more than", "more than or equal to", "not fewer than", "higher than", "higher than or equal to", "not lower than", "above", etc. can be used interchangeably, and terms such as "less than", "less than or equal to", "not greater than", "fewer than", "fewer than or equal to", "not more than", "lower than", "lower than or equal to", "not higher than", "below", etc. can be used interchangeably.

[0089] The prefixes such as "first", "second", etc. in the embodiments of the present disclosure are only used to distinguish different described objects, and do not constitute limitations on the position, order, priority, quantity, content, etc. of the described objects. The description of the described objects refers to the description in the context of the claims or embodiments, and should not constitute unnecessary limitations due to the use of prefixes.

[0090] In the embodiments of the present disclosure, "a plurality of" means two or more.

[0091] In the embodiments of the present disclosure, terms such as "import", "input", "read in" can be used interchangeably.

[0092] In some embodiments, a device, etc. can be interpreted as physical or virtual, and its name is not limited to the name recorded in the embodiments. Terms such as "device", "equipment", "device", "circuit", "network element", "node", "function", "unit", "section", "system", "network", "chip", "chip system", "entity", "subject", etc. can be used interchangeably.

[0093] In some embodiments, terms such as "terminal", "terminal device", "user equipment (UE)", "user terminal", "mobile station (MS)", "mobile terminal (MT)", subscriber station, mobile unit, subscriber unit, wireless unit, remote unit, mobile device, wireless device, wireless communication device, remote device, mobile subscriber station, access terminal, mobile terminal, wireless terminal, remote terminal, handset, user agent, mobile client, client, etc. may be used interchangeably.

[0094] Figure 1 The figure is a flowchart of a data verification method provided by an embodiment of the present disclosure. This method can be applied to application scenarios such as chips, processors, etc. For example, it can be executed by a terminal integrated with a data verification function or a processor in the terminal, or by other devices suitable for data verification, which is not limited in the present disclosure. As Figure 1 shown, the data verification method includes steps 101-103.

[0095] In step 101, after generating the frame header of the data to be transmitted, control the parallel execution of the transmission of the data frame and the verification of the frame header verification information in the frame header; the data to be transmitted includes at least the frame header, the data frame, and the frame tail, the frame header contains frame header verification information, and the frame header verification information is determined according to the frame header keyword and the dynamic variable.

[0096] As Figure 2 shown, Figure 2A schematic diagram of a data transmission architecture provided by an embodiment of the present disclosure. In a digital communication terminal system, when the antenna receives a signal from the base station, it needs to go through the processing of radio frequency, base station, physical layer, and protocol stack in sequence before being received by the user layer. Among them, the baseband is the core digital processing part, which will perform processing such as descrambling, despreading, demodulating, and decoding on the physical channel data. If different nodes of the baseband can be collected, or the configuration information of multiple cores can be captured, it can help with joint debugging and positioning, thereby accelerating the design and development cycle. To undertake the above-mentioned maintenance and measurement requirements, the maintenance and measurement data transmission is responsible for packing the maintenance and measurement information collected from the baseband and transmitting it to the memory chip through the on-chip bus, that is, double data rate SDRAM (DDR), or PCIE, for background data analysis. The data verification method provided by the embodiment of the present disclosure can be applied to the data transmission process in the above scenario, and determine whether there are abnormalities such as data being tampered with or lost during the transmission process through the verification of data transmission.

[0097] It should be noted that, in addition to being applied to Figure 2 the data transmission scenario shown, it can also be applied to wired or wireless transmission scenarios of other architectures. Specifically, the embodiments of the present disclosure do not limit this.

[0098] When generating the data to be transmitted, the frame header information of the data packet to be transmitted is generated at the same time, as Figure 3 shown, Figure 3 A schematic diagram of the composition of a data packet to be transmitted provided by an embodiment of the present disclosure is shown. The data to be transmitted in the data transmission path includes a frame header, a data frame, and a frame tail. Among them, the frame header includes a frame header keyword, a dynamic variable, and frame header verification information, where the frame header verification information is calculated based on the frame header keyword and the dynamic variable. The calculation method can adopt, but is not limited to, any algorithm in the related art, such as the cyclic redundancy check (CRC) algorithm.

[0099] In some embodiments, in order to achieve the pure hardening implementation of the chip, when controlling the parallel execution of the transmission of the data frame and the verification of the frame header verification information in the frame header, only an auxiliary bypass branch needs to be added to the path for transmitting the data to be transmitted to achieve the parallel execution of data transmission and data verification. While based on the path for transmitting the data to be transmitted, the auxiliary bypass extracts the data (frame header verification information and frame tail verification information) and sends the data into the auxiliary bypass for verification, without modifying the content of the data packet and without affecting the function of the path for transmitting the data to be transmitted.

[0100] In some embodiments, in order to improve the verification efficiency, when sending the data into the auxiliary bypass for verification, the data (frame header verification information and frame tail verification information) can be verified based on the instantiated CRC module.

[0101] Step 102, when the frame tail keyword of the frame tail is detected, obtain the frame tail check information for verification; the frame tail includes frame tail check information, and the frame tail check information is determined according to the data frame.

[0102] In the embodiments of the present disclosure, the transmission of the data to be transmitted and the data verification are performed in parallel at the same time, rather than performing data verification after the transmission of the data to be transmitted is completed.

[0103] When the frame tail (frame tail keyword) of the data to be transmitted is detected, all or part of the data frames in the data frame, as well as the frame tail check information, will be captured for verification.

[0104] For the verification, any method in the related art can be referred to, so it will not be elaborated one by one here.

[0105] Step 103, determine whether there is an abnormality in the transmission of the data to be transmitted according to the verification result of the frame tail check information.

[0106] In some embodiments, if the check information calculated by the verification is consistent with the frame tail check information, it indicates that the frame tail detection is successful, and there are no abnormalities such as tampering or loss in the transmission of the data to be transmitted, and it is trustworthy data. If the check information calculated by the verification is inconsistent with the frame tail check information, it indicates that the frame tail detection fails, indicating that there are abnormalities such as tampering or loss in the transmission of the data to be transmitted, and it is untrustworthy data.

[0107] For untrustworthy data, the following methods can be used but are not limited to:

[0108] Method 1, when the frame head check information or the frame tail check information fails, discard or temporarily store the data packet to be transmitted as a whole;

[0109] Method 2: Retain the analysis of the error frame on the premise of not affecting the hardware transmission.

[0110] The above two processing methods are exemplary descriptions, and are not the only processing methods for untrustworthy data, and can also be flexibly set according to the actual data transmission requirements.

[0111] According to the data verification method proposed by the present disclosure, the method includes generating a frame header of the data to be transmitted, controlling the parallel execution of the transmission of the data frame, and verifying the frame header verification information in the frame header; the data to be transmitted at least includes the frame header, the data frame, and the frame tail, the frame header contains frame header verification information, the frame header verification information is determined according to the frame header keyword and the dynamic variable, when the frame tail keyword of the frame tail is detected, obtaining the frame tail verification information for verification; the frame tail includes frame tail verification information, the frame tail verification information is determined according to the data frame, and it is determined whether there is an abnormality in the transmission of the data to be transmitted according to the verification result of the frame tail verification information. The solution of the present disclosure enables the parallel execution of data frame transmission and verification, that is, it does not require modifying the data to be transmitted and does not affect the transmission of the data to be transmitted. In addition, when performing data verification, based on the fact that the frame header verification information is determined according to the frame header keyword and the dynamic variable, and the frame tail verification information is determined according to the data frame, real-time and effective data can be obtained, improving the reliability of data verification.

[0112] In some embodiments, when executing the transmission of the data frame, the transmission of the data to be transmitted is performed through a data transmission path, where the data transmission path includes a source channel and a destination channel, and the number of source channels is the same as or different from the number of destination channels. As Figure 4 shown, Figure 4 FIG. shows a schematic diagram of multi-channel data transmission provided by an embodiment of the present disclosure. Figure 4 An example is given where the number of source channels is different from the number of destination channels, but it is not used to limit the scenario where the number of source channels is the same as the number of destination channels.

[0113] The data transmission path is divided into a source channel and a destination channel. The source channel carries the data to be transmitted to be sent, and the destination channel carries the data to be transmitted transmitted through the data transmission channel.

[0114] For the case where the number of source channels and the number of destination channels are not equal (different), when multiple source channels transmit the data to be transmitted simultaneously, a routing mechanism is adopted inside the data transmission channel for transmission at the channel granularity, that is, a connectivity routing table is pre-configured, and the connectivity routing table records the destination channels that each source channel needs to connect to. For example, source channel 0 and source channel 1 connect to destination channel 0, source channel 2 and source channel 3 connect to destination channel 1; or, source channel 0 and source channel 2 connect to destination channel 0, source channel 1 and source channel 3 connect to destination channel 1, etc. Figure 4 This is for exemplary illustration, rather than limiting the specific number of source channels and destination channels, and the connectivity settings between the source channels and the destination channels.

[0115] Figure 5 Further shows a flowchart of a data verification method proposed by the present disclosure. Based on Figure 5For the illustrated embodiment, a further explanation of the transmission of the data to be transmitted through the data transmission path Figure 5 may include the following steps:

[0116] Step 201: Control the data to be transmitted to be written into the source channel and update the write pointer of the source channel.

[0117] As Figure 6 shown, Figure 6 FIG. is an interaction schematic diagram of a data transmission channel provided by an embodiment of the present disclosure. When the data source generates data to be transmitted, the data to be transmitted is written into the source channel, and the write pointer of the source channel is updated.

[0118] Step 202: In response to the update of the write pointer of the source channel, read the data to be transmitted from the source channel to the destination channel, and update the write pointer of the source channel pointing to the destination channel.

[0119] In some embodiments of the present disclosure, when reading the data to be transmitted from the source channel to the destination channel, in the case where it is determined that the number of source channels is different from the number of destination channels, the corresponding destination channel is determined through a preset connection routing table, and the data to be transmitted is read from the source channel to the corresponding destination channel. For the description of determining the corresponding destination channel based on the connection routing table, reference can be made to Figure 4 and Figure 4 the relevant descriptions, so it will not be elaborated here.

[0120] Step 203: After detecting that the data to be transmitted in the destination channel has been read, update the read pointer of the destination channel.

[0121] Step 204: After all data frames of the data to be transmitted are transmitted through the source channel, update the read pointer of the source channel pointing to the source of the data to be transmitted.

[0122] After the data transmission path detects the pointer update, it starts to sort out the data in the channel, including the following steps:

[0123] Stp1: Generate frame header information, add timestamp information and frame header CRC check content.

[0124] Stp2: When the data to be transmitted is too large, after automatic unpacking, start moving the data to be transmitted from the source channel to the destination channel. When unpacking, unpacking can be performed according to a fixed frame length, and the fixed frame length is the same as the length of the data packet processed in the analysis platform.

[0125] Stp3: After the destination channel has received all the data of a data frame, the source channel updates the write pointer to the destination channel. Meanwhile, in order to let the data source sense that the data to be transmitted has been moved away, the source channel also needs to update the read pointer to the data source.

[0126] Stp4: If a data frame cannot transmit all the data sources, repeat according to Stp1-3 until the data transmission is completed.

[0127] Stp5: The parsing platform extracts the data frame for parsing and updates the read pointer of the destination channel, so that the data transmission path can sense that the data to be transmitted has been read.

[0128] In some embodiments of the present disclosure, when verifying the frame header check information in the frame header, it is implemented but not limited to verifying the frame header check information in the frame header through an auxiliary bypass. The auxiliary bypass is independent of the data transmission path, and the auxiliary bypass has the permission to read the frame header check information and the frame tail check information. Please continue to refer to Figure 3 In the embodiments of the present disclosure, the chip is realized in pure hardening. When performing verification based on the auxiliary bypass, the CRC algorithm can be used. Since the CRC algorithm has a mature algorithm model and implementation code, during the design and development process, only a bypass branch needs to be added to the data transmission path to extract data (the check codes in the frame header check bits and the frame tail check bits), and the check codes in the frame header check bits and the frame tail check bits are sent to the instantiated CRC module for verification, without modifying the content of the data packet to be transmitted and without affecting the function of the main path (data transmission path).

[0129] Figure 7 Further shows a flowchart of a data verification method proposed by the present disclosure. Based on Figure 7 the embodiments shown, for a further explanation of the frame header of the data to be transmitted, Figure 7 it may include the following steps:

[0130] Step 301, determine the frame header check code according to the frame header keyword and the timestamp when the data to be transmitted is initiated.

[0131] Add a frame header check bit (CRC check bit) to the frame header. The frame header CRC check content is all the information of the frame header (including the frame header keyword and the timestamp when the data to be transmitted is initiated).

[0132] In the embodiments of the present disclosure, since the CRC check is an auxiliary bypass and does not affect the generation of the normal frame header in the data transmission path, as the frame header in the data transmission path is generated.

[0133] Step 302, fill the frame header check code into the frame header check information.

[0134] The CRC check result in the auxiliary bypass will also be generated simultaneously and filled into the CRC position of the frame header (the frame header check information of the frame header check bit).

[0135] In some embodiments, Figure 8 The flowchart of a data verification method proposed by the present disclosure is further shown, and the method further includes:

[0136] Step 401, select a preset number of target data frames from all data frames of the data to be transmitted according to a preset granularity.

[0137] The preset granularity refers to the size of the data frame used when calculating the frame tail check code, which can be the entire content of all data frames, or partial data frame content selected at a preset interval. It should be noted that the specific number of the preset number is not limited in the embodiments of the present disclosure and can be set according to the computing resources of the chip.

[0138] Step 402, determine the frame tail check code according to the frame tail keyword and the target data frame.

[0139] Step 403, fill the frame tail check code into the frame tail check information.

[0140] At the end of a data frame, a frame tail will be generated, starting with the flag field frame tail keyword, and at the same time, the CRC check result of the data frame part will be filled. Similar to Figure 7 the frame header CRC, the frame tail CRC will perform CRC calculation on the extraction of the data frame (target data frame) in the auxiliary bypass, which does not affect the transmission of the normal data frame content. As the frame tail is generated, the CRC check result will also be generated simultaneously and filled into the CRC position of the frame tail (frame tail check information).

[0141] In some embodiments of the present disclosure, the obtaining the frame tail check information for verification includes: re-determining the check code to be verified according to the frame tail keyword and the target data frame. If the check code to be verified is consistent with the frame tail check code in the frame tail check information, it is determined that the verification is passed and the data is trustworthy; if the check code to be verified is inconsistent with the frame tail check code in the frame tail check information, it is determined that the verification fails and the data is untrustworthy.

[0142] The verification method for the frame header check information is the same as that for the frame tail check information, and will not be elaborated here.

[0143] It should be noted that during a data transmission process, if the frame header check information fails to pass the verification or the frame tail check information fails to pass the verification, or both the frame header check information and the frame tail check information fail to pass the verification, it can be determined that the data to be transmitted in this transmission is untrustworthy data.

[0144] The method provided by the embodiments of the present disclosure can achieve the following beneficial effects:

[0145] 1. The embodiments of the present disclosure do not rewrite the data frame and generate check information by using an auxiliary bypass, which can be applied to general hardware accelerators.

[0146] 2. The embodiments of the present disclosure only require the software to be able to correctly parse the frame header information, and the subsequent data is completely a real data frame, without additional overhead, and can obtain real-time and effective data to the greatest extent.

[0147] 3. The embodiments of the present disclosure do not expand the frame. Therefore, there is no problem of adding invalid data to the data frame, which will cause the length of the data frame to expand, thus affecting the efficiency of transmitting data, and at the same time causing waste of hardware cache.

[0148] Corresponding to the above data verification method, the present disclosure also proposes a data verification device. Since the device embodiments of the present disclosure correspond to the above method embodiments, for the details not disclosed in the device embodiments, reference may be made to the above method embodiments, and the present disclosure will not elaborate further.

[0149] Figure 9 FIG. is a schematic structural diagram of a data verification device 900 provided by the embodiments of the present disclosure. The data verification device includes:

[0150] A control unit 51, configured to generate a frame header of data to be transmitted, then control the parallel transmission of the data frame, and verify the frame header check information in the frame header; the data to be transmitted includes at least the frame header, the data frame, and the frame tail, the frame header contains frame header check information, and the frame header check information is determined according to the frame header keyword and the dynamic variable;

[0151] An acquisition unit 52, configured to acquire and verify the frame tail check information when detecting the frame tail keyword of the frame tail; the frame tail includes frame tail check information, and the frame tail check information is determined according to the data frame;

[0152] A verification unit 53, configured to determine whether there is an abnormality in the transmission of the data to be transmitted according to the verification result of the frame tail check information.

[0153] According to the data verification device proposed by the present disclosure, the device includes generating a frame header of the data to be transmitted, controlling the parallel execution of the transmission of the data frame, and verifying the frame header verification information in the frame header; the data to be transmitted at least includes the frame header, the data frame, and the frame tail, the frame header contains frame header verification information, the frame header verification information is determined according to the frame header keyword and the dynamic variable, when the frame tail keyword of the frame tail is detected, the frame tail verification information is obtained for verification; the frame tail includes frame tail verification information, the frame tail verification information is determined according to the data frame, and whether there is an abnormality in the transmission of the data to be transmitted is determined according to the verification result of the frame tail verification information. The solution of the present disclosure enables the parallel execution of data frame transmission and verification, that is, it does not require modification of the data to be transmitted and does not affect the transmission of the data to be transmitted. In addition, when performing data verification, based on the fact that the frame header verification information is determined according to the frame header keyword and the dynamic variable, and the frame tail verification information is determined according to the data frame, real-time and effective data can be obtained, improving the reliability of data verification.

[0154] Further, in a possible implementation manner of the embodiment of the present disclosure, as Figure 10 shown, the control unit controls the execution of the transmission of the data frame, including:

[0155] Executing the transmission of the data to be transmitted through a data transmission path, where the data transmission path includes a source channel and a destination channel, and the number of the source channels is the same as or different from the number of the destination channels.

[0156] Further, in a possible implementation manner of the embodiment of the present disclosure, as Figure 10 shown, the control unit 51 controls the execution of the transmission of the data frame, including:

[0157] A control module 511, configured to control the writing of the data to be transmitted into the source channel;

[0158] A first update module 512, configured to update the write pointer of the source channel;

[0159] A reading module 513, configured to read the data to be transmitted from the source channel to the destination channel in response to the update of the write pointer of the source channel;

[0160] A second update module 514, configured to update the write pointer of the source channel pointing to the destination channel;

[0161] A third update module 515, configured to update the read pointer of the destination channel after detecting that the data to be transmitted in the destination channel has been read.

[0162] Further, in a possible implementation manner of the embodiment of the present disclosure, as Figure 10 shown, the control unit 51 controlling the execution of the transmission of the data frame further includes:

[0163] A fourth update module 516, configured to update a read pointer of the source channel pointing to a data generation source of the data to be transmitted after all data frames of the data to be transmitted are transmitted via the source channel.

[0164] Further, in a possible implementation manner of the embodiment of the present disclosure, as Figure 10 shown, the reading module 513 is further configured to:

[0165] When it is determined that the number of source channels is different from the number of destination channels, determine a corresponding destination channel through a preset connection routing table;

[0166] Read the data to be transmitted from the source channel to the corresponding destination channel.

[0167] Further, in a possible implementation manner of the embodiment of the present disclosure, as Figure 10 shown, the verification of the frame header check information by the control unit 51 includes:

[0168] Verify the frame header check information in the frame header through an auxiliary bypass, where the auxiliary bypass is independent of the data transmission path, and the auxiliary bypass has the permission to read the frame header check information and the frame tail check information.

[0169] Further, in a possible implementation manner of the embodiment of the present disclosure, as Figure 10 shown, the device further includes a generation unit, configured to:

[0170] Determine a frame header check code according to the frame header keyword and the timestamp for initiating the data to be transmitted;

[0171] Fill the frame header check code into the frame header check information.

[0172] Further, in a possible implementation manner of the embodiment of the present disclosure, as Figure 10 shown, the device further includes:

[0173] A selection unit 54, configured to select a preset number of target data frames from all data frames of the data to be transmitted according to a preset granularity before the acquisition unit 52 acquires the frame tail check information for verification;

[0174] A determination unit 55, configured to determine the frame tail check code according to the frame tail keyword and the target data frames;

[0175] A filling unit 56, configured to fill the frame tail check code into the frame tail check information.

[0176] Further, in a possible implementation manner of the embodiments of the present disclosure, as Figure 10 shown, the verification unit 53 is further configured to:

[0177] re-determine the check code to be verified according to the frame tail keyword and the target data frame;

[0178] If the check code to be verified is consistent with the frame tail check code in the frame tail check information, it is determined that the verification is passed.

[0179] Since the device provided in the embodiments of the present disclosure corresponds to the methods provided in the above several embodiments, the implementation manners of the methods are also applicable to the device provided in this embodiment and will not be described in detail in this embodiment.

[0180] In the above embodiments provided by the present disclosure, the methods and devices provided by the embodiments of the present disclosure are introduced. To implement each function in the methods provided by the above embodiments of the present disclosure, an electronic device may include a hardware structure and software modules, and implement the above functions in the form of a hardware structure, software modules, or a combination of a hardware structure and software modules. A certain function among the above functions may be executed in the form of a hardware structure, software module, or a combination of a hardware structure and software module.

[0181] Figure 11 is a block diagram of an electronic device 1000 for implementing the above data verification method according to an exemplary embodiment. For example, the electronic device 1000 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0182] Referring to Figure 11 , the electronic device 1000 may include one or more of the following components: a processing component 1002, a memory 1004, a power supply component 1006, a multimedia component 1008, an audio component 1010, an input / output (I / O) interface 1012, a sensor component 1014, and a communication component 1016.

[0183] The processing component 1002 generally controls the overall operation of the electronic device 1000, such as operations associated with display, telephone call, data communication, camera operation, and recording operation. The processing component 1002 may include one or more processors 1020 to execute instructions to complete all or part of the steps of the above methods. In addition, the processing component 1002 may include one or more modules to facilitate the interaction between the processing component 1002 and other components. For example, the processing component 1002 may include a multimedia module to facilitate the interaction between the multimedia component 1008 and the processing component 1002.

[0184] The memory 1004 is configured to store various types of data to support the operation of the electronic device 1000. Examples of such data include instructions for any application or method operating on the electronic device 1000, contact data, phone book data, messages, pictures, videos, and the like. The memory 1004 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, a magnetic disk, or an optical disk.

[0185] The power supply component 1006 provides power for various components of the electronic device 1000. The power supply component 1006 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 1000.

[0186] The multimedia component 1008 includes a screen that provides an output interface between the electronic device 1000 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen can be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors can sense not only the boundaries of the touch or swipe actions but also detect the duration and pressure associated with the touch or swipe operations. In some embodiments, the multimedia component 1008 includes a front camera and / or a rear camera. When the electronic device 1000 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera can receive external multimedia data. Each of the front camera and the rear camera can be a fixed optical lens system or have focal length and optical zoom capabilities.

[0187] The audio component 1010 is configured to output and / or input audio signals. For example, the audio component 1010 includes a microphone (MIC) that is configured to receive external audio signals when the electronic device 1000 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signals can be further stored in the memory 1004 or transmitted via the communication component 1016. In some embodiments, the audio component 1010 further includes a speaker for outputting audio signals.

[0188] The I / O interface 1012 provides an interface between the processing component 1002 and a peripheral interface module, and the peripheral interface module can be a keyboard, a click wheel, buttons, etc. These buttons can include, but are not limited to: a home button, a volume button, a start button, and a lock button.

[0189] The sensor assembly 1014 includes one or more sensors for providing status assessments of various aspects for the electronic device 1000. For example, the sensor assembly 1014 can detect the on / off state of the electronic device 1000, the relative positioning of components, such as the display and keypad of the electronic device 1000, the sensor assembly 1014 can also detect a change in the position of the electronic device 1000 or a component of the electronic device 1000, the presence or absence of user contact with the electronic device 1000, the orientation or acceleration / deceleration of the electronic device 1000, and the temperature change of the electronic device 1000. The sensor assembly 1014 can include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 1014 can also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 1014 can also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0190] The communication component 1016 is configured to facilitate communication between the electronic device 1000 and other devices in a wired or wireless manner. The electronic device 1000 can access a wireless network based on communication standards, such as WiFi, 2G or 3G, 4G LTE, 5G NR (New Radio), or a combination thereof. In an exemplary embodiment, the communication component 1016 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 1016 further includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0191] In an exemplary embodiment, the electronic device 1000 can be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components for performing the above method.

[0192] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as the memory 1004 including instructions, and the above instructions can be executed by the processor 1020 of the electronic device 1000 to complete the above method for image processing. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, and an optical data storage device, etc.

[0193] Embodiments of the present disclosure also propose a non-transitory computer-readable storage medium storing computer instructions, where the computer instructions are used to cause a computer to execute the methods described in the above embodiments of the present disclosure.

[0194] For the case where the electronic device may be a chip or a chip system, reference may be made to Figure 12 the structural schematic diagram of the chip shown. Figure 12 The chip shown includes a processor 1101 and an interface 1102. Among them, the number of processors 1101 may be one or more, and the number of interfaces 1102 may be multiple.

[0195] Optionally, the chip further includes a memory 1103, and the memory 1103 is used to store necessary computer programs and data.

[0196] Those skilled in the art can also understand that the various illustrative logical blocks and steps listed in the embodiments of the present disclosure can be implemented by electronic hardware, computer software, or a combination of both. Whether such a function is implemented by hardware or software depends on the specific application and the design requirements of the entire system. Those skilled in the art can use various methods to implement the functions for each specific application, but such implementation should not be construed as exceeding the scope protected by the embodiments of the present disclosure.

[0197] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0198] In the description of this specification, the descriptions with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present disclosure. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0199] Any process or method description represented in a flowchart or otherwise described herein can be understood to represent a module, segment, or portion of code including one or more executable instructions for implementing a specific logical function or process. The scope of the preferred embodiments of the present disclosure includes additional implementations where functions may be executed not in the order shown or discussed, including in substantially simultaneous fashion according to the involved functions or in reverse order, which should be understood by those skilled in the art to which the embodiments of the present disclosure pertain.

[0200] The logic and / or steps represented in a flowchart or otherwise described herein, for example, can be considered a sequenced list of executable instructions for implementing a logical function and can be embodied specifically in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, a system including a processing module, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device. As used in this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium include the following: an electrical connection having one or more wires (control method), a portable computer diskette (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can even be paper or other suitable medium on which a program can be printed, as the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpretation, or other suitable processing as necessary, and then stored in a computer memory.

[0201] It should be understood that various parts of the embodiments of the present disclosure can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or a combination of the following techniques well known in the art can be used: discrete logic circuits having logic gates for implementing logical functions on data signals, application specific integrated circuits having appropriate combinational logic gates, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), and the like.

[0202] Those of ordinary skill in the art can understand that all or part of the steps carried out in implementing the above-described embodiment methods can be completed by instructing relevant hardware through a program. The program can be stored in a computer-readable storage medium, and when the program is executed, it includes one or a combination of the steps of the method embodiment.

[0203] In addition, each functional unit in various embodiments of the present disclosure can be integrated in a processing module, can exist physically alone for each unit, or two or more units can be integrated in one module. The above-mentioned integrated module can be implemented in the form of hardware or in the form of a software functional module. When the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. The storage medium mentioned above can be a read-only memory, a magnetic disk, an optical disc, or the like.

[0204] Although the embodiments of the present disclosure have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present disclosure.

Claims

1. A method for verifying data, characterized in that, The method includes: After generating the frame header of the data to be transmitted, controlling the parallel execution of the transmission of the data frame and the verification of the frame header verification information in the frame header; the data to be transmitted at least includes the frame header, the data frame, and the frame tail, the frame header contains frame header verification information, and the frame header verification information is determined according to the frame header keyword and the dynamic variable; When detecting the frame tail keyword of the frame tail, obtaining the frame tail verification information for verification; the frame tail includes frame tail verification information, and the frame tail verification information is determined according to the data frame; Determining whether there is an abnormality in the transmission of the data to be transmitted according to the verification result of the frame tail verification information.

2. The method according to claim 1, wherein Executing the transmission of the data frame includes: Executing the transmission of the data to be transmitted through the data transmission path, where the data transmission path includes a source channel and a destination channel, and the number of the source channels is the same as or different from the number of the destination channels.

3. The method according to claim 2, wherein The executing the transmission of the data to be transmitted through the data transmission path includes: Controlling the data to be transmitted to be written into the source channel and updating the write pointer of the source channel; In response to the update of the write pointer of the source channel, reading the data to be transmitted from the source channel to the destination channel and updating the write pointer of the source channel pointing to the destination channel; After detecting that the data to be transmitted in the destination channel is read, updating the read pointer of the destination channel.

4. The method according to claim 3, wherein The method further includes: After all data frames of the data to be transmitted are transmitted through the source channel, updating the read pointer of the source channel pointing to the source of the data to be transmitted.

5. The method according to claim 3, wherein The reading the data to be transmitted from the source channel to the destination channel includes: In the case of determining that the number of the source channels is different from the number of the destination channels, determining the corresponding destination channel through a preset connection routing table; Reading the data to be transmitted from the source channel to the corresponding destination channel.

6. The method according to claim 2, wherein The verification of the frame header verification information in the frame header includes: Verifying the frame header verification information in the frame header through an auxiliary bypass, the auxiliary bypass is independent of the data transmission path, and the auxiliary bypass has the permission to read the frame header verification information and the frame tail verification information.

7. The method according to claim 1, wherein The generating the frame header of the data to be transmitted includes: Determining the frame header verification code according to the frame header keyword and the timestamp of initiating the data to be transmitted; Filling the frame header verification code into the frame header verification information.

8. The method according to claim 1, characterized in that Before obtaining the frame tail verification information for verification, the method further includes: Selecting a preset number of target data frames from all data frames of the data to be transmitted according to a preset granularity; Determining the frame tail verification code according to the frame tail keyword and the target data frame; Filling the frame tail verification code into the frame tail verification information.

9. The method according to claim 8, wherein The obtaining the frame tail verification information for verification includes: Redetermining the verification code to be verified according to the frame tail keyword and the target data frame; If the verification code to be verified is consistent with the frame tail verification code in the frame tail verification information, determining that the verification is passed.

10. A data verification device, characterized in that, The device includes: A control unit, configured to generate a frame header of data to be transmitted, and then control the parallel execution of the transmission of the data frame and the verification of the frame header verification information in the frame header; the data to be transmitted includes at least the frame header, the data frame, and the frame tail, the frame header contains frame header verification information, and the frame header verification information is determined according to the frame header keyword and the dynamic variable; An acquisition unit, configured to acquire and verify the frame tail verification information when detecting the frame tail keyword of the frame tail; the frame tail includes frame tail verification information, and the frame tail verification information is determined according to the data frame; A verification unit, configured to determine whether there is an abnormality in the transmission of the data to be transmitted according to the verification result of the frame tail verification information.

11. An electronic device, characterized in that, Comprising: At least one processor; And A memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method according to any one of claims 1-9.

12. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to execute the method according to any one of claims 1-9.

13. A chip, characterized in that, Comprising one or more interface circuits and one or more processors; the interface circuit is configured to receive a signal and send the signal to the processor, and the signal includes computer instructions; when the processor executes the computer instructions, the chip is caused to execute the method according to any one of claims 1 to 9.

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