Coding and decoding transmission module based on national multi-channel video and coding and decoding method thereof

Abstract

The invention discloses a nationwide multi-channel video coding and decoding transmission module and a coding and decoding method thereof. The coding and decoding transmission module comprises an FPGA (Field Programmable Gate Array), a domestic processor and an interface unit, the FPGA is used for receiving a video data stream input from the outside and analyzing video information and original image data; sending the original image data to a domestic processor, and sending the video information and a received external control instruction to the domestic processor for encoding processing; receiving a compressed code stream transmitted back by the domestic processor after encoding, and outputting the compressed code stream to an external matching device; receiving a compressed code stream input from the outside, analyzing the compressed code stream according to a preset rate control strategy, and forwarding the compressed code stream to a decoding end of a domestic processor; and converting the decoded image data into a target interface protocol format, and outputting the target interface protocol format to an external display device. The invention also comprises a coding and decoding method. The invention has the advantages of low cost, abundant interfaces, good compatibility, stable optimization delay and the like.

Description

Technical Field

[0001] The present invention relates to the technical field of video encoding and decoding, and in particular to a domestic multi-channel video encoding and decoding transmission module and its encoding and decoding method. Background Art

[0002] With the continuous development of technology, the applications of in-vehicle and airborne video transmission systems have gradually increased in multiple industries. Especially in the fields of transportation, finance, public security, power, energy, education, etc., the demand for image encoding and decoding modules has become more urgent.

[0003] At present, on the one hand, most of the solutions adopted in the market are based on foreign dedicated encoding or decoding chips, which not only have high costs but also poor autonomy and controllability, increasing the risk of sanctions during use. On the other hand, most of the existing solutions are pure encoding or decoding schemes, which have limitations in usage scenarios and interfaces. That is, the existing encoding or decoding modules usually can only perform one of the operations, resulting in the need for additional hardware or software modules to complete the other operation in actual applications, which increases the complexity and cost of the system. In addition, a single encoding or decoding scheme may not be able to meet the requirements in real-time and efficient video processing applications, especially in high-resolution and high-frame-rate scenarios, where it is unable to efficiently process input and output video data simultaneously. Moreover, it cannot provide flexible operations in variable usage scenarios, especially when multiple video formats and protocols need to be processed simultaneously, and it cannot ensure the compatibility and stability of the system. Summary of the Invention

[0004] The purpose of the present invention is to overcome the above deficiencies of the prior art and provide a domestic multi-channel video encoding and decoding transmission module and its encoding and decoding method with low cost, rich interfaces, good compatibility and stability, simple circuit structure, optimized delay, and wide application range.

[0005] The technical solution of the present invention is as follows: A domestic multi-channel video encoding and decoding transmission module of the present invention includes: An FPGA is used to receive an externally input video data stream through an SDI interface or a Cameralink interface, and parse the video data stream to obtain video information and raw image data; to send the raw image data to a domestic processor, and send the video information and received external control instructions to the domestic processor for encoding processing; to receive the compressed code stream returned by the domestic processor after encoding, adapt the transmission rate of the LVDS interface according to the received rate control instruction, and output the compressed code stream to an external matching device through the LVDS interface; and to receive an externally input compressed code stream through the LVDS interface, parse the compressed code stream according to a preset rate control strategy, and forward the compressed code stream to the decoding end of the domestic processor through the SPI interface; it is also used to convert the decoded image data into a target interface protocol format and output it to an external display device; A domestic processor is used to dynamically adjust encoding parameters and select a target video source according to the received video information and external control instructions; it is also used to encode the raw image data to generate a compressed code stream, and send the compressed code stream back to the FPGA through the SPI interface; it is also used to decode the compressed code stream sent by the FPGA according to a pre-configured working mode to generate decoded image data; and send the decoded image data to the FPGA; An interface unit is used to connect various externally adapted devices.

[0006] Further, the interface unit is connected to the FPGA through a multi-channel SDI input interface via an equalizer, and is used to send an external video data stream to the FPGA; the output end of the FPGA is connected to the SDI output interface of the interface unit through a serializer, and is used to convert the image data decoded by the domestic processor into a target interface protocol format and output it to an external device; and / or, The interface unit is also connected to the FPGA through at least one Cameralink input interface via a receiver, and is used to send an external video data stream to the FPGA; the output end of the FPGA is connected to the Cameralink output interface of the interface unit through a transmitter, and is used to convert the image data decoded by the domestic processor into a target interface protocol format and output it to an external device.

[0007] Further, the FPGA is electrically connected to the interface unit through a multi-channel LVDS interface, and is used to receive an externally input compressed code stream through the LVDS interface, and output the compressed code stream encoded by the domestic processor to an external matching device through the LVDS interface.

[0008] Further, the FPGA is electrically connected to the interface unit through an RS422 interface, and is used to receive external control instructions.

[0009] Further, the FPGA is connected to the domestic processor through multiple SPI interfaces, which is used to enable the domestic processor to transmit the encoded compressed bitstream back to the FPGA through the SPI interface; it is also used to enable the FPGA to send the externally input compressed bitstream to the decoding end of the domestic processor through the SPI interface.

[0010] Further, the FPGA is connected to the domestic processor through multiple MIPI interfaces; it is used to enable the FPGA to send the original image data to the domestic processor through the MIPI interface; it is also used to enable the domestic processor to send the decoded image data to the FPGA through the MIPI interface.

[0011] Further, the FPGA is connected to the domestic processor through multiple UART serial ports, which is used to encapsulate the video information and the received external control instructions through the UART serial port protocol and send them to the domestic processor.

[0012] Further, the domestic processor uses the domestic Rockchip RK3588 chip as the processor; the interface unit includes multiple connectors.

[0013] A coding and decoding method of a domestic multi-channel video coding and decoding transmission module according to the present invention includes a coding method and a decoding method; The coding method includes the following steps: S1-1. The FPGA receives the externally input video data stream through the SDI interface or the Cameralink interface, and parses the video data stream to obtain video information and original image data; at the same time, the FPGA also receives external control instructions; S1-2. Send the original image data to the domestic processor; at the same time, send the video information and the received external control instructions to the domestic processor; S1-3. The domestic processor dynamically adjusts the coding parameters and selects the target video source according to the received video information and external control instructions; S1-4. The domestic processor encodes the original image data to generate a compressed bitstream, and sends the compressed bitstream back to the FPGA; S1-5. The FPGA adapts the transmission rate of the LVDS interface according to the received rate control instruction, and outputs the compressed bitstream to the external matching device through the LVDS interface; The decoding method includes the following steps: S2-1. The FPGA receives the externally input compressed bitstream, parses the compressed bitstream according to the preset rate control strategy, and forwards the compressed bitstream to the decoding end of the domestic processor; S2-2. The domestic processor decodes the compressed bitstream according to the pre-configured working mode to generate decoded image data; S2-3. Send the decoded image data to the FPGA; S2-4. The FPGA converts the decoded image data into the target interface protocol format and outputs it to an external display device through the SDI interface or the Cameralink interface.

[0014] Furthermore, it also includes a coding bitstream optimization method, which specifically includes the following steps: S3-1: Optimize bitstream control: Set the bitstream control mode to the fixed bitstream rate mode, and ensure the fixity of the bitstream by dynamically adjusting the image quality; S3-2: Set the intra-frame refresh parameters: Set the periodic intra-frame refresh parameters and distribute the reference frame data to each bitstream data frame; S3-3: Recoding mechanism: Set the bitstream fluctuation threshold Δ, and calculate the deviation between the current frame bitstream size and the historical sliding window average value in real time; When the deviation exceeds Δ, trigger the recoding process to make the bitstream data size smoother.

[0015] Advantages of the present invention: (1) All the chips of the entire module are designed with 100% domestic chips, with rich peripheral interfaces, and at the same time have the functions of encoding and decoding multiple videos, which can be flexibly applied according to different usage scenarios of customers; And the delay is optimized to the extreme, solving the problem of transmission picture delay; (2) Through the collaborative processing of the FPGA and the RK3588, the split transmission of control instructions and image data in the encoding and decoding process is realized, improving the system response efficiency; At the same time, using the rate adaptive mechanism of the SPI and LVDS interfaces to ensure the stability of bitstream transmission, which is suitable for real-time processing scenarios of high-resolution videos; (3) By providing SDI input / output interfaces, Cameralink input / output interfaces, LVDS interfaces, SPI interfaces, MIPI interfaces, UART serial ports, and RS422 interfaces, etc., the encoding and decoding processing of the video data stream of the entire module can be realized, and this module can support multiple video data stream formats and transmission methods, realizing flexible encoding and decoding processing. This multi-interface design greatly improves the compatibility and expandability of the module, enabling it to be widely applied to different industry requirements and device environments, ensuring efficient and stable operation in various complex scenarios. In addition, the module can encode and decode video signals simultaneously, reducing the dependence on external devices, simplifying the system architecture, improving the overall performance and reliability, and reducing the complexity and cost of system integration; (4) Through the multi-level collaborative control strategy, the bitstream smoothness can be greatly improved, effectively eliminating the transmission delay jitter caused by bitstream fluctuations and optimizing the delay stability. Description of the Drawings

[0016] Figure 1 It is a schematic diagram of the circuit connection principle of the encoding and decoding transmission module according to an embodiment of the present invention; Figure 2 It is a schematic block diagram of the encoding method according to an embodiment of the present invention; Figure 3 It is a schematic block diagram of the decoding method according to an embodiment of the present invention. Specific Embodiments

[0017] The present invention will be further described in detail below with reference to the accompanying drawings of the specification and specific embodiments.

[0018] As Figure 1 shown: A domestic multi-channel video encoding and decoding transmission module includes a processing unit, an interface unit, and a power supply system; the power supply system is used to supply power to the entire module; the processing unit includes an FPGA and a domestic processor, the FPGA is used to complete video preprocessing and data forwarding, and the domestic processor is used to perform encoding and decoding processing on video data; the interface unit includes at least three connectors, namely a first connector, a second connector, and a third connector.

[0019] The encoding and decoding transmission module of this embodiment uses an LPDDR4 memory with a board-mounted capacity of 8GB, provides a board-mounted EMMC memory of 128GB, and has at least 1 HDMI display interface, 4 SDI video inputs, 1 SDI video output, 1 Cameralink video input, 1 Cameralink video output, 4 LVDS data outputs, 2 LVDS data inputs, and 1 gigabit network interface.

[0020] In this embodiment, the power supply system accesses a 12V voltage through the first connector, and is converted into the required voltage by a soft-start over-current over-voltage protection circuit and a DC / DC conversion chip to supply power to the FPGA and the processor.

[0021] In this embodiment, a domestic Rockchip RK3588 processor is used as the main control chip. RK3588 is a high-end general-purpose SoC using 8nm process technology. The CPU adopts an octa-core architecture of four-core A76 and four-core A55, the GPU adopts MailG610 MP4, integrates a 6TOPS independent NPU, and supports four-channel LPDDR4 / 5, effectively ensuring the performance output of the RK3588 chip. RK3588 is also very prominent in video encoding and decoding, supporting the hard encoding and decoding of 8K videos, with a maximum support for decoding and output of 8K@60fps, which can provide stable and high-definition pictures for video applications. RK3588 uses an independent hardware decoder, with higher decoding efficiency, which can effectively reduce power consumption and does not occupy CPU resources, allowing the CPU to continue to process other applications, ensuring performance. In addition, RK3588 supports LPDDR4X memory particles, and the operating memory adopts a four-channel design, which can fully guarantee the performance of the RK3588 platform. The powerful computing power of RK3588 itself can be used for post-processing of the data collected by the camera to achieve image optimization processing, stitching processing, overlay processing, etc.

[0022] The RK3588 processor integrates 4 16-bit DDR channels, supports LPDDR4 / LPDDR4X / LPDDR5, and the maximum supported capacity is 32GB. To meet the requirements of localization and environmental adaptability, etc., in this embodiment, domestic Jingcun's RS1G32LO4D2BDS-46IT board-mounted memory particles are selected, with a bit width of 32 bits, a capacity of 32Gbit, using a dual-channel 64-bit LPDDR4 design, with 1 memory chip used for each channel, a total of 2 chips are designed, and the total capacity is 8GB.

[0023] In this embodiment, Jiangbo Long's FEMDRW0128G-88A19 board-mounted EMMC is selected as the memory, with a capacity of 128GB, providing necessary system and application program files for RK3588, supporting the EMMC5.1 specification, and having the characteristics of high performance, small size, large capacity, low power consumption, etc., making it the best embedded solution for industrial-grade platforms. It has a power-off protection function, which can ensure the security of system data in the event of an accidental power-off.

[0024] In this embodiment, the RGMII interface of the RK3588 processor is connected to the first connector through a gigabit Ethernet chip, providing 1 gigabit Ethernet, supporting 1000 / 100Mbps auto-negotiation. The gigabit Ethernet chip design selects the domestic Yutai Microelectronics YT8521SH gigabit Ethernet PHY chip to implement the function of converting the RGMII of the RK3588 processor to a gigabit Ethernet port.

[0025] In this embodiment, the HDMI display interface of the RK3588 processor is connected to the third connector via the HDMI interface protection circuit. This embodiment reserves one HDMI display interface, which is brought out from the HDMI function pin of the RK3588 chip and supports the HDMI 2.1 protocol. Since it is an external connector, the HDMI interface protection circuit is used to protect the chip interface.

[0026] In this embodiment, due to the functional requirements of the codec transmission module, multiple SDI interface inputs and one Cameralink input must be designed, but the video input interface of the RK3588 processor cannot support direct video input in the current technical protocol. Therefore, this embodiment uses FPGA to complete the video data format conversion and interface design, and preferably uses Fudan Micro's JFM7K325T as the FPGA chip for the domestically produced video codec transmission module. In addition, the FPGA designs 4GB of DDR3 memory, and selects 8 pieces of memory particles launched by Tsinghua Unigroup to form 4GB of DDR3 memory. The memory particle model is SCB13H4G800AF-11MI. The FPGA is also equipped with a Flash chip, for example, a 16MB capacity of EFM25F128A is used to store the FPGA configuration file.

[0027] In this embodiment, the SDI video signal output by the external device is connected to the codec transmission module via the SDI input interface of the second connector, and further connected to the GTH port of the FPGA via the equalizer of the codec transmission module. The SDI video signal input by the codec transmission module uses the equalizer for signal compensation. After processing by the equalizer, the SDI video signal has improved signal quality and is suitable for long-distance transmission. The high-speed signal output after the equalizer is input to the FPGA through the GTH port of the FPGA. The FPGA uses its built-in deserializer to perform deserialization processing to convert the serial signal into a parallel signal. The equalizer model is preferably TI's LMH0384.

[0028] In this embodiment, the FPGA's GTH port is connected to the SDI output interface of the second connector via a serial driver. Specifically, the SDI video signal output by the codec transmission module is amplified by the serial driver. The FPGA's GTH port outputs a high-speed SDI serial signal to the serial driver, which amplifies the signal before transmitting it to the external device via the second connector. The serial driver model used is the TI LMH0302.

[0029] In this embodiment, the Cameralink signal video output by the external device is accessed to the encoding and decoding transmission module through the Cameralink input interface of the second connector, and further connected to the FPGA through the receiver of the encoding and decoding transmission module. The receiver is a decoding chip, which is used to convert the input Cameralink signal video in video format, decode the high-speed serial LVDS signal into parallel TTL data to the FPGA, and transmit it to the RK3588 processor. The decoding chip GM8284DD of Chengdu Guoteng is selected. As the receiving part in video / image transmission, the function achieved is to decode the high-speed serial LVDS signal into parallel TTL data and complete the data decoding function. This device can decode 4 pairs of serial LVDS differential signals into 28-bit parallel data output under the action of the clock signal.

[0030] In this embodiment, the output end of the FPGA is connected to the Cameralink output interface of the first connector through the transmitter. The transmitter is an encoding chip, which is used to encode the parallel TTL data output by the FPGA into a high-speed serial LVDS signal to the first connector to achieve fast and reliable signal transmission. This device can convert 28-bit parallel data into 4 pairs of serial LVDS differential signals and output 1 path of LVDS differential clock signal in parallel at the same time.

[0031] In this embodiment, the four LVDS output interfaces of the FPGA are electrically connected to the second connector; or the output end of the FPGA is electrically connected to the second connector through the LVDS driver chip. The encoding and decoding transmission module has 4 LVDS output interfaces to transmit the compressed bitstream. The LVDS differential signal is directly output from the pin of the FPGA. To protect the FPGA, an LVDS driver chip is added in the connection with the second connector, and the single-ended signal from the FPGA pin is converted into a differential signal and output to the second connector. The LVDS driver chip MS90C031 of Ruimeng Technology is selected.

[0032] In this embodiment, the second connector is electrically connected to the two LVDS input interfaces of the FPGA; or the second connector is electrically connected to the input end of the FPGA through the LVDS receiving chip. The encoding and decoding transmission module has 2 LVDS input interfaces for receiving the externally input compressed bitstream. To protect the FPGA, the external differential LVDS signal is converted into a single-ended signal after accessing the LVDS receiving chip and then accessed to the FPGA. The LVDS receiving chip MS90C032 of Ruimeng Technology is selected.

[0033] In this embodiment, the FPGA is electrically connected to the second connector through the RS422 interface chip, which is used to receive external control instructions and for image control and image feedback. The RS422 interface chip HT3490E of Haitianxin Technology is selected.

[0034] In this embodiment, the encoding and decoding transmission module also reserves a GTX interface, and this function can be implemented according to the actual usage scenario of the user and specific protocol requirements. That is, the GTX interface of the FPGA is electrically connected to the second connector.

[0035] In this embodiment, the JTAG interface of the FPGA is electrically connected to the first connector. The FPGA also provides a test interface connected to the first connector for delay testing.

[0036] In this embodiment, the RK3588 processor is electrically connected to the FPGA through no less than four SPI interfaces for input and output of compressed bitstreams. The RK3588 processor is electrically connected to the FPGA through one IIC interface to implement functions such as parameter configuration and device initialization of the FPGA and the RK3588 processor. The RK3588 processor is electrically connected to the FPGA through 2 GPIO interfaces for interrupt and reset of the RK3588 processor to read the bitstream data in the FPGA through the SPI interface. The RK3588 processor is electrically connected to the FPGA through 2 UART serial ports. One of them is used for serial port debugging of the core board where the RK3588 processor is located, and the other is used for communication with the FPGA, so that the video information obtained by the FPGA and the received external control instructions are encapsulated through the UART serial port protocol and sent to the RK3588 processor.

[0037] In this embodiment, the RK3588 processor is connected to the input end of the FPGA through 2 MIPI output interfaces, and is also connected to the output end of the FPGA through 4 MIPI input interfaces. It is used to enable the FPGA to send the original image data to the RK3588 processor through the MIPI input interface of the RK3588; it is also used to enable the RK3588 processor to send the decoded image data to the FPGA through the MIPI output interface.

[0038] In this embodiment, the RK3588 processor is connected to an indicator light through a GPIO interface for functional indication. The RK3588 processor is also connected to a temperature sensor through another IIC interface. The number of temperature sensors can be multiple, mainly used to detect the working temperature of the circuit board.

[0039] As Figure 2 shown: The encoding method of the encoding and decoding transmission module in this embodiment includes the following steps: S101. The FPGA receives the video data stream input by an external device through an SDI interface or a Cameralink interface, such as a camera interface; parses the video data stream to obtain video information and original image data; the video information includes resolution, interlaced / progressive scanning mode; at the same time, the FPGA receives external control instructions through an RS422 interface; S102. Send the original image data to RK3588 through the MIPI interface; meanwhile, encapsulate the video information and the external control instructions received through the RS422 interface according to the UART serial protocol and send them to the control end of RK3588. S103. RK3588 dynamically adjusts the encoding parameters and selects the target video source according to the received video information and external control instructions; the encoding parameters include bit rate, frame rate, and encoding format. S104. RK3588 encodes the original image data to generate a compressed bitstream and sends the compressed bitstream back to the FPGA through the SPI interface. S105. The FPGA adapts the transmission rate of the LVDS interface according to the rate control instructions received through the RS422 interface and outputs the compressed bitstream to the downstream device through the LVDS interface.

[0040] As Figure 3 shown: The decoding method of the encoding and decoding transmission module in this embodiment includes the following steps: S201. The FPGA receives the externally input compressed bitstream through the LVDS interface, parses the compressed bitstream according to the preset rate control strategy, and forwards the compressed bitstream to the decoding end of RK3588 through the SPI interface. S202. RK3588 decodes the compressed bitstream according to the pre-configured working mode to generate the decoded image data; the working mode includes resolution adaptation, color space conversion, and output format selection. S203. Send the decoded image data to the input end of the FPGA through the MIPI DSI interface. S204. The FPGA converts the decoded image data into the target interface protocol format and outputs it to an external display device, such as a monitor, through the SDI interface or the Cameralink interface.

[0041] In this embodiment, through the collaborative processing of the FPGA and RK3588, the separate transmission of control instructions and image data in the encoding and decoding process is realized, improving the system response efficiency; meanwhile, the rate adaptation mechanism of the SPI and LVDS interfaces is used to ensure the stability of the bitstream transmission, which is suitable for real-time processing scenarios of high-resolution videos.

[0042] In this embodiment, during the video bitstream transmission process, if there are significant differences in the sizes of the encoded bitstream data packets for each frame, it will lead to a non-uniform distribution characteristic of the transmission delay of the data packets in the transmission channel. The specific manifestation is as follows: there is a large timing jitter in the time window for the receiving end to obtain a complete single-frame bitstream, which in turn causes a non-uniform interval in the output timing of the decoded image. The intuitive reflection of this phenomenon on the display terminal is that the picture delay shows periodic fluctuations (i.e., the delay peak and valley appear alternately), seriously disrupting the stability of the display timing. Especially in the transmission scenario with limited bandwidth, due to the increased restrictive effect of the channel capacity constraint on the data packet transmission rate, the above-mentioned timing jitter effect will be further amplified, resulting in the difficulty of meeting the transmission requirements of high-real-time application scenarios for the delay time index.

[0043] For scenarios with limited bandwidth and high requirements for delay time, in this embodiment, through optimizing the bitstream control, a series of strategies are adopted, such as setting intra-frame refresh parameters, advanced frame configuration, SliceSplit, and re-encoding mechanism, etc., and finally a smooth encoding method is achieved. Through these optimizations, the average nature of the bitstream is ensured, and the size of each P frame is made as close as possible, so that the time consumed for the transmission of each frame of bitstream data is as consistent as possible. Therefore, this embodiment provides a video encoding optimization method for the codec transmission module, which realizes the smoothing of the encoded bitstream through a multi-level bitstream control strategy, specifically including the following steps: S301: Optimize the bitstream control: Set the bitstream control mode to the fixed bitstream rate mode, and ensure the fixity of the bitstream by dynamically adjusting the image quality; S302: Set the intra-frame refresh parameters: Set the periodic intra-frame refresh parameters, and distribute the reference frame data to each bitstream data frame; S303: Re-encoding mechanism: Set the bitstream fluctuation threshold Δ, and calculate the deviation amount between the current frame bitstream size and the historical sliding window mean value in real time; when the deviation amount exceeds Δ, trigger the re-encoding process, so as to make the bitstream data size relatively smooth.

[0044] Through the above multi-level collaborative control strategy, this embodiment can greatly improve the bitstream smoothness, effectively eliminate the transmission delay jitter caused by the bitstream fluctuation, and optimize the delay stability.

[0045] In summary, on the one hand, the present invention performs video encoding and decoding through domestic chips, reducing the cost; on the other hand, it has rich external video input and output interfaces, can provide higher flexibility and compatibility, support the connection of various different types of video signals and devices, and can be flexibly applied according to different usage scenarios; and greatly improves the bitstream smoothness and optimizes the video transmission delay.

[0046] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In the description of this application, "a plurality of" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0047] Although the embodiments of this application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting this application. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of this application.

Claims

1. A domestic multi-channel video encoding, decoding and transmission module, characterized in that Including: An FPGA, configured to receive an externally input video data stream through an SDI interface or a Cameralink interface, and parse the video data stream to obtain video information and raw image data; configured to send the raw image data to a domestic processor, and send the video information and the received external control instructions to the domestic processor for encoding processing; Configured to receive the compressed bitstream returned by the domestic processor after encoding, adapt the transmission rate of the LVDS interface according to the received rate control instruction, and output the compressed bitstream to an external matching device through the LVDS interface; And configured to receive an externally input compressed bitstream through the LVDS interface, parse the compressed bitstream according to a preset rate control strategy, and forward the compressed bitstream to the decoding end of the domestic processor through the SPI interface; also configured to convert the decoded image data into a target interface protocol format and output it to an external display device; A domestic processor, configured to dynamically adjust encoding parameters and select a target video source according to the received video information and external control instructions; also configured to encode the raw image data to generate a compressed bitstream, and send the compressed bitstream back to the FPGA through the SPI interface; also configured to decode the compressed bitstream sent by the FPGA according to a pre-configured working mode to generate decoded image data; and send the decoded image data to the FPGA; An interface unit, configured to connect various externally adapted devices.

2. The multi-channel video encoding, decoding and transmission module based on domestic products according to claim 1, wherein The interface unit is connected to the FPGA through a multi-channel SDI input interface via an equalizer, and is configured to send an external video data stream to the FPGA; The output end of the FPGA is connected to the SDI output interface of the interface unit through a serializer, and is configured to convert the image data decoded by the domestic processor into a target interface protocol format and output it to an external device; and / or, The interface unit is also connected to the FPGA through at least one Cameralink input interface via a receiver, and is configured to send an external video data stream to the FPGA; The output end of the FPGA is connected to the Cameralink output interface of the interface unit through a transmitter, and is configured to convert the image data decoded by the domestic processor into a target interface protocol format and output it to an external device.

3. The multi-channel video encoding, decoding and transmission module based on domestic components according to claim 1, characterized in that The FPGA is electrically connected to the interface unit through a multi-channel LVDS interface, and is configured to receive an externally input compressed bitstream through the LVDS interface, and output the compressed bitstream encoded by the domestic processor to an external matching device through the LVDS interface.

4. The multi-channel video encoding, decoding and transmission module based on domestic products according to claim 1, wherein, The FPGA is electrically connected to the interface unit through an RS422 interface, and is configured to receive external control instructions.

5. The multi-channel video encoding, decoding and transmission module based on domestic products according to claim 1, wherein The FPGA is connected to the domestic processor through a multi-channel SPI interface, and is configured to enable the domestic processor to send the encoded compressed bitstream back to the FPGA through the SPI interface; also configured to enable the FPGA to send the externally input compressed bitstream to the decoding end of the domestic processor through the SPI interface.

6. The multi-channel video encoding, decoding and transmission module based on domestic products according to claim 1, characterized in that The FPGA is connected to the domestic processor through multiple MIPI interfaces; it is used to enable the FPGA to send the original image data to the domestic processor through the MIPI interface; it is also used to enable the domestic processor to send the decoded image data to the FPGA through the MIPI interface.

7. The multi-channel video encoding, decoding and transmission module based on domestic products according to claim 1, characterized in that The FPGA is connected to the domestic processor through multiple UART serial ports, and is used to encapsulate the video information and the received external control instructions through the UART serial port protocol and send them to the domestic processor.

8. The multi-channel video encoding, decoding and transmission module based on domestic components according to claim 1, characterized in that The domestic processor uses the domestic Rockchip RK3588 chip as the processor; the interface unit includes multiple connectors.

9. A codec method based on a domestic multi-channel video codec transmission module, characterized in that, It includes an encoding method and a decoding method; The encoding method includes the following steps: S1-1. The FPGA receives the externally input video data stream through the SDI interface or the Cameralink interface, and parses the video data stream to obtain video information and original image data; at the same time, the FPGA also receives external control instructions; S1-2. Send the original image data to the domestic processor; at the same time, send the video information and the received external control instructions to the domestic processor; S1-3. The domestic processor dynamically adjusts the encoding parameters and selects the target video source according to the received video information and external control instructions; S1-4. The domestic processor encodes the original image data to generate a compressed bitstream, and sends the compressed bitstream back to the FPGA; S1-5. The FPGA adapts the transmission rate of the LVDS interface according to the received rate control instruction, and outputs the compressed bitstream to an external matching device through the LVDS interface; The decoding method includes the following steps: S2-1. The FPGA receives the externally input compressed bitstream, parses the compressed bitstream according to a preset rate control strategy, and forwards the compressed bitstream to the decoding end of the domestic processor; S2-2. The domestic processor decodes the compressed bitstream according to a pre-configured working mode to generate decoded image data; S2-3. Send the decoded image data to the FPGA; S2-4. The FPGA converts the decoded image data into the target interface protocol format, and outputs it to an external display device through the SDI interface or the Cameralink interface.

10. The decoding method based on the domestic multi-channel video encoding and decoding transmission module according to claim 9, characterized in that, It also includes an encoding bitstream optimization method, which specifically includes the following steps: S3-1: Optimize bitstream control: Set the bitstream control method to the fixed bitstream rate method, and ensure the fixity of the bitstream by dynamically adjusting the image quality; S3-2: Set the intra-frame refresh parameters: Set the periodic intra-frame refresh parameters, and distribute the reference frame data to each bitstream data frame; S3-3: Re-encoding mechanism: Set the bitstream fluctuation threshold Δ, and calculate the deviation between the current frame bitstream size and the historical sliding window mean value in real time; when the deviation exceeds Δ, trigger the re-encoding process to make the bitstream data size smoother.

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