Multi-channel video decoding method, video decoding chip, computer device and readable storage medium

By using a serial video decoding engine in the video decoding chip to decode multiple video streams, the problems of high cost and low efficiency in the prior art are solved, and low-cost and efficient video decoding is achieved.

CN120416495APending Publication Date: 2025-08-01SHENZHEN X-POWERS TECH CO LTD
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Patent Information

Application Number
CN202510802435.6
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-06-16
Publication Date
2025-08-01

AI Technical Summary

Technical Problem

The existing network video recorder video decoding chips are costly and have a large system load, and the existing decoding methods are complex and inefficient.

Method used

The serial-operated video decoding engine is used to decode multiple video streams, reduce the number of decoding units in the video decoding chip, and improve decoding efficiency by combining video frames to share decoding information and reducing interrupt signal frequency.

Benefits of technology

It reduces the production cost of video decoding chips, improves the efficiency of video decoding and the processing capability of the system.

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Abstract

The invention provides a multi-channel video decoding method, a video decoding chip, a computer device and a storage medium. The method comprises the following steps: acquiring more than two channels of video streams; furthermore, multiple video frames are acquired from at least two paths of video streams in the multiple paths of video streams and form a group of video frames, and the group of video frames comprises the video frames from the at least two paths of video streams; and sending the group of video frames to a video decoding engine, sequentially decoding each video frame in the group of video frames by the video decoding engine in a serial working mode to obtain a plurality of decoded frames, and sending the decoded frames to a display. The video decoding chip, the computer device and the storage medium can realize the method. According to the invention, the production cost of the video decoding chip can be reduced.
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Description

Technical Field

[0001] The present invention relates to the technical field of battery internal resistance compensation calculation. Specifically, it is a multi-channel video decoding method, a computer device for implementing this method, a computer-readable storage medium, and also relates to a video decoding chip for implementing the above method. Background Art

[0002] Network Video Recorders are widely used in video surveillance scenarios. Network Video Recorders often need to connect multiple cameras to obtain a video stream from each camera. The Network Video Recorder needs to decode the multiple video streams obtained and transmit the decoded video to a display. Usually, the display uses a split-screen display method for display, and users can view multiple videos simultaneously.

[0003] Traditional Network Video Recorders have high performance requirements for multi-channel video decoding, requiring real-time preview of multiple video bitstreams and smooth output video images. To meet the requirements of real-time decoding, the video decoding chips used in existing Network Video Recorders usually have multiple decoding units, and multiple decoding units are used to decode multiple video streams in parallel.

[0004] However, since the video decoding chip integrates multiple decoding units, for example, the decoding method disclosed in the publication number CN117425014A, this method uses multiple decoding units for parallel decoding, analyzes and controls the decoding situation of each unit decoder through an increased multi-channel decoding speed analysis device, and then controls the decoding strategy. However, this method results in too high production costs of the video decoding chip, and the synchronous parallel operation of multiple decoding units will also increase the system load.

[0005] The invention patent application with the publication number CN118338060A discloses a method for maintaining synchronization when a player plays multiple videos. This method selects frames with the same PTS from each bitstream as a group of frames and decodes them simultaneously. However, this method requires selecting frames with the same PTS as a group of frames for decoding, has strict requirements for the decoded video frames, and the frame selection process is complex, affecting the efficiency of video decoding. Summary of the Invention

[0006] The first object of the present invention is to provide a multi-channel video decoding method capable of dynamically calculating the internal resistance parameters of a lithium battery.

[0007] The second object of the present invention is to provide a video decoding chip for implementing the above multi-channel video decoding method.

[0008] The third object of the present invention is to provide a computer device for implementing the above multi-channel video decoding method.

[0009] The fourth object of the present invention is to provide a readable storage medium for implementing the above multi-channel video decoding method.

[0010] To achieve the first object of the present invention, the multi-channel video decoding method provided by the present invention includes obtaining two or more video streams; and obtaining multiple video frames from at least two video streams among the multiple video streams and forming a group of video frames, where a group of video frames contains video frames from at least two video streams; sending the group of video frames to a video decoding engine, and the video decoding engine sequentially decodes each video frame in the group of video frames in a serial working mode to obtain multiple decoded frames, and sending the decoded frames to a display.

[0011] As can be seen from the above solution, after the present invention obtains multiple video streams, it obtains multiple video frames from the multiple video streams and forms a group of video frames to be decoded. Only one video decoding engine is set in the video decoding chip, and the video decoding engine sequentially decodes the multiple video decoded frames in a serial working mode. In this way, it is not necessary to set multiple video decoding engines or video decoding units in the video decoding chip, and the production cost of the video decoding chip is low. In addition, a group of video decoded frames of the present invention do not need to have the same PTS, that is, it is not necessary to perform frame selection operations, which can save the time of video decoding and improve the efficiency of video decoding.

[0012] A preferred solution is that a group of video frames contains one video frame from each video stream.

[0013] As can be seen, one video frame from each video stream is included in a group of video frames. In this way, the video decoding engine is equivalent to decoding one video frame from each video stream each time, avoiding the problem of uneven decoding of each video stream.

[0014] An optional solution is that a group of video frames contains multiple consecutive video frames from the same video stream.

[0015] As can be seen, multiple consecutive video frames from the same video stream can be placed in the same group of video frames for simultaneous decoding, and these video frames can share decoding information, such as sharing context information, thereby improving the decoding efficiency and being beneficial to fast decoding in the decoding scenario of high-frame-rate videos.

[0016] A further solution is that each video frame of a group of video frames corresponds to a video decoding channel, and the video decoding engine sequentially decodes the video frames of each video decoding channel.

[0017] It can be seen that by using multiple video decoding channels to decode multiple video frames respectively, a one-to-one correspondence between the video decoding channels and the video frames is established, and the corresponding relationship between the decoded frames after decoding and the video frames is recorded, ensuring that each decoded frame is accurately combined into a decoded video stream.

[0018] A further solution is that after obtaining two or more video streams, the decoding information of each video stream is also obtained; when a group of video frames is sent to the video decoding engine, the decoding information corresponding to each video frame in the group of video frames is also obtained, and the corresponding decoding information is sent to the register of the video decoding engine.

[0019] It can be seen that before the video decoding engine performs decoding, the decoding information required for decoding is first sent to the register of the video decoding engine to ensure that the video decoding engine can obtain the correct information for decoding and avoid decoding errors.

[0020] A further solution is that the decoding information includes the context information, reference frames, and timestamps of the video frames.

[0021] An even further solution is that after the video decoding engine finishes decoding a group of video frames, the multi-channel video decoding engine task scheduling and control unit sends an interrupt signal.

[0022] It can be seen that the multi-channel video decoding engine task scheduling and control unit sends an interrupt signal only once after a group of video frames is decoded, thereby reducing the frequency of sending interrupt signals, enabling the video decoding engine to perform decoding operations at high speed, and thus improving the decoding efficiency.

[0023] To achieve the above second objective, the video decoding chip provided by the present invention includes a video decoding engine and a multi-channel video decoding engine task scheduling and control unit. The multi-channel video decoding engine task scheduling and control unit is used to obtain two or more video streams, obtain multiple video frames from at least two video streams among the multiple video streams and form a group of video frames, where a group of video frames contains video frames from at least two video streams; send a group of video frames to the video decoding engine, and after the video decoding engine sequentially decodes each video frame in the group of video frames in a serial working manner to obtain multiple decoded frames, send the decoded frames to the display.

[0024] To achieve the above third objective, the computer device provided by the present invention includes a processor and a memory. The memory stores a computer program, and when the computer program is executed by the processor, each step of the above multi-channel video decoding method is implemented.

[0025] To achieve the above fourth objective, a computer program is stored on the storage medium provided by the present invention, and when the computer program is executed by the processor, each step of the above multi-channel video decoding method is implemented. Description of the Drawings

[0026] Figure 1 is a block diagram of video decoding in an embodiment of the video decoding chip of the present invention.

[0027] Figure 2 is a flowchart of an embodiment of the multi-channel video decoding method of the present invention.

[0028] The present invention will be further described below in conjunction with the drawings and embodiments. Detailed Embodiments

[0029] The multi-channel video decoding method of the present invention is used to decode multi-channel video streams. Only one video decoding engine is provided in the video decoding chip to achieve synchronous decoding of multi-channel video streams, reducing the production cost of the video decoding chip. The computer device of the present invention has a processor and a memory. The memory is the readable storage medium of the present invention. A computer program is stored on the memory. When the computer program is executed by the processor, the above multi-channel video decoding method is implemented.

[0030] Embodiment of the video decoding chip: Refer to Figure 1 , the video decoding chip has a multi-channel video decoding engine task scheduling and control unit 10 and a video decoding engine 30. The multi-channel video decoding engine task scheduling and control unit 10 is used to receive multi-channel video streams, for example, obtain initial video streams from multiple cameras, and obtain multiple video frames from the multi-channel video streams to form a group of video frames. For example, one video frame can be obtained from each video stream to form a group of video frames, or multiple consecutive video frames can be obtained from one of the video streams and form a group of video frames with multiple video frames of other video streams. The same group of video frames is input to the video decoding engine 30, and the video decoding engine 30 decodes each video frame in the group of video frames in a serial processing manner to obtain multiple decoded frames. Finally, the multi-channel video decoding engine task scheduling and control unit 10 sorts the decoded frames obtained by decoding in the order of each video frame in the initial video stream to form multi-channel decoded bitstreams, and outputs each bitstream to the display. The display displays each bitstream at the corresponding position. Preferably, the display is displayed in a split-screen form, that is, multiple videos can be displayed on the display screen at the same time, so as to facilitate the display of videos captured by multiple cameras at the same time.

[0031] Embodiment of the multi-channel video decoding method: The multi-channel video decoding method of this embodiment is applied to the above video decoding chip. The following combines Figure 1 and Figure 2Introduce the decoding method of the above video decoding chip. First, the multi-channel video decoding engine task scheduling control unit 10 executes step S1 to obtain more than two video streams from multiple cameras. Preferably, each video stream contains multiple video frames, and each video frame corresponds to corresponding decoding information, such as context information, reference frames, timestamps, etc. When the multi-channel video decoding engine task scheduling control unit 10 obtains the video stream, it also needs to obtain the decoding information of each video frame in the video stream. Of course, for consecutive multiple video frames in the same video stream, part of the context information required for decoding is often the same, and even the reference frames of multiple video frames are the same. Therefore, when storing the decoding information of multiple video frames, it is not necessarily necessary to store all the decoding information of each video frame. For the case of the same decoding information, these decoding information are shared to reduce the data storage amount.

[0032] Each video stream comes from a camera, and the video stream output by each camera is an encoded video stream. Therefore, it is necessary to decode the video stream to obtain a playable video.

[0033] Then, execute step S2 to obtain multiple video frames from more than two video streams and form a group of video frames. Preferably, one video frame is obtained from each video stream to form the group of video frames. For example, a network video recorder is connected to eight cameras, and each camera outputs one video stream. At this time, the multi-channel video decoding engine task scheduling control unit 10 will obtain eight video streams and obtain one video frame from each of the eight video streams. In this way, a group of video frames contains eight video frames, and the eight video frames come from different video streams respectively.

[0034] Of course, in another implementation, a group of video frames may contain consecutive multiple video frames in one of the video streams. For example, a group of video frames contains 16 video frames, 8 of which come from the same video stream, and the 8 video frames from the same video stream are consecutive video frames, and the other 8 frames come from the remaining multiple video streams. Since consecutive multiple video frames in the same video stream often share context information and even reference frame information, the shared decoding information of these video frames only needs to be sent to the video decoding engine once, which can reduce the amount of data sent to the video decoding engine, reduce the occupied bandwidth, and also occupy fewer registers in the video decoding engine.

[0035] Then, execute step S3 to send a group of video frames to the video decoding engine 30. Specifically, each video frame of a group of video frames corresponds to a video decoding channel, and the video decoding engine 30 decodes the video frames of each video decoding channel in turn. As Figure 1As shown, a group of video frames includes multiple video frames, such as video frames 21, 22, 23, etc. Each video frame 21, 22, 23 corresponds to a video decoding channel. Preferably, each video decoding channel has its own unique identifier. In this way, a one-to-one correspondence can be established between each video frame and each video decoding channel.

[0036] When sending the video frames to the video decoding engine 30, it is also necessary to send the decoding information required for decoding this group of video frames to the video decoding engine 30, that is, to configure the registers of the video decoding engine 30, and store decoding information such as the context information, reference frames, and timestamps of each video frame in the registers of the video decoding engine 30. Preferably, it is necessary to mark the context information, reference frames, and timestamps and other information corresponding to each video frame.

[0037] If several video frames in a group of video frames are consecutive video frames from the same video stream, then these video frames will share the same context information and even share reference frames. In this case, it is not necessary to repeatedly store the shared decoding information in the registers of the video decoding engine 30, but only mark that these decoding information are shared by multiple video frames. This method can reduce the amount of data transmitted to the video decoding engine 30. On the one hand, it can reduce the occupied bandwidth, and on the other hand, it can reduce the time required for decoding, thereby improving the efficiency of video decoding.

[0038] Next, step S4 is executed. The video decoding engine 30 decodes each video frame 21, 22, 23 in sequence in a serial processing manner to generate decoded frames 31, 32, 33. Specifically, each video decoding channel decodes a video frame to obtain a corresponding decoded frame. Therefore, a one-to-one correspondence can be established among each video frame, video decoding channel, and decoded frame, so that each video frame is decoded to obtain a corresponding decoded frame. Finally, the decoded frames are corresponded to the corresponding video frames. For example, decoded frame 31 corresponds to video frame 21, decoded frame 32 corresponds to video frame 22, and so on.

[0039] Then, step S5 is executed to determine whether all the video frames being decoded by the video decoding engine 30 have been decoded. If not, decoding continues. If all the video frames in this group have been decoded, step S6 is executed. The multi-channel video decoding engine task scheduling control unit 10 will generate an interrupt signal and execute step S7 to send a group of decoded frames obtained by decoding to the display. In this way, the display will receive multiple decoded frames. It can be seen that the video decoding engine 30 will send an interrupt signal only after a group of video frames have been decoded, rather than sending an interrupt signal every time a single video frame is decoded. Therefore, the frequency of sending the interrupt signal is greatly reduced, and the number of times the video decoding chip responds to the interrupt signal is reduced. If the number of video frames included in a group of video frames is larger, the number of interrupts is fewer, and the number of times the video decoding chip responds to the interrupt signal is also fewer, which can improve the overall data processing efficiency of the video decoding chip.

[0040] After the display receives multiple decoded frames, it sorts the decoded frames output by each video decoding channel according to each video decoding channel, so as to obtain the decoded video stream corresponding to the original video stream and display it in the corresponding display area. Since each video frame has a timestamp, after the display receives multiple decoded frames from the same video decoding channel, it can sort the decoded frames according to the chronological order of the timestamps.

[0041] Of course, for the case where a group of video frames includes multiple video frames from the same video stream, it is necessary to record which video stream each video frame belongs to, and record the chronological order of each video frame in each video stream, for example, record the positions of each video frame in each video stream according to the timestamps. After decoding, it is necessary to associate each decoded frame with the corresponding video stream and record the chronological order of each decoded frame in the decoded video stream, so as to form the decoded video stream.

[0042] It can be seen that in this embodiment, by combining multiple video frames of multiple video streams into a group of video frames and decoding them sequentially in a serial manner by one video decoding engine, the number of video decoding engines used is reduced, and the production cost of the video decoding chip is reduced. In addition, since the video frames in the same group of video frames do not need to have the same PST and frame selection operations are not required, the video decoding operation is more flexible and the video decoding efficiency can be improved.

[0043] Embodiment of the computer device: The computer device in this embodiment can be a device with video decoding function, which has a processor, a memory, and a computer program stored in the memory and executable on the processor, such as an information processing program for implementing the above information processing method. When the processor executes the computer program, it implements each step of the above multi-channel video decoding method.

[0044] For example, a computer program can be divided into one or more modules. One or more modules are stored in a memory and executed by a processor to complete the various modules of the present invention. One or more modules can be a series of computer program instruction segments capable of performing specific functions, and these instruction segments are used to describe the execution process of the computer program in a terminal device.

[0045] The processor referred to in the present invention may be a Central Processing Unit (CPU), or may also be other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The processor is the control center of the terminal device and connects various parts of the entire terminal device through various interfaces and lines.

[0046] The memory can be used to store computer programs and / or modules. The processor realizes various functions of the terminal device by running or executing the computer programs and / or modules stored in the memory, and by calling the data stored in the memory. The memory mainly includes a program storage area and a data storage area. Among them, the program storage area can store an operating system, application programs required for at least one function, etc.; the data storage area can store data created according to the use of the mobile phone, etc. In addition, the memory may include high-speed random access memory, and may also include non-volatile memory, such as hard disks, memories, plug-in hard disks, Smart Media Cards (SMCs), Secure Digital (SD) cards, FlashCards, at least one magnetic disk storage device, flash memory device, or other volatile solid-state storage devices.

[0047] Embodiment of the storage medium: If the computer program stored in the computer device is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, to implement all or part of the processes in the above-mentioned embodiment methods of the present invention, it can also be completed by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor, it can implement each step of the above-mentioned multi-channel video decoding method.

[0048] Among them, the computer program includes computer program code, and the computer program code can be in the form of source code, object code, executable file or some intermediate form, etc. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disc, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal, and software distribution medium, etc. It should be noted that the content included in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice within the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, the computer-readable medium does not include electrical carrier signals and telecommunication signals.

[0049] Finally, it should be emphasized that the above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. Multi-channel video decoding method, comprising: Obtaining two or more video streams; Characterized in that: Obtaining multiple video frames from at least two of the multiple video streams and forming a set of video frames, where the set of video frames includes video frames from at least two of the video streams; Sending a set of the video frames to a video decoding engine, and the video decoding engine decodes each video frame in the set of video frames in a serial working manner to obtain multiple decoded frames, and sends the decoded frames to a display.

2. The multi-channel video decoding method according to claim 1, characterized in that: A set of the video frames includes one video frame from each of the video streams.

3. The multi-channel video decoding method according to claim 1, characterized in that: A set of the video frames includes multiple consecutive video frames from the same video stream.

4. The multi-channel video decoding method according to any one of claims 1 to 3, characterized in that: Each video frame in a set of the video frames corresponds to a video decoding channel, and the video decoding engine sequentially decodes the video frames of each of the video decoding channels.

5. The multi-channel video decoding method according to any one of claims 1 to 3, characterized in that: After obtaining two or more video streams, decoding information of each video stream is also obtained; When sending a set of the video frames to the video decoding engine, decoding information corresponding to each video frame in the set of video frames is also obtained, and the corresponding decoding information is sent to a register of the video decoding engine.

6. The multi-channel video decoding method according to claim 5, characterized in that: The decoding information includes context information, reference frames, and timestamps of the video frames.

7. The multi-channel video decoding method according to any one of claims 1 to 3, characterized in that: After the video decoding engine finishes decoding a set of the video frames, a multi-channel video decoding engine task scheduling control unit sends an interrupt signal.

8. A video decoding chip, comprising a video decoding engine, characterized in that: A multi-channel video decoding engine task scheduling control unit is further provided, and the multi-channel video decoding engine task scheduling control unit is used to obtain two or more video streams, obtain multiple video frames from at least two of the multiple video streams and form a set of video frames, where the set of video frames includes video frames from at least two of the video streams; Sending a set of the video frames to the video decoding engine, and after the video decoding engine decodes each video frame in the set of video frames in a serial working manner to obtain multiple decoded frames, sending the decoded frames to a display.

9. A computer device, characterized in that, Including a processor and a memory, the memory stores a computer program, and when the computer program is executed by the processor, each step of the multi-channel video decoding method according to any one of claims 1 to 7 is implemented.

10. A readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by the processor, each step of the multi-channel video decoding method according to any one of claims 1 to 7 is implemented.

Citation Information

Patent Citations

  • Multi-channel video decoding method and device for realizing load balancing

    CN117425014A

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