Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, and electronic equipment, and relates to the technical field of semiconductors, and the semiconductor device comprises a plurality of storage units which are distributed in different layers and are distributed in a stacking manner in the direction perpendicular to a substrate; the storage unit comprises a first electrode of a transistor, a semiconductor layer and a second electrode which are arranged along a first direction parallel to the substrate; a plurality of bit lines extending along a second direction parallel to the substrate, wherein the bit lines are connected with the first electrode; the bit lines and the connected transistors are periodically distributed in a first direction; the first electrode and the second electrode have a first end surface in contact with the semiconductor layer, a second end surface opposite to the first end surface, and a side wall between the first end surface and the second end surface; and a contact layer covering the first end surfaces and the sidewalls of the first electrode and the second electrode. The semiconductor device provided by the embodiment of the invention is beneficial to reducing the manufacturing process risk and improving the performance of the semiconductor device.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of semiconductor technology, and more particularly to a semiconductor device, a manufacturing method thereof, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking day by day, and the types and quantities of devices included in a single chip are increasing accordingly. As a result, minor differences in the process production may affect the device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to fabricate as many device units as possible on a limited substrate. Since Moore's law came out, the industry has proposed various semiconductor structure designs and process optimizations to meet the requirements of current products. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of the present application.

[0005] Embodiments of the present application provide a semiconductor device, a manufacturing method thereof, and an electronic device, which are beneficial to reducing the manufacturing process risk and improving the performance of the semiconductor device.

[0006] Embodiments of the present application provide a semiconductor device, including:

[0007] A plurality of memory cells, distributed in different layers and stacked in a direction perpendicular to the substrate; the memory cells include a first electrode of a transistor arranged in a first direction parallel to the substrate, a semiconductor layer, and a second electrode;

[0008] A plurality of bit lines extending in a second direction parallel to the substrate, the bit lines being connected to the first electrode, and the first direction intersecting with the second direction; each bit line is connected to the transistors of a column of the memory cells in the same layer, and the bit lines and the connected transistors are periodically distributed in the first direction;

[0009] Both the first electrode and the second electrode have a first end face in contact with the semiconductor layer, a second end face opposite to the first end face, and side walls between the first end face and the second end face;

[0010] A contact layer covering the first end face and each side wall of the first electrode and the second electrode.

[0011] In some embodiments, the memory cell further includes a capacitor, the capacitor including an inner electrode, a dielectric layer, and an outer electrode, the inner electrode being a part of the second electrode, and the dielectric layer and the outer electrode are sequentially wrapped around the side walls of the second electrode and the contact layer on the side walls are in contact.

[0012] In some embodiments, the semiconductor device further includes word lines extending in a direction perpendicular to the substrate, the word lines passing through the memory cells of different layers, the semiconductor layer being annular around the word lines, and the semiconductor layers of the memory cells of different layers being disconnected from each other.

[0013] In some embodiments, the first electrode and the bit line are of an integral structure; the vertical sidewall close to the semiconductor layer and the upper and lower horizontal sidewalls of the integral structure are covered with a contact layer, and the vertical sidewall of the bit line far from the semiconductor layer is not covered with the contact layer.

[0014] An embodiment of the present application provides a method for manufacturing a semiconductor device, the semiconductor device including: memory cells of different layers stacked and distributed in a direction perpendicular to the substrate and bit lines extending in a direction parallel to the substrate, each bit line being connected to a transistor of a column of the memory cells of the same layer, and the bit lines and the connected transistors being periodically distributed in a first direction;

[0015] The manufacturing method includes:

[0016] Successively and alternately depositing an insulating layer and a sacrificial layer on the substrate to obtain a stacked structure;

[0017] Forming a plurality of first holes penetrating the stacked structure by etching, the plurality of first holes being spaced apart in a first direction and a second direction parallel to the substrate, and forming dummy word lines in the first holes;

[0018] Forming a first trench extending in the first direction and penetrating the stacked structure at every other first hole in the second direction of the stacked structure, and forming a second trench extending in the second direction between any two adjacent columns of first holes; the first trench exposes the sidewalls of the dummy word lines located in the insulating layer and the sacrificial layer, and the sacrificial layer located on both sides of the first hole in the first direction is disconnected;

[0019] Filling the insulating layer in the first trench;

[0020] Etching back the sacrificial layer exposed by the two second trenches in the adjacent second trenches until the opposite sidewalls of the dummy word lines in the first direction are exposed, and the space after etching the sacrificial layer includes a third trench and a fourth trench respectively located on both sides of the dummy word line;

[0021] Depositing a conductive layer in the second trench, the third trench and the fourth trench, and the conductive layer filling the third trench and the fourth trench.

[0022] In some embodiments, the depositing a conductive layer in the second trench, the third trench and the fourth trench includes:

[0023] Deposit a conductive layer in the second trench, the third trench, and the fourth trench;

[0024] Remove the conductive layer at the bottom and on the two sidewalls of the second trench. Form a first electrode and a bit line in the fourth trench on one side of the dummy word line, and form a second electrode in the third trench on the other side of the dummy word line. At the same time, the second electrodes in different layers are disconnected from each other, and the bit lines in different layers are disconnected from each other.

[0025] In some embodiments, depositing a conductive layer in the second trench, the third trench, and the fourth trench includes:

[0026] Deposit a contact layer and a metal conductive layer in the second trench, the third trench, and the fourth trench in sequence. The metal conductive layer fills the third trench and the fourth trench, and the contact layers of the third trench and the fourth trench are in contact with the dummy word line respectively.

[0027] In some embodiments, the manufacturing method further includes: after filling the conductive layer in the third trench and the fourth trench, perform an etch-back on the insulating layer exposed in the adjacent second trench, and fill a support layer in the second trench and the etched-back area. The material of the support layer is different from the material of the insulating layer.

[0028] In some embodiments, it further includes: after forming the support layer,

[0029] Remove the insulating layer covering the second electrode to expose the sidewalls of the second electrode away from the dummy word line, and deposit a dielectric layer and a conductive layer on the exposed area of the second electrode in sequence.

[0030] In some embodiments, forming a plurality of first holes penetrating the stacked structure by etching, and forming a dummy word line in the first holes includes:

[0031] Etch the stacked structure to form an initial hole penetrating the stacked structure;

[0032] Perform a lateral etch on the insulating layer in the initial hole to form the first hole;

[0033] Form the dummy word line in the first hole. The dummy word line includes a body extending in a direction perpendicular to the substrate and a protrusion extending into the insulating layer.

[0034] In some embodiments, in a second direction of the stacked structure, a first trench extending in the first direction and penetrating the stacked structure is formed every other first hole, and a second trench extending in the second direction is formed between every two adjacent columns of first holes; the first trench exposes sidewalls of the dummy word line located in the insulating layer and the sacrificial layer, and the sacrificial layer located on both sides of the first hole in the first direction is disconnected, including:

[0035] In a second direction of the stacked structure, a first trench extending in the first direction and penetrating the stacked structure is formed every other first hole, and a second trench extending in the second direction is formed between every two adjacent columns of first holes. Each of the second trenches intersects with a plurality of the first trenches only on the same side, and the first trench only exposes the sidewall of the dummy word line located in the insulating layer, and the sidewall of the dummy word line located in the sacrificial layer is surrounded by the sacrificial layer;

[0036] Etch-back the sacrificial layer in the first trench and the second trench so that the first trench and the second trench expand towards the sacrificial layer, and the expanded first trench exposes the sidewalls of the dummy word line located in the insulating layer and the sacrificial layer at the same time.

[0037] In some embodiments, it further includes:

[0038] Remove the body of the dummy word line and retain the protruding portion to form a word line hole, and sequentially form a semiconductor layer, a gate insulating layer, and a word line in the word line hole;

[0039] Remove the protruding portion to expose the semiconductor layer, and remove the exposed semiconductor layer.

[0040] In some embodiments, the removing the body of the dummy word line and retaining the protruding portion to form a word line hole, and sequentially forming a semiconductor layer, a gate insulating layer, and a word line in the word line hole includes:

[0041] Etch and remove the body of the dummy word line located in the initial hole, and the remaining protruding portion of the dummy word line formed by the word line hole is annular. Sequentially form a semiconductor layer, a gate insulating layer, and a word line in the word line hole;

[0042] The removing the protruding portion to expose the semiconductor layer, and removing the exposed semiconductor layer includes:

[0043] Etch and form a second hole between two adjacent first holes along the second direction. Both sides of the second hole expose the annular protruding portions of two adjacent dummy word lines, and the protruding portions are located in the parasitic MOS region;

[0044] Remove the annular protruding portion to expose the semiconductor layer located in the parasitic MOS region;

[0045] Remove the semiconductor layer located in the parasitic MOS region;

[0046] Fill the insulating layer between adjacent transistors.

[0047] In some embodiments, filling the insulating layer in the first trench includes:

[0048] Deposit the insulating layer in the first trench and the second trench, and fill the insulating layer in the first trench;

[0049] Remove the insulating layer in the second trench, and both ends of the sacrificial layer are exposed in two adjacent second trenches.

[0050] An embodiment of the present application further provides an electronic device, which includes the semiconductor device provided by the embodiment of the present application, or a semiconductor device manufactured by the method.

[0051] The semiconductor device of the embodiment of the present application is beneficial to reducing the manufacturing process risk and improving the performance of the semiconductor device.

[0052] Other features and advantages of the present application will be described in the following specification, and, in part, will be obvious from the specification, or will be understood by implementing the present application. The objectives and advantages of the present application can be achieved and obtained by the structures specifically pointed out in the specification and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] The drawings are used to provide an understanding of the technical solutions of the present application, and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solutions of the present application, and do not constitute a limitation to the technical solutions of the present application.

[0054] Figure 1A is a schematic cross-sectional view of the semiconductor device of the exemplary embodiment of the present application parallel to the substrate;

[0055] Figure 1B is Figure 1A a schematic longitudinal cross-sectional view of the semiconductor device shown perpendicular to the substrate;

[0056] Figure 1C is Figure 1A a partial enlarged view of;

[0057] Figure 2 is a process flow chart of a manufacturing method of a semiconductor device provided by an exemplary embodiment of the present application;

[0058] Figure 3 is a schematic three-dimensional structure diagram of a manufacturing method of a semiconductor device provided by an exemplary embodiment of the present application after forming a stacked structure;

[0059] Figure 4A A cross-sectional view of a manufacturing method of a semiconductor device provided by an exemplary embodiment of the present application in a C1 plane parallel to the substrate after forming an initial via hole;

[0060] Figure 4B For Figure 4A The cross-sectional view of the structure shown in a C2 plane perpendicular to the substrate;

[0061] Figure 5A A cross-sectional view of a manufacturing method of a semiconductor device provided by an exemplary embodiment of the present application in a C1 plane parallel to the substrate after forming a dummy word line;

[0062] Figure 5B For Figure 5A The cross-sectional view of the structure shown in a C2 plane perpendicular to the substrate;

[0063] Figure 6A A cross-sectional view of a manufacturing method of a semiconductor device provided by an exemplary embodiment of the present application in a C1 plane parallel to the substrate after forming a first trench and a second trench;

[0064] Figure 6B For Figure 6A The cross-sectional view of the structure shown in a C2 plane perpendicular to the substrate;

[0065] Figure 6C For Figure 6A The cross-sectional view of the structure shown in a C3 plane perpendicular to the substrate;

[0066] Figure 7A A cross-sectional view of a manufacturing method of a semiconductor device provided by an exemplary embodiment of the present application in a C1 plane parallel to the substrate after filling the first trench and the second trench with an insulating layer;

[0067] Figure 7B For Figure 7A The cross-sectional view of the structure shown in a C3 plane perpendicular to the substrate;

[0068] Figure 8A A cross-sectional view of a manufacturing method of a semiconductor device provided by an exemplary embodiment of the present application in a C1 plane parallel to the substrate after removing the insulating layer in the second trench to expose the sacrificial layer;

[0069] Figure 8B For Figure 8A The cross-sectional view of the structure shown in a C2 plane perpendicular to the substrate;

[0070] Figure 9A A cross-sectional view of a manufacturing method of a semiconductor device provided by an exemplary embodiment of the present application in a C1 plane parallel to the substrate after removing the sacrificial layer;

[0071] Figure 9B is Figure 9A a cross-sectional view of the structure shown in the C2 plane perpendicular to the substrate;

[0072] Figure 10A is a cross-sectional view of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application in the C1 plane parallel to the substrate after filling the third trench and the fourth trench with a conductive layer;

[0073] Figure 10B is Figure 10A a cross-sectional view of the structure shown in the C2 plane perpendicular to the substrate;

[0074] Figure 11A is a cross-sectional view of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application in the C1 plane parallel to the substrate after forming bit lines;

[0075] Figure 11B is Figure 11A a cross-sectional view of the structure shown in the C2 plane perpendicular to the substrate;

[0076] Figure 12A is a cross-sectional view of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application in the C1 plane parallel to the substrate after forming a support layer;

[0077] Figure 12B is Figure 12A a cross-sectional view of the structure shown in the C2 plane perpendicular to the substrate;

[0078] Figure 13A is a cross-sectional view of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application in the C1 plane parallel to the substrate after exposing the inner electrode;

[0079] Figure 13B is Figure 13A a cross-sectional view of the structure shown in the C2 plane perpendicular to the substrate;

[0080] Figure 14A is a cross-sectional view of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application in the C1 plane parallel to the substrate after forming a capacitor;

[0081] Figure 14B is Figure 14A a cross-sectional view of the structure shown in the C2 plane perpendicular to the substrate;

[0082] Figure 15A is a cross-sectional view of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application in the C1 plane parallel to the substrate after forming word lines;

[0083] Figure 15B is Figure 15A a cross-sectional view of the structure shown in the C2 plane perpendicular to the substrate;

[0084] Figure 16 is a cross-sectional view of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application in the C1 plane parallel to the substrate after forming the second via hole K2;

[0085] Figure 17A is a cross-sectional view of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application in the C1 plane parallel to the substrate after removing the protrusion of the dummy word line;

[0086] Figure 17B is Figure 17A a cross-sectional view of the structure shown in the C2 plane perpendicular to the substrate.

[0087] The meanings of the reference symbols in the drawings are as follows:

[0088] 10 - Substrate; 11 - Insulating layer; 12 - Sacrificial layer; 13 - Support layer; 20 - Memory cell; 30 - Bit line 30; 40 - Transistor; 41 - First electrode; 42 - Second electrode; 43 - Semiconductor layer; 44 - Gate insulating layer; 50 - Conductive layer; 51 - Contact layer; 60 - Capacitor; 61 - Inner electrode; 62 - Dielectric layer; 63 - Outer electrode; 70 - Word line; 71 - Gate electrode; 81 - First trench; 82 - Second trench; 83 - Third trench; 84 - Fourth trench; K0 - Initial hole; K1 - First hole; K2 - Second hole; 200 - Parasitic MOS region; 300 - Channel region. Detailed implementation manners

[0089] To make the objectives, technical solutions, and advantages of the present application clearer and more understandable, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that, without conflict, the embodiments and features in the embodiments of the present application can be combined with each other arbitrarily.

[0090] The implementation manners of the present application do not necessarily limit the sizes shown in the drawings. The shapes and sizes of the components in the drawings are preferred implementation schemes and can also be other shapes and sizes. In addition, the drawings schematically show ideal examples, and the implementation manners of the present application are not limited to the shapes or values shown in the drawings.

[0091] The size and proportional relationships between the various film layers or components in the drawings of the present application can be used as a reference in actual processes and are implementation manners with better technical effects, but are not limited thereto. For example: the aspect ratio of the semiconductor layer, the thickness and spacing of the various film layers can be adjusted according to actual needs.

[0092] The ordinal numbers such as "first" and "second" in this application are set to avoid confusion of components and do not indicate any order, quantity or importance.

[0093] In this application, for convenience, terms indicating orientation or positional relationship such as "middle part", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer" are used to describe the positional relationship of components with reference to the accompanying drawings. This is only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to this application. The positional relationship of components changes appropriately according to the directions describing each component. Therefore, it is not limited to the terms described in the disclosure and can be replaced appropriately according to the circumstances.

[0094] In this application, unless otherwise clearly specified and defined, the terms "mount", "connect" and "couple" shall be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate member, or the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0095] In this application, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region or drain electrode) and the source electrode (source electrode terminal, source region or source electrode), and current can flow through the drain electrode, the channel region and the source electrode. In this application, the channel region refers to the region where current mainly flows.

[0096] In this application, it may be that the first electrode is the drain electrode and the second electrode is the source electrode, or it may be that the first electrode is the source electrode and the second electrode is the drain electrode. In cases such as using transistors with opposite polarities or changes in the current direction during the operation of a circuit, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this application, if not specifically stated, the "source electrode" and the "drain electrode" can be interchanged with each other.

[0097] In this application, "electrically connected" or "connected" includes cases where components are connected together through elements having a certain electrical effect. For example, electrical signal connection (coupled connection, such as coupled to), or physical direct connection. There are no particular restrictions on the "element having a certain electrical effect" as long as it can transfer electrical signals between the components to be connected. Examples of the "element having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0098] In this application, "parallel" means approximately parallel or almost parallel. For example, the state where the angle formed by two straight lines is above -10° and below 10°. Therefore, it also includes the state where the angle is above -5° and below 5°. In addition, "perpendicular" means approximately perpendicular. For example, the state where the angle formed by two straight lines is above 80° and below 100°. Therefore, it also includes the state where the angle is above 85° and below 95°.

[0099] In this application, "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be replaced with "conductive film". Similarly, sometimes "insulating film" can be replaced with "insulating layer".

[0100] As used in this application, "A and B are on the same layer" means that A and B are distributed on the same horizontal plane, or although not on the same horizontal plane, they are in different regions on the same support surface. One embodiment is that A and B are formed simultaneously by the same patterning process on the same film layer.

[0101] "A and B are of an integral structure" in the embodiments of this application can mean that there is no obvious fault or gap or other obvious boundary interface in the microscopic structure. Generally, the patterned and connected film layers on one film layer are of an integral structure. For example, A and B are formed of the same material to form one film layer and have a connected structure formed simultaneously by the same patterning process, or B is directly grown on A by epitaxy, and the materials of the two may not be completely the same.

[0102] In this application, spaced distribution can be understood as separated and independent (separated) distribution, which can be achieved by physical disconnection in the physical structure or by electrical disconnection in electrical characteristics. For example, the semiconductor layer between the effective channels corresponding to two transistors is modified to achieve insulation to realize electrical spacing between the two channels.

[0103] To obtain higher integration, memories are gradually developing towards three-dimensional (3D) stereoscopic structures.

[0104] The embodiments of this application provide a semiconductor device.

[0105] Figure 1A Cross-sectional schematic view of a semiconductor device according to an exemplary embodiment of the present application; Figure 1B is Figure 1A Partial enlarged view of Figure 1C is Figure 1A Longitudinal cross-sectional schematic view of the semiconductor device shown in

[0106] As Figures 1A to 1C shown, the semiconductor device includes: a plurality of memory cells 20 (denoted by the dotted box) located on a substrate 10, a plurality of bit lines 30, and a contact layer 51;

[0107] The plurality of memory cells 20 are distributed in different layers and stacked in a direction perpendicular to the substrate 10; the memory cells 20 include a first electrode 41, a semiconductor layer 43, and a second electrode 42 of a transistor 40 arranged along a first direction parallel to the substrate 10;

[0108] A plurality of bit lines 30 extending along a second direction parallel to the substrate 10, the bit lines 30 are connected to the first electrode 41, and the first direction intersects the second direction; each bit line 30 is connected to the transistors 40 of a column of the memory cells 20 located in the same layer, and the bit lines 30 and the connected transistors 40 are periodically distributed in the first direction;

[0109] Both the first electrode 41 and the second electrode 42 have a first end face in contact with the semiconductor layer 43, a second end face opposite to the first end face, and side walls between the first end face and the second end face; in the embodiments of the present application, the side walls include two upper and lower horizontal side walls and two front and rear vertical side walls.

[0110] The contact layer 51 covers the first end face and each side wall of the first electrode 41 and the second electrode 42; exemplarily, the second end face of the second electrode 42 is not covered with the contact layer 51.

[0111] In the semiconductor device according to the embodiments of the present application, a contact layer is provided on the first end face and each side wall of the first electrode and the second electrode of the transistor, so that a dielectric layer and an external electrode of a capacitor can be directly deposited on the contact layer, thereby avoiding the process risks brought by the direct contact of the dielectric layer with a large area of the first electrode or the internal electrode.

[0112] Moreover, in the semiconductor device according to the embodiments of the present application, a contact layer is provided on the first end face where the first electrode and the second electrode are in contact with the semiconductor layer, which can reduce the formation of Schottky contacts (metal-semiconductor contacts) when the first electrode and the second electrode of the metal material are in direct contact with the semiconductor layer, and improve the performance of the device.

[0113] Exemplarily, as Figure 1CAs shown, the storage unit 20 may further include a capacitor 60, which may include an inner electrode 61, a dielectric layer 62, and an outer electrode 63. The inner electrode 61 is a part of the second electrode 42, and both the dielectric layer 62 and the outer electrode 63 wrap around the sidewalls of the second electrode 42 and contact the contact layer 51 on each sidewall.

[0114] In the semiconductor device according to the embodiment of the present application, contact layers are provided at the ends and sidewalls of the inner electrode. For example, a contact layer made of TiN material is used, so that the dielectric layer and the outer electrode can be directly deposited on the contact layer, which can avoid the process risks brought by the direct contact of the dielectric layer with the large-area first electrode or inner electrode.

[0115] Exemplarily, as Figures 1A to 1C shown, the semiconductor layer 43 may be annular, for example, a circular ring or an elliptical ring.

[0116] Exemplarily, as Figures 1A to 1C shown, the semiconductor device may further include a word line 70 extending in a direction perpendicular to the substrate 10. The word line 70 penetrates through the storage units 20 of different layers, and annular semiconductor layers 43 are distributed at intervals in the vertical substrate direction on the sidewalls of the word line 70; the sidewalls of the annular semiconductor layers 43 are adapted to the sidewalls of the word line 70, that is, the sidewall shapes of the annular semiconductor layers 43 are the same as those of the sidewalls of the word line 70.

[0117] Exemplarily, as Figure 1A shown, the first electrode 41 and the bit line 30 are of an integrated structure; the vertical sidewall and the upper and lower two horizontal sidewalls of the integrated structure close to the semiconductor layer 43 are all covered with the contact layer 51, and the vertical sidewall of the bit line 30 far from the semiconductor layer 43 is not covered with the contact layer 51.

[0118] Exemplarily, the first direction may be parallel to the substrate, the second direction may be parallel to the substrate, and the first direction and the second direction may be perpendicular to each other. For example, the first direction may be the X direction as Figure 1A shown, and the second direction may be the Y direction as Figure 1A shown.

[0119] Exemplarily, the bit line in the same layer and the first electrode, the second electrode, and the inner electrode of the storage unit connected to the bit line may be distributed in different regions of the same conductive layer, and the second electrode and the inner electrode share the same electrode.

[0120] Exemplarily, the physical structures of the multiple semiconductor layers of multiple transistors located in different layers are spaced apart in the direction perpendicular to the substrate, and the multiple semiconductor layers are distributed in different regions on the sidewalls of the word line.

[0121] In the embodiments of the present application, the semiconductor layers of the transistors in at least some adjacent layers of the semiconductor device are spaced apart, which can eliminate the parasitic MOS transistors (referred to as parasitic MOS for short) between the memory cells of different layers and improve the device stability.

[0122] Exemplarily, the transistor may further include a gate electrode 71, and the semiconductor layer 43 may surround the gate electrode 71. Insulation between the semiconductor layer 43 and the gate electrode 71 is achieved through a gate insulating layer.

[0123] Surrounding can be understood as partial surrounding or full surrounding.

[0124] Exemplarily, the gate electrode may be a part of the word line.

[0125] Exemplarily, the material of the semiconductor layer may be silicon or polysilicon with a bandgap less than 1.65 eV, or it may also be a wide-bandgap material, such as a metal oxide material with a bandgap greater than 1.65 eV.

[0126] For example, the material of the metal oxide semiconductor layer or the channel may include metal oxides of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, compounds containing other elements, such as N, Si, etc., are not excluded in the metal oxide, and other minor doping elements are not excluded either.

[0127] In some embodiments, the material of the metal oxide semiconductor layer or the channel may include any one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO, IWO), titanium oxide (TiO), zinc oxide nitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), etc. As long as the leakage current of the transistor can meet the requirements, it can be adjusted according to the actual situation specifically.

[0128] These materials have a wide bandgap and low leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 -15 A to 10 -18 A, thereby improving the operating performance of the dynamic memory.

[0129] The material of the above-mentioned metal oxide semiconductor layer or channel only emphasizes the element type of the material, and does not emphasize the atomic ratio in the material and the film quality of the material.

[0130] Exemplarily, the material of the bit line can be selected from any one or more of other metal materials with similar properties such as tungsten, molybdenum, cobalt, etc. The bit line can be a single-layer or multi-layer structure. For example, it can be a multi-layer structure formed by titanium (Ti), titanium nitride (TiN), and tungsten (W).

[0131] In the exemplary embodiments of the present application, the electrode material of the gate electrode can be any one or more of the following different types of materials: for example, metals containing tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it can be a metal alloy containing the aforementioned metals; it can also be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as highly conductive metal oxide materials such as indium tin oxide ITO, indium zinc oxide IZO, indium oxide InO, etc.; for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), etc.; of course, it can also be a polysilicon material; it can also be a conductive material doped with a semiconductor material, for example, silicon doped with conductivity, germanium doped with conductivity, silicon germanium doped with conductivity, etc.; other materials showing conductivity, etc.

[0132] In the exemplary embodiments of the present application, the material of the gate insulating layer can include one or more layers of Low-K and / or High-K dielectric materials, or include two or more regions with different dielectric constants K. The characteristics of the gate insulating layer of the present application will be exemplarily described below. Low-K materials, such as silicon oxide. High-K materials, such as dielectric materials with a dielectric constant K≥3.9. In some embodiments, it can include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, it can include at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), etc. high-K materials.

[0133] Exemplarily, transistors of different layers can share an annular gate insulating layer extending along a direction perpendicular to the substrate.

[0134] Exemplarily, the gate insulating layers of transistors in at least partially adjacent layers may be spaced apart in a direction perpendicular to the substrate.

[0135] Exemplarily, the gate insulating layers of transistors in different layers are spaced apart in a direction perpendicular to the substrate.

[0136] Exemplarily, the material components of different regions of the word line extending in a direction perpendicular to the substrate may be the same, which can be understood as being formed using the same film layer manufacturing process. The same material components can be understood as the same main elements tested in the material. For example, they are all formed by conductive materials such as metals, metal nitrides, or metal oxides. For example, they are made of conductive materials such as TI, TiN, W, ITO, IZO, etc.

[0137] Exemplarily, the outer electrodes of capacitors of a column of memory cells distributed in a direction perpendicular to the substrate may be of an integral structure.

[0138] Exemplarily, adjacent two of the transistors may be insulated by an insulating layer. The material of the insulating layer may be a low-K material, such as silicon oxide or other materials, or air (i.e., forming an air gap), which can reduce the parasitic capacitance between adjacent two transistors distributed in the second direction.

[0139] In an exemplary embodiment of the present application, the material of the dielectric layer may be silicon oxide or a High-K dielectric material. The High-K material, in some embodiments, may include oxides of any one or more of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, it may include but is not limited to at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2) and other High-K materials.

[0140] Exemplarily, the memory cell at least includes the above-mentioned transistor. This memory cell can be applied to 1T or 2T scenarios.

[0141] The memory cell may further include other components, such as a capacitor in a 1T1C memory cell.

[0142] Exemplarily, the semiconductor device may be a 3D memory, for example, memories such as 3D DRAM, or ferroelectric memories. The 3D memory may be of 1T1C, 2T1C structure, and may also be of 1T0C or 2T0C (including read transistors and write transistors) structure.

[0143] The embodiments of the present application further provide a method for manufacturing a semiconductor device. The semiconductor device includes: different layer memory cells stacked and distributed in a direction perpendicular to the substrate, and bit lines extending in a direction parallel to the substrate. Each bit line is connected to a transistor of a column of the memory cells in the same layer, and the bit lines and the connected transistors are periodically distributed in a first direction.

[0144] Figure 2 It is a process flow chart of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application. As Figure 2 shown, the manufacturing method includes:

[0145] The manufacturing method includes:

[0146] Deposit an insulating layer and a sacrificial layer alternately on the substrate in sequence to obtain a stacked structure;

[0147] Form a plurality of first holes penetrating the stacked structure by etching. The plurality of first holes are spaced apart in a first direction and a second direction parallel to the substrate, and dummy word lines are formed in the first holes;

[0148] In the second direction of the stacked structure, form a first trench extending in the first direction and penetrating the stacked structure every other first hole. A second trench extending in the second direction is formed between any two adjacent columns of first holes; the first trench exposes the side walls of the dummy word lines located in the insulating layer and the sacrificial layer, and the sacrificial layer located on both sides of the first hole in the first direction is disconnected;

[0149] Fill the insulating layer in the first trench. The insulating layer has the same material as the insulating layer stacked with the sacrificial layer;

[0150] Etch back the sacrificial layer exposed by the two second trenches in the adjacent second trenches until the opposite side walls of the dummy word lines in the first direction are exposed. The space after etching the sacrificial layer includes a third trench and a fourth trench located on both sides of the dummy word line respectively;

[0151] Deposit a conductive layer in the second trench, the third trench and the fourth trench. The conductive layer fills the third trench and the fourth trench.

[0152] When manufacturing the first electrode and the second electrode in the embodiments of the present application, by etching back the sacrificial layer exposed by the second trench in the second trench, a third trench and a fourth trench extending in the first direction are formed, and a conductive layer is filled in the third trench and the fourth trench. The conductive layer replaces the sacrificial layer. In this way, when digging deep trenches between adjacent word lines, there is no need to consider the width limitation of the replacement metal layer on the first trench, and the width of the first trench between adjacent word lines can be minimized as much as possible, which is beneficial to improving the device density.

[0153] The semiconductor device provided by the embodiment of the present application can be obtained by the manufacturing method described above.

[0154] Exemplarily, depositing a conductive layer in the second trench, the third trench, and the fourth trench includes:

[0155] Depositing a conductive layer in the second trench, the third trench, and the fourth trench;

[0156] Removing the conductive layer at the bottom and two sidewalls of the second trench, forming a first electrode and a bit line in the fourth trench on one side of the dummy word line, forming a second electrode in the third trench on the other side of the dummy word line, and simultaneously disconnecting the second electrodes in different layers from each other and disconnecting the bit lines in different layers from each other.

[0157] Exemplarily, depositing a conductive layer in the second trench, the third trench, and the fourth trench includes:

[0158] Successively depositing a contact layer and a metal conductive layer in the second trench, the third trench, and the fourth trench, wherein the contact layers in the third trench and the fourth trench are respectively in contact with the dummy word line. The metal conductive layer fills the third trench and the fourth trench.

[0159] Exemplarily, the manufacturing method may further include: after filling the conductive layer in the third trench and the fourth trench, etching back the insulating layer between the second electrodes and between the first electrode or the bit lines in the adjacent second trench, forming a trench between the second electrodes and the bit lines, and filling a support layer in the trench and the second trench, wherein the material of the support layer is different from the insulating layer when stacking and filling the first trench;

[0160] Forming a support layer in the second trench, and the second electrode extends into the support layer.

[0161] Exemplarily, the manufacturing method may further include: after forming the support layer,

[0162] Removing the insulating layer covering the second electrode, exposing the sidewalls of the second electrode away from the dummy word line, and successively depositing a dielectric layer and a conductive layer on the exposed area of the second electrode.

[0163] Exemplarily, forming a plurality of first holes penetrating the stacked structure by etching and forming a dummy word line in the first holes includes:

[0164] Etching the stacked structure to form an initial hole penetrating the stacked structure;

[0165] Transversely etching the insulating layer in the initial hole to form the first hole;

[0166] A dummy word line is formed in the first hole. The dummy word line includes a body extending in a direction perpendicular to the substrate and a protrusion extending into the insulating layer.

[0167] Exemplarily, a first trench extending in the first direction and penetrating the stacked structure is formed every other first hole in the second direction in the stacked structure, and a second trench extending in the second direction is formed between every two adjacent columns of first holes; the first trench exposes the side walls of the dummy word line located in the insulating layer and the sacrificial layer, and the sacrificial layer located on both sides of the first hole in the first direction is disconnected, including:

[0168] A first trench extending in the first direction and penetrating the stacked structure is formed every other first hole in the second direction in the stacked structure, and a second trench extending in the second direction is formed between every two adjacent columns of first holes. Each of the second trenches intersects with a plurality of the first trenches only on the same side. The first trench only exposes the side wall of the dummy word line located in the insulating layer, and the side wall of the dummy word line located in the sacrificial layer is surrounded by the sacrificial layer;

[0169] The sacrificial layer is etched back in the first trench and the second trench, so that the first trench and the second trench expand towards the sacrificial layer, and the expanded first trench exposes the side walls of the dummy word line located in the insulating layer and the sacrificial layer at the same time.

[0170] Exemplarily, the manufacturing method may further include:

[0171] The body of the dummy word line is removed and the protrusion is retained to form a word line hole, and a semiconductor layer, a gate insulating layer, and a word line are sequentially formed in the word line hole;

[0172] The protrusion is removed to expose the semiconductor layer, and the exposed semiconductor layer is removed.

[0173] Exemplarily, the removing the body of the dummy word line and retaining the protrusion to form a word line hole, and sequentially forming a semiconductor layer, a gate insulating layer, and a word line in the word line hole includes:

[0174] The body of the dummy word line in the initial hole is etched away, and the remaining protrusion of the dummy word line forming the word line hole is annular. A semiconductor layer, a gate insulating layer, and a word line are sequentially formed in the word line hole.

[0175] Exemplarily, removing the protrusion to expose the semiconductor layer and removing the exposed semiconductor layer includes:

[0176] A second hole is etched between two adjacent first holes along the second direction, and annular protrusions of two adjacent dummy word lines are respectively exposed on two sides of the second hole, and the protrusions are located in a parasitic MOS region;

[0177] The annular protrusions are removed to expose a semiconductor layer located in the parasitic MOS region;

[0178] The semiconductor layer located in the parasitic MOS region is removed, and the remaining semiconductor layer, the first electrode, the second electrode, and a partial region of the word line surrounded by the remaining semiconductor layer form a transistor;

[0179] An insulating layer is filled between adjacent transistors.

[0180] Exemplarily, filling the insulating layer in the first trench includes:

[0181] Depositing the insulating layer in the first trench and the second trench, and filling the insulating layer in the first trench;

[0182] The insulating layer in each second trench is removed, and the ends of the sacrificial layer between adjacent second trenches are exposed.

[0183] The technical solution of the embodiment of the present application is further described below through the manufacturing process of a semiconductor device in an exemplary embodiment. The "patterned etching" mentioned in this embodiment includes processes such as depositing a film layer, coating a photoresist, mask exposure, development, etching, and stripping the photoresist, which are mature preparation processes in the related art. The "lithography" process mentioned in this embodiment includes coating a film layer, mask exposure, and development, which are mature preparation processes in the related art. Deposition can adopt known processes such as sputtering, evaporation, and chemical vapor deposition, coating can adopt known coating processes, and etching can adopt known methods, which are not specifically limited herein.

[0184] Figures 3 to 17B It is a cross-sectional view of the structure obtained by each step of a manufacturing method of a semiconductor device provided in an exemplary embodiment of the present application on a C1 plane parallel to the substrate, and C2 and C3 planes perpendicular to the substrate. The C2 and C3 planes are perpendicular to each other, and the intercepting positions of the C1 plane, C2 plane, and C3 plane in each drawing can be different.

[0185] Figures 3 to 17B As shown, in an exemplary embodiment, the manufacturing method of the semiconductor device may include the following process.

[0186] S10: Provide a substrate 10, and sequentially and alternately deposit an insulating layer 11 and a sacrificial layer 12 on the substrate 10 to obtain a stacked structure composed of the insulating layer 11 and the sacrificial layer 12 distributed in a stacked manner, as Figure 3 shown.

[0187] The substrate in the embodiments of the present application can be understood as the support structure of the storage unit. For example, a silicon substrate, or a support structure on which other film layers, functions, or circuits are already distributed on the silicon substrate. The devices involved in the inventive configuration of the embodiments of the present application are arranged on the main surface of the support structure.

[0188] The materials of the insulating layer and the sacrificial layer are different, so that when etching and removing one of the sacrificial layer and the insulating layer subsequently, the sacrificial layer and the insulating layer can have different etching rates, thereby removing the insulating layer that is desired to be removed.

[0189] Exemplarily, the material of the insulating layer can be a low-K dielectric material, that is, a dielectric material with a dielectric constant K < 3.9, including but not limited to oxides of silicon, such as silicon dioxide (SiO2), etc.

[0190] Exemplarily, the material of the sacrificial layer can be polycrystalline silicon (poly-Si), or the material of the sacrificial layer can be polycrystalline germanium silicon (poly-GeSi), or the material of the sacrificial layer can be any one of silicon oxynitride (SiON), silicon nitride (SiN), and silicon carbonitride (SiCN).

[0191] Figure 3 The shown stacked structure includes 5 insulating layers 11 and 4 sacrificial layers 12. This is only an example. In other embodiments, the stacked structure may include more or fewer alternately arranged insulating layers 11 and sacrificial layers 12.

[0192] S20: Etch the stacked structure in the direction towards the substrate 10, such as dry etching, to form a plurality of initial holes K0 spaced apart in a first direction and a second direction in the stacked structure. The first direction intersects the second direction, as Figure 4A and Figure 4B shown.

[0193] Exemplarily, the step S20 may include:

[0194] Define a photolithography pattern by photolithography, etch the stacked structure in the direction towards the substrate 10, to form a plurality of spaced-apart initial holes K0 in the stacked structure. Each initial hole K0 can penetrate the stacked structure and extend to the surface or inside of the substrate 10. Each initial hole K0 can extend in a direction perpendicular to the substrate 10; the plurality of initial holes K0 can be spaced apart in the first direction and the second direction to form a hole array.

[0195] Exemplarily, the first direction and the second direction may be perpendicular to each other; the first direction may be parallel to the substrate 10. For example, it may be the X direction as shown in 4A; the second direction may be parallel to the substrate 10. For example, it may be the Y direction as shown in 4A.

[0196] Exemplarily, the initial hole K0 may be perpendicular to the substrate 10.

[0197] S30: Horizontally etch the insulating layer 11 within the initial hole K0 to extend the initial hole K0 towards the insulating layer 11, forming a first hole K1. The aperture of the first hole K1 located in the insulating layer 11 is larger than the aperture of the first hole K1 located in the sacrificial layer 12; form a dummy word line 70' within the first hole K1. The dummy word line 70' includes a body extending towards the substrate 10 and a protrusion extending into the insulating layer 11, as Figure 5A and Figure 5B shown, wherein, Figure 5A the concentration plane C1 in [figure] passes through the insulating layer 11.

[0198] S40: Pattern etch the stacked structure to form a first trench 81 extending along the first direction and penetrating the stacked structure at intervals of one first hole K1 in the second direction of the stacked structure, and form a second trench 82 extending along the second direction between any two adjacent columns of first holes K1. One column of memory cells is included between two second trenches. Each second trench 82 communicates with only a plurality of first trenches 81 on the same side. The first trench 81 exposes only the sidewall of the dummy word line 70' located in the insulating layer 11. The sidewall of the dummy word line 70' located in the sacrificial layer 12 is surrounded by the sacrificial layer 12, as Figures 6A to 6C shown, wherein, Figure 6A the plane C1 in [figure] passes through the sacrificial layer 12, Figure 6B the plane C2 in [figure] and Figure 6C the plane C3 in [figure] both pass through the dummy word line 70'.

[0199] The width of the first trench is the same as the shortest distance between two adjacent dummy word lines in the column direction. The first trench may expose the dummy word line of the insulating layer. The dummy word line located in the sacrificial layer is wrapped by the sacrificial layer on all sides.

[0200] S50: Etch back the sacrificial layer 12 in the first trench 81 and the second trench 82 so that the first trench 81 and the second trench 82 expand towards the sacrificial layer 12 until the expanded first trench 81 exposes the sidewalls of the dummy word line 70' located in the insulating layer 11 and the sacrificial layer 12 at the same time, ensuring that the sacrificial layer on both sides of the dummy word line is disconnected. The size of the etch back is approximately the pitch of the sacrificial layer outside the dummy word line in the second direction, and the size of the remaining sacrificial layer in the second direction is approximately equal to the size of the corresponding dummy word line in the second direction; the disconnected sacrificial layers are respectively the regions for the second electrodes of the transistors to be formed, the regions for the first electrodes and the bit lines; Fill the insulating layer 11 in the first trench 81, the second trench 82 and the regions after the sacrificial layer is etched back, as Figure 7A and Figure 7B shown.

[0201] S60: Remove the insulating layer 11 in the second trench 82. The second trench 82 exposes the sacrificial layer 12 on both sides, as Figure 8A and Figure 8B shown.

[0202] S70: Etch back the sacrificial layer 42 in the second trench 82 by wet etching until the sacrificial layer 12 is removed, exposing two opposite sidewalls of the dummy word line 70' in the first direction. The space vacated after etching the sacrificial layer 42 includes the third trench 83 and the fourth trench 84 respectively located on both sides of the dummy word line 70'. The third trench 83 communicates with the first trench 81 in the direction perpendicular to the substrate 10, and the fourth trench 84 communicates with the second trench 82 in the direction perpendicular to the substrate 10, as Figure 9A and Figure 9B shown.

[0203] S80: Fill the conductive layer 50 into the third trench 83 and the fourth trench 84 from the exposed two sides of the dummy word line 70'.

[0204] Exemplarily, step S80 may include:

[0205] S81: Fill the conductive layer 50 into the second trench 82, the third trench 83 and the fourth trench 84 from the exposed two sides of the dummy word line 70', and make the conductive layer 50 cover the sidewalls on both sides of the second trench 82, as Figure 10A and Figure 10B shown.

[0206] Exemplarily, the conductive layer 50 may be a single-layer or multi-layer structure. For example, it may be a double-layer structure including a metal conductive layer and a contact layer. When depositing the conductive layer 50, first deposit the contact layer on the inner wall of the third trench 83, and then fill the third trench 83 with the metal conductive layer.

[0207] S82: Remove the conductive layer 50 on the bottom and two sidewalls of the second trench 82 to expose the insulating layer 11 on one side of the second trench 82. Space the conductive layer 50 in the fourth trench 84 in a direction perpendicular to the substrate 10 to form the first electrode 41 and a plurality of bit lines 30 extending along the second direction. The conductive layer 50 located in the third trench 83 forms the second electrode 42. A plurality of first electrodes 41 in the same layer are connected to the same bit line 30, as Figure 11A and Figure 11B shown.

[0208] S90: Etch the insulating layer 11 that wraps the end of the second electrode 42 away from the bit line 30 in the second trench 82 to expose a certain depth of the sidewall at the end of the second electrode 42 away from the bit line 30. Form a support layer 13 in the second trench 82, and the second electrode 42 extends into the support layer 13, as Figure 12A and Figure 12B shown.

[0209] S100: Remove the insulating layer 11 covering the inner electrode 61 to expose the sidewalls of the inner electrode 61, as Figure 13A and Figure 13B shown.

[0210] The exposed surfaces of the inner electrode 61 are all TiN, and the inside is a metal conductive layer wrapped by TiN. The TiN surface is beneficial for directly depositing the dielectric layer and the outer electrode of the capacitor subsequently.

[0211] S110: Deposit a dielectric layer 62 and an outer electrode 63 in sequence on the exposed area of the inner electrode 61. The inner electrode 61, the dielectric layer 62, and the outer electrode 63 constitute the capacitor 60, as Figure 14A and Figure 14B shown.

[0212] S120: Etch and remove the body of the dummy word line 70' in the first hole K1 to form a word line hole. The protruding part of the remaining dummy word line 70' is ring-shaped. Form a semiconductor layer 43, a gate insulating layer 44, and a word line 70 in sequence in the word line hole, as Figure 15A and Figure 15B shown.

[0213] S130: Etch and form a second hole K2 between two adjacent first holes K1 along the second direction. The two sides of the second hole K2 expose the ring-shaped protruding parts of two adjacent dummy word lines 70', and the protruding parts are located in the parasitic MOS region, as Figure 16 shown.

[0214] S140: Remove the ring-shaped protruding parts to expose the semiconductor layer 43 in the parasitic MOS region 200, and retain the semiconductor layer 43 in the channel region 300, as Figure 17Aand Figure 17B as shown

[0215] S150: Remove the semiconductor layer 43 in the parasitic MOS region 200. The remaining semiconductor layer 43, the first electrode 41, the second electrode 42, and a partial region of the word line 70 surrounded by the remaining semiconductor layer 43 form a transistor 40. Fill an insulating layer 11 between adjacent transistors 40 to obtain a semiconductor device as shown Figures 1A to 1C as shown

[0216] The embodiment of the present application further provides an electronic device, and the electronic device includes the semiconductor device provided by the embodiment of the present application

[0217] In an exemplary embodiment of the present application, the electronic device may be: a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply, etc. The storage device may include the memory in a computer, etc., which is not limited herein

[0218] Although the disclosed embodiments of the present application are as above, the described content is only an embodiment adopted for facilitating the understanding of the present application, and is not used to limit the present application. Any person skilled in the art within the scope of the present application can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed by the present application. However, the protection scope of the present application shall still be subject to the scope defined by the appended claims

Claims

1. A semiconductor device, characterized in that, Comprising: A plurality of memory cells, distributed in different layers and stacked in a direction perpendicular to the substrate; the memory cells include a first electrode of a transistor arranged in a first direction parallel to the substrate, a semiconductor layer, and a second electrode. A plurality of bit lines extending in a second direction parallel to the substrate, the bit lines being connected to the first electrode, and the first direction intersecting the second direction. Each of the bit lines is connected to the transistors of a column of the memory cells in the same layer, and the bit lines and the connected transistors are periodically distributed in the first direction. Both the first electrode and the second electrode have a first end face in contact with the semiconductor layer, a second end face opposite to the first end face, and side walls between the first end face and the second end face. A contact layer covering the first end face and each side wall of the first electrode and the second electrode.

2. The semiconductor device according to claim 1, wherein The memory cell further includes a capacitor, the capacitor including an inner electrode, a dielectric layer, and an outer electrode, the inner electrode being a part of the second electrode, and the dielectric layer and the outer electrode are sequentially wrapped around the side walls of the second electrode and in contact with the contact layer on each side wall.

3. The semiconductor device according to claim 1 or 2, wherein Also included is a word line extending in a direction perpendicular to the substrate, the word line passing through the memory cells of different layers, the semiconductor layer being annular around the word line, and the semiconductor layers of the memory cells of different layers being disconnected.

4. The semiconductor device according to claim 1 or 2, characterized in that, The first electrode and the bit line are of an integral structure; the vertical side wall and the upper and lower horizontal side walls of the integral structure close to the semiconductor layer are covered with a contact layer, and the vertical side wall of the bit line far from the semiconductor layer is not covered with the contact layer.

5. A method for manufacturing a semiconductor device, characterized in that, The semiconductor device includes: different layer memory cells stacked in a direction perpendicular to the substrate and bit lines extending in a direction parallel to the substrate, each of the bit lines being connected to the transistors of a column of the memory cells in the same layer, and the bit lines and the connected transistors being periodically distributed in the first direction. The manufacturing method includes: Successively and alternately depositing an insulating layer and a sacrificial layer on the substrate to obtain a stacked structure. Forming a plurality of first holes penetrating the stacked structure by etching, the plurality of first holes being spaced apart in a first direction and a second direction parallel to the substrate, and forming dummy word lines in the first holes. Forming a first trench extending in the first direction and penetrating the stacked structure at every other first hole in the second direction of the stacked structure, and forming a second trench extending in the second direction between any two adjacent columns of first holes; the first trench exposes the side walls of the dummy word lines located in the insulating layer and the sacrificial layer, and the sacrificial layers located on both sides of the first hole in the first direction are disconnected. Filling the insulating layer in the first trench. Etching back the sacrificial layer exposed by the two second trenches in the adjacent second trenches until the two opposite side walls of the dummy word line in the first direction are exposed, and the space after etching the sacrificial layer includes a third trench and a fourth trench located on both sides of the dummy word line respectively. Depositing a conductive layer in the second trench, the third trench, and the fourth trench, and the conductive layer fills the third trench and the fourth trench.

6. The manufacturing method according to claim 5, characterized in that, Depositing a conductive layer in the second trench, the third trench, and the fourth trench includes: Depositing a conductive layer in the second trench, the third trench, and the fourth trench; Removing the conductive layer at the bottom and two sidewalls of the second trench, forming a first electrode and a bit line in the fourth trench on one side of the dummy word line, and forming a second electrode in the third trench on the other side of the dummy word line. At the same time, the second electrodes in different layers are disconnected from each other, and the bit lines in different layers are disconnected from each other.

7. The manufacturing method according to claim 6, characterized in that, Depositing a conductive layer in the second trench, the third trench, and the fourth trench includes: Successively depositing a contact layer and a metal conductive layer in the second trench, the third trench, and the fourth trench. The metal conductive layer fills the third trench and the fourth trench, and the contact layers of the third trench and the fourth trench are respectively in contact with the dummy word line.

8. The manufacturing method according to claim 7, characterized in that, Further included is: After filling the conductive layer in the third trench and the fourth trench, performing an etch-back on the insulating layer exposed in the adjacent second trench, and filling a support layer in the second trench and the etched-back area. The material of the support layer is different from the material of the insulating layer.

9. The manufacturing method according to claim 8, wherein, Further included is: After forming the support layer, Removing the insulating layer covering the second electrode to expose the sidewalls of the second electrode away from the dummy word line, and successively depositing a dielectric layer and a conductive layer on the exposed area of the second electrode.

10. The manufacturing method according to any one of claims 5 to 9, characterized in that, Forming a plurality of first holes penetrating the stacked structure by etching, and forming a dummy word line in the first holes includes: Etching the stacked structure to form initial holes penetrating the stacked structure; Performing a lateral etch on the insulating layer in the initial holes to form the first holes; Forming the dummy word line in the first holes. The dummy word line includes a body extending in a direction perpendicular to the substrate and a protrusion extending into the insulating layer.

11. The manufacturing method according to claim 10, characterized in that, Forming a first trench extending in the first direction and penetrating the stacked structure at intervals of one of the first holes in the second direction of the stacked structure, and forming a second trench extending in the second direction between every two adjacent columns of first holes; The first trench exposes the sidewalls of the dummy word line located in the insulating layer and the sacrificial layer, and the sacrificial layer located on both sides of the first hole in the first direction is disconnected, including: Forming a first trench extending in the first direction and penetrating the stacked structure at intervals of one of the first holes in the second direction of the stacked structure, and forming a second trench extending in the second direction between every two adjacent columns of first holes. Each of the second trenches intersects with a plurality of the first trenches only on the same side. The first trench only exposes the sidewalls of the dummy word line located in the insulating layer, and the sidewalls of the dummy word line located in the sacrificial layer are surrounded by the sacrificial layer; Performing an etch-back on the sacrificial layer in the first trench and the second trench, so that the first trench and the second trench expand towards the sacrificial layer. After expansion, the first trench exposes the sidewalls of the dummy word line located in the insulating layer and the sacrificial layer at the same time.

12. The manufacturing method according to claim 10, characterized in that, Further included is: Remove the body of the dummy word line and retain the protruding portion to form a word line hole, and sequentially form a semiconductor layer, a gate insulating layer, and a word line in the word line hole; Remove the protruding portion to expose the semiconductor layer, and remove the exposed semiconductor layer.

13. The manufacturing method according to claim 12, characterized in that, The removing the body of the dummy word line and retaining the protruding portion to form a word line hole, and sequentially forming a semiconductor layer, a gate insulating layer, and a word line in the word line hole includes: Etch and remove the body of the dummy word line located in the initial hole, and the protruding portion of the dummy word line retained to form the word line hole is annular. Sequentially form a semiconductor layer, a gate insulating layer, and a word line in the word line hole; Remove the protruding portion to expose the semiconductor layer, and the removing the exposed semiconductor layer includes: Etch between two adjacent first holes along the second direction to form a second hole. The two sides of the second hole respectively expose the annular protruding portions of two adjacent dummy word lines, and the protruding portions are located in the parasitic MOS region; Remove the annular protruding portion to expose the semiconductor layer located in the parasitic MOS region; Remove the semiconductor layer located in the parasitic MOS region; Fill the insulating layer between adjacent transistors.

14. The manufacturing method according to claim 10, characterized in that, Filling the insulating layer in the first trench includes: Deposit the insulating layer in the first trench and the second trench, and fill the insulating layer in the first trench; Remove the insulating layer in the second trench, and the two ends of the sacrificial layer are exposed by two adjacent second trenches.

15. An electronic device, characterized in that, Include the semiconductor device according to any one of claims 1 to 4, or the semiconductor device manufactured by the method according to any one of claims 5 to 14.

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