A high-K metal field plate silicon carbide on insulator power device

Abstract

This invention discloses a silicon carbide power device on a high-k metal field plate insulator, comprising a silicon carbide active region and a high-k metal gate structure arranged sequentially from bottom to top. The high-k metal gate structure includes a metal gate and a high-k dielectric material at least partially covering the top of the metal gate. A source and a drain are respectively disposed on the top of the silicon carbide active region located on both sides of the high-k metal gate structure. The source is provided with a finger-shaped field plate located on top of the high-k dielectric and above the metal gate. The finger-shaped field plate includes several fingers. Each finger is arranged along the width direction of the metal gate, with one end connected to the source and the other end extending beyond the long side of the metal gate on the side away from the source. This invention can effectively ensure the gate stability of the device and reduce the channel resistance. At the same time, it can introduce an electric field peak on the surface of the silicon carbide active region, optimize the electric field distribution on the surface of the silicon carbide active region, and solve the problem of premature breakdown of the device due to excessive concentration of the electric field on the surface of the silicon carbide active region near the edge of the metal gate.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor technology, and in particular to a high-K metal field plate silicon carbide on insulator power device. Background Technology

[0002] Power semiconductor devices are one of the cornerstones of modern semiconductor electronics, and silicon carbide materials have been widely used and promoted due to their excellent performance. However, excessive substrate leakage current and gate reliability issues have become major obstacles to the development of silicon carbide power devices.

[0003] Excessive substrate leakage current increases device energy loss and affects its switching characteristics. To address this issue, a silicon carbide-on-insulator (SiC-OI) structure is proposed, which significantly reduces substrate leakage current and improves vertical breakdown through dielectric isolation.

[0004] However, in the silicon dioxide / 4H-SiC interface, the silicon carbide near the interface contains numerous traps that significantly reduce the device channel mobility, leading to unstable threshold voltage and greatly reduced gate reliability. Furthermore, device design also faces the problem of uneven surface electric field distribution and excessively high electric field peaks causing premature device breakdown.

[0005] Silicon carbide-on-insulator (SiCOI) structures have attracted widespread attention due to their excellent dielectric isolation, faster switching speeds, and lower leakage current. However, SiCOI devices also face challenges such as low channel mobility and uneven surface electric field distribution in the drift region, which greatly limit their application potential. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to address the shortcomings of the prior art by providing a high-K metal field plate silicon carbide on insulator power device, which can simultaneously solve the gate reliability problem and the surface electric field uniform distribution problem.

[0007] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0008] A silicon carbide power device on a high-K metal field plate insulator includes a silicon carbide active region and a high-K metal gate structure arranged sequentially from bottom to top.

[0009] The high-K metal gate structure includes a metal gate and a high-K dielectric that at least partially encloses the top of the metal gate.

[0010] The active and drain electrodes are respectively located on the top of the silicon carbide active regions on both sides of the high-K metal gate structure.

[0011] The source is provided with a finger-shaped field plate located on top of the high-k dielectric and above the metal gate.

[0012] Finger-type field plates include those evenly spaced along the length of the metal gate. X f Each finger is arranged along the width of the metal gate, with one end connected to the source and the other end extending beyond the long side of the metal gate away from the source.

[0013] Number of fingers X f The value is determined based on the FOM peak value of the device.

[0014] X f =3, the length of each finger extending beyond the long side of the metal gate is 3. L fp ,but L fp =1~2 µm.

[0015] The width of each finger W f The value range is 0.5 µm to 1.5 µm, and the specific value is determined based on the optimal value of the device's FOM.

[0016] Spacing between adjacent fingers d The values ​​range from 0.5 µm to 1.5 µm, and satisfy the following conditions: W f : d = 1:1 or 1:2.

[0017] The high-K metal gate structure is a composite high-K metal gate structure, which includes a bottom dielectric layer, a metal gate, and a high-K dielectric. The bottom dielectric layer is disposed on top of the silicon carbide active region, and the metal gate is disposed on top of the bottom dielectric layer. The high-K dielectric covers the metal gate around and on top. The dielectric constant of the bottom dielectric layer is less than or equal to the dielectric constant of the high-K dielectric.

[0018] The high-k dielectric is a high-k dielectric material filled with a dielectric constant greater than that of silicon dioxide, and its dielectric constant is not less than that of the bottom dielectric layer.

[0019] The metal gate is made of titanium nitride.

[0020] The drain electrode is provided with a drain field plate located on top of the high-K dielectric and facing the finger field plate, and the length of the drain field plate facing the finger field plate is greater than or equal to 1 micrometer.

[0021] The active region of silicon carbide has a semiconductor drift region, and the doping concentration of the semiconductor drift region is... N d It can reach 3.5×1016 cm -3 .

[0022] The present invention has the following beneficial effects:

[0023] 1. This invention, from a three-dimensional perspective, introduces a high-K metal gate structure and a finger-shaped field plate on the basis of a silicon carbide-on-insulator structure. The high-K metal gate structure improves gate stability, reduces device channel resistance, and increases device breakdown voltage by optimizing the interface defects of the high-K dielectric / 4H-SiC and mitigating the surface electric field spikes of the silicon carbide active region. The finger-shaped field plate reshapes the surface electric field distribution of the silicon carbide active region through potential modulation, further optimizing the surface electric field distribution of the silicon carbide active region, alleviating the problem of premature device breakdown caused by the concentration of electric field at the edge of the metal gate, and providing a new paradigm for the innovative application of finger-shaped field plates in high-voltage power devices.

[0024] 2. By rationally setting parameters such as the number of fingers, finger length, and finger width of the finger-shaped field plate, this invention can better suppress the problem of excessive electric field concentration at the edge of the metal gate, further improve the device breakdown voltage, and reduce the device on-resistance. At the same time, the finger-shaped field plate can also reduce the gate-drain capacitance of the device and improve dynamic performance.

[0025] 3. The silicon carbide structure on the insulator of this invention can provide better dielectric isolation and effectively reduce substrate leakage current. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the structure of a silicon carbide power device on a high-K metal field plate insulator according to the present invention.

[0027] Figure 2 This is a schematic diagram after step 1 of the method for fabricating silicon carbide power devices on high-K metal field plate insulators according to the present invention.

[0028] Figure 3 This is a schematic diagram showing the results after steps 2-4 of the high-K metal field plate insulator silicon carbide power device fabrication method of the present invention.

[0029] Figure 4 This is a schematic diagram showing the results after steps 5-6 of the high-K metal field plate insulator silicon carbide power device fabrication method of the present invention.

[0030] Figure 5 This is a schematic diagram after step 7 of the method for fabricating silicon carbide power devices on high-K metal field plate insulators according to the present invention.

[0031] Figure 6 This is a schematic diagram after step 8 of the method for fabricating silicon carbide power devices on high-K metal field plate insulators according to the present invention.

[0032] Figure 7 For along Figure 6 Longitudinal section view of line A in the middle.

[0033] Figure 8 The curves show the effect of the number of fingers on the device performance of the finger-type field plate; where (a) is the relationship between the number of fingers and the breakdown voltage; (b) is the relationship between the number of fingers and the specific on-resistance; and (c) is the relationship between the number of fingers and the FOM.

[0034] Figure 9 For finger-shaped field plate L fp The curves showing the impact on device performance; where (a) is... L fp The curve showing the relationship between the voltage and the breakdown voltage; (b) is L fp The curve showing the relationship between the on-resistance and the specific resistance; (c) is L fp The relationship curve with FOM.

[0035] Figure 10 The width of the fingers in the finger-shaped field plate W f The curves showing the impact on device performance; where (a) is the curve showing the relationship between finger width and breakdown voltage; (b) is the curve showing the relationship between finger width and specific on-resistance; and (c) is the curve showing the relationship between finger width and FOM.

[0036] Figure 11 Semiconductor drift region concentration for three different devices N d The curves showing the impact on device performance; where (a) is... N d The curve showing the relationship between the voltage and the breakdown voltage; (b) is N d The curve showing the relationship between the on-resistance and the specific resistance; (c) is N d The relationship curve with FOM.

[0037] Figure 12 The semiconductor drift region concentration of conventional devices N d The curves showing the impact on device performance; where (a) is... N d The curve showing the relationship between the voltage and the breakdown voltage; (b) is N d The curve showing the relationship between the on-resistance and the specific resistance; (c) is N d The relationship curve with FOM.

[0038] Figure 13This is a schematic diagram of the 3D surface electric field distribution of a silicon carbide lateral power device on a conventional insulator.

[0039] Figure 14 This is a schematic diagram of the 3D surface electric field distribution of the silicon carbide power device on the high-K metal field plate insulator of the present invention.

[0040] Figure 15 The graph shows the relationship between gate charge and gate voltage for two different devices.

[0041] Figure 16 The graph shows the relationship between the gate-drain capacitance and the drain voltage for two different devices.

[0042] The following are the labels in the diagram: 1. Substrate; 2. Buried oxide layer; 3. Silicon carbide active region; 4. Semiconductor P-well region; 5. Semiconductor bulk contact P+ region; 6. Semiconductor N+ source region; 7. Semiconductor drift region; 8. Semiconductor drain region; 9. Bottom dielectric layer; 10. Metal gate; 11. Source; 12. Finger field plate; 13. High-K dielectric; 14. Drain field plate; 15. Drain. Detailed Implementation

[0043] The present invention will now be described in further detail with reference to the accompanying drawings and specific preferred embodiments.

[0044] In the description of this invention, it should be understood that the terms "left side," "right side," "upper part," "lower part," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. "First," "second," etc., do not indicate the importance of the components, and therefore should not be construed as a limitation of this invention. The specific dimensions used in this embodiment are only for illustrating the technical solution and do not limit the scope of protection of this invention.

[0045] This example uses a silicon carbide-based N-type drift region power device on an insulator as an example to illustrate the high-K metal field plate silicon carbide power device on an insulator in detail. In addition, the high-K metal field plate structure of the present invention is also applicable to various lateral power devices such as P-type drift region lateral double diffusion power devices, HEMT devices, and lateral power devices without buried oxide layer isolation.

[0046] like Figure 1 and Figure 7 As shown, a high-K metal field plate silicon carbide power device on insulator includes a substrate 1, a buried oxide layer 2, a silicon carbide active region 3 and a high-K metal gate structure arranged sequentially from bottom to top.

[0047] The aforementioned buried oxide layer can separate the substrate 1 and the silicon carbide active region 3.

[0048] The preferred material for the active region of the aforementioned silicon carbide is silicon carbide, but other wide bandgap semiconductor materials such as silicon and gallium nitride can also be used.

[0049] The aforementioned silicon carbide active region includes a semiconductor P-well region 4, a semiconductor drain region 8, and a semiconductor drift region 7. Preferably, the semiconductor P-well region is located at the upper left corner of the silicon carbide active region, and this upper left corner includes a semiconductor body contact P+ region 5 and a semiconductor N+ source region 6 arranged side-by-side from the outside in. The semiconductor drain region 8 is preferably located at the upper right corner of the silicon carbide active region.

[0050] The high-K metal gate structure is preferably a composite high-K metal gate structure, which preferably includes a bottom dielectric layer 9, a metal gate 10, and a high-K dielectric layer 13. The bottom dielectric layer is disposed on top of the silicon carbide active region, and the metal gate is disposed on top of the bottom dielectric layer.

[0051] The high-k dielectric described above at least partially covers the top of the metal gate; in this embodiment, it is preferably covered around and on top of the metal gate. The high-k dielectric is a high-k dielectric material with a dielectric constant greater than that of silicon dioxide, and its thickness is preferably 1 micrometer. The high-k dielectric can improve channel mobility, reduce interface state density, and simultaneously enhance the metal gate capacitance and reduce channel resistance by utilizing its higher dielectric constant.

[0052] The dielectric constant of the aforementioned bottom dielectric layer is less than or equal to that of the high-k dielectric, and is preferably silicon dioxide or hafnium dioxide. In this embodiment, the bottom dielectric layer is preferably hafnium dioxide with a thickness of 50 nanometers, and the high-k dielectric is preferably hafnium dioxide or a material with a higher dielectric constant than hafnium dioxide, such as La2O3.

[0053] The bottom dielectric layer uses HfO2, which has a lower dielectric constant than La2O3. This is mainly because La2O3 and other materials with excessively high dielectric constants have poor interface quality with the semiconductor and a very narrow bandgap, which may lead to problems such as excessive leakage current. Therefore, using a bottom dielectric layer with a slightly lower dielectric constant as a transition layer can avoid direct contact with the semiconductor, while simultaneously increasing the overall dielectric constant of the high-k metal gate structure, which is beneficial for improving device performance.

[0054] Hafnium dioxide (HfO2) is used as the gate dielectric and field oxide layer in the device structure. In the off-state, the excellent electric field modulation effect of the high-k dielectric helps to increase the breakdown voltage (BV); in the on-state, the high-k dielectric enhances channel mobility, thereby reducing channel resistance. Preliminary simulation results show that the breakdown voltage of the silicon carbide-on-insulator lateral power device with a high-k metal gate structure can reach up to 1398 V, which is higher than that of conventional silicon carbide-on-insulator lateral power devices (breakdown voltage...). BV = 1231 V) improved by 13.5%. Meanwhile, its channel mobility exceeds 300 cm² / (V·s), resulting in a lower specific on-resistance. Ron,sp It decreased by 24%.

[0055] When HfO2 is used as the bottom dielectric layer, the bottom dielectric layer and the high-k dielectric are collectively referred to as the high-k gate dielectric. The high-k gate dielectric can effectively reduce the interface state density D in SiC power MOSFETs. it This improves channel carrier mobility and significantly reduces device on-resistance. While traditional SiO2 gate dielectrics can enhance channel mobility through oxidation followed by annealing, this type of N-based... X The annealing process of O is usually accompanied by a threshold voltage V. th The issue of instability. In contrast, SiC devices employing high-k metal gate structures exhibit almost no drift in their flat-band voltage, and their threshold voltage is insensitive to changes in the starting gate voltage and scan speed, effectively improving gate reliability. Simultaneously, the high-k metal gate structure has a positive effect on improving the device's TDDB (Time-Dependent Dielectric Breakdown) lifetime.

[0056] Breakdown in power devices like silicon carbide (SiC) and silicon often occurs in regions of highest impact ionization, which typically correspond to locations of strongest electric fields. According to the potential gradient relationship, the denser the equipotential lines, the stronger the electric field. For SiC lateral power devices on insulators, a high-k gate dielectric can effectively control the potential line distribution within the device, particularly at the right edge of the gate and the left edge of the drain, helping to alleviate electric field concentration issues, thereby suppressing premature breakdown and increasing the breakdown voltage. Simultaneously, this structure also improves the tolerance of the semiconductor drift region to doping concentration; the increased semiconductor drift region concentration will reduce the specific on-resistance.

[0057] The aforementioned metal gate is preferably titanium nitride (TiN), which has higher work function and thermal stability. Simulation results show that the threshold voltage of the silicon carbide lateral double-diffused power device on a high-K metal gate insulator containing TiN, extracted by the maximum transconductance method, is... V th The voltage reached 4.62 V, which is a 13.8% improvement compared to aluminum gate devices (4.06 V).

[0058] For high-k metal gate structures, their higher dielectric constant allows for an increase in the physical thickness of the high-k dielectric without increasing the equivalent oxide thickness (EOT).

[0059] Source 11 and drain 15 are respectively disposed on the top of the silicon carbide active regions on the left and right sides of the high-K metal gate structure; wherein, the bottom of the source is in contact with the semiconductor P-well region, and the bottom of the drain is in contact with the semiconductor drain region.

[0060] Field plate technology, with its simple fabrication process, excellent compatibility, and effective surface electric field modulation capability, is widely used in junction termination protection. In SiCOI devices, the integration of high-k metal gate structures with field plate technology is expected to effectively optimize the surface electric field in the silicon carbide (SiC) drift region.

[0061] In this invention, the source electrode is provided with a finger-shaped field plate 12 deposited on top of a high-k dielectric and above a metal gate. The combination of the finger-shaped field plate and the high-k dielectric effectively optimizes the static performance of the device. The static performance includes breakdown voltage and specific on-resistance.

[0062] Finger-type field plates include those evenly spaced along the length of the metal gate. X f Each finger is arranged along the width of the metal gate, that is, extending from the right edge of the source towards the center of the semiconductor drift region. One end of each finger is connected to the source, and the other end extends beyond the long side of the metal gate away from the source.

[0063] The number of fingers mentioned above X f It is determined based on the peak value of the device's quality factor (FOM).

[0064] The number of fingers in a finger-shaped field plate has a crucial impact on the surface electric field distribution and static properties. This study sets the width of the basic simulation element to 5.5 µm, and by setting... X f = 1 to 6, studying the impact of the number of fingers on device performance. For example... Figure 8 As shown, when X f When the value is 3, the device's quality factor (FOM) reaches its peak (1070 MV / cm²). X f =4 and X f =5 has a slightly lower FOM (approximately 1000 MV / cm²). However, the number of fingers... X f A value greater than 3 increases the process complexity; therefore, in this embodiment, it is preferable to... X f =3.

[0065] The length of each finger extending beyond the long side of the metal gate (i.e., the right edge of the metal gate) is... L fp The specific value is determined based on the optimal range of the device's FOM (Form of Memory). For example... Figure 9 As shown, the simulation results indicate that when L fp When the length is 1~2 µm, the device performance FOM is optimal, which indicates that the fingers used in high-K metal gate structures should not be too long.

[0066] To avoid the field oxide layer surface being completely covered by metal, W f The width of each finger must not exceed 1.5 µm. W f The preferred value range is 0.5 µm to 1.5 µm, specifically determined based on the optimal value of the device's FOM. For example... Figure 10 show, W f Compared to on-resistance, which has a smaller impact, breakdown voltage varies. W f An increase in the rate of decline leads to a decrease in the Form of Meaning (FOM). For example, when... W f When the finger width is increased from 0.5 µm to 1 µm, the FOM decreases by 11.5%. Therefore, considering practical manufacturing feasibility, the finger width should be as small as possible. This invention reduces the finger width... W f The value is set to 0.5 µm. A performance comparison is made between the optimized high-K metal field plate silicon carbide-on-insulator lateral power device and the high-K metal gate structure silicon carbide-on-insulator lateral power device. Figure 11 As shown, its FOM improved by 28.4%, mainly due to the optimized modulation of the electric field by the finger-shaped field plate.

[0067] Furthermore, the spacing between adjacent fingers d The values ​​range from 0.5 µm to 1.5 µm, and satisfy the following conditions: W f : d =1:1 or 1:2. A reasonable finger spacing helps ensure that the electric field peaks introduced by the finger field plate on the surface of the semiconductor drift region are close and do not overlap, which helps to better optimize the surface electric field of the device and improve the device breakdown voltage and specific on-resistance.

[0068] The drain is provided with a drain field plate located on top of the high-K dielectric and facing the finger field plate, and the length of the drain field plate toward the finger field plate (that is, the length extending from the left edge of the drain to the center of the semiconductor drift region) is greater than or equal to 1 micrometer.

[0069] Finger-type field plates and drain field plates can shield the gate-drain capacitance of a device. For example... Figure 16 As shown, when a frequency is applied between the gate and drain... f When a small-signal sinusoidal voltage of 1MHz is applied and the gate is grounded, the gate voltage is... V gs =0V, the gate-drain capacitance of silicon carbide-on-insulator lateral power devices containing high-K metal gate structure, finger field plate and drain field plate is reduced by 69.3% compared with silicon carbide-on-insulator lateral power devices with only high-K metal gate structure.

[0070] After adopting the high-k metal gate structure and finger-shaped field plate structure of the present invention, the doping concentration of the semiconductor drift region is reduced under their synergistic effect. N d It can reach 3.5×10 16 cm -3 .

[0071] In this invention, three different silicon carbide-on-insulator lateral power devices were simulated and designed, namely, silicon carbide-on-insulator lateral power devices with only high-k metal gate structures ( Figure 11 (referred to as high-K metal gate structure in Chinese) is a silicon carbide-on-insulator lateral power device with a high-K metal gate structure and a conventional planar source field plate. Figure 11 (referred to as high-K metal gate structure + conventional field plate), a silicon carbide-on-insulator lateral power device having a high-K metal gate structure and the finger-shaped field plate of this invention ( Figure 11 (Simply referred to as high-K metal gate structure + finger field plate), this describes the semiconductor drift region doping concentration of silicon carbide lateral power devices on three different insulators. N d The effects of these factors on breakdown voltage, specific on-resistance, and FOM were simulated and plotted as follows: Figure 11 The relationship curve shown. From Figure 11 As can be seen, the optimal FOM value of the silicon carbide-on-insulator (SiCII) lateral power device with only a high-K metal gate structure is not significantly different from that of the SiCII lateral power device with a high-K metal gate structure and a conventional planar source field plate. This indicates that the conventional planar source field plate has a limited optimization effect on the SiCII lateral power device with a high-K metal gate structure. However, compared with the conventional SiCII lateral power device (… Figure 12 For conventional devices (referred to as conventional devices), the optimal FOM was improved by 114%, fully demonstrating the advantages of high-K metal gate structures. This is mainly due to the following three points:

[0072] A. High-K gate dielectric improves channel mobility.

[0073] B. High dielectric constant reduces threshold voltage V th Thus, at the same gate voltage ( V gs Reduce the on-resistance at 15 V.

[0074] C. High-K field oxide layer enhances the depletion capability of semiconductor drift region.

[0075] from Figure 11 and Figure 12 Simulation results also show that, compared with conventional silicon carbide-on-insulator lateral power devices ( Figure 12 Compared to conventional devices (referred to as conventional devices in Chinese), in terms of gate voltage Vgs At 15 V, the high-K silicon carbide lateral power device on a metal-gate insulator corresponds to the maximum FOM. N d From 1.8 × 10¹ 6 cm⁻³ increased to 3.5×10¹ 6 The specific on-resistance decreased by 42.7% in cm⁻³, while the breakdown voltage only increased by 10.7%, indicating that the decrease in specific on-resistance caused by the increase in doping concentration in the semiconductor drift region is the dominant factor in the improvement of FOM.

[0076] Regarding surface electric field optimization, three-dimensional surface electric field distribution simulations were performed for both conventional silicon carbide lateral power devices on insulators and silicon carbide power devices on insulators with high-K metal field plates as described in this invention.

[0077] like Figure 13 As shown, the surface electric field of a conventional silicon carbide lateral power device on an insulator is "saddle-shaped", with significant electric field accumulation on both sides of the semiconductor drift region, reaching a peak value of 3 MV / cm.

[0078] like Figure 14 As shown, after introducing the finger-shaped field plate, the maximum electric field peak value on both sides of the semiconductor drift region is reduced to 2.3 MV / cm, and a local electric field peak value is formed at the tip of each finger within the semiconductor drift region, exhibiting a multi-peak distribution. This design can alleviate electric field accumulation, thereby effectively avoiding premature breakdown.

[0079] Gate charge Q g These are key parameters affecting the switching speed and dynamic losses of SiC MOS devices. Finger-type field plates and drain field plates help reduce device losses. Q g This improves the dynamic characteristics of high-K metal grid structures.

[0080] In this invention, simulations are performed on two different silicon carbide lateral power devices on insulators.

[0081] 1. Silicon-on-insulator lateral power devices with high-K metal gate structure ( Figure 15 (High-K metal grid, abbreviated as high-K metal grid).

[0082] 2. A silicon carbide-on-insulator lateral power device with a high-K metal gate structure, finger-shaped field plate, and drain field plate. Figure 15 In Chinese, it is simply referred to as a high-K metal gate + multi-finger source field plate + drain field plate.

[0083] For the two types of silicon carbide lateral power devices on different insulators mentioned above, the diagrams are as follows: Figure 15The graph showing the relationship between gate charge and gate voltage reveals the gate voltage of a silicon carbide-on-insulator lateral power device with a high-K metal gate structure, finger field plates, and drain field plates. Q gd1 =66 nC / cm², which is relatively high compared to the gate voltage of silicon carbide-on-insulator lateral power devices with high-K metal gate structures. Q gd2 =114 nC / cm², a decrease of 43%.

[0084] A method for fabricating a silicon carbide power device on a high-K metal field plate insulator includes the following steps.

[0085] Step 1: An oxide layer 2 is formed on a semiconductor silicon substrate 1 by oxidation. The silicon carbide active region 3, doped with the first conductivity type, is then bonded to the oxide layer 2 using a bonding technique to form a structure as shown in the figure. Figure 2 The silicon carbide power device on the insulator is shown; next, the silicon carbide on the insulator is cleaned to remove surface impurities.

[0086] Step 2: Using a photoresist mask and an ion implantation process, a second conductivity type impurity is implanted into the left side of the active region of silicon carbide to form a semiconductor P-well region 4.

[0087] Step 3: Using a photoresist mask and an ion implantation process, high-doped semiconductor impurities of the first conductivity type are implanted into the semiconductor P-well region 4 on the left side of the silicon carbide active region and the outer edge region on the right side of the silicon carbide active region, respectively forming the semiconductor N+ source region 6 and the semiconductor drain region 8.

[0088] Step 4: Using a photoresist mask and an ion implantation process, highly doped semiconductor impurities of the second conductivity type are implanted into the semiconductor P-well region 4 outside the semiconductor N+ source region 6, forming the semiconductor bulk contact P+ region 5. This completes the ion implantation structure of the silicon carbide-on-insulator power device as shown below. Figure 3 As shown.

[0089] Step 5: Using atomic layer deposition technology, an insulating dielectric material is deposited on the surface of the active region of silicon carbide to form a bottom dielectric layer 9. The area covered by the bottom dielectric layer includes the semiconductor P-well region 4, the semiconductor N+ source region 6, the semiconductor drift region 7, and the semiconductor drain region 8, but at the same time, the left and right edges retain the reserved positions for the source and drain contacts.

[0090] Step 6: Planarize the surface of the bottom dielectric layer and deposit the metal gate 10. The completed silicon carbide-on-insulator power device is as follows: Figure 4 As shown.

[0091] Step 7: Using a photoresist mask and a magnetron sputtering instrument, a high-k dielectric material 13 is deposited on the surface of the bottom dielectric layer. The surface of the high-k dielectric is then chemically and mechanically polished to improve surface smoothness. After the high-k dielectric is deposited, the silicon carbide power device on the insulator is as follows: Figure 5 As shown.

[0092] Step 8: Fabricate and form source 11 and drain 15, and deposit finger-shaped field plates 12 and drain field plates 14 on the high-k dielectric surface using electron beam evaporation technology through a photoresist mask. After the field plate deposition is completed, the final structure of the silicon carbide power device on insulator is as follows. Figure 6 and Figure 7 As shown.

[0093] The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present invention, various equivalent transformations can be made to the technical solutions of the present invention, and these equivalent transformations all fall within the protection scope of the present invention.

Claims

1. A silicon carbide power device on a high-K metal field plate insulator, characterized in that: It includes silicon carbide active regions and high-K metal gate structures arranged sequentially from bottom to top; The active region of silicon carbide has a semiconductor drift region, and the doping concentration of the semiconductor drift region is... N d It can reach 3.5×10 16 cm -3 ; The high-k metal gate structure includes a metal gate and a high-k dielectric material that at least partially encloses the top of the metal gate; The active electrode and drain electrode are respectively located on the top of the silicon carbide active region on both sides of the high-K metal gate structure; The source is provided with a finger-shaped field plate located on top of the high-k dielectric and above the metal gate; Finger-type field plates include those evenly spaced along the length of the metal gate. X f Each finger is arranged along the width of the metal gate, with one end connected to the source and the other end extending beyond the long side of the metal gate away from the source. Number of fingers X f The value is determined based on the FOM peak value of the device; The length of each finger extending beyond the long side of the metal gate is [missing information]. L fp ,but L fp =1~2 µm; The width of each finger is W f The distance between adjacent fingers is d ,but W f : d = 1:1 or 1:2; The finger-shaped field plate configuration reduces the maximum electric field peak on both sides of the semiconductor drift region to 2.3 MV / cm, and creates a local electric field peak at the tip of each finger within the semiconductor drift region, thus exhibiting... X f The distribution of local electric field peaks can alleviate electric field accumulation and prevent premature breakdown.

2. The silicon carbide power device on a high-K metal field plate insulator according to claim 1, characterized in that: X f =3。 3. The silicon carbide power device on a high-K metal field plate insulator according to claim 1, characterized in that: The width of each finger W f The value range is 0.5 µm to 1.5 µm, and the specific value is determined based on the optimal value of the device's FOM.

4. The silicon carbide power device on a high-K metal field plate insulator according to claim 3, characterized in that: Spacing between adjacent fingers d The values ​​range from 0.5 µm to 1.5 µm.

5. The silicon carbide power device on a high-K metal field plate insulator according to claim 1, characterized in that: The high-K metal gate structure is a composite high-K metal gate structure, which includes a bottom dielectric layer, a metal gate, and a high-K dielectric. The bottom dielectric layer is disposed on top of the silicon carbide active region, and the metal gate is disposed on top of the bottom dielectric layer. The high-K dielectric covers the metal gate around and on top. The dielectric constant of the bottom dielectric layer is less than or equal to the dielectric constant of the high-K dielectric.

6. The silicon carbide power device on a high-K metal field plate insulator according to claim 5, characterized in that: The high-k dielectric is a high-k dielectric material filled with a dielectric constant greater than that of silicon dioxide, and its dielectric constant is not less than that of the bottom dielectric layer.

7. The silicon carbide power device on a high-K metal field plate insulator according to claim 1 or 5, characterized in that: The metal gate is made of titanium nitride.

8. The silicon carbide power device on a high-K metal field plate insulator according to claim 1, characterized in that: The drain electrode is provided with a drain field plate located on top of the high-K dielectric and facing the finger field plate, and the length of the drain field plate facing the finger field plate is greater than or equal to 1 micrometer.

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