Semiconductor device, power module, power conversion circuit, vehicle, and method for manufacturing semiconductor device

Abstract

The invention discloses a semiconductor device, a power module, a power conversion circuit, a vehicle and a manufacturing method of the semiconductor device, and the semiconductor device comprises a semiconductor body which comprises a well region and a first region, the first region is arranged on a first surface, the well region is arranged on one side, far away from the first surface, of the first region, and the first region is of a first conductivity type; the well region is of a second conductive type; the first surface is provided with a gate trench, the side walls of the gate trench comprise a first side wall and a second side wall, the two side walls are parallel to each other and are respectively in contact with the well region and the first region, and the first side wall and the second side wall belong to a (0338) crystal plane family or a (1120) crystal plane family under the condition of a hexagonal crystal system; the insulating layer is positioned on the bottom wall and the side wall of the gate trench; the grid electrode is positioned on one side, far away from the semiconductor body, of the insulating layer in the grid groove; the source electrode is located on the first surface; the drain electrode is located on the second surface. The first side wall and the second side wall of the gate trench have high electron mobility at the same time, so that the semiconductor device has low on-resistance and high current.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology. More specifically, the present invention relates to a semiconductor device, a power module, a power conversion circuit, a vehicle, and a manufacturing method of the semiconductor device. Background Art

[0002] Silicon carbide (SiC) is a semiconductor material that has properties required for many applications. These properties of the required SiC include a high maximum electron velocity, a high thermal conductivity, and a high electric breakdown field strength; the high maximum electron velocity enables the operation of SiC components at high frequencies, the high thermal conductivity simplifies the discharge of excess heat from SiC components, and the high electric breakdown field strength enables the operation of SiC components at high voltage levels.

[0003] Existing MOSFETs adopt an asymmetric trench structure. The left sidewall of the trench contains a MOS channel, which is aligned to the a-plane surface. Using the surface improves the channel mobility on the left side, but the right channel is not used, or the right side is a channel with higher mobility but the left channel is not used.

[0004] In summary, existing MOSFETs only achieve high mobility on one side of the channel, that is, there is only one channel with high mobility in a single cell, and the channel mobility on the other side is low, and the improvement ratio of Rds_on is limited. Summary of the Invention

[0005] The present invention provides a semiconductor device, a power module, a power conversion circuit, a vehicle, and a manufacturing method of the semiconductor device, aiming to improve the electron mobility on both sides of the gate trench.

[0006] An embodiment of the present invention provides a semiconductor device, including:

[0007] A semiconductor body, including a first surface and a second surface arranged opposite to each other. The semiconductor body includes a well region and a first region. The first region is arranged on the first surface, and the well region is arranged on a side of the first region away from the first surface. The first region is of a first conductivity type, and the well region is of a second conductivity type;

[0008] The first surface is further provided with a gate trench, which extends from the first surface into the semiconductor body. The sidewalls of the gate trench include a first sidewall and a second sidewall. The first sidewall and the second sidewall are parallel and are respectively in contact with the well region and the first region. The first sidewall and the second sidewall belong to the crystal plane family or A family of crystal planes, the semiconductor body further includes an insulating layer, and the insulating layer is located on the bottom wall and side walls of the gate trench;

[0009] A gate, the gate is located on the side of the insulating layer away from the semiconductor body within the gate trench;

[0010] A source electrode, the source electrode is located on the first surface;

[0011] A drain electrode, the drain electrode is located on the second surface.

[0012] Optionally, the side walls of the gate trench belong to a family of crystal planes or a family of crystal planes in the case of a hexagonal crystal system.

[0013] Optionally, the side walls of the gate trench include a first side wall and a second side wall, the first side wall and the second side wall are parallel, and are respectively in contact with the well region and the first region.

[0014] Optionally, the first side wall is in contact with the bottom wall of the gate trench and forms a first included angle, and the first included angle is an acute angle; the second side wall is in contact with the bottom wall of the gate trench and forms a second included angle, and the second included angle is an obtuse angle.

[0015] Optionally, the thickness of the insulating layer at the first included angle is greater than the thickness of the insulating layer at other positions;

[0016] and / or the semiconductor body further includes a spacer insulating layer, the spacer insulating layer is located at the first included angle and is located between the insulating layer and the gate;

[0017] and / or the semiconductor body further includes a buried layer, the buried layer is located on the bottom wall and side walls of the gate trench and covers the first included angle, the buried layer is of a second conductivity type, and the ion concentration of the buried layer is greater than the ion concentration of the well region.

[0018] Optionally, the gate trench includes a first sub-gate trench and a second sub-gate trench, and a plurality of third included angles are formed between the bottom wall and the side walls of the first sub-gate trench and the second sub-gate trench. The first sub-gate trench includes the first side wall and a third side wall arranged oppositely, the first side wall and the third side wall are respectively in contact with the bottom wall of the first sub-gate trench, and the formed third included angle is an obtuse angle; the second sub-gate trench includes the second side wall and a fourth side wall arranged oppositely, the second side wall and the fourth side wall are respectively in contact with the bottom wall of the second sub-gate trench, and the formed fourth included angle is an acute angle.

[0019] Optionally, it further includes a second region located between the first sub-gate trench and the second sub-gate trench. The second region is of a second conductivity type, and the ion concentration of the second region is greater than that of the well region.

[0020] Optionally, the thickness of the insulating layer at the plurality of fourth included angles is greater than that at other positions.

[0021] And / or the semiconductor body further includes a spacer insulating layer located at the plurality of fourth included angles and between the insulating layer and the gate.

[0022] And / or the semiconductor body further includes a buried layer located on the bottom wall and side walls of the second sub-gate trench and covering the plurality of fourth included angles. The buried layer is of a second conductivity type, and the ion concentration of the buried layer is greater than that of the well region.

[0023] In a second aspect, an embodiment of the present invention provides a manufacturing method of a semiconductor device, including:

[0024] Providing a semiconductor structure, the semiconductor structure includes a first surface and a second surface arranged opposite to each other. The semiconductor body includes a well region and a first region. The first region is disposed on the first surface, and the well region is disposed on a side of the first region away from the first surface. The first region is of a first conductivity type, and the well region is of a second conductivity type.

[0025] Forming a gate trench extending from the first surface into the semiconductor body. The side walls of the gate trench include a first side wall and a second side wall. The first side wall and the second side wall are parallel and are respectively in contact with the well region and the first region. The first side wall and the second side wall belong to the crystal plane family or crystal plane family in the hexagonal crystal system; forming an insulating layer on the bottom wall and side walls of the gate trench.

[0026] Forming a gate in the gate trench, and the gate is located on a side of the insulating layer away from the semiconductor body.

[0027] Forming a source electrode on the first surface.

[0028] Forming a drain electrode on the second surface.

[0029] In a third aspect, an embodiment of the present invention provides a power module, including a substrate and at least one semiconductor device according to any embodiment of the present invention. The substrate is used to carry the semiconductor device.

[0030] Fourth aspect, an embodiment of the present invention provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction;

[0031] The power conversion circuit includes a circuit board and at least one semiconductor device according to an embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0032] Fourth aspect, an embodiment of the present invention provides a vehicle, including a load and the power conversion circuit according to an embodiment of the present invention. The power conversion circuit is used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current, and then input it to the load.

[0033] The semiconductor device provided by the technical solution in the embodiment of the present invention includes: a semiconductor body, including a first surface and a second surface arranged opposite to each other. The semiconductor body includes a well region and a first region. The first region is disposed on the first surface, and the well region is disposed on the side of the first region away from the first surface. The first region is of a first conductivity type, and the well region is of a second conductivity type; a gate trench is further provided on the first surface, and the gate trench extends from the first surface into the semiconductor body and is inclined relative to a first direction, where the first direction is the direction from the first surface to the second surface; the semiconductor body further includes an insulating layer, and the insulating layer is located on the bottom wall and side walls of the gate trench; a gate, the gate is located on the side of the insulating layer away from the semiconductor body within the gate trench; a source electrode, the source electrode is located on the first surface; a drain electrode, the drain electrode is located on the second surface. The side walls of the gate trench include a first side wall and a second side wall, the first side wall and the second side wall are parallel and are respectively in contact with the well region and the first region, and the electron migration directions of the first side wall and the second side wall are the same. Since and the electron mobility in this direction is high, therefore, when the side walls of the gate trench are in the hexagonal crystal system, they belong to the crystal plane family or the crystal plane family. The first side wall and the second side wall of the gate trench both have high electron mobility, so that the semiconductor device has a low on-resistance (RDS_on) and a high current. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a schematic structural diagram of the semiconductor device provided in Embodiment 1 of the present invention;

[0035] Figure 2 It is a passivation schematic diagram of the first included angle provided in the embodiment of the present invention. Among them, (a) is the first passivation treatment, (b) is the second passivation treatment, and (c) is the third passivation treatment;

[0036] Figure 3 It is a schematic structural diagram of the semiconductor device provided in Embodiment 2 of the present invention;

[0037] Figure 4 Flow chart of the manufacturing method of the semiconductor device provided by the embodiment of the present invention. Detailed implementation manners

[0038] The following describes the detailed implementation manners of the present invention in further detail by describing the embodiments with reference to the accompanying drawings, so as to help those skilled in the art have a more complete, accurate and in-depth understanding of the inventive concept and technical solution of the present invention.

[0039] Figure 1 Schematic diagram of the semiconductor device structure provided by the first embodiment of the present invention. For the sake of convenience of description, only the parts related to the embodiment of the present invention are shown. The semiconductor device includes:

[0040] A semiconductor body (1), including a first surface and a second surface arranged oppositely. The semiconductor body (1) includes a well region (2) and a first region (3). The first region (3) is arranged on the first surface, and the well region (2) is arranged on the side of the first region (3) away from the first surface. The first region (3) is of a first conductivity type, and the well region (2) is of a second conductivity type;

[0041] A gate trench is further arranged on the first surface. The gate trench extends from the first surface into the semiconductor body (1). The side walls of the gate trench include side wall (41) and side wall (42). The side wall (41) and the side wall (42) are parallel and are respectively in contact with the well region (2) and the first region (3). In the case of a hexagonal crystal system, the side wall (41) and the side wall (42) belong to a crystal plane family or a crystal plane family; The semiconductor body (1) further includes an insulating layer (5), and the insulating layer (5) is located on the bottom wall and side walls of the gate trench;

[0042] A gate (7), and the gate (7) is located on the side of the insulating layer (5) away from the semiconductor body (1) in the gate trench;

[0043] A source electrode (8), and the source electrode (8) is located on the first surface;

[0044] A drain electrode (9), and the drain electrode (9) is located on the second surface.

[0045] Due to and the high electron mobility in the direction, in the case of a hexagonal crystal system, the side walls of the gate trench belong to a crystal plane family or

[0046] a crystal plane family. The side walls (41) and (42) of the gate trench have high electron mobility at the same time, so that the semiconductor device has a low on-resistance (RDS_on) and a high current.In an embodiment of the present invention, the semiconductor body (1) may include a substrate (11) and an epitaxial layer (12). The materials of the substrate (11) and the epitaxial layer (12) may be silicon carbide. An epitaxial layer is formed on one side of the substrate (11). Exemplarily, the epitaxial layer (12) may be formed on the surface of the substrate (11) by epitaxial growth. A well region (2) is provided on the side of the epitaxial layer away from the substrate. A first region (3) is provided on the side of the well region (2) away from the substrate (11). The well region (2) and the first region (3) may be formed by means such as epitaxial growth, ion implantation, or chemical vapor deposition. The well region (2) and the first region (3) are used to form a conductive channel of the semiconductor device. Among them, the first region (3) has a first doping type, and the well region (2) has a second doping type.

[0047] The first doping type in the embodiment of the present invention may be N-type doping, and the second doping type may be P-type doping, or the first doping type may be P-type doping, and the second doping type may be N-type doping. P+ and N+ shown in the drawings indicate that the ion doping concentration in this region is high, and P- and N- indicate that the ion doping concentration in this region is low. Among them, the N-type doping ions may be P (phosphorus) or N (nitrogen) ions, and the P-type doping ions may be Al (aluminum) ions or B (boron) ions. Exemplarily, in the embodiment of the present invention, taking the first doping type as N-type doping and the second doping type as P-type doping as an example, when the semiconductor device is an N-type device, the substrate (11) is N+ type doped, for example, it may be an N+ silicon carbide substrate; the epitaxial layer (12) is N- type doped, for example, it may be an N- silicon carbide epitaxial layer.

[0048] In an embodiment of the present invention, the semiconductor device includes: a third region (10), which is provided on the first surface, on the side of the well region (2) close to the first surface, and is in contact with the first region (3).

[0049] In an embodiment of the present invention, the sidewall (41) contacts the bottom wall of the gate trench and forms a first angle, and the first angle is an acute angle; the sidewall (42) contacts the bottom wall of the gate trench and forms a second angle, and the second angle is an obtuse angle. In order to increase the breakdown voltage, avoid tip discharge, and keep the high channel mobility on both sides of the semiconductor device, passivation treatment needs to be performed on the first angle formed by the sidewall (41) and the bottom wall of the gate trench. The passivation treatment method for the acute angle includes the following:

[0050] The thickness of the insulating layer (5) at the first angle is greater than the thickness of the insulating layer (5) at other positions, as Figure 2 (a) shown;

[0051] and / or the semiconductor body (1) further includes a spacer insulating layer (16), and the spacer insulating layer (16) is located at the first angle and between the insulating layer (5) and the gate (7), as Figure 2 (b) shown

[0052] and / or the semiconductor body (1) further includes a buried layer (13) located at the bottom and side walls of the gate trench and covering the first included angle. The buried layer (13) is of the second conductivity type, and the ion concentration of the buried layer (13) is greater than that of the well region (2), as shown in Figure 2 (c).

[0053] Figure 3 The figure is a schematic structural diagram of the semiconductor device provided by the embodiment of the present invention. For the sake of convenience of description, only the parts related to the embodiment of the present invention are shown. The semiconductor device includes:

[0054] A semiconductor body (1) including a first surface and a second surface arranged oppositely. The semiconductor body (1) includes a well region (2) and a first region (3). The first region (3) is arranged on the first surface, and the well region (2) is arranged on the side of the first region (3) away from the first surface. The first region (3) is of the first conductivity type, and the well region (2) is of the second conductivity type;

[0055] The first surface is further provided with a first sub-gate trench and a second sub-gate trench. The first gate trench and the second sub-gate trench extend from the first surface into the semiconductor body (1) and are inclined relative to the first direction, where the first direction is the direction from the first surface to the second surface. The semiconductor body (1) further includes an insulating layer (51) and an insulating layer (52). The insulating layer (51) is located at the bottom and side walls of the first sub-gate trench, and the insulating layer (52) is located at the bottom and side walls of the second sub-gate trench;

[0056] A first gate (71) located on the side of the insulating layer (51) away from the semiconductor body (1) within the first sub-gate trench;

[0057] A second gate (72) located on the side of the insulating layer (52) away from the semiconductor body (1) within the second sub-gate trench;

[0058] A source electrode (8) located on the first surface;

[0059] A drain electrode (9) located on the second surface.

[0060] In the embodiment of the present invention, the first sub-gate trench includes oppositely arranged side walls (43) and side walls (45). The side walls (43) and side walls (45) are respectively in contact with the bottom wall of the first sub-gate trench, and the formed third included angle is an obtuse angle. The second sub-gate trench includes oppositely arranged side walls (44) and side walls (46). The side walls (44) and side walls (46) are respectively in contact with the bottom wall of the second sub-gate trench, and the formed fourth included angle is an acute angle.

[0061] In an embodiment of the present invention, the electron migration directions of sidewalls (43) and sidewalls (44) are the same. Since and the electron mobility in this direction is high, therefore, in the case of a hexagonal crystal system, sidewalls (43) and sidewalls (44) belong to crystal plane family or crystal plane family. Sidewalls (43) and sidewalls (44) have high electron mobility at the same time, making the semiconductor device have a low on-resistance (RDS_on) and high current.

[0062] In an embodiment of the present invention, the semiconductor body (1) may include a substrate (11) and an epitaxial layer (12). The materials of the substrate (11) and the epitaxial layer (12) may be silicon carbide. An epitaxial layer (12) is formed on one side of the substrate (11). Exemplarily, the epitaxial layer (12) may be formed on the surface of the substrate (11) by epitaxial growth. A well region (2) is provided on the side of the epitaxial layer (12) away from the substrate (11), and a first region (3) is provided on the side of the well region (2) away from the substrate (11). The well region (2) and the first region (3) may be formed by epitaxial growth, ion implantation, or vapor deposition. The well region (2) and the first region (3) are used to form a conductive channel of the semiconductor device, where the first region (3) is of a first doping type and the well region (2) is of a second doping type.

[0063] The first doping type in the embodiment of the present invention may be N-type doping, and the second doping type may be P-type doping, or the first doping type may be P-type doping and the second doping type may be N-type doping. P+ and N+ shown in the drawings indicate that the ion doping concentration in this region is high, and P- and N- indicate that the ion doping concentration in this region is low. Among them, the N-type doping ions may be P (phosphorus) or N (nitrogen) ions, and the P-type doping ions may be Al (aluminum) ions or B (boron) ions. Exemplarily, in the embodiment of the present invention, taking the first doping type as N-type doping and the second doping type as P-type doping as an example, when the semiconductor device is an N-type device, the substrate (11) is of N+ type doping, for example, it may be an N+ silicon carbide substrate; the epitaxial layer (12) is of N- type doping, for example, it may be an N- silicon carbide epitaxial layer.

[0064] In an embodiment of the present invention, the semiconductor device includes: a third region (10), which is provided on the first surface, on the side of the well region (2) close to the first surface, and in contact with the first region (3).

[0065] In an embodiment of the present invention, the semiconductor device further includes a second region (14). The second region (14) is located between the first sub-gate trench and the second sub-gate trench. The second region (14) has a second conductivity type, and the ion concentration of the second region (14) is greater than that of the well region (2). The second region (14) forms a body diode with a relatively large area between the first gate in the first sub-gate trench and the second gate in the second sub-gate trench, improving the maximum instantaneous current and surge current that the body diode can withstand, so as to improve the reliability of the semiconductor device.

[0066] In order to increase the breakdown voltage, avoid tip discharge, and maintain high channel mobility on both sides of the device, it is necessary to passivate the fourth angle. The passivation treatment method includes the following:

[0067] The thickness of the insulating layer (52) at multiple fourth angles is greater than that at other positions;

[0068] And / or the semiconductor body (1) further includes a spacer insulating layer. The spacer insulating layer is located at multiple fourth angles and between the insulating layer (52) and the corresponding gate;

[0069] And / or the semiconductor body (1) further includes a buried layer (15). The buried layer (15) is located on the bottom wall and side wall of the second sub-gate trench and covers multiple fourth angles. The buried layer has a second conductivity type, and the ion concentration of the buried layer (15) is greater than that of the well region (2).

[0070] In an embodiment of the present invention, the semiconductor body (1) further includes a buried layer (15). The buried layer (15) is located on the bottom wall and side wall of the first sub-gate trench and covers multiple third angles. The buried layer (15) has a second conductivity type, and the ion concentration of the buried layer (15) is greater than that of the well region (2).

[0071] Based on the above embodiments, an embodiment of the present invention provides a power module, which includes a substrate and the semiconductor device of any embodiment of the present invention. The substrate is used to carry the semiconductor device.

[0072] The power module provided by the technical solution of the embodiment of the present invention has the same beneficial effects as the semiconductor device of any embodiment of the present invention.

[0073] Based on the above embodiments, an embodiment of the present invention provides a power conversion circuit. The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device of any embodiment of the present invention. The semiconductor device is electrically connected to the circuit board.

[0074] The power conversion circuit provided by the technical solution of the embodiment of the present invention has the same beneficial effects as the semiconductor device of any embodiment of the present invention.

[0075] Based on the above embodiment, the embodiment of the present invention provides a vehicle, including a load and a power conversion circuit according to any embodiment of the present invention. The power conversion circuit is used to convert alternating current into direct current, convert alternating current into alternating current, convert direct current into direct current, or convert direct current into alternating current, and then input it to the load.

[0076] Figure 4 It is a flowchart of a manufacturing method of a semiconductor device provided by an embodiment of the present invention. The method includes:

[0077] Providing a semiconductor structure, the semiconductor structure includes a first surface and a second surface arranged opposite to each other. The semiconductor body (1) includes a well region (2) and a first region (3). The first region (3) is arranged on the first surface, and the well region (2) is arranged on the side of the first region (3) away from the first surface. The first region (3) is of a first conductivity type, and the well region (2) is of a second conductivity type;

[0078] Forming a gate trench extending from the first surface into the semiconductor body (1). The sidewalls of the gate trench include sidewalls (41, 44) and sidewalls (42, 43). The sidewalls (41, 44) and the sidewalls (42, 43) are parallel and are in contact with the well region (2) and the first region (3) respectively. In the case of a hexagonal crystal system, the sidewalls (41, 44) and the sidewalls (42, 43) belong to a crystal plane family or a crystal plane family; forming an insulating layer (5) on the bottom wall and sidewalls of the gate trench;

[0079] Forming a gate in the gate trench. The gate is located on the side of the insulating layer (5) away from the semiconductor body (1);

[0080] Forming a source electrode (8) on the first surface;

[0081] Forming a drain electrode (9) on the second surface.

[0082] The present invention has been described by way of example. Obviously, the specific implementation of the present invention is not limited by the above methods. As long as various non-substantive improvements are made by adopting the method concept and technical solution of the present invention, or the concept and technical solution of the present invention are directly applied to other occasions without improvement, they are all within the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that, Comprising: A semiconductor body, including a first surface and a second surface arranged opposite to each other, the semiconductor body including a well region and a first region, the first region being disposed on the first surface, the well region being disposed on a side of the first region away from the first surface, the first region being of a first conductivity type, and the well region being of a second conductivity type; The first surface is further provided with a gate trench, the gate trench extends from the first surface into the semiconductor body, the sidewalls of the gate trench include a first sidewall and a second sidewall, the first sidewall and the second sidewall are parallel, and are respectively in contact with the well region and the first region, and in the case of a hexagonal crystal system, the first sidewall and the second sidewall belong to a crystal plane family or a crystal plane family; the semiconductor body further includes an insulating layer, and the insulating layer is located on the bottom wall and sidewalls of the gate trench; A gate, the gate being located on a side of the insulating layer away from the semiconductor body within the gate trench; A source electrode, the source electrode being located on the first surface; A drain electrode, the drain electrode being located on the second surface.

2. The semiconductor device according to claim 1, wherein The first sidewall contacts the bottom wall of the gate trench and forms a first angle therewith, the first angle being an acute angle; the second sidewall contacts the bottom wall of the gate trench and forms a second angle therewith, the second angle being an obtuse angle.

3. The semiconductor device according to claim 2, wherein, The thickness of the insulating layer at the first angle is greater than the thickness of the insulating layer at other positions; And / or the semiconductor body further includes a spacer insulating layer, the spacer insulating layer being located at the first angle and between the insulating layer and the gate; And / or the semiconductor body further includes a buried layer, the buried layer being located on the bottom wall and sidewalls of the gate trench and covering the first angle, the buried layer being of a second conductivity type, and the ion concentration of the buried layer being greater than the ion concentration of the well region.

4. The semiconductor device according to claim 1, characterized in that, The gate trench includes a first sub-gate trench and a second sub-gate trench, and a plurality of third angles are formed between the bottom wall and the sidewalls of the first sub-gate trench and the second sub-gate trench. The first sub-gate trench includes the first sidewall and a third sidewall arranged opposite to each other. The first sidewall and the third sidewall respectively contact the bottom wall of the first sub-gate trench, and the formed third angle is an obtuse angle; the second sub-gate trench includes the second sidewall and a fourth sidewall arranged opposite to each other. The second sidewall and the fourth sidewall respectively contact the bottom wall of the second sub-gate trench, and the formed fourth angle is an acute angle.

5. The semiconductor device according to claim 4, wherein It further includes a second region, the second region being located between the first sub-gate trench and the second sub-gate trench, the second region being of a second conductivity type, and the ion concentration of the second region being greater than the ion concentration of the well region.

6. The semiconductor device according to claim 4, characterized in that, The thickness of the insulating layer at the plurality of fourth angles is greater than the thickness of the insulating layer at other positions; And / or the semiconductor body further includes a spacer insulating layer, the spacer insulating layer being located at the plurality of fourth angles and between the insulating layer and the gate; And / or the semiconductor body further includes a buried layer, the buried layer being located on the bottom wall and sidewalls of the second sub-gate trench and covering the plurality of fourth angles, the buried layer being of a second conductivity type, and the ion concentration of the buried layer being greater than the ion concentration of the well region.

7. A method for manufacturing a semiconductor device, characterized in that, Comprising: Providing a semiconductor structure, the semiconductor structure including a first surface and a second surface arranged opposite to each other, the semiconductor body including a well region and a first region, the first region being disposed on the first surface, the well region being disposed on a side of the first region away from the first surface, the first region being of a first conductivity type, and the well region being of a second conductivity type; Form a gate trench extending from the first surface into the semiconductor body, the sidewalls of the gate trench including a first sidewall and a second sidewall, the first sidewall and the second sidewall being parallel and respectively in contact with the well region and the first region, and the first sidewall and the second sidewall belonging to a family of crystal planes or a family of crystal planes; form an insulating layer on the bottom wall and sidewalls of the gate trench; Forming a gate within the gate trench, the gate being located on a side of the insulating layer away from the semiconductor body; Form a source electrode on the first surface; Form a drain electrode on the second surface.

8. A power module, characterized in that, Comprise a substrate and at least one semiconductor device as described in any one of claims 1-6, the substrate being used for carrying the semiconductor device.

9. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit comprises a circuit board and at least one semiconductor device as described in any one of claims 1-6, the semiconductor device being electrically connected to the circuit board.

10. A vehicle, characterized in that, Comprise a load and the power conversion circuit as described in claim 9, the power conversion circuit being used for converting alternating current into direct current, converting alternating current into alternating current, converting direct current into direct current, or converting direct current into alternating current and then inputting the converted current into the load.

Images