Manufacturing method of epitaxial layer, epitaxial layer and noise-reduction super junction power device

Abstract

The invention relates to a manufacturing method of an epitaxial layer, the epitaxial layer and a noise-reduction super junction power device. The method comprises the following steps: providing an N-type substrate with high doping concentration; forming a first epitaxial layer; manufacturing a second epitaxial layer on the first epitaxial layer; the second epitaxial layer comprises a first P-type epitaxial layer, an insertion layer, a second P-type epitaxial layer, an insertion layer, a third P-type epitaxial layer, an insertion layer... an (n-1) th P-type epitaxial layer, an insertion layer and an nth P-type epitaxial layer which are sequentially grown from bottom to top along the upper surface of the first epitaxial layer; forming a barrier layer; forming a trapezoidal groove; and growing an N-type semiconductor on the front surface of the wafer, filling the trapezoidal groove, forming an N-type column of the super junction power device by the N-type semiconductor in the trapezoidal groove, then grinding the front surface of the wafer to the barrier layer, and finally removing the barrier layer. According to the invention, the noise problem caused by a grooving filling process is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for manufacturing an epitaxial layer, an epitaxial layer, and a noise-reducing superjunction power device. Background Art

[0002] The superjunction power MOSFET device is a power device that achieves charge balance during voltage withstand by arranging N-columns and P-columns at intervals. There are usually two manufacturing methods for it. One is the trench filling process widely used by domestic manufacturers. Specifically, as Figure 6 shown, in the first step, a highly doped N-type substrate 1 is provided, and a low-doped N-type semiconductor is grown from bottom to top on the surface of the N-type substrate 1 to form a first epitaxial layer 2; as Figure 7 shown, in the second step, a barrier layer 8 is formed on the upper surface of the first epitaxial layer 2. Then, the barrier layer 8 is selectively etched, and then the first epitaxial layer 2 is etched to form a plurality of trapezoidal trenches 5 with a wider upper part and a narrower lower part. The first epitaxial layer 2 between adjacent trapezoidal trenches 5 becomes the N-type column 7 of the superjunction power device; as Figure 8 shown, in the third step, a P-type semiconductor is grown and fills the trapezoidal trenches 5 completely. The P-type semiconductor in the trapezoidal trenches 5 constitutes the P-type column 6 of the superjunction power device. Then, the front surface of the wafer is polished to the barrier layer 8 in the third step, and finally the barrier layer 8 is removed. From the above trench filling process, it can be seen that the doping concentration of the semiconductor in the P-type column 6 is completely the same, which results in obvious noise in the trench-filled superjunction power MOSFET device.

[0003] The other is the multiple epitaxial manufacturing process adopted by the current international advanced manufacturer Infineon. The P-type column of the superjunction power MOSFET device produced by the multiple epitaxial manufacturing process is formed by connecting multiple P-type impurity concentration centers through thermal annealing. Therefore, the concentration distribution of this P-type column from bottom to top presents a wavy shape. This P-type column makes the noise of the device extremely low. Domestic manufacturers do not adopt the multiple epitaxial manufacturing process because of the high cost.

[0004] In order to solve the noise problem brought by the trench filling process, a new manufacturing process for the epitaxial layer is needed. Summary of the Invention

[0005] For this reason, the technical problem to be solved by the present invention is to overcome the noise problem brought by the trench filling process in the existing superjunction power MOSFET device.

[0006] To solve the above technical problem, in the first aspect, the present invention provides a method for manufacturing an epitaxial layer, including the following steps: Step 1: Provide a highly doped N-type substrate, and grow a low-doped N-type semiconductor from bottom to top on the surface of the N-type substrate to form a first epitaxial layer; Step 2: fabricate a second epitaxial layer on the first epitaxial layer; wherein, the second epitaxial layer includes, from bottom to top along the upper surface of the first epitaxial layer, successively grown: a No. 1 P-type epitaxial layer, an insertion layer, a No. 2 P-type epitaxial layer, an insertion layer, a No. 3 P-type epitaxial layer, an insertion layer... a No. n-1 P-type epitaxial layer, an insertion layer, and a No. n P-type epitaxial layer; where n is a positive integer; the upper surface of the second epitaxial layer is the front side of the wafer. Step 3: form a blocking layer on the upper surface of the second epitaxial layer, then selectively etch the blocking layer, and then etch and penetrate the second epitaxial layer to form a plurality of trapezoidal trenches that are wider at the top and narrower at the bottom. The second epitaxial layer between adjacent trapezoidal trenches constitutes the P-type columns of the superjunction power device. Step 4: grow an N-type semiconductor on the front side of the wafer and fill the trapezoidal trenches. The N-type semiconductor in the trapezoidal trenches constitutes the N-type columns of the superjunction power device. Then grind the front side of the wafer to the blocking layer in Step 3, and finally remove the blocking layer.

[0007] In an embodiment of the present invention, each of the insertion layers is an intrinsic semiconductor.

[0008] In an embodiment of the present invention, each of the insertion layers is a P-type semiconductor, and the doping concentration of each of the insertion layers is lower than the doping concentration of each of the No. 1 P-type epitaxial layer, No. 2 P-type epitaxial layer, No. 3 P-type epitaxial layer... No. n-1 P-type epitaxial layer, and No. n P-type epitaxial layer.

[0009] In an embodiment of the present invention, the insertion layer is an N-type semiconductor.

[0010] In an embodiment of the present invention, the thickness of the insertion layer is less than 10 microns.

[0011] In an embodiment of the present invention, the thicknesses of the No. 1 P-type epitaxial layer, No. 2 P-type epitaxial layer, No. 3 P-type epitaxial layer... No. n-1 P-type epitaxial layer, and No. n P-type epitaxial layer are equal.

[0012] In an embodiment of the present invention, the doping concentrations of the No. 1 P-type epitaxial layer, No. 2 P-type epitaxial layer, No. 3 P-type epitaxial layer... No. n-1 P-type epitaxial layer, and No. n P-type epitaxial layer gradually increase.

[0013] In a second aspect, the present invention provides an epitaxial layer fabricated based on the manufacturing method of the epitaxial layer described above.

[0014] In a third aspect, the present invention provides a noise-reducing superjunction power device including the epitaxial layer described above.

[0015] The above technical solution of the present invention has the following advantages compared with the prior art: A method for manufacturing an epitaxial layer, the epitaxial layer and a noise-reducing superjunction power device according to the present invention, by adding an insertion layer into the P-type epitaxial layer, makes the concentration distribution of the P-type column from bottom to top present a wavy shape, similar to the P-type column of the multi-epitaxial manufacturing process, can significantly reduce the noise of the trenched-filled superjunction power MOSFET device, and the process of the present invention is compatible with the existing process, and the manufacturing method is simple. Description of the Drawings

[0016] In order to make the content of the present invention easier to be clearly understood, the present invention will be further described in detail below according to the specific embodiments of the present invention in conjunction with the drawings.

[0017] Figure 1 It is a schematic cross-sectional structure diagram of forming a first epitaxial layer in step 1 of Embodiment 1 of the present invention.

[0018] Figure 2 It is a schematic cross-sectional structure diagram of forming a second epitaxial layer in step 2 of Embodiment 1 of the present invention.

[0019] Figure 3 It is a schematic cross-sectional structure diagram of forming a trapezoidal trench in step 3 of Embodiment 1 of the present invention.

[0020] Figure 4 It is a schematic cross-sectional structure diagram of forming an N-type column in step 4 of Embodiment 1 of the present invention.

[0021] Figure 5 It is along Figure 2 The schematic cross-sectional structure diagram of the boron doping concentration obtained by cutting along the dashed line A-A' in

[0022] Figure 6 It is a schematic cross-sectional structure diagram of forming a first epitaxial layer in step 1 of the traditional process.

[0023] Figure 7 It is a schematic cross-sectional structure diagram of forming a trapezoidal trench in step 2 of the traditional process.

[0024] Figure 8 It is a schematic cross-sectional structure diagram of forming a P-type column in step 3 of the traditional process. Detailed Description of the Invention

[0025] The present invention will be further described below in conjunction with the drawings and specific embodiments, so that those skilled in the art can better understand the present invention and be able to implement it, but the embodiments cited are not intended to limit the present invention.

[0026] In the present invention, when directions (up, down, left, right, front, and back) are described, it is only for the convenience of describing the technical solution of the present invention, rather than indicating or implying that the technical features referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present invention.

[0027] In the present invention, the meaning of "several" is one or more, the meaning of "multiple" is two or more, and "greater than", "less than", "exceeding", etc. are understood as not including the base number; "above", "below", "within", etc. are understood as including the base number. In the description of the present invention, if "first" and "second" are described, they are only used to distinguish technical features and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features or implicitly indicating the sequence relationship of the indicated technical features.

[0028] In the present invention, unless otherwise clearly defined, terms such as "arranged", "installed", "connected", etc. should be understood in a broad sense. For example, they can be directly connected, or indirectly connected through an intermediate medium; they can be fixedly connected, or detachably connected, or integrally formed; they can be mechanically connected, or electrically connected or capable of communicating with each other; they can be the communication inside two components or the interaction relationship between two components. Those skilled in the art can reasonably determine the specific meaning of the above terms in the present invention in combination with the specific content of the technical solution.

[0029] Embodiment 1 This embodiment provides a method for manufacturing an epitaxial layer of a noise-reducing superjunction power device, including the following steps: Step 1: As Figure 1 shown, provide an N-type substrate 1 with a high doping concentration, and grow an N-type semiconductor with a low doping concentration on the surface of the N-type substrate 1 from bottom to top to form a first epitaxial layer 2; Step 2: As Figure 2 shown, grow a No. 1 P-type epitaxial layer 3a, an insertion layer 4, a No. 2 P-type epitaxial layer 3b, an insertion layer 4, a No. 3 P-type epitaxial layer 3c, an insertion layer 4, a No. 4 P-type epitaxial layer 3d, an insertion layer 4, a No. 5 P-type epitaxial layer 3e, an insertion layer 4, and a No. 6 P-type epitaxial layer 3f on the upper surface of the first epitaxial layer 2 from bottom to top. The No. 1 P-type epitaxial layer 3a, the insertion layer 4, the No. 2 P-type epitaxial layer 3b, the insertion layer 4, the No. 3 P-type epitaxial layer 3c, the insertion layer 4, the No. 4 P-type epitaxial layer 3d, the insertion layer 4, the No. 5 P-type epitaxial layer 3e, the insertion layer 4, and the No. 6 P-type epitaxial layer 3f form a second epitaxial layer 3; wherein, the upper surface of the second epitaxial layer 3 is the front side of the wafer.

[0030] It should be noted that the number of P-type epitaxial layers can be selected as needed.

[0031] In addition, each of the insertion layers 4 is an intrinsic semiconductor with a thickness of 1 micron. The thicknesses of the first P-type epitaxial layer 3a, the second P-type epitaxial layer 3b, the third P-type epitaxial layer 3c, the fourth P-type epitaxial layer 3d, the fifth P-type epitaxial layer 3e, and the sixth P-type epitaxial layer 3f are equal, all being 4 microns, and they are all boron-doped, with the doping concentration gradually increasing.

[0032] As Figure 5 shown, it is a schematic cross-sectional structure diagram of the boron doping concentration taken along the dashed line A-A' in Figure 2 . The concentration relationships of the first P-type epitaxial layer 3a, the second P-type epitaxial layer 3b, the third P-type epitaxial layer 3c, the fourth P-type epitaxial layer 3d, the fifth P-type epitaxial layer 3e, and the sixth P-type epitaxial layer 3f are visually displayed. The setting of the insertion layer 4 makes the concentration distribution of boron present a wavy shape.

[0033] Step three: As Figure 3 shown, a blocking layer 8 is formed on the upper surface of the second epitaxial layer 3, then the blocking layer 8 is selectively etched, and then the second epitaxial layer 3 is etched and penetrated to form a plurality of trapezoidal trenches 5 with a wider upper part and a narrower lower part. The second epitaxial layer 3 between adjacent trapezoidal trenches 5 becomes the P-type column 6 of the superjunction power device.

[0034] Step four: As Figure 4 shown, an N-type semiconductor is grown on the front surface of the wafer and fills the trapezoidal trenches 5. The N-type semiconductor in the trapezoidal trenches 5 constitutes the N-type column 7 of the superjunction power device. Then, the front surface of the wafer is polished to the blocking layer 8 in step three, and finally the blocking layer 8 is removed.

[0035] Embodiment 2 This embodiment provides a method for manufacturing an epitaxial layer of a noise-reducing superjunction power device. Compared with Embodiment 1, in this embodiment, each of the insertion layers 4 is a P-type semiconductor, and the doping concentration of each of the insertion layers 4 is lower than the doping concentration of each of the first P-type epitaxial layer 3a, the second P-type epitaxial layer 3b, the third P-type epitaxial layer 3c, the fourth P-type epitaxial layer 3d, the fifth P-type epitaxial layer 3e, and the sixth P-type epitaxial layer 3f.

[0036] In addition, the thickness of each of the insertion layers is less than 10 microns. The thicknesses of the first P-type epitaxial layer 3a, the second P-type epitaxial layer 3b, the third P-type epitaxial layer 3c, the fourth P-type epitaxial layer 3d, the fifth P-type epitaxial layer 3e, and the sixth P-type epitaxial layer 3f are equal, and they are all boron-doped, with the doping concentration gradually increasing.

[0037] In the present invention, by adding an insertion layer into the P-type epitaxial layer, the concentration distribution of the P-type column from bottom to top presents a wavy shape, similar to that of the P-type column in the multi-epitaxial manufacturing process. In fact, the parasitic resistance of the P-type column is increased. The greater the parasitic resistance, the slower the reverse recovery speed of the diode composed of the P-type column and the N-type column, and the smaller the noise of the device. Therefore, the present invention can significantly reduce the noise of the trenched and filled superjunction power MOSFET device.

[0038] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention rather than to limit them. Although the present invention has been described in detail with reference to the examples, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention, and they should all be covered by the scope of the claims of the present invention.

Claims

1. A method for manufacturing an epitaxial layer, characterized in that, It includes the following steps: Step 1: Provide an N-type substrate with a high doping concentration, and grow an N-type semiconductor with a low doping concentration from bottom to top on the surface of the N-type substrate to form a first epitaxial layer; Step 2: Fabricate a second epitaxial layer on the first epitaxial layer; wherein, the second epitaxial layer includes, grown from bottom to top along the upper surface of the first epitaxial layer in sequence: a No. 1 P-type epitaxial layer, an insertion layer, a No. 2 P-type epitaxial layer, an insertion layer, a No. 3 P-type epitaxial layer, an insertion layer... a No. (n - 1) P-type epitaxial layer, an insertion layer, a No. n P-type epitaxial layer; wherein, n is a positive integer; the upper surface of the second epitaxial layer is the front side of the wafer; Step 3: Form a blocking layer on the upper surface of the second epitaxial layer, then selectively etch the blocking layer, and then etch and penetrate the second epitaxial layer to form a plurality of trapezoidal trenches with a wider upper part and a narrower lower part. The second epitaxial layer between adjacent trapezoidal trenches constitutes the P-type columns of the superjunction power device; Step 4: Grow an N-type semiconductor on the front side of the wafer and fill the trapezoidal trenches. The N-type semiconductor in the trapezoidal trenches constitutes the N-type columns of the superjunction power device. Then grind the front side of the wafer to the blocking layer in Step 3, and finally remove the blocking layer.

2. The manufacturing method of an epitaxial layer according to claim 1, characterized in that, Each of the insertion layers is an intrinsic semiconductor.

3. The manufacturing method of an epitaxial layer according to claim 1, characterized in that, Each of the insertion layers is a P-type semiconductor, and the doping concentration of each insertion layer is lower than the doping concentration of each of the No. 1 P-type epitaxial layer, No. 2 P-type epitaxial layer, No. 3 P-type epitaxial layer... No. (n - 1) P-type epitaxial layer and No. n P-type epitaxial layer.

4. The manufacturing method of an epitaxial layer according to claim 1, characterized in that Each of the insertion layers is an N-type semiconductor.

5. A method for manufacturing an epitaxial layer according to claim 1, characterized in that, The thickness of each of the insertion layers is less than 10 microns.

6. The manufacturing method of an epitaxial layer according to claim 1, characterized in that, The thicknesses of the No. 1 P-type epitaxial layer, No. 2 P-type epitaxial layer, No. 3 P-type epitaxial layer... No. (n - 1) P-type epitaxial layer and No. n P-type epitaxial layer are equal.

7. The manufacturing method of an epitaxial layer according to claim 1, wherein, The doping concentrations of the No. 1 P-type epitaxial layer, No. 2 P-type epitaxial layer, No. 3 P-type epitaxial layer... No. (n - 1) P-type epitaxial layer and No. n P-type epitaxial layer gradually increase.

8. An epitaxial layer, characterized in that, Manufactured by the manufacturing method of the epitaxial layer according to any one of claims 1 - 7.

9. A superjunction power device for noise reduction, characterized in that, Including the epitaxial layer according to claim 8.

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