Device with outer conductive spacer

Abstract

The present disclosure relates to semiconductor structures, and more particularly, to devices with outer conductive spacers and methods of manufacture. The structure comprises a gate structure; a gate metal connected to the gate structure; an inner spacer contacting and surrounding the gate metal; a passivation layer on the inner spacer; and an outer conductive spacer on the passivation layer and adjacent to a side surface of the gate structure.

Description

Technical Field

[0001] The present disclosure relates to semiconductor structures, and more particularly, to devices and manufacturing methods having outer conductive spacers. Background Art

[0002] A high electron mobility transistor (HEMT) is a field effect transistor that includes a junction (i.e., a heterojunction) between two materials having different bandgaps as a channel, rather than a doped region (which is typically the case for MOSFETs). Commonly used material families are GaN or GaAs, although other materials may be used depending on the application of the device.

[0003] Due to the higher critical field and switching figures of merit of the GaN material system, GaN HEMT devices typically have a higher electric field strength than silicon MOSFETs, thus providing substantial performance improvements in terms of, for example, on-resistance and breakdown voltage, while providing a fast switching speed and other important parameters. Since these characteristics fundamentally result in higher system efficiency, HEMTs can be used in various power management applications, such as AC-DC and DC-DC conversion in the consumer or automotive fields. In RF applications, they can be used in high-frequency power amplifiers, low-noise amplifiers, or switches in applications such as mobile phones, satellites, or receiver or radar devices. Summary of the Invention

[0004] In one aspect of the present disclosure, a structure includes: a gate structure; a gate metal connected to the gate structure; an inner spacer contacting and surrounding the gate metal; a passivation layer located on the inner spacer; and an outer conductive spacer located on the passivation layer and adjacent to a side surface of the gate structure.

[0005] In one aspect of the present disclosure, a structure includes: a gate structure; an inner dielectric spacer; an outer conductive spacer surrounding the inner dielectric spacer; a gate metal connected to the gate structure and surrounded by the inner dielectric spacer, the gate metal also being adjacent to the outer conductive spacer on an opposite side of the inner dielectric spacer.

[0006] In one aspect of the present disclosure, a method includes: forming a gate structure; forming a gate metal connected to the gate structure; forming an inner spacer contacting and surrounding the gate metal; forming a passivation layer on the inner spacer sidewall; and forming an outer conductive spacer on the passivation layer and adjacent to a side surface of the gate structure. Brief Description of the Drawings

[0007] In the following detailed description, the present disclosure is described with reference to the several drawings mentioned, by way of non-limiting examples of exemplary embodiments of the present disclosure.

[0008] Figure 1 shows a structure and corresponding manufacturing process in accordance with some aspects of the present disclosure.

[0009] Figure 2 shows a structure in accordance with additional aspects of the present disclosure.

[0010] Figures 3A - 3C shows a top view of an outer conductive spacer in accordance with some aspects of the present disclosure, among other features.

[0011] Figures 4A - 4D shows a manufacturing process for manufacturing a Figure 1 structure in accordance with some aspects of the present disclosure. DETAILED DESCRIPTION

[0012] The present disclosure relates to semiconductor structures, and more particularly, to devices and manufacturing methods having outer conductive spacers. More specifically, the device can be an enhancement-mode (e.g., normally-off) high electron mobility transistor (HEMT) having an inner dielectric spacer, an outer conductive spacer, and a field plate including a gate metal. In an embodiment, the outer conductive spacer can be a field plate connected to the source of the device. Advantageously, these devices can be scalable enhancement-mode devices necessary for high-performance GaN power technology. In an embodiment, for example, these devices can be scaled to extremely short lengths to minimize channel resistance, especially when the operating voltage is reduced. Additionally, the methods described herein can reduce stress at the edges of the p-GaN gate structure (e.g., during the formation of the gate metal).

[0013] In a more specific embodiment, the HEMT can be a high-voltage p-GaN HEMT having a p-GaN gate structure (e.g., a gate electrode) for an e-mode GaN HEMT device and based on a self-aligned spacer structure. In an embodiment, the self-alignment method is based on the use of an inner dielectric spacer and an outer conductive spacer, where the gate metal is precisely aligned with the gate structure without causing stress or short circuits. In addition to protecting the gate structure and a passivation layer formed, for example, by atomic layer deposition (ALD) during a metal gate deposition process, the outer conductive spacer can also be used as a field plate connected to the source of the device.

[0014] The structures of the present disclosure can be fabricated in a variety of ways using a variety of different tools. Generally, however, methods and tools are used to form structures having micron and nanoscale dimensions. Methods (i.e., techniques) for fabricating the structures of the present disclosure have been adopted in accordance with integrated circuit (IC) technology. For example, these structures are built on a wafer and realized in a material film patterned on top of the wafer by means of a lithography process. Specifically, the fabrication of the structures uses three basic building blocks: (i) depositing a thin film of material on a substrate; (ii) applying a patterned mask on top of the film by lithographic imaging; and (iii) selectively etching the film with respect to the mask. Additionally, as is known in the art, a pre-cleaning process can be used to clean any contaminants on the etched surface. Additionally, as is known in the art, a rapid thermal annealing process can be used to drive in dopants or material layers when necessary.

[0015] Figure 1 Structures and corresponding fabrication processes in accordance with some aspects of the present disclosure are shown. More specifically, Figure 1 the structure 10 can be a HEMT including a p-GaN gate structure 14 having a gate metal 16 surrounded by an inner dielectric spacer 22 and an outer conductive spacer 23. The outer conductive spacer 23 can serve as a field plate connected to the source 17. It should be appreciated that the field plate 21a can be a separate field plate formed from the gate metal. Additionally, in embodiments, although the field plate can be connected to the source 17, there are other applications where the field plate can be connected to the gate in other applications.

[0016] A passivation layer 20 can be provided between the inner dielectric spacer 22 and the outer conductive spacer 23, where another passivation layer (insulating material) 25 covers the outer conductive spacer 23 and the passivation layer 20. In embodiments, in addition to reducing process variations and the electric field when a voltage is applied to the drain side 19 of the device, the outer conductive spacer 23 will also protect the p-GaN gate structure 14 during subsequent fabrication processes (e.g., forming the field plate and depositing the gate metal). A gate metal 16a can be formed on top of the passivation layer 25 on the outside of the outer conductive spacer 23. The passivation layer 25 isolates the gate metal 16a from the outer conductive spacer 23. It should be understood that there can be an additional field plate 21a that can be connected to the source 17. The gate metal 16a can serve as a self-aligned field plate 21a (e.g., a gate metal field plate) connected to the source 17.

[0017] More specifically, structure 10 includes a semiconductor substrate 12. The semiconductor substrate 12 may include a Si-containing semiconductor substrate 12a; although other suitable materials are contemplated herein, including but not limited to SiGe, SiGeC, SiC, GaN, AlN, GaAs, InAs, InP, and other group III / V or II / VI compound semiconductors, or may be an engineered substrate having multiple layers, such as silicon-on-insulator (SOI). In a preferred embodiment, the semiconductor material substrate may include a suitable crystal orientation, e.g., in the case of silicon, the crystal orientation is <111>.

[0018] The remaining semiconductor materials 12b-12d may be a stack of semiconductor materials for forming a GaN HEMT device. By way of illustrative and non-limiting example, the wide-bandgap semiconductor layer 12b may be, for example, an AlGaN material stack well-known in the art. For example, and as a non-limiting illustrative example, the wide-bandgap semiconductor layer 12b may include a seed layer (e.g., AlN) on the underlying semiconductor substrate 12a, a buffer layer (e.g., AlGaN / GaN superlattice), and a channel layer 12c (e.g., GaN) in a layered semiconductor material stack. In an embodiment, the channel layer 12c may be undoped GaN formed above the wide-bandgap semiconductor layer 12b, and the barrier layer 12d may be AlGaN formed above the undoped GaN. In other embodiments, the layer 12d may be AlN, InAlN, InGaN, GaN, or a plurality of materials. The stack of semiconductor materials may be formed by a conventional epitaxial growth process or other known deposition methods, such as metalorganic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).

[0019] A p-doped GaN layer may be formed above the barrier layer 12d and patterned to form a p-GaN gate structure 14. An optional undoped thin GaN layer or Si3N4 material may be disposed on the surface of the p-GaN gate structure 14, as shown by reference numeral 14a. As described with respect to Figures 4A - 4D The additional passivation layer 14a acts as an etch stop. The passivation layer 14a may be formed by any conventional deposition method (e.g., CVD or ALD) and patterned with gate materials using conventional lithography and etching processes well-known in the art, and thus, no further explanation is required to fully understand the present disclosure.

[0020] Still referring to Figure 1, the device 10 (e.g., including the p-GaN gate structure 14) can be disposed over the channel layer 12c and the blocking layer 12d. For example, the device 10 can include source regions 17 and drain regions 19 of the channel layer 12c and / or the layer 12d. Portions of the semiconductor material can be epitaxially grown with in-situ doping (e.g., p-type doping such as magnesium (Mg)), as is well known in the art.

[0021] The gate metal 16, such as TiN, TiAl, and / or TaN, can be disposed on top of and in contact with the semiconductor material of the p-GaN gate structure 14. In an embodiment, the gate metal 16a can also be deposited simultaneously over the passivation layer 25 to form a lower field plate 21a connected to the source 17. The gate metals 16, 16a can be deposited by conventional deposition methods (e.g., CVD, plasma vapor deposition (PVD), atomic layer deposition (ALD), and other techniques), and patterned by conventional etching processes (e.g., reactive ion etching (RIE)) before depositing the interlayer dielectric material 24 as shown in Figure 4C and 4D . The gate metals 16, 16a can be refractory metals or their compounds, such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), palladium (Pd), tungsten (W), or tungsten silicide (WSi2). As further disclosed herein, the lower field plate 21a will be self-aligned using an outer conductive spacer 23.

[0022] Figure 1 Also shown are metal materials 16b, 16c (metal materials) and an optional metal layer (e.g., power metal) 16d. The metal materials 16b, 16c, 16d include an upper metal layer 16''' (e.g., a force metal at the first metal layer), and the metal materials 16a, 16c also include an ohmic contact 16' and a via 16'' connecting the upper metal layer 16''' to the ohmic contact 16'. The metal materials 16b, 16c and the metal layer 16d can be the same or different metal materials as the gate metals 16, 16a. For example, the metal materials 16b, 16c, 16d can be aluminum (Al) or other conductive materials for the wiring layer. In an embodiment, the metal materials 16b, 16c, 16d can be deposited after the patterning (e.g., lithography and etching processes) of the interlayer dielectric material 24 as shown in Figure 4D . Additional interlayer dielectric layers 24a, 24b can also be deposited over the interlayer dielectric material 24 and the gate metals 16, 16a. The ohmic contact 16c can be connected to the drain region 19, such as the blocking layer 12d; while the ohmic contacts 16b and the optional metal layer 16d embedded within the interlayer dielectric material 24a can be used as field plates 21b, 21c at different wiring levels connected to the source 17.

[0023] Although field plates 21b, 21c may be formed of the metal materials of ohmic contacts 16b and metal layer 16d, it is also conceivable that field plates 21b, 21c may be separate wiring layers connected to metal materials 16b and metal layer 16d. For example, in an alternative embodiment, a metal wiring (e.g., TiN) may be used as field plate 21b connected to metal material 16b. Additionally, it should be understood that the thicknesses of the interlayer dielectric material 24 and passivation layer 25 between field plates 21a, 21b, 21c and passivation layer 20 may be used to reduce the electric field on gate structure 14 as the electric field on the drain side 19 depletes.

[0024] In an embodiment, passivation layers 20, 25 may be, for example, nitride materials. In a more specific embodiment, passivation layer 20 may be silicon nitride, silicon oxide, or multiple materials, and may be deposited using ALD, CVD, or any other known deposition process; while passivation layer 25 may be deposited over outer conductive spacer 23 by an ALD or CVD process. In an embodiment, passivation layer 20 may be Al2O3 and passivation layer 25 may be SiO2 or Si3N4.

[0025] Passivation layer 20 may be located on the outer sidewalls of inner dielectric spacer 22 and over semiconductor substrate 12, including at the edges and sides of active device 10 (e.g., p-GaN gate structure). In this way, inner dielectric spacer 22 is encapsulated between passivation layer 20, passivation layer 14a, pGaN gate structure 14 (located on the bottom surface of dielectric spacer 22), and gate metal stack 16 (located on the inner and top surfaces). Inner dielectric spacer 22 may be a single-layer or multi-layer dielectric insulator material, such as nitride, oxide, or oxynitride, and may be a material different from passivation layers 14a, 20, 25.

[0026] Still referring to Figure 1 , outer conductive spacer 23 may be formed over passivation layer 20, opposite inner dielectric spacer 22. Outer conductive spacer 23 may extend over the sides and corners of p-GaN gate structure 14. As an example, outer conductive spacer 23 may be tungsten, polysilicon, or tungsten silicide, and may be used to protect gate structure 14 (e.g., p-GaN gate structure) during a manufacturing process (e.g., an etching process for forming field plates). For example, outer conductive spacer 23 will protect passivation layer 20 during the etching processes for forming metal material 16a (and field plate 21a) and metal material 16b and corresponding field plate 21b. Additionally, outer conductive spacer 23 may reduce the stress on gate structure 14 that would otherwise be caused by the different coefficients of expansion between gate metals 16, 16a and gate structure 14. Outer conductive spacer 23 may also be self-aligned with gate metal 16a on the gate side and optional additional field plate 21a on the drain side.

[0027] As Figure 1 Further shown, in the embodiment, the gate metal 16a is disposed on the passivation layer 25 and can be self-aligned by the thickness of the outer conductive spacer 23. Additionally, the gate metal 16 disposed on the p-GaN gate structure 14 can be self-aligned and surrounded by the inner dielectric spacer 22 and the outer conductive spacer 23. Further, the gate metal 16 can be symmetrically positioned above the active device 10 and surrounded by the inner dielectric spacer 22 and the outer conductive spacer 23, which is offset by a distance "X" from the edge of the p-GaN gate structure 14. The offset distance "X" is the thickness of the inner dielectric spacer 22. Additionally, the profile of the gate metal 16 will follow the profile of the inner dielectric spacer 22.

[0028] Figure 2 A structure according to an additional aspect of the present disclosure is shown. In Figure 2 the structure 10a, the gate metal 16a extends above the outer conductive spacer 23. Additionally, the outer conductive spacer 23 further extends into the drift region (e.g., the drain side 19 of the device). In this way, the field plate 21a including the outer conductive spacer 23 can have an extended length (compared to Figure 1 the structure shown). The remaining features are similar to Figure 1 the structure 10.

[0029] Figures 3A - 3C A top view of the outer conductive spacer 23 according to some aspects of the present disclosure is shown. Figure 3A And 3B the top view of the outer conductive spacer 23 shown can correspond to Figure 1 the structure 10 shown; while Figure 3C the top view of the outer conductive spacer 23 of Figure 2 can correspond to the structure 10a shown.

[0030] In Figure 3A the structure, the outer conductive spacer 23 includes a narrow end 23a, where the contact 27 is connected to the narrow end 23a. In Figure 3B , the outer conductive spacer 23 includes a wider (e.g., larger) end 23b, where the contact 27 is connected to the end 23b. Figure 3B The embodiment of Figure 3C allows the contact 27 to have a larger landing space. Figure 2 A top view of the outer conductive spacer 23 shown in Figure 3A is shown, which has an extended length 23c in the drift region. The contact 27 can also be placed at the larger end 23b of the outer conductive spacer 23; however, it is also contemplated that the structure includes a narrow end as shown in

[0031] Figures 4A - 4Dillustrates a corresponding manufacturing process for the structure according to some aspects of the present disclosure Figure 1 of the structure. Those skilled in the art should understand that similar manufacturing processes can be used to manufacture Figure 2 the structure, but there are some modifications to the patterning processes for the gate metal and field plates, as should be understood by those skilled in the art.

[0032] As Figure 4A shown, a (e.g., patterned) p-GaN gate structure 14 can be formed on a semiconductor substrate 12 using a hard mask 28. In an embodiment, the hard mask 28 can be a nitride material or other hard mask materials known in the art. For example, the p-GaN gate structure 14 can be formed by depositing p-GaN material on the substrate 12, and then depositing a passivation layer 14a (etch stop) and the hard mask 28. The p-GaN material, the passivation layer 14a, and the hard mask 28 can be patterned using conventional lithography and etching processes, such as reactive ion etching (RIE) known in the art.

[0033] Conventional lithography and etching processes include forming a resist above the hard mask material, which is exposed to energy (light) and developed using a conventional resist developer to form a pattern (opening). An etching process with selective chemical action, such as reactive ion etching (RIE), will be used to transfer the pattern into the hard mask material and the p-GaN material to form the gate structure 14. The resist can be removed by a conventional oxygen ashing process or other known strippers.

[0034] Figure 4B illustrates the formation of the outer conductive spacer 23. To form the outer conductive spacer 23, a passivation layer 20 is formed above the patterned gate structure 14 and the hard mask 28. In an embodiment, the passivation layer 20 can be a nitride or oxide material (or a combination thereof) by ALD or CVD or other known processes. An optional oxide material can be deposited on the passivation layer 20 according to the desired thickness of a specific field plate design.

[0035] The outer conductive spacer 23 is formed by conformally depositing a conductive material above the passivation layer 20 and then performing an anisotropic etching process to form the outer conductive spacer 23. For example, tungsten, polysilicon, or tungsten silicide material can be deposited on the structure using, for example, a CVD process. The material can be etched by an anisotropic etching process to form the outer conductive spacer 23. A passivation layer 25 can be deposited above the outer conductive spacer 23 and the hard mask 28.

[0036] In Figure 4CIn it, the inner dielectric spacer 22 is formed on the sidewalls of the trench 30. For example, the passivation layers 20, 25 above the hard mask and the hard mask itself can be selectively removed to form the trench 30, which exposes the underlying passivation layer 14a above the p-GaN gate structure 14. In an embodiment, the passivation layer 14a will act as an etch stop layer to protect the p-GaN gate structure 14. Those skilled in the art should understand that the trench 30 will have sidewalls including the passivation layer 20.

[0037] The inner dielectric spacer 22 is formed on the sidewalls of the trench 30, more specifically, above the passivation layers 14a, 20 within the trench 30. The spacer material can be, for example, an oxide, a nitride, an oxynitride, or other dielectric material or a combination thereof. In an embodiment, the inner dielectric spacer 22 can be formed by performing a conventional blanket deposition process (e.g., CVD or ALD, etc.) followed by a etch-back process (e.g., an anisotropic etching process) to remove the spacer material from the top surface of the passivation layer 14a above the p-GaN gate structure 14. In this way, the inner dielectric spacer 22 is self-aligned with the edge of the p-GaN gate structure 14. After the inner dielectric spacer 22 is formed, the exposed portion of the passivation layer 14a can be removed by a selective etching process to expose the underlying p-GaN gate structure 14.

[0038] As Figure 4D shown, the gate metals 16, 16a can be formed by deposition and patterning processes. In an embodiment, when fabricating the gate metals 16, 16a, the outer conductive spacer 23 will reduce the stress on the gate structure (which is caused by the different coefficients of thermal expansion between the metal material and the gate structure), while also providing a self-alignment mechanism for forming at least the bottom field plate 21.

[0039] By way of example, except above the passivation layer 25 outside the trench, the metal material can be blanket deposited (e.g., CVD) within the trench to form contact with the underlying p-GaN gate structure 14. For example, the metal material will also be deposited above the inner dielectric spacer 22, the outer conductive spacer 23, and the passivation layer 25, followed by a conventional patterning process to form Figure 1 and 2 any configuration among the different configurations shown in

[0040] Thus, it should be recognized that the patterning process can be used to form the field plate 21a from the gate metal 16a. It should be understood that the gate metal 16 will be self-aligned with the p-GaN gate structure 14 and will also be offset from the edge of the p-GaN gate structure 14 by the inner dielectric spacer 22, while the gate metal 16a will be self-aligned to the outer conductive spacer 23.

[0041] The process flow continues as described with respect to Figure 1The described conventional back-end-of-line (BEOL) process, wherein during additional manufacturing processes such as field plates and ohmic contacts, the outer conductive spacer 23 protects the p-GaN gate structure 14. For example, an interlayer dielectric material 24 can be deposited over the gate metals 16, 16a, and then a patterning process is performed to form different patterns including Figure 4D the pattern 29 shown, which follow Figure 1 and 2 the shape of the metal materials 16b, 16c shown. The metal material on the drain side 19 can be deposited within the patterned interlayer dielectric material 24. Those skilled in the art should understand that the same process can be repeated for each different field plate at different levels of the device.

[0042] HEMTs can be used as a single device in discrete applications, or can be combined with several other devices of the same or different types in a single package through co-packaging or multi-chip 3D integration techniques, or can be combined with several other devices in system-on-chip (SoC) technology. An SoC is an integrated circuit (also called a "chip") that integrates all components of an electronic system on a single chip or substrate. Since the components are integrated on a single substrate, an SoC consumes much less power and occupies much less area compared to a multi-chip design with equivalent functionality. Therefore, SoCs are becoming a dominant force in the mobile computing (e.g., in smartphones) and edge computing markets. SoCs are also used in embedded systems and the Internet of Things. Additionally, GaN devices are increasingly being adopted in SoC designs, in which multiple GaN HEMTs are formed on a single substrate.

[0043] The above method is used for the manufacture of discrete device chips or integrated circuit chips. The resulting chips can be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in packaged form. In the latter case, the chips are mounted in the form of single-chip packages (e.g., plastic carriers whose leads are fixed to a motherboard or other higher-level carrier) or multi-chip packages (e.g., ceramic carriers having one or both of surface interconnections or buried interconnections). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, ranging from toys and other low-end applications to high-end computer products with a display, keyboard, or other input devices and a central processor.

[0044] The description of various embodiments of the present disclosure has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles of the embodiments, the practical application, or the technical improvement of technologies found in the marketplace, or to enable other ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A structure, comprising: A gate structure; A gate metal connected to the gate structure; An inner spacer contacting and surrounding the gate metal; A passivation layer located on the inner spacer; And An outer conductive spacer located on the passivation layer and adjacent to a side surface of the gate structure.

2. The structure according to claim 1, wherein, The gate structure includes a p-GaN material.

3. The structure according to claim 2, wherein, The inner spacer includes a dielectric material.

4. The structure according to claim 1, wherein The passivation layer is a nitride material located between the inner spacer and the outer conductive spacer.

5. The structure according to claim 1, wherein, The outer conductive spacer surrounds the gate structure and the gate metal.

6. The structure according to claim 5, wherein, The outer conductive spacer includes a field plate connected to a source.

7. The structure according to claim 6, further comprising an additional gate metal adjacent to the outer conductive spacer on a drain side, the additional gate metal including a second field plate connected to the source.

8. The structure according to claim 7, further comprising a metal material on the drain side.

9. The structure according to claim 8, wherein, The metal material includes at least another field plate on the first field plate adjacent to the outer conductive spacer on the drain side.

10. The structure according to claim 9, wherein, The another field plate, the first field plate, and the second field plate are located at different levels.

11. The structure according to claim 1, wherein, The outer conductive spacer includes a lower field plate having a length extending into a drift region on the drain side and connected to the source, and further includes a gate metal including a second field plate adjacent to the outer conductive spacer and connected to the source.

12. A structure, comprising: A gate structure; An inner dielectric spacer; An outer conductive spacer surrounding the inner dielectric spacer; A gate metal connected to the gate structure and surrounded by the inner dielectric spacer, the gate metal also being adjacent to the outer conductive spacer on an opposite side of the inner dielectric spacer.

13. The structure according to claim 12 further comprises: An insulator material isolating the outer conductive spacer from the gate metal adjacent to the outer conductive spacer.

14. The structure according to claim 13 further comprises: A passivation layer located between the outer conductive spacer and the inner dielectric spacer.

15. The structure according to claim 14, wherein, The outer conductive spacer includes a first field plate on the passivation layer, and the metal gate adjacent to the outer conductive spacer includes a second field plate on the insulator material.

16. The structure according to claim 15, wherein, The gate metal adjacent to the outer conductive spacer is adjacent to the outer conductive sidewall spacer, wherein the insulator material is located between the gate metal and the outer conductive spacer.

17. The structure according to claim 15 further comprises: At least one additional field plate including an ohmic contact on a drain side of the device.

18. The structure according to claim 12, wherein, The outer conductive spacer includes a length extending into a drift region on a drain side of the device.

19. The structure according to claim 12, wherein, The gate metal connected to the gate structure and the gate metal adjacent to the outer conductive spacer include the same metal material.

20. A method, comprising: Forming a gate structure; Forming a gate metal connected to the gate structure; Forming an inner spacer contacting and surrounding the gate metal; Forming a passivation layer on the inner sidewall spacer; And Forming an outer conductive spacer on the passivation layer and adjacent to a side surface of the gate structure.

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