Stacked chips

Abstract

The present invention provides a stacked chip. For each device bare core, a corresponding combination of an enable signal and a gear control signal can be generated through different combination states of a chip select signal and a plurality of power status signals provided by a logic bare core, thereby disabling or enabling a corresponding voltage regulator in the device bare core, and adjusting the tail current gear of the enabled voltage regulator at the same time. Thus, the power consumption of each device bare core can be adjusted individually. This not only greatly reduces the total power consumption of the entire stacked chip and avoids the problem of further increasing the total power consumption due to an increase in the overall chip temperature, but also meets the different requirements of different users for power consumption and the time to return to a normal power supply mode on the basis of reduced power consumption, thereby greatly improving flexibility and scope of application.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a stacked chip. Background Art

[0002] The standby power consumption of stacked chip (3DIC) products is proportional to the number of stacked layers. The inactive layers are in standby mode. If their standby power consumption is high, the total power consumption of the entire stacked chip will be even greater, causing the overall chip temperature to rise, thereby further increasing the total power consumption.

[0003] Therefore, it is necessary to reduce the standby power consumption of each layer of the stacked chips and control the total power consumption and temperature of the entire stacked chips. Summary of the Invention

[0004] An object of the present invention is to provide a stacked chip, which can reduce the total power consumption of the entire stacked chip and facilitate temperature control of the entire stacked chip.

[0005] To achieve the above objectives, the present invention provides a stacked chip comprising a stacked logic die and f+1 device die, wherein the logic die comprises a controller configured to provide a corresponding chip select signal and a+1 power configuration signals to each device die, respectively, to configure a corresponding power consumption mode for the device die, wherein a and f are integers, a≥1, f≥1, and different combinations of the chip select signal and the a+1 power configuration signals corresponding to each device die correspond to different power consumption modes of the device die;

[0006] Each of the device bare cores has a chip select decoder, peripheral circuits, a device core, and d+1 voltage regulators, wherein:

[0007] The chip select decoder is used to generate b+1 enable signals and c+1 gear control signals of the device die according to the chip select signal and the a+1 power configuration signals provided by the controller to the device die;

[0008] Each of the voltage regulators is respectively coupled to the corresponding enable signal and the gear control signal, and is enabled or disabled by the enable signal coupled thereto, and each of the voltage regulators after being enabled and turned on adjusts the corresponding gear of the tail current according to the gear control signal coupled thereto;

[0009] b, c, and d are all integers, d≥b≥1, d≥c≥0, and the device die has different numbers of the enabled voltage regulators and tail current superposition values ​​in different power consumption modes.

[0010] Optionally, for each device bare core, when the device bare core is selected by the corresponding chip select signal, each of the voltage regulators inside it is enabled and turned on; when it is not selected by the corresponding chip select signal, at least one of the voltage regulators inside it is disabled and turned off.

[0011] Optionally, for each of the device bare cores, the different combination states of the a+1 power configuration signals of the device bare core depend on the user's requirements for the power consumption of the device bare core and the priority of the time for exiting the disable state of each of the voltage regulators.

[0012] Optionally, for each device core, the d+1 voltage regulators include 1 first voltage regulator and d second voltage regulators, and the first voltage regulator of the device core is enabled to be in a normally open state. The more second voltage regulators that are turned off in the device core, the smaller the superposition value of the tail current of the device core, the lower the power consumption of the device core, and the longer the time required for the device core to return to a normal power supply mode. Among the voltage regulators, the minimum value of the tail current after the first voltage regulator is enabled to turn on is the smallest.

[0013] Optionally, for each device core, in the lowest power consumption mode of the device core, only the first voltage regulator is enabled and turned on and the tail current of the first voltage regulator is adjusted to its minimum tail current value, and the tail current superposition value of the device core reaches the minimum; the normal power supply mode of the device core is the highest power consumption mode. In the normal power supply mode, all the voltage regulators of the device core are enabled and turned on, and the tail current of each voltage regulator is adjusted to its maximum value, and the tail current superposition value of the device core reaches the maximum.

[0014] Optionally, the size of transistors in the error amplifier of each second voltage regulator is larger than the size of transistors in the error amplifier of the first voltage regulator.

[0015] Optionally, for each of the device bare cores, each of the gear control signals is at least a 1-bit signal, and each of the voltage regulators is connected to at least one of the gear control signals.

[0016] Optionally, each of the voltage regulators includes an error amplifier, an input switching circuit, an output power circuit, and an output switching circuit, wherein:

[0017] The input switch circuit and the output switch circuit are coupled to the same corresponding enable signal and are configured to be synchronously turned on or off under the control of the enable signal to turn the voltage regulator on or off;

[0018] The error amplifier is coupled to a reference voltage, the corresponding gear control signal, the input switch circuit, and the output power circuit. The error amplifier is configured to adjust its own tail current to a corresponding gear according to the gear control signal, and amplify the difference between the reference voltage and the output voltage of the output power circuit under the action of its own tail current;

[0019] The output power circuit is coupled to the output switch circuit, and is configured to generate and output the output voltage under the output control of the error amplifier.

[0020] Optionally, the error amplifier has a tail current circuit, which includes a tail current tube and a first variable resistor connected in series, the control end of the first variable resistor is coupled to the corresponding gear control signal, the control end of the tail current tube is coupled to the reference voltage, and the gear control signal adjusts the resistance gear of the first variable resistor to adjust the gear of the tail current of the error amplifier.

[0021] Optionally, the error amplifier has a tail current circuit, which includes a controllable current mirror, which is coupled to the corresponding gear control signal and the reference voltage. The controllable current mirror is used to convert the reference voltage into a reference current and output the reference current as the tail current according to a corresponding mirror ratio, and the size of the mirror ratio is adjusted by the gear control signal.

[0022] Optionally, the output power circuit includes a power tube and a second variable resistor connected in series, the control end of the second variable resistor is coupled to the corresponding gear control signal, and the gear control signal adjusts the resistance gear of the second variable resistor to adjust the load capacity of the voltage regulator.

[0023] Optionally, the controller includes:

[0024] a decoder coupled to a corresponding master device and configured to parse a first instruction and a second instruction sent by the master device, perform address decoding on an execution address of the first instruction, and then generate the chip select signal corresponding to each of the device dies according to the address decoding result;

[0025] A mode register group includes f+1 mode registers arranged in a one-to-one correspondence with f+1 device bare cores, each of the mode registers is coupled to the decoder and is used to provide the corresponding a+1 power configuration signals for the coupled device bare core based on the analysis result of the second instruction by the decoder.

[0026] Optionally, the stacked chip is a three-dimensional stacked memory chip, each device die is a memory die, the controller is a memory controller, and multiple memory die are hybrid-bonded together and to the logic die through silicon vias.

[0027] Compared with the prior art, the stacked chip of the present invention can generate a corresponding combination of enable signals and gear control signals for each device bare core through the different combination states of the chip select signal and multiple power status signals provided by the logic bare core, and then can disable (disable) or enable (enable) the corresponding voltage regulator in the device bare core, and at the same time adjust the tail current gear of the enabled voltage regulator, thereby individually adjusting the power consumption of each device bare core. This not only greatly reduces the total power consumption of the entire stacked chip, avoiding the problem of further increasing the total power consumption due to the increase in the overall temperature of the chip, but also can meet the different needs of different users for power consumption and the time to return to normal power supply mode on the basis of reduced power consumption, and greatly improves the flexibility and scope of application. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0029] Figure 1 Schematic diagram of the packaging of stacked chips according to a specific embodiment of the present invention.

[0030] Figure 2 It is a schematic diagram of the internal structure of the device bare core of the stacked chip according to a specific embodiment of the present invention.

[0031] Figure 3 Schematic diagram of the LDO architecture within the device die of the stacked chip according to a specific embodiment of the present invention.

[0032] Figure 4 and Figure 5 They are Figure 3 The circuit example schematic of the LDO is shown.

[0033] Figure 6 This is a schematic diagram of an example circuit of a reference voltage source inside a device die of a stacked chip according to a specific embodiment of the present invention.

[0034] Figure 7 This is an exemplary schematic diagram of a stacked chip according to a specific embodiment of the present invention being applied to a three-dimensional stacked memory chip.

[0035] Figure 8 This is a schematic diagram illustrating an example of a signal combination state when the stacked chip according to a specific embodiment of the present invention is applied to a three-dimensional stacked memory chip. DETAILED DESCRIPTION

[0036] In the following description, a large number of specific details are given to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, some technical features known in the art are not described to avoid confusion with the present invention. It should be understood that the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present invention to those skilled in the art. The same reference numerals throughout represent the same elements. It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected to the other element, or there can be intervening elements. Conversely, when an element is referred to as being "directly connected to" another element, there are no intervening elements. When used herein, the singular forms "a," "an," and "said / the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of certain features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0037] Please refer to Figure 1 An embodiment of the present invention provides a stacked chip, which includes a stacked logic die 1 and f+1 device dies 30 to 3f, where f is an integer and f≥1. The logic die 1 includes a controller 10.

[0038] The controller 10 can be configured to provide a corresponding chip select signal (CS) and a+1 power configuration signals (PM) to each device die 30-3f, thereby configuring the device die in a user-defined power consumption mode. For each device die, different combinations of the chip select signal and a+1 power configuration signals received correspond to different power consumption modes for that device die. Where a and f are integers, and a ≥ 1, f ≥ 1.

[0039] In one example, the controller 10 can be coupled to a corresponding master device (not shown) and generate chip select signals and a+1 power configuration signals for each device die 30~3f according to the corresponding instructions of the master device. The different combination states of the chip select signals and a+1 power configuration signals of each device die 30~3f depend on the user's requirements for power consumption and the disable state exit time priority of each voltage regulator (voltage regulator, low-dropout linear regulator LDO is used as an example below, but the present invention is not limited to this and other voltage regulators can also be used) LDO_0~LDO_d in the device die. The instructions of the master device carry these user requirements.

[0040] As an example, see Figure 1 , the controller 10 includes a decoder 11 and a mode register group.

[0041] Among them, the decoder 11 is coupled to a master device (not shown) to parse the first instruction (such as read, write, refresh, read first then write, write first then read, etc.) and the second instruction sent by the master device, and performs address decoding on the execution address ADD of the parsed first instruction, and then generates chip select signals CS0~CSf corresponding to each device bare core 30~3f according to the corresponding address decoding results.

[0042] The mode register group includes f+1 mode registers MR0-MRf, which correspond one-to-one to f+1 device dies 30-3f. Each mode register MR0-MRf can be a single register or a register group consisting of multiple registers. Each mode register is coupled to the decoder 11 and is configured to generate a+1 power configuration signals for the corresponding device die based on the decoder 11's parsing result of a second instruction (e.g., a register value configuration instruction) (e.g., one of the parsed register configuration values ​​MRS0-MRSf).

[0043] For example, decoder 11 parses the chip select signal corresponding to device die 30 as CS0 and the register configuration value as MRS0. Mode register MR0 generates a+1 power configuration signals PM0_0, PM0_1, ..., PM0_a based on register configuration value MRS0 and provides them to the chip select decoder of device die 30. Decoder 11 parses the chip select signal corresponding to device die 31 as CS1 and the register configuration value as MRS1. Mode register MR1 generates a+1 power configuration signals PM1_0, PM1_1, ..., PM1_a based on register configuration value MRS1 and provides them to the chip select decoder of device die 31. Similarly, decoder 11 parses the chip select signal corresponding to device die 3f as CSf and the register configuration value as MRSf. Mode register MRf generates a+1 power configuration signals PMf_0, PMf_1, ..., PMf_a based on register configuration value MRSf and provides them to the chip select decoder of device die 3f.

[0044] Please refer to Figure 1 and Figure 2 Each device die 3k (k is an integer and 0≤k≤f) among the device die 30~3f includes a device core 300, a peripheral circuit 301, a power management circuit 302 and a chip select decoder 303.

[0045] For each device die 3k, the chip select decoder 303 is coupled to the controller 10 and the power management circuit 302, and is used to generate b+1 enable signals ENk_0~ENk_b and c+1 gear control signals I_ENk_0~I_ENk_c for the device die 3k based on the chip select signal CSk and a+1 power configuration signals PMk_0~PMk_a provided by the controller 10 for the device die 3k, where a, b, and c are all integers, a≥0, b≥1, and c≥0.

[0046] For each device die 3k, the power management circuit 302 includes d+1 voltage regulators LDO_0 through LDO_d. Each voltage regulator LDO_0 through LDO_d is coupled to a corresponding voltage Vref, a corresponding enable signal ENk from b+1 enable signals ENk_0 through ENk_b, and a corresponding gear control signal I_ENk from c+1 gear control signals I_ENk_0 through I_ENk_c. Each voltage regulator LDO_0 through LDO_d is enabled or disabled by the enable signal ENk coupled to it, and the tail current Is of each voltage regulator LDO_0 through LDO_d after being enabled is adjusted to the corresponding gear by the gear control signal I_ENk coupled to it. Where d is an integer, and d ≥ b and d ≥ c.

[0047] For each device die 3 k , in different power consumption modes thereof, at least one of the number n of enabled second voltage regulators and the tail current superposition value ΣIs is different.

[0048] Optionally, for each device bare core 3k, the voltage regulator LDO_0 is the first voltage regulator, and the voltage regulators LDO_1~LDO_d are all second voltage regulators. Among the voltage regulators LDO_0~LDO_d of the device bare core 3k, the first voltage regulator LDO_0 is enabled to be in the normally open state, and the minimum tail current Is_min after the first voltage regulator LDO_0 is enabled to be turned on is the smallest, and the more the number n of the closed second voltage regulators is, the smaller the tail current superposition value ∑Is of the device bare core 3k, the lower the power consumption of the device bare core 3k, and the longer the time required for the device bare core 3k to return to the normal power supply mode.

[0049] It is worth noting that for each device die 3k, each voltage regulator LDO therein receives a corresponding gear control signal I_ENk. When I_ENk is a 1-bit signal, it can implement two gears of tail current adjustment. When I_ENk is a multi-bit signal, it can implement tail current adjustment for more gears. In other embodiments, when each gear control signal I_ENk is a 1-bit signal, each voltage regulator LDO can also receive multiple gear control signals I_ENk, which can implement tail current adjustment for more gears of the voltage regulator LDO.

[0050] In addition, for each device die 3k, the internal voltage regulators LDO_0 to LDO_d can be coupled to the same reference voltage Vref or different reference voltages Vref. The reference voltage Vref coupled to each voltage regulator LDO can be provided by a corresponding reference voltage source 3020. The reference voltage source 3020 can be implemented using any suitable circuit design.

[0051] For example, please refer to Figure 6The reference voltage source 3020 includes an operational amplifier A0, switches M0-M1, a resistor R0, a first current source I1, and a second current source I2. The switch M0 can be any suitable switching element, such as an NMOS transistor. One input of the operational amplifier A0 is coupled to a bandgap voltage VBG, and another input is coupled to one end of the resistor R0 and one end of the switch M0 (e.g., the source of the NMOS transistor). The other end of the resistor is grounded. The output of the operational amplifier A0 is coupled to the control end of the switch M0 (e.g., the gate of the NMOS transistor), and the other end of the switch M0 (e.g., the drain of the NMOS transistor) is coupled to a power supply voltage VDD. The first current source I1 employs a current mirror design and can include PMOS transistors PU0-PUe and PMOS transistors PD0-PDe. The drain of PMOS transistor PU0 is coupled to the source of PMOS transistor PD0, the drain of PMOS transistor PU1 is coupled to the source of PMOS transistor PD1, and so on. The drain of PMOS transistor PUe is coupled to the source of PMOS transistor PDe. The gates of the PMOS transistors PD0 to PDe are coupled to the trim signal e+1 bit. <e:0>, the gates of PMOS transistors PU0 to PUe are all coupled to the output terminal of operational amplifier A0, the sources of PMOS transistors PU0 to PUe are all coupled to power supply voltage VDD, and the drains of PMOS transistors PD0 to PDe are all coupled to the drain and gate of switching transistor M1 and the output terminal of this reference voltage source. The source of this switching transistor M1 is grounded. Among them, the superimposed value of the current provided by first current source I1 and the current provided by second current source I2 is converted into reference voltage Vref.

[0052] In one example, please refer to Figure 2 , in one of the device dies 3k (k is an integer and 0 ≤ k ≤ f) among device dies 30 to 3f, first voltage regulator LDO_0 is coupled to enable signal ENk_0, and this enable signal ENk_0 enables first voltage regulator LDO_0 to be in a normally open state. d second voltage regulators LDO_1 to LDO_d are respectively coupled to corresponding enable signals ENk among enable signals ENk_1 to ENk_b. When b < d, at least two second voltage regulators can be coupled to the same enable signal ENk to be opened or closed synchronously. In addition, when c < d, at least two of voltage regulators LDO_0 to LDO_d can be coupled to the same gear control signal I_ENk to be adjusted to the same tail current gear. For example, please refer to Figure 2 , first voltage regulator LDO_0 is coupled to enable signal ENk_0 and gear control signal I_ENk_0, both second voltage regulators LDO_1 and LDO_2 are coupled to enable signal ENk_1 and gear control signal I_ENk_1, both second voltage regulators LDO_d - 1 and LDO_d are coupled to gear control signal I_ENk_c, but second voltage regulator LDO_d - 1 is coupled to enable signal ENk_b - 1, and second voltage regulator LDO_d is coupled to enable signal ENk_b.

[0053] In addition, for each device die 3k (k is an integer and 0 ≤ k ≤ f) among device dies 30 to 3f, only when it is selected by its corresponding chip select signal CSk, all of its voltage regulators LDO_0 to LDO_d are enabled and opened, and when it is not selected by its corresponding chip select signal CSk, at least one of voltage regulators LDO_0 to LDO_d inside this device die 3k is disabled and closed (for example, only LDO_0 is enabled and opened, or LDO_0 is enabled and opened, and at the same time one or more of LDO_1 to LDO_d are disabled and closed). And the superimposed value ∑Is of the tail current of this device die 3k is the sum of the tail currents of all the opened LDOs among LDO_0 to LDO_d.

[0054] In one example, for each device die 3k (k is an integer and 0≤k≤f) among the device die 30~3f, its first voltage regulator LDO_0 is enabled to be in a normally open state by the enable signal ENK_0 coupled thereto, and among its second voltage regulators LDO_1~LDO_d, the more second voltage regulators that are turned off, the smaller the tail current superposition value ∑Is of the device die 3k, the lower the power consumption of the device die 3k, and the longer the time required for the device die 3k to recover to the normal power supply mode. Accordingly, the total power consumption of the stacked chip is also lower, and the longer the time required for the stacked chip to recover to the normal power supply mode is also.

[0055] Optionally, for each device die 3k (where k is an integer and 0≤k≤f) among the device die 30-3f, in the lowest power consumption mode of the device die 3k, only the first voltage regulator LDO_0 thereof is turned on and the tail current Is of the first voltage regulator LDO_0 is 3k_LDO_0 Is adjusted to its minimum tail current value Is 3k_min_LDO_0 , the tail current superposition value ∑Is of the bare core 3k of the device 3k Reach its minimum (i.e. Is 3k_min_LDO_0 The normal power supply mode of the bare core 3k of the device is the highest power consumption mode. In this normal power supply mode, LDO_0~LDO_d of the bare core 3k of the device are all turned on, and the tail currents of LDO_0~LDO_d are all adjusted to their respective maximum values ​​(i.e. Is 3k__LDO_0 =Is 3k_max_LDO_0 , Is 3k_LDO_1 =Is 3k_max_LDO_1 , ...Is 3k_LDO_d =Is 3k_max_LDO_d ), the tail current superposition value ∑Is of the bare core 3k of the device 3k Reaching the maximum ∑Is 3k_max= Is 3k_max_LDO_0 +Is 3k_max_LDO_1 +……+ Is 3k_max_LDO_d Among them, Is 3k__LDO_0 、Is 3k_LDO_1 These tail currents are not shown in the figures and are described here only to distinguish the tail currents and their sizes of each LDO.

[0056] In this embodiment, the internal circuit structures of the second voltage regulators LDO_1 to LDO_d inside each device bare core can be the same. In other embodiments, inside each device bare core, at least two second voltage regulators have different minimum tail currents after being enabled because of their different internal circuit structures or because the internal circuit structures of the at least two second voltage regulators are the same but the transistor sizes used are different.

[0057] In an example, see Figure 3 , each voltage regulator LDO_0~LDO_d l ( l is an integer and 0≤ l ≤d) each includes an error amplifier 51 , an input switching circuit 52 , an output power circuit 53 and an output switching circuit 54 .

[0058] The input switch circuit 52 and the output switch circuit 54 are coupled to the same corresponding enable signal ENk_j (where j is an integer and 0≤j≤b), and are used to be synchronously turned on or off under the control of the enable signal ENk_j, so that the voltage regulator LDO_ l When ENk_j is high, the voltage regulator LDO_ l When ENk_j is low, the voltage regulator LDO_ l closure.

[0059] The error amplifier 51 is coupled to a reference voltage Vref, a corresponding gear control signal I_ENk_i (where i is an integer and 0≤i≤c), an input switch circuit 52, and an output power circuit 53. When the input switch circuit 52 is turned on, the error amplifier 51 adjusts its own tail current to the corresponding gear according to the gear control signal I_ENk_i, and amplifies the difference between the reference voltage Vref and the output voltage VDLY of the power management circuit 302 under the action of its own tail current.

[0060] The output power circuit 53 is coupled to the output switch circuit 54 and the output terminal of the power management circuit 302 , and is configured to generate and output the output voltage VDLY under the output control of the error amplifier 51 when the input switch circuit 52 and the output switch circuit 54 are turned on.

[0061] It should be understood that the error amplifier 51 , the input switch circuit 52 , the output power circuit 53 and the output switch circuit 54 may adopt any appropriate circuit design, and the present invention does not impose any specific limitation thereto.

[0062] In an example, see Figures 3 to 5 The input switch circuit 52 includes an NMOS transistor N0, and the output switch circuit 54 includes an NMOS transistor N2. The gates of N0 and N2 are both coupled to the enable signal ENk_j, the sources of N0 and N2 are both grounded, the drain of N0 is coupled to the tail current circuit 513, and the drain of N2 is coupled to one end of the output power circuit 53. In other examples, N0 and N2 can also be replaced by any suitable switching element such as an NPN transistor.

[0063] In an example, see Figures 3 to 5 The output power circuit 53 includes a power tube T5 and a second variable resistor R2 connected in series between the power supply voltage VDD and the output switch circuit 54. The control end of the power tube T5 is coupled to the output end of the error amplifier 51. The control end of the second variable resistor R2 is coupled to the corresponding gear control signal I_ENk_i. The gear control signal I_ENk_i adjusts the resistance gear of the second variable resistor R2 to adjust the voltage regulator LDO_ l The power tube T5 may be a PMOS tube or a PNP transistor.

[0064] In addition, the output power circuit 53 may also have other circuit parts. For example, the output power circuit 53 also includes a compensation circuit 55 coupled between the control terminal of the power tube T5 and the error amplifier 51. The compensation circuit 55 may include a Miller capacitor C. The Miller capacitor C is used for frequency compensation to ensure that the voltage regulator LDO_ l Maintaining stability in a wider frequency band and reasonably designing the value and position of the Miller capacitor C can effectively control the pole position and ensure that the voltage regulator LDO_ l Stability under various load conditions. For another example, the output power circuit 53 may further include a buffer circuit (not shown) disposed between the control terminal of the power transistor T5 and the error amplifier 51. The buffer circuit is used to overcome the feedforward effect of the Miller capacitor C and eliminate the zero point introduced by the Miller capacitor C.

[0065] In one example, the error amplifier 51 includes a differential input circuit 511 , an active load circuit 512 , and a tail current circuit 513 .

[0066] The differential input circuit 511 includes an input pair of transistors N3 and N4. Both N3 and N4 can be NMOS transistors. The gate of N3 serves as the first input terminal of the error amplifier 51, coupled to the reference voltage Vref. The gate of N4 serves as the second input terminal of the error amplifier 51, coupled to the output terminal of the power management circuit 302 (i.e., coupled to the output voltage VDLY). The sources of N3 and N4 are coupled to the tail current circuit 513, and the drains of N3 and N4 are coupled to the active load circuit 512. In other examples, N3 and N4 can also be replaced by any suitable switching element, such as an NPN transistor.

[0067] The tail current circuit 513 is coupled to the reference voltage Vref and the gear control signal I_ENk_i, and generates a tail current based on the reference voltage Vref, and provides the generated tail current to N3 and N4 respectively, so that N3 and N4 are always in a suitable working state. The gear of the tail current generated by the tail current circuit 513 is adjusted by the gear control signal I_ENk_i. The setting of the tail current circuit 513 can play the following roles: (1) ensuring that the operating points of N3 and N4 can be constant, avoiding problems such as nonlinear distortion caused by unstable operating points of the circuit, and improving circuit stability; (2) eliminating the influence of noise and interference signals, improving the anti-interference ability of the circuit, and ensuring the sensitivity and reliability of the circuit; (3) providing a stable DC operating point, thereby improving the DC gain of the circuit, so that the error amplifier 51 can amplify small signals, and improving the amplification capability of the circuit.

[0068] The tail current circuit 513 may adopt any suitable design, and the present invention does not impose any specific limitation on this.

[0069] For example, see Figure 4 The tail current circuit 513 includes a tail current tube N1 and a first variable resistor R1 connected in series. The control terminal of the first variable resistor R1 is coupled to a corresponding gear control signal I_ENk_i. The control terminal of the tail current tube N1 is coupled to a reference voltage Vref. The gear control signal I_ENk_i adjusts the resistance gear of the first variable resistor R1 to adjust the gear of the tail current of the error amplifier 51. Among them, N1, N3 and N4 can all be NMOS. The control terminal of N1 is the gate of the NMOS. The source of N1 is connected to one end of R1. The drain of N1 is connected to the source of the input pair of tubes N3 and N4. The other end of R1 is grounded. In other examples, N1, N3 and N4 can be replaced by any suitable switching element such as a transistor.

[0070] For another example, please refer to Figure 3 The tail current circuit 513 includes a controllable current mirror 5131, which can adopt any suitable current mirror design and couple the corresponding gear control signal I_ENk_i and the reference voltage Vref. The controllable current mirror 5131 is used to convert the reference voltage Vref into a reference current, and mirror the reference current according to the corresponding mirror ratio m to output the tail current Is of the corresponding gear, wherein the size of the mirror ratio m is adjusted by the gear control signal I_ENk_i, thereby I_ENk_i can adjust the gear of the tail current Is.

[0071] The active load circuit 512 is coupled to the differential input circuit 511 and the power supply voltage VDD, and can adopt any suitable circuit design such as a current mirror. The setting of the active load circuit 512 can increase the output power and output voltage of the error amplifier 51, while increasing the circuit stability and frequency response capability of the error amplifier 51, and reducing the power loss caused by the passive load, thereby improving the efficiency of the error amplifier 51.

[0072] For example, see Figure 4 The active load circuit 512 includes PMOS transistors T1-T4. The gates of the PMOS transistors T1-T4 are coupled to each other and to the drain of N3 and the drain of the PMOS transistor T2. The drain of the PMOS transistor T1 is coupled to the source of the PMOS transistor T2. The drain of the PMOS transistor T4 is coupled to the source of the PMOS transistor T3. The drain of the PMOS transistor T3 is coupled to the drain of N4. The sources of the PMOS transistors T1 and T4 are both coupled to the power supply voltage VDD.

[0073] For another example, please refer to Figure 5 The active load circuit 512 includes PMOS transistors T1-T4 and NMOS transistors N5-N8. The sources of the PMOS transistors T1-T4 are all coupled to the power supply voltage VDD. The gates of the PMOS transistors T1 and T2 are coupled to each other and to the drain of N3. The gates of the PMOS transistors T3 and T4 are coupled to each other and to the drain of N4. The drain of the PMOS transistor T1 is coupled to the drain of the NMOS transistor N5 and the gates of the NMOS transistors N5-N8. The source of the NMOS transistor N5 is coupled to the drain of the NMOS transistor N6. The drain of the PMOS transistor T4 is coupled to the gate of the PMOS transistor T5 and the drain of the NMOS transistor N7. The source of the NMOS transistor N7 is coupled to the source of the NMOS transistor N8. The sources of the NMOS transistors N6 and N8 are both grounded.

[0074] In one example, the first voltage regulator LDO_0 adopts Figure 4 The circuit design shown in the figure uses the second voltage regulator LDO_1~LDO_d. Figure 5 In the circuit design shown, the transistors in the second voltage regulators LDO_1 through LDO_d are larger than those in the first voltage regulator LDO_0. As a result, the transistors in the second voltage regulators LDO_1 through LDO_d are larger, resulting in greater tail current and faster circuit response, providing stronger power supply capabilities and transient response capabilities.

[0075] The stacked chip of this embodiment can flexibly select the combination of chip select signal CSk and power configuration signals PMk_0-PMk_a for each device die 3k, based on different customer requirements for power consumption and disable exit time priorities. This generates b+1 enable signals ENk_0-ENk_b and c+1 range control signals I_ENk_0-I_ENk_c corresponding to the device die 3k, thereby adjusting the device die 3k to a power consumption mode having corresponding tail current superposition values. This provides more comprehensive control over the power consumption mode of the stacked chip. Power consumption can be reduced by disabling unselected device die, while multiple controls, such as corresponding voltage regulator LDO control and tail current range adjustment control, can be superimposed on each selected and unselected device die. Ultimately, the disable exit time can be further reduced while reducing power consumption. This stacked chip can be applied to various chips, such as three-dimensional stacked memory chips (e.g., three-dimensional stacked DRAM).

[0076] The following takes the stacked chip as a three-dimensional stacked memory chip, a=1, b=2, c=0 as an example, and combines Figures 7 and 8 , the principle of the technical solution of the present invention is described in detail. In other examples, a, b, and c can also take other integer values.

[0077] Please combine Figure 1 and Figure 7 The f+1 device dies 30-30f stacked in this three-dimensional stacked memory chip are all memory dies (e.g., DRAM dies). Their controller 10 is a memory controller, which can be integrated into the logic die 1. The f+1 device dies 30-30f and the logic die 1 are connected via through-silicon vias (TSVs) and hybrid bonding (HB). Each memory die includes a power management circuit 302, a chip select decoder 303, peripheral circuits 301, and a memory array (i.e., the device core 300 is the memory array of the memory die). The power management circuit 302 includes a reference voltage source 3020 and seven voltage regulators LDO_0-LDO_6. Each voltage regulator LDO_0-LDO_6 has an input coupled to the output of the reference voltage source 3020 to receive the same reference voltage Vref. The outputs of the voltage regulators LDO_0-LDO_6 are coupled to the output of the power management circuit 302 to provide an output voltage VDLY.

[0078] In this embodiment, the voltage regulators LDO_1 to LDO_6 use the same circuit design, and the voltage regulator LDO_0 uses a circuit design different from that of the voltage regulator LDO_1. For example, the voltage regulators LDO_1 to LDO_6 all use Figure 5 The circuit design shown in the figure uses the voltage regulator LDO_0 Figure 4 In the circuit design shown, compared to voltage regulator LDO_0, voltage regulators LDO_1 to LDO_6 have larger transistors, larger tail currents, and faster response speeds, providing stronger power supply capabilities and transient response capabilities.

[0079] The memory controller 10 can implement interface conversion between a corresponding master device (not shown) and the f+1 memory die (i.e., device die 30-3f), and complete address decoding, data format conversion (such as data bit width), and instruction (CMD) parsing between the master device and the f+1 memory die (i.e., device die 30-3f), as well as converting the corresponding instructions issued by the master device into signals that can be recognized by the f+1 memory die (i.e., device die 30-3f), thereby achieving the necessary control of the master device's access to the f+1 memory die (i.e., device die 30-3f) (including control of address signals, data signals, and various instruction signals).

[0080] The peripheral circuits 301 may include a row address decoder, a column address decoder, a sense amplifier (SA), an input / output (IO) circuit, a latch circuit, and other peripheral circuits. These peripheral circuits 301 are powered by the output voltage VDLY of the power management circuit 302 (i.e., the output voltage of the output terminals of the voltage regulators LDO_0 to LDO_6 coupled together).

[0081] The memory controller 10 parses the master device's command CMD and the instruction execution address to obtain chip select signals CS0-CSf and power configuration signals for each device die 30-3f. For each device die 3k (k is an integer and 0≤k≤3f), it has two power configuration signals PMk_0 and PMk_1. The combination of CSk and PMk_0 and PMk_1 can reflect the power consumption mode configured by the user for the memory die 3k. This generates a corresponding combination of three enable signals ENk_0-ENk_2 and a gear control signal I_ENk_0 for the memory die 3k. Among them, ENk_0 is coupled to the voltage regulator LDO_0 inside the memory bare core 3k, ENk_1 is coupled to the voltage regulators LDO_1~LDO_3 inside the memory bare core 3k, ENk_2 is coupled to the voltage regulators LDO_4~LDO_6 inside the memory bare core 3k, and the voltage regulators LDO_0~LDO_6 inside the memory bare core 3k are all coupled to I_ENk_0.

[0082] In this embodiment, for any layer of memory die (i.e., "device die 3k", hereinafter referred to as "memory die 3k" for ease of understanding), the combination of CSk, PMk_0, and PMk_1 generates six combination states of ENk_0 to ENk_2 and I_ENk_0, thereby realizing six different low power modes, such as Figure 8 As shown. Among them:

[0083] (1) CSk = 1, PMk_0 = 0, PMk_1 = 0, the memory die 3k is selected (i.e., chip selected), and its power consumption mode is its normal power supply mode, which is also its maximum power consumption mode. In this mode, no recovery time is required, instructions can be issued at any time, and two word lines (WL) in the memory die 3k are allowed to be refreshed simultaneously. For the memory die 3k, its ENk_0 = 1, ENk_1 = 1, ENk_2 = 1, I_ENk_0 = 1, its voltage regulators LDO_0 to LDO_6 are all turned on, and the tail current in each LDO in LDO_0 to LDO_6 is adjusted to the maximum tail current. As a result, the tail current superposition value of the memory die 3k is the largest, and its standby power consumption is the largest. The tail current superposition value in this mode is, for example, 825 μA.

[0084] (2) CSk = 1, PMk_0 = 0, PMk_1 = 1. The memory die 3k is selected (i.e., chip-selected), and its power consumption mode is a low-power mode (referred to as the "first low-power mode") with lower power consumption than its normal power supply mode. In this mode, the recovery time is very short, and there is essentially no need to wait for the power supply to stabilize before issuing instructions. For the memory die 3k, its ENk_0 = 1, ENk_1 = 1, ENk_2 = 1, and I_ENk_0 = 1. Its voltage regulators LDO_0 to LDO_6 are all turned on, and the tail current in each of the LDOs in the voltage regulators LDO_0 to LDO_6 is adjusted to the minimum tail current value. As a result, the tail current sum value and standby power consumption of the selected memory die 3k are both smaller than those in the normal power supply mode. The tail current sum value in the first low-power mode is, for example, 568 μA.

[0085] (3) CSk=0, PMk_0=0, PMk_1=0, the memory die 3k is not selected (i.e., not chip selected), and its power consumption mode is a second low power consumption mode with lower power consumption than its first low power consumption mode. In this mode, there is no recovery time, and instructions can be issued at any time, allowing only one word line WL in the memory die 3k to be refreshed separately. For the memory bare core 3k, in the second low power mode, its ENk_0=1, ENk_1=1, ENk_2=0, I_ENk_0=1, its voltage regulators LDO_0~LDO_3 are all turned on, its voltage regulators LDO_4~LDO_6 are all turned off, and the tail current in each LDO in its voltage regulators LDO_0~LDO_3 is adjusted to the maximum tail current value. Therefore, the tail current superposition value and standby power consumption of the selected memory bare core 3k are smaller than the above-mentioned first low power mode. The tail current superposition value in the second low power mode is, for example, 436μA.

[0086] (4) CSk = 0, PMk_0 = 0, PMk_1 = 1. The memory die 3k is not selected (i.e., not chip selected), and its power consumption mode is a third low-power mode with lower power consumption than its second low-power mode. In this mode, the recovery time is medium, and it is necessary to wait for the power supply to stabilize before issuing instructions. For the memory die 3k, in this third low-power mode, its ENk_0 = 1, ENk_1 = 1, ENk_2 = 0, I_ENk_0 = 0, its voltage regulators LDO_0 to LDO_3 are all turned on, its voltage regulators LDO_4 to LDO_6 are all turned off, and the tail current of each LDO in its voltage regulators LDO_0 to LDO_3 is adjusted to the minimum tail current value. As a result, the tail current superposition value and standby power consumption of the selected memory die 3k are both smaller than those in the second low-power mode. The tail current superposition value in this third low-power mode is, for example, 369 μA.

[0087] (5) CSk = 0, PMk_0 = 1, PMk_1 = 0. The memory die 3k is not selected (i.e., not chip-selected), and its power consumption mode is a fourth low-power mode with lower power consumption than its third low-power mode. In this mode, the recovery time is longer, and it is necessary to wait for the power supply to stabilize before issuing instructions. For the memory die 3k, in this fourth low-power mode, its ENk_0 = 1, ENk_1 = 0, ENk_2 = 0, I_ENk_0 = 1, its voltage regulator LDO_0 is turned on, its voltage regulators LDO_1 to LDO_6 are turned off, and the tail current of its voltage regulator LDO_0 is adjusted to the maximum tail current value. As a result, the tail current superposition value and standby power consumption of the selected memory die 3k are both smaller than those in the third low-power mode. The tail current superposition value in this fourth low-power mode is, for example, 237 μA.

[0088] (6) CSk = 0, PMk_0 = 1, PMk_1 = 1. The memory die 3k is not selected (i.e., not chip selected), and its power consumption mode is a fifth low-power mode with lower power consumption than its fourth low-power mode. This is also the lowest power consumption mode of the memory die 3k. In this mode, the recovery time is the longest, and it is necessary to wait for the power supply to stabilize before issuing instructions. For the memory die 3k, in this fifth low-power mode, its ENk_0 = 1, ENk_1 = 0, ENk_2 = 0, I_ENk_0 = 0, its voltage regulator LDO_0 is turned on, its voltage regulators LDO_1 to LDO_6 are all turned off, and the tail current of its voltage regulator LDO_0 is adjusted to the minimum tail current value. As a result, the tail current superposition value and standby power consumption of the selected memory die 3k are both smaller than those in the fourth low-power mode. The tail current superposition value in the fourth low-power mode is, for example, 138 μA.

[0089] Obviously, for each device bare core 3k, different combination states of ENk_0, ENk_1, ENk_2 and I_ENk_0 can be configured through different combination states of its corresponding chip select signal CSk and power configuration signals PMk_0~PMk_1, thereby realizing different low-power modes of the device bare core 3k. Therefore, the chip select signal CSk and power configuration signals PMk_0~PMk_1 of each device bare core 3k can be flexibly configured according to user needs, thereby meeting the user's requirements for reliability, low power consumption and short recovery time of the device bare core 3k and the entire stacked chip. Moreover, in this example, CSk, PMk_0, PMk_1, ENk_0, ENk_1, ENk_2, and I_ENk_0 are all 1-bit signals, and each signal has only two states, "1" and "0". I_ENk_0 can implement two-speed tail current adjustment for each voltage regulator LDO in the device bare core 3k. However, the technical solution of the present invention is not limited to this. In other embodiments of the present invention, when there are more power configuration signals, that is, a is greater than 1, each I_ENk generated is a multi-bit signal. Figure 4 For example, a corresponding number of first variable resistors can be set in series or in parallel in the tail current circuit 513 of each voltage regulator LDO, so that each LDO can achieve more gears of tail current adjustment when connected to one I_ENk. For example, each I_ENk is a 2-bit signal, and each voltage regulator LDO is still connected to one I_ENk (which is a 2-bit signal). The I_ENk can achieve 2 gears of tail current adjustment for the voltage regulator LDO. 2 = 4 tail current gear adjustments, and so on, when each I_ENk is an x-bit signal, each voltage regulator LDO is still connected to 1 I_ENk (which is an x-bit signal), and the I_ENk can achieve 2 for the voltage regulator LDO. x The tail current gear adjustment.

[0090] In other examples, according to control requirements, for each device bare core 3k, one or more of its chip select signal CSk, each power configuration signal PMk, and each gear control signal I_ENk can be set as a multi-bit signal, wherein, as the number of bits of a certain signal increases, the corresponding circuit can be adaptively adjusted and deployed. The present invention does not make specific limitations on this, as long as the technical purpose of the present invention can be achieved.

[0091] To sum up, the stacked chip of the present invention can generate a corresponding combination of enable signals and gear control signals for each device bare core through the different combination states of the chip select signal and multiple power status signals provided by the logic bare core, and then can disable (disable) or enable (enable) the corresponding voltage regulator in the device bare core, and at the same time adjust the tail current gear of the enabled voltage regulator, thereby adjusting the power consumption of each device bare core individually. This not only greatly reduces the total power consumption of the entire stacked chip, avoiding the problem of further increasing the total power consumption due to the increase in the overall temperature of the chip, but also meets the different requirements of different users for power consumption and the time to return to normal power supply mode on the basis of reduced power consumption, and greatly improves the flexibility and scope of application.

[0092] In addition, the stacked chip of the present invention can be shipped in any desired and appropriate form, such as a wafer, a bare die, or a packaged stacked chip, and the present invention does not make any specific limitation on this.

[0093] The above description is only a description of the preferred embodiment of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure are within the scope of protection of the technical solution of the present invention.

Claims

1. A stacked chip, characterized in that: The method comprises a stacked logic die and f+1 device die, wherein the logic die includes a controller, the controller being configured to provide a corresponding chip select signal and a+1 power configuration signals to each of the device die, so as to configure a corresponding power consumption mode for the device die, wherein a and f are integers, a≥1, f≥1, and different combinations of the chip select signal and the a+1 power configuration signals corresponding to each of the device die correspond to different power consumption modes of the device die; Each device die has a chip select decoder, peripheral circuits, a device core, and d+1 voltage regulators, wherein: The chip select decoder is used to generate b+1 enable signals and c+1 gear control signals of the device die according to the chip select signal and the a+1 power configuration signals provided by the controller to the device die; Each of the voltage regulators is respectively coupled to the corresponding enable signal and the gear control signal, and is enabled or disabled by the enable signal coupled thereto, and each of the voltage regulators after being enabled and turned on adjusts the corresponding gear of the tail current according to the gear control signal coupled thereto; b, c, and d are all integers, d≥b≥1, d≥c≥0, and the device die has different numbers of the enabled voltage regulators and tail current superposition values ​​in different power consumption modes.

2. The stacked chip according to claim 1, wherein: For each device bare core, when the device bare core is selected by the corresponding chip select signal, each of the voltage regulators inside it is enabled and turned on; when the device bare core is not selected by the corresponding chip select signal, at least one of the voltage regulators inside it is disabled and turned off.

3. The stacked chip according to claim 1, wherein: For each of the device bare cores, the different combination states of the a+1 power configuration signals of the device bare core depend on the user's requirements for the power consumption of the device bare core and the priority of the exit time of the disable state of each of the voltage regulators.

4. The stacked chip according to claim 1, wherein: For each device core, its d+1 voltage regulators include 1 first voltage regulator and d second voltage regulators. The first voltage regulator of the device core is enabled to be in a normally open state. The more the second voltage regulators that are turned off in the device core are, the smaller the superposition value of the tail current of the device core is, the lower the power consumption of the device core is, and the longer the time required for the device core to return to a normal power supply mode is. Among the voltage regulators, the minimum value of the tail current after the first voltage regulator is enabled and turned on is the smallest.

5. The stacked chip according to claim 4, wherein: For each of the device cores, in the lowest power consumption mode of the device core, only the first voltage regulator is enabled and turned on, and the tail current of the first voltage regulator is adjusted to its minimum tail current value, and the superposition value of the tail currents of the device core reaches the minimum; the normal power supply mode of the device core is the highest power consumption mode. In the normal power supply mode, all the voltage regulators of the device core are enabled and turned on, and the tail current of each voltage regulator is adjusted to its maximum value, and the superposition value of the tail currents of the device core reaches the maximum.

6. The stacked chip according to claim 4, wherein: The size of transistors in the error amplifier of each of the second voltage regulators is larger than the size of transistors in the error amplifier of the first voltage regulator.

7. The stacked chip according to claim 1, wherein: For each of the device bare cores, each of the gear control signals is at least a 1-bit signal, and each of the voltage regulators is connected to at least one of the gear control signals.

8. The stacked chip according to claim 1, wherein: Each of the voltage regulators includes an error amplifier, an input switching circuit, an output power circuit, and an output switching circuit, wherein: The input switch circuit and the output switch circuit are coupled to the same corresponding enable signal and are configured to be synchronously turned on or off under the control of the enable signal to turn the voltage regulator on or off; The error amplifier is coupled to a reference voltage, the corresponding gear control signal, the input switch circuit, and the output power circuit. The error amplifier is configured to adjust its own tail current to a corresponding gear according to the gear control signal, and amplify the difference between the reference voltage and the output voltage of the output power circuit under the action of its own tail current; The output power circuit is coupled to the output switch circuit, and is configured to generate and output the output voltage under the output control of the error amplifier.

9. The stacked chip according to claim 8, wherein: The error amplifier has a tail current circuit, which includes a tail current tube and a first variable resistor connected in series. The control end of the first variable resistor is coupled to the corresponding gear control signal, and the control end of the tail current tube is coupled to the reference voltage. The gear control signal adjusts the resistance gear of the first variable resistor to adjust the gear of the tail current of the error amplifier.

10. The stacked chip according to claim 8, wherein: The error amplifier has a tail current circuit, which includes a controllable current mirror. The controllable current mirror is coupled to the corresponding gear control signal and the reference voltage. The controllable current mirror is used to convert the reference voltage into a reference current and output the reference current as the tail current according to a corresponding mirror ratio. The size of the mirror ratio is adjusted by the gear control signal.

11. The stacked chip according to claim 8, wherein: The output power circuit includes a power tube and a second variable resistor connected in series, the control end of the second variable resistor is coupled to the corresponding gear control signal, and the gear control signal adjusts the resistance gear of the second variable resistor to adjust the load capacity of the voltage regulator.

12. The stacked chip according to claim 1, wherein: The controller includes: a decoder coupled to a corresponding master device and configured to parse a first instruction and a second instruction sent by the master device, perform address decoding on an execution address of the first instruction, and then generate the chip select signal corresponding to each of the device dies according to the address decoding result; A mode register group includes f+1 mode registers arranged in a one-to-one correspondence with f+1 device bare cores, each of the mode registers is coupled to the decoder and is used to provide the corresponding a+1 power configuration signals for the coupled device bare core based on the analysis result of the second instruction by the decoder.

13. The stacked chip according to any one of claims 1 to 12, wherein: The stacked chip is a three-dimensional stacked memory chip, each device bare core is a memory bare core, the controller is a memory controller, and multiple memory bare cores and the logic bare cores are hybrid bonded together through silicon vias.

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