Formation method of semiconductor structure
By forming side walls on the side wall surface of the fin layer during the silicon/silicon germanium dual-channel manufacturing process and controlling the material differences of the fin layer, the problems of high consistency and quality control of the fin layer are solved, and the device performance is improved.
Patent Information
- Application Number
- CN202410117712.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-26
- Publication Date
- 2025-08-01
AI Technical Summary
In the manufacturing process of silicon/silicon germanium dual channels, the prior art is difficult to effectively control the high consistency and quality of the fin layer, resulting in the impact of device performance.
Side walls are formed on the side wall surface of the initial fin layer, and a second fin layer with different materials is formed in the openings between the side walls, the size and morphology of the fin layer are controlled by independent process steps, and a siloxane-based polymer is used as the sacrificial layer to ensure growth space and quality.
It improves the process controllability and quality of the fin layer, reduces the load effect of device performance, and improves the overall performance of the device.
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Figure CN120417469A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Art
[0002] In the development of the semiconductor industry, one of the main reasons silicon has been chosen as the standard material for semiconductor devices is the interface quality between silicon oxide and silicon. When considering other channel materials, interface quality control has always been a challenge.
[0003] The dimensions of logic CMOS devices continue to scale down to further improve performance, and the MOSFET is changed from a planar structure to a fin structure, thus improving the short-channel effect and current leakage. However, due to the influence of the fin width on the deterioration of the drive current, further miniaturization of the device has become increasingly difficult.
[0004] Currently, through innovations such as creating strain in the channel, it can help improve the charge carrier mobility and provide a higher drive current, thus continuing to make progress. A promising method of strain engineering is to replace the traditional silicon channel material with mature material silicon germanium in P-type field effect transistors, which may increase the interface trap density (Dit) and have an adverse effect on hole mobility and subthreshold leakage.
[0005] However, there are still some problems in the manufacturing process of silicon / silicon germanium dual channels that need to be further improved. Summary of the Invention
[0006] The technical problem solved by the present invention is to improve the manufacturing process of silicon / silicon germanium dual channels.
[0007] To solve the above technical problem, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including a first region and a second region; forming a plurality of discrete initial fin layers on the substrate; forming a first isolation layer on the substrate, the first isolation layer being located on the sidewall surfaces of the initial fin layers and the top surface of the first isolation layer being lower than the top surface of the initial fin layers; forming a sacrificial structure on the first isolation layer and on the initial fin layers, the sacrificial structure exposing the sidewall surfaces of the initial fin layers on the second region; forming sidewalls on the sidewall surfaces of the initial fin layers on the second region exposed by the sacrificial structure; removing the initial fin layers exposed by the sacrificial structure to form a first opening between the sidewalls; forming a second fin layer in the first opening, the material of the second fin layer being different from the material of the initial fin layer; after forming the second fin layer, removing the sidewalls.
[0008] Optionally, the method for forming the second fin layer in the first opening includes: forming an initial second fin layer in the first opening, the top of the initial second fin layer being higher than the top surface of the sidewall; performing a re-etching on the initial second fin layer to form the second fin layer, the top surface of the second fin layer being flush with the top surface of the sidewall.
[0009] Optionally, the process for forming the initial second fin layer in the first opening includes an epitaxial growth process.
[0010] Optionally, forming a sacrificial structure on the first isolation layer and the initial fin layer includes: forming an initial sacrificial layer on the first isolation layer and the initial fin layer, the initial sacrificial layer being located on the top surface and the sidewall surface of the initial fin layer; forming a patterned first mask structure on the initial sacrificial layer, the patterned first mask structure exposing the surface of the initial sacrificial layer on the second region; using the first mask structure as a mask to remove the initial sacrificial layer on the second region until the sidewall surface of the initial fin layer on the second region is exposed, and forming a first sacrificial layer on the first isolation layer and the initial fin layer, the sacrificial structure including the first sacrificial layer and the first mask structure located on the first sacrificial layer.
[0011] Optionally, the material of the initial sacrificial layer includes a siloxane-based polymer; the siloxane-based polymer includes a deep ultraviolet oxide.
[0012] Optionally, the first mask structure includes: a first buffer layer, a first anti-reflection layer located on the first buffer layer, and a first photoresist layer located on the first anti-reflection layer.
[0013] Optionally, during the process of forming the second fin layer in the first opening, it further includes: removing the first sacrificial layer.
[0014] Optionally, before forming a sidewall on the sidewall surface of the initial fin layer in the second region where the sacrificial structure is exposed, it further includes: removing the first mask structure.
[0015] Optionally, the process for removing the first sacrificial layer includes a wet etching process.
[0016] ] Optionally, before forming a sidewall on the sidewall surface of the initial fin layer in the second region where the sacrificial structure is exposed, it further includes: etching the initial fin layer in the exposed second region along a direction perpendicular to the sidewall surface of the initial fin layer to form a transition fin layer, the width of the transition fin layer being smaller than the width of the initial fin layer.
[0017] Optionally, the process for etching the initial fin layer in the second region along a direction perpendicular to the sidewall surface of the initial fin layer includes: an isotropic dry etching process or a wet etching process.
[0018] Optionally, the material of the second fin layer comprises silicon germanium; the material of the initial fin layer comprises silicon.
[0019] Optionally, further comprising: etching the initial fin layer on the first region along a direction perpendicular to the sidewall surface of the initial fin layer to form a first fin layer on the first region, and the width of the first fin layer located on the first isolation layer is smaller than the width of the initial fin layer.
[0020] Optionally, the method for forming the substrate and the initial fin layer comprises: providing an initial substrate; forming an initial protective layer on the initial substrate; forming a second mask structure on the initial protective layer, and the second mask structure exposes a part of the initial substrate surface; etching the initial protective layer and the initial substrate using the second mask structure as a mask to form a substrate, a plurality of discrete initial fin layers located on the substrate, a protective layer located on the initial fin layer, and a second mask structure located on the protective layer; the sacrificial structure is further located on the sidewall surface and the top surface of the second mask structure.
[0021] Optionally, the second mask structure comprises: a hard mask layer and a second photoresist layer located on the hard mask layer.
[0022] Optionally, further comprising: removing the second mask structure and the protective layer; the method for removing the sidewall, the second mask structure and the protective layer comprises: forming an initial second sacrificial layer on the first isolation layer, and the top surface of the initial second sacrificial layer is higher than the top surface of the second mask structure; planarizing the initial second sacrificial layer until the surface of the protective layer is exposed to form a second sacrificial layer; removing the protective layer exposed by the second sacrificial layer; removing the second sacrificial layer to expose the sidewall sidewall surface; removing the sidewall.
[0023] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:
[0024] In the forming method of the present invention, a sidewall is formed on the sidewall surface of the initial fin layer in the second region, and then the initial fin layer is removed, and a second fin layer is formed in the first opening between the sidewalls, and the material of the second fin layer is different from the material of the initial fin layer. On the one hand, the second fin layer in the second region is formed in a separate process step, and the size and morphology of the second fin layer can be better controlled; on the other hand, a sidewall is formed on the sidewall surface of the initial fin layer in the second region, and the first opening between the sidewalls provides a growth space for the second fin layer, so that the formed second fin layer has better quality.
[0025] Further, the material of the initial sacrificial layer includes a siloxane-based polymer, the siloxane-based polymer includes a deep ultraviolet oxide, the siloxane-based polymer has good void filling properties and natural flatness, and has good stability and is not easily volatilized during the process of epitaxial growth to form the second fin layer, thereby avoiding the situation of contaminating the chamber.
[0026] Further, the widths of the first fin layer and the second fin layer can be controlled in different steps, and the height of the second fin layer can also be controlled in a separate process step, improving the process controllability of the formed first fin layer and second fin layer. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figure 1 and Figure 2 are schematic diagrams of the formation process of a semiconductor structure in an embodiment;
[0028] Figure 3 and Figure 4 are schematic diagrams of the formation process of a semiconductor structure in another embodiment; [[ID=E18]]
[0029] Figures 5 to 18 are schematic diagrams of the formation process of a semiconductor structure in an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0030] As described in the background art, there are still some problems in the manufacturing process of the silicon / silicon germanium dual-channel, which need to be further improved. The following is an analysis and description in combination with specific embodiments.
[0031] Figure 1 and Figure 2 are schematic diagrams of the formation process of a semiconductor structure in an embodiment.
[0032] Please refer to Figure 1 , provide an initial substrate 100, the initial substrate 100 includes a first region I and a second region II; remove a part of the initial substrate 100 in the second region II to form a groove (not shown) in the initial substrate 100; form an epitaxial layer 101 in the groove, and the material of the epitaxial layer 101 is different from that of the initial substrate 100.
[0033] Please refer to Figure 2, a patterned mask structure (not shown) is formed on the surface of the initial substrate 100 and the surface of the epitaxial layer 101. The patterned mask structure exposes a part of the surface of the initial substrate 100 in the first region I and exposes a part of the surface of the epitaxial layer 101 in the second region II; the initial substrate 100 and the epitaxial layer 101 are etched using the patterned mask structure as a mask, a first fin 102 is formed in the first region I, and a second fin 103 is formed in the second region II. The second fin 103 includes a first part and a second part located on the first part, and the material of the second part is different from the material of the first part.
[0034] During the formation process of the semiconductor structure, the epitaxial layer 101 is first formed, and then the initial substrate 100 and the epitaxial layer 101 are etched to form the first fin 102 and the second fin 103. The second fin 103 is used as the channel layer of the P-type device subsequently. The first fin 102 and the first part are obtained by etching the initial substrate 100, the materials of the first fin 102 and the first part include silicon, the second part is obtained by etching the epitaxial layer 101, and the material of the second part includes silicon germanium.
[0035] When etching the initial substrate 100 and the epitaxial layer 101 using the patterned mask structure as a mask, the initial substrate 100 and the epitaxial layer 101 are etched synchronously by a dry etching process. Since the materials of the initial substrate 100 and the epitaxial layer 101 are different, when etching using a single etching process, there are differences in the etching rates of the initial substrate 100 and the epitaxial layer 101, which makes it difficult to control the heights of the first fin 102 and the second fin 103 to the same level. In the case of smaller and smaller device sizes, the height difference between the first fin 102 and the second fin 103 will produce a loading effect and affect the performance of the device.
[0036] Figure 3 and Figure 4 is a schematic diagram of the formation process of a semiconductor structure in another embodiment.
[0037] Please refer to Figure 3 , a substrate 200 and a plurality of discrete fin layers 201 located on the substrate 200 are provided. The substrate 200 includes a first region I and a second region II; an isolation layer 202 is formed on the substrate 200, and the top surface of the fin layer 201 is exposed on the surface of the isolation layer 202; a part of the fin layer 201 on the second region II is removed, and a groove 203 is formed in the isolation layer 201 on the second region II, and the depth of the groove 203 is less than the depth of the fin layer 201.
[0038] Please refer to Figure 4 , an epitaxial layer 204 is formed in the groove 203, and the material of the epitaxial layer 204 is different from the material of the fin layer 201.
[0039] During the formation process of the semiconductor structure, discrete fin layers 201 are first formed in the first region I and the second region II, then a part of the fin layer 201 on the second region II is removed to form a groove 203, and then an epitaxial layer 204 is formed in the groove 203. The material of the fin layer 201 includes silicon, and the material of the epitaxial layer 204 includes silicon germanium. The epitaxial layer 204 is used as the channel layer of the P-type device subsequently.
[0040] The process of forming a silicon germanium epitaxial layer 204 in the groove 203 includes an epitaxial process. The aspect ratio of the groove 203 is relatively large. When growing silicon germanium epitaxially in the groove 203, the silicon germanium grows on the surface of the fin layer 201 at the bottom of the groove 203. The surface area of the fin layer 201 is small, and the side wall of the groove 203 is an isolation layer 202. The epitaxial growth region is restricted. Therefore, defects are likely to occur during the epitaxial growth to form the epitaxial layer 204, and there is also a risk of lattice misalignment with the isolation layer 202, resulting in poor quality of the formed epitaxial layer 204.
[0041] To solve the above problems, the technical solution of the present invention provides a method for forming a semiconductor structure. A sidewall is formed on the sidewall surface of the initial fin layer on the second region, and then the initial fin layer is removed. A second fin layer is formed in the first opening between the sidewalls, and the material of the second fin layer is different from that of the initial fin layer. On the one hand, the second fin layer on the second region is formed in a separate process step, which can better control the size and morphology of the second fin layer; on the other hand, a sidewall is formed on the sidewall surface of the initial fin layer on the second region, and the first opening between the sidewalls provides a growth space for the second fin layer, so that the formed second fin layer has better quality.
[0042] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.
[0043] Figures 5 to 18 It is a schematic diagram of the formation process of the semiconductor structure in the embodiment of the present invention.
[0044] Please refer to Figure 5 , a substrate 300 is provided, and the substrate 300 includes a first region I and a second region II; a plurality of discrete initial fin layers 301 are formed on the substrate 300.
[0045] The method for forming the substrate 300 and the initial fin layer 301 includes: providing an initial substrate (not shown); forming an initial protective layer (not shown) on the initial substrate; forming a second mask structure on the initial protective layer, the second mask structure exposing a part of the initial substrate surface; etching the initial protective layer and the initial substrate using the second mask structure as a mask to form the substrate 300, a plurality of discrete initial fin layers 301 on the substrate 300, a protective layer 303 on the initial fin layer 301, and a second mask structure on the protective layer 303.
[0046] The second mask structure includes: a hard mask layer 304 and a second photoresist layer (not shown) on the hard mask layer 304. The second photoresist layer is naturally consumed during the process of etching the initial protective layer and the initial substrate.
[0047] The process of etching the initial protective layer and the initial substrate includes a dry etching process.
[0048] The material of the protective layer 303 includes a dielectric material, and the dielectric material includes one or a combination of more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon carbon oxynitride.
[0049] The material of the hard mask layer 304 includes a dielectric material, and the dielectric material includes one or a combination of more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon carbon oxynitride.
[0050] The material of the protective layer 303 is different from the material of the hard mask layer 304.
[0051] In this embodiment, the material of the protective layer 303 includes silicon nitride; the material of the hard mask layer 304 includes silicon oxide.
[0052] In this embodiment, the material of the initial substrate is silicon.
[0053] In other embodiments, the material of the initial substrate includes silicon carbide, silicon germanium, a multi-component semiconductor material composed of group III-V elements, silicon on insulator (SOI), or germanium on insulator (GOI). Among them, the multi-component semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.
[0054] Please continue to refer to Figure 5 , and form a first isolation layer 305 on the substrate 300, the first isolation layer 305 being located on the sidewall surface of the initial fin layer 301 and the top surface of the first isolation layer 305 being lower than the top surface of the initial fin layer 301.
[0055] The method for forming the first isolation layer 305 includes: forming an initial isolation layer (not shown) on the substrate 300, where the top surface of the initial isolation layer is higher than the top surface of the initial fin layer 301; performing etch-back on the initial isolation layer to form the first isolation layer 305.
[0056] By etching back the height of the initial isolation layer, the height of the subsequently formed second isolation layer can be controlled, as well as the height of the subsequently formed second fin layer and the height of the gate structure.
[0057] The material of the first isolation layer 305 includes a dielectric material, and the dielectric material includes one or a combination of multiple of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon carbon oxynitride.
[0058] In this embodiment, the material of the first isolation layer 305 includes silicon oxide.
[0059] Next, a sacrificial structure is formed on the first isolation layer 305 and the initial fin layer 301. The sacrificial structure exposes the sidewall surface of the initial fin layer 301 in the second region II, and the sacrificial structure is also located on the sidewall surface and the top surface of the second mask structure. For the process of forming the sacrificial structure, please refer to Figure 6 and Figure 7 .
[0060] Please refer to Figure 6 , an initial sacrificial layer 306 is formed on the first isolation layer 305 and the initial fin layer 301. The initial sacrificial layer 306 is located on the top surface and the sidewall surface of the initial fin layer 301; a patterned first mask structure 307 is formed on the initial sacrificial layer 306, and the patterned first mask structure 307 exposes the surface of the initial sacrificial layer 306 in the second region II.
[0061] The first mask structure 307 includes: a first cushion layer (not shown), a first anti-reflection layer (not shown) located on the first cushion layer, and a first photoresist layer (not shown) located on the first anti-reflection layer.
[0062] The material of the first cushion layer includes an amorphous material, and the amorphous material includes amorphous silicon or amorphous carbon; the first anti-reflection layer includes a thin silicon anti-reflection layer (Si-ARC), an organic bottom anti-reflection layer (organicBARC), a dielectric anti-reflection layer (DARC), or a combination of an organic bottom anti-reflection layer and a dielectric anti-reflection layer.
[0063] In this embodiment, the material of the first cushion layer includes amorphous carbon; the first anti-reflection layer includes a thin silicon anti-reflection layer (Si-ARC).
[0064] The material of the initial sacrificial layer 306 includes a siloxane-based polymer, and the siloxane-based polymer includes Deep Ultraviolet Oxide (DUO).
[0065] The siloxane-based polymer can be baked into a solid after a soft coating, has the same properties as the Si-O-based dielectric, and has good void filling and natural flatness.
[0066] The forming method of the initial sacrificial layer 306 includes: forming a sacrificial material layer on the first isolation layer 305 and the initial fin layer 301; planarizing the sacrificial material layer and baking the sacrificial material layer to form the initial sacrificial layer 306.
[0067] Please refer to Figure 7 , using the first mask structure 307 as a mask to remove the initial sacrificial layer 306 on the second region II until the sidewall surface of the initial fin layer 301 on the second region II is exposed, forming a first sacrificial layer 302 on the first isolation layer 305 and the initial fin layer 301, and forming a second opening 308 in the first sacrificial layer 302, and the second opening 308 exposes the sidewall surface of the initial fin layer 301 on the second region II.
[0068] The sacrificial structure includes a first sacrificial layer 302 and a first mask structure 307 located on the first sacrificial layer 302.
[0069] The process of removing the initial sacrificial layer 306 on the second region II includes a dry etching process. The parameters of the dry etching process include: the gas includes carbon tetrafluoride, oxygen, argon, and helium.
[0070] In this embodiment, when removing the initial sacrificial layer 306 on the second region II, the first photoresist layer and the first anti-reflection layer of the first mask structure 307 are naturally consumed.
[0071] Please refer to Figure 8 , etching the initial fin layer 301 on the second region II exposed by the second opening 308 along a direction perpendicular to the sidewall surface of the initial fin layer 301 to form a transition fin layer 320, and the width of the transition fin layer 320 is smaller than the width of the initial fin layer 301.
[0072] The degree of etching the initial fin layer 301 along a direction perpendicular to the sidewall surface of the initial fin layer 301 determines the width of the subsequent formed second fin, and the width of the subsequent formed second fin is controlled by controlling the depth of etching the initial fin layer 301 along a direction perpendicular to the sidewall surface of the initial fin layer 301.
[0073] The process of etching the initial fin layer 301 in a direction perpendicular to the sidewall surface of the initial fin layer 301 includes: an isotropic dry etching process or a wet etching process.
[0074] Etching the initial fin layer 301 in a direction perpendicular to the sidewall surface of the initial fin layer 301 can also be called cavity etching.
[0075] In other embodiments, the initial fin layer on the second region exposed by the first opening may not be etched in a direction perpendicular to the sidewall surface of the initial fin layer.
[0076] Please continue to refer to Figure 8 , and remove the first mask structure 307.
[0077] Since the first photoresist layer and the first anti-reflection layer of the first mask structure 307 are naturally consumed when removing the initial sacrificial layer 306 on the second region II, removing the first mask structure 307 at this time includes removing the first liner layer.
[0078] The material of the first liner layer includes amorphous carbon, and the process of removing the first liner layer includes an ashing process. The remaining part of the first anti-reflection layer is also naturally removed in the ashing process.
[0079] Next, a sidewall is formed on the sidewall surface of the transition fin layer 320 on the second region II exposed by the second opening 308. For the process of forming the sidewall, please refer to Figure 9 and Figure 10 .
[0080] In other embodiments, a sidewall is formed on the sidewall surface of the initial fin layer on the second region where the sacrificial structure is exposed.
[0081] Please refer to Figure 9 , and a sidewall material layer 309 is formed on the sidewall surface of the transition fin layer 320 exposed by the second opening 308, on the surface of the first isolation layer 305 at the bottom of the second opening 308, on the sidewall surface and the top surface of the protective layer 303, on the sidewall surface and the top surface of the hard mask layer 304, and on the top surface of the first sacrificial layer 302.
[0082] The material of the sidewall material layer 309 includes a dielectric material, and the dielectric material includes one or a combination of more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon carbon oxynitride.
[0083] In this embodiment, the material of the sidewall material layer 309 includes silicon nitride.
[0084] Please refer to Figure 10, remove the sidewall material layer 309 on the surface of the first isolation layer 305 at the bottom of the second opening 308, the sidewall surface of the protective layer 303, the sidewall surface and the top surface of the hard mask layer 304, and the top surface of the first sacrificial layer 302, and form a sidewall 311 on the sidewall surface of the transition fin portion layer 320.
[0085] The process of removing the sidewall material layer 309 includes: a dry etching process.
[0086] The method of removing the sidewall material layer 309 includes: using a first etching process to remove the sidewall material layer 309 on the top surface of the first sacrificial layer 302 and the top surface of the hard mask layer 304; then using a second etching process to remove the hard mask layer 304, and in the process of removing the hard mask layer 304, part of the sidewall material layer 309 on the sidewall of the first sacrificial layer 302 will also be removed; then using a third etching process to remove the sidewall material layer 309 on the surface of the protective layer 303, the sidewalls of the first sacrificial layer 302 and the first isolation layer 305 until the top surface of the transition fin portion layer 320 is exposed, and form the sidewall �11 on the sidewall surface of the transition fin portion layer 320.
[0087] The first etching process includes a dry etching process, and the etching gas of the dry etching process includes oxygen, fluoromethane and helium.
[0088] The second etching process includes a dry etching process, and the etching gas of the dry etching process includes carbon tetrafluoride and nitrogen.
[0089] The third etching process includes a dry etching process, and the etching gas of the dry etching process includes oxygen, fluoromethane and helium.
[0090] Please continue to refer to Figure 10 , remove the exposed transition fin portion layer 320 of the first sacrificial layer 302, and form a first opening 310 between the sidewalls 311.
[0091] The process of removing the transition fin portion layer 320 includes: a dry etching process, and the etching gas of the dry etching process includes hydrogen, methane, nitrogen trifluoride, argon and helium. The etching rate of the dry etching process for the transition fin portion layer 320 is greater than the etching rate for the sidewall 311, so that during the process of removing the transition fin portion layer 320, the damage to the sidewall 311 is smaller.
[0092] In other embodiments, remove the exposed initial fin portion layer of the first sacrificial layer, and form a first opening between the sidewalls.
[0093] Next, form a second fin portion layer in the first opening 310. For the formation process of the second fin portion layer, please refer to Figures 11 to 13 .
[0094] Please refer to Figure 11 , an initial second fin layer 312 is formed within the first opening 310, and the top of the initial second fin layer 312 is higher than the top surface of the sidewall 311.
[0095] The material of the initial second fin layer 312 is different from that of the initial fin layer 301.
[0096] In this embodiment, the material of the initial second fin layer 312 includes silicon germanium; the material of the initial fin layer 301 includes silicon.
[0097] The process of forming the initial second fin layer 312 within the first opening 310 includes an epitaxial growth process, and the parameters of the epitaxial growth process include: the gas includes germane (GeH4) and dichlorosilane (SiH2Cl2), and the reaction temperature is 600°C to 700°C.
[0098] The material of the first sacrificial layer 302 includes a silicon-based oxide, and the silicon-based oxide has good stability and is not easily volatilized during the process of epitaxially growing the initial second fin layer 312, thereby avoiding the situation of contaminating the chamber.
[0099] Please refer to Figure 12 , and the first sacrificial layer 302 is removed.
[0100] The process of removing the first sacrificial layer 302 includes the Certas process. The process parameters of the Certas process include: the etching gas includes hydrogen fluoride and ammonia.
[0101] In this embodiment, when the first sacrificial layer 302 is removed, the hard mask layer 304 is also removed.
[0102] Please refer to Figure 13 , the initial second fin layer 312 is etched back to form the second fin layer 313, and the top surface of the second fin layer 313 is flush with the top surface of the sidewall 311.
[0103] The height of the sidewall 311 determines the height of the second fin layer 313, and the height of the second fin layer 313 is controlled by controlling the height of the sidewall 311.
[0104] Next, after forming the second fin layer, the sidewall 311 and the protective layer 303 are removed. Please refer to the process of removing the sidewall 311 and the protective layer 303 Figures 14 to 17 .
[0105] Please refer to Figure 14, an initial second sacrificial layer 314 is formed on the first isolation layer 305, and the top surface of the initial second sacrificial layer 314 is higher than the top surface of the protective layer 303.
[0106] In this embodiment, the material of the initial second sacrificial layer 314 includes silicon oxide.
[0107] Please refer to Figure 15 , the initial second sacrificial layer 314 is planarized until the surface of the protective layer 303 is exposed, forming a second sacrificial layer 315.
[0108] Please refer to Figure 16 , the protective layer 303 exposed by the removal of the second sacrificial layer 315 is removed.
[0109] In this embodiment, the process of removing the protective layer 303 includes a dry etching process or a wet etching process.
[0110] The material of the protective layer 303 is different from that of the second sacrificial layer 315, and the process of removing the protective layer 303 has a large etching selectivity for the protective layer 303 and the second sacrificial layer 315.
[0111] Please refer to Figure 17 , the second sacrificial layer 315 is removed to expose the sidewall surface of the sidewall 311; the sidewall 311 is removed.
[0112] The process of removing the second sacrificial layer 315 includes a Certas process; the process of removing the sidewall 311 includes a dry etching process or a wet etching process.
[0113] Please refer to Figure 18 , the initial fin layer 301 in the first region I is etched along a direction perpendicular to the sidewall surface of the initial fin layer 301, and a first fin layer 316 is formed in the first region I, and the width of the first fin layer 316 located on the first isolation layer 305 is smaller than the width of the initial fin layer 301.
[0114] The initial fin layer 301 in the first region I is etched along a direction perpendicular to the sidewall surface of the initial fin layer 301, and a first fin layer 316 is formed in the first region I, which can accurately control the width of the first fin layer 316.
[0115] The first fin layer 316 and the second fin layer 313 located on the first isolation layer 305 are used as the channel layers of the gate structure formed subsequently on the first isolation layer 305.
[0116] In other embodiments, the initial fin layer in the first region may not be etched along a direction perpendicular to the sidewall surface of the initial fin layer.
[0117] In this embodiment, it further includes: forming a first gate structure and a second gate structure on the first isolation layer 305, where the first gate structure straddles the first fin layer 316, and the second gate structure straddles the second fin layer 313.
[0118] In the forming method, a spacer 311 is formed on the sidewall surface of the initial fin layer 301 in the second region II, and then the initial fin layer 301 is removed. A second fin layer 313 is formed in the first opening 310 between the spacers 311, and the material of the second fin layer 313 is different from that of the initial fin layer 301. On the one hand, the second fin layer 313 in the second region II is formed in a separate process step, which can better control the size and morphology of the second fin layer 313. On the other hand, a spacer 311 is formed on the sidewall surface of the initial fin layer 301 in the second region II, and the first opening 310 between the spacers 311 provides a growth space for the second fin layer 313, so that the formed second fin layer 313 has good quality.
[0119] In addition, the widths of the first fin layer 316 and the second fin layer 313 can be controlled in different steps, and the height of the second fin layer 313 can also be controlled in a separate process step, improving the process controllability of the formed first fin layer 316 and second fin layer 313.
[0120] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate, the substrate including a first region and a second region; Forming a plurality of discrete initial fin layers on the substrate; Forming a first isolation layer on the substrate, the first isolation layer being located on the sidewall surfaces of the initial fin layers and the top surface of the first isolation layer being lower than the top surface of the initial fin layers; Forming a sacrificial structure on the first isolation layer and on the initial fin layers, the sacrificial structure exposing the sidewall surfaces of the initial fin layers on the second region; Forming sidewalls on the sidewall surfaces of the initial fin layers on the second region exposed by the sacrificial structure; Removing the initial fin layers exposed by the sacrificial structure to form a first opening between the sidewalls; forming a second fin layer in the first opening, the material of the second fin layer being different from the material of the initial fin layer; After forming the second fin layer, removing the sidewalls.
2. The method for forming a semiconductor structure according to claim 1, wherein, The method of forming a second fin layer in the first opening includes: forming an initial second fin layer in the first opening, the top of the initial second fin layer being higher than the top surface of the sidewalls; back-etching the initial second fin layer to form the second fin layer, the top surface of the second fin layer being flush with the top surface of the sidewalls.
3. The method for forming a semiconductor structure according to claim 2, wherein, The process of forming an initial second fin layer in the first opening includes an epitaxial growth process.
4. The method for forming a semiconductor structure as claimed in claim 1, wherein Forming a sacrificial structure on the first isolation layer and on the initial fin layers includes: forming an initial sacrificial layer on the first isolation layer and on the initial fin layers, the initial sacrificial layer being located on the top surface and the sidewall surfaces of the initial fin layers; forming a patterned first mask structure on the initial sacrificial layer, the patterned first mask structure exposing the surface of the initial sacrificial layer on the second region; using the first mask structure as a mask to remove the initial sacrificial layer on the second region until the sidewall surfaces of the initial fin layers on the second region are exposed, and forming a first sacrificial layer on the first isolation layer and on the initial fin layers, the sacrificial structure including the first sacrificial layer and the first mask structure located on the first sacrificial layer.
5. The method for forming a semiconductor structure according to claim 4, wherein, The material of the initial sacrificial layer includes a siloxane-based polymer; the siloxane-based polymer includes a deep ultraviolet oxide.
6. The method for forming a semiconductor structure according to claim 4, wherein, The first mask structure includes: a first cushion layer, a first anti-reflection layer located on the first cushion layer, and a first photoresist layer located on the first anti-reflection layer.
7. The method for forming a semiconductor structure according to claim 4, wherein, During the process of forming a second fin layer in the first opening, it further includes: removing the first sacrificial layer.
8. The method for forming a semiconductor structure according to claim 4, wherein Before forming sidewalls on the sidewall surfaces of the initial fin layers on the second region exposed by the sacrificial structure, it further includes: removing the first mask structure.
9. The method for forming a semiconductor structure according to claim 8, wherein, The process of removing the first sacrificial layer includes a Certas process.
10. The method for forming a semiconductor structure according to claim 1, characterized in that, Before forming sidewalls on the sidewall surfaces of the initial fin layers on the second region exposed by the sacrificial structure, it further includes: etching the initial fin layers on the exposed second region in a direction perpendicular to the sidewall surfaces of the initial fin layers to form a transition fin layer, the width of the transition fin layer being smaller than the width of the initial fin layer.
11. The method for forming a semiconductor structure according to claim 10, wherein, The process of etching the initial fin layers on the second region in a direction perpendicular to the sidewall surfaces of the initial fin layers includes: an isotropic dry etching process or a wet etching process.
12. The method for forming a semiconductor structure according to claim 1, wherein The material of the second fin layer includes silicon germanium; the material of the initial fin layer includes silicon.
13. The method for forming a semiconductor structure according to claim 1, wherein, Further included is: Etch the initial fin layer on the first region along a direction perpendicular to the sidewall surface of the initial fin layer to form a first fin layer on the first region, and the width of the first fin layer located on the first isolation layer is smaller than the width of the initial fin layer.
14. The method for forming a semiconductor structure according to claim 1, wherein, The method for forming the substrate and the initial fin layer includes: providing an initial substrate; forming an initial protective layer on the initial substrate; forming a second mask structure on the initial protective layer, and the second mask structure exposes a part of the initial substrate surface; using the second mask structure as a mask to etch the initial protective layer and the initial substrate to form a substrate, a plurality of discrete initial fin layers located on the substrate, a protective layer located on the initial fin layer, and a second mask structure located on the protective layer; the sacrificial structure is further located on the sidewall surface and the top surface of the second mask structure.
15. The method for forming a semiconductor structure according to claim 14, wherein, The second mask structure includes: a hard mask layer and a second photoresist layer located on the hard mask layer.
16. The method for forming a semiconductor structure as described in claim 15, wherein, Further included is: Remove the second mask structure and the protective layer; The method for removing the sidewall, the second mask structure and the protective layer includes: forming an initial second sacrificial layer on the first isolation layer, and the top surface of the initial second sacrificial layer is higher than the top surface of the second mask structure; planarize the initial second sacrificial layer until the surface of the protective layer is exposed to form a second sacrificial layer; remove the protective layer exposed by the second sacrificial layer; remove the second sacrificial layer to expose the sidewall sidewall surface; remove the sidewall.