Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the semiconductor structure comprises a substrate which comprises a P-type device region and an N-type device region, the N-type device region comprises a first threshold voltage region, a second threshold voltage region and a third threshold voltage region, and the P-type device region comprises a fourth threshold voltage region, a fifth threshold voltage region and a sixth threshold voltage region; a first gate structure located in the first threshold voltage region; a second gate structure located in a second threshold voltage region; the third gate structure is located in a third threshold voltage region; the contents of N-type polarized particles in the first gate dielectric layer, the second gate dielectric layer and the third gate dielectric layer are different; a fourth gate structure located in a fourth threshold voltage region; a fifth gate structure located in a fifth threshold voltage region; and the contents of P-type polarized particles contained in the fourth gate dielectric layer, the fifth gate dielectric layer and the sixth gate dielectric layer in the sixth threshold voltage region are different, so that the performance of the formed multi-threshold voltage fin field effect transistor is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technologies, and particularly to a semiconductor structure and a method for forming the same. Background Art

[0002] The MOS (Metal-Oxide-Semiconductor) transistor is one of the most important components in modern integrated circuits. The basic structure of the MOS transistor includes: a semiconductor substrate; a gate structure located on the surface of the semiconductor substrate, and the gate structure includes: a gate dielectric layer located on the surface of the semiconductor substrate and a gate electrode layer located on the surface of the gate dielectric layer; source / drain doping regions in the semiconductor substrate on both sides of the gate structure. MOS includes PMOS transistors and NMOS transistors.

[0003] In order to meet the requirements of different switching speeds of transistors in integrated circuit design, it is necessary to form multiple transistors with different threshold voltages. In order to reduce the threshold voltages of PMOS transistors and NMOS transistors, corresponding work function layers are formed on the surfaces of the gate dielectric layers of PMOS transistors and NMOS transistors. Among them, the work function layer of the PMOS transistor needs to have a higher work function, while the work function layer of the NMOS transistor needs to have a lower work function. In PMOS transistors and NMOS transistors, the materials of the work function layers are different to meet the requirements of their respective work function adjustments.

[0004] Moreover, PMOS transistors may also require multiple different threshold voltages. The common practice in the industry now is to adjust the thickness of the work function of PMOS transistors. For example, the thickness of the work function layer of a PMOS transistor with a low threshold voltage is thicker than that of a PMOS transistor with a standard threshold voltage.

[0005] However, in the prior art, the use of Dipole, and the method of still using the buffer thickness or its own thickness to adjust the amount of Dipole in the prior art. When adjusting the metal work function under FinFET technology, due to the fact that the fin pitch is getting smaller and the distance between fins is also getting smaller in some cases, the work function adjustment ability of the work function layer is limited by the fin pitch. Summary of the Invention

[0006] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed multi-threshold voltage fin field effect transistor.

[0007] In order to solve the above problems, the present invention provides a semiconductor structure, comprising: providing a substrate, the substrate comprising a P-type device region and an N-type device region, the N-type device region comprising a first threshold voltage region, a second threshold voltage region and a third threshold voltage region, and the P-type device region comprising a fourth threshold voltage region, a fifth threshold voltage region and a sixth threshold voltage region; a first gate structure located on the substrate in the first threshold voltage region, the first gate structure comprising a first gate dielectric layer, the first gate layer located on the surface of the first gate dielectric layer; a second gate structure located on the substrate in the second threshold voltage region, the second gate structure comprising a second gate dielectric layer, the second gate layer located on the surface of the second gate dielectric layer; a third gate structure located on the substrate in the third threshold voltage region, the third gate structure comprising a third gate dielectric layer , the third gate layer located on the surface of the third gate dielectric layer, the first gate dielectric layer, the second gate dielectric layer and the third gate dielectric layer have different contents of N-type polarized particles; the fourth gate structure located on the substrate in the fourth threshold voltage region, the fourth gate structure includes a fourth gate dielectric layer, and the fourth gate layer is located on the surface of the fourth gate dielectric layer; the fifth gate structure located on the substrate in the fifth threshold voltage region, the fifth gate structure includes a fifth gate dielectric layer, and the fifth gate layer is located on the surface of the fifth gate dielectric layer; the sixth gate structure located on the substrate in the sixth threshold voltage region, the sixth gate structure includes a sixth gate dielectric layer, and the sixth gate layer is located on the surface of the sixth gate dielectric layer, and the fourth gate dielectric layer, the fifth gate dielectric layer and the sixth gate dielectric layer have different contents of P-type polarized particles.

[0008] Optionally, the N-type polarized particles include lanthanum.

[0009] Optionally, the P-type polarized particles include aluminum.

[0010] Optionally, the concentration range of the N-type polarized particles in the first gate dielectric layer is 1*10 11 cm -2 ~1*10 16 cm -2 The concentration range of N-type polarized particles in the second gate dielectric layer is 1*10 11 cm -2 ~1*10 16 cm -2 , and the concentration range of N-type polarized particles in the third gate dielectric layer is 1*10 11 cm -2 ~1*10 16 cm -2 .

[0011] Optionally, the concentration range of the P-type polarized particles in the third gate dielectric layer is 1*10 11 cm -2 ~1*10 16 cm -2, the concentration range of P-type polarization particles in the fourth gate dielectric layer is 1×10 11 cm -2 ~1×10 16 cm -2 , and the concentration range of P-type polarization particles in the sixth gate dielectric layer is 1×10 11 cm -2 ~1×10 16 cm -2 .

[0012] Optionally, the materials of the first gate dielectric layer, the second gate dielectric layer, the third gate dielectric layer, the fourth gate dielectric layer, the fifth gate dielectric layer, and the sixth gate dielectric layer include high-K dielectric materials, and the high-K dielectric materials include: lanthanum oxide, cerium oxide, or hafnium oxide.

[0013] Optionally, the substrate includes: a substrate; fins located on the surface of the substrate, and the first gate structure, the second gate structure, the third gate structure, the fourth gate structure, the fifth gate structure, and the sixth gate structure straddle the fins.

[0014] Optionally, it further includes: a first source / drain doping layer in the fins on both sides of the first gate structure, a second source / drain doping layer in the fins on both sides of the second gate structure, a third source / drain doping layer in the fins on both sides of the third gate structure, a fourth source / drain doping layer in the fins on both sides of the fourth gate structure, a fifth source / drain doping layer in the fins on both sides of the fifth gate structure, and a sixth source / drain doping layer in the fins on both sides of the sixth gate structure.

[0015] Correspondingly, the present invention further provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including a P-type device region and an N-type device region, the N-type device region including a first threshold voltage region, a second threshold voltage region, and a third threshold voltage region, and the P-type device region including a fourth threshold voltage region, a fifth threshold voltage region, and a sixth threshold voltage region; forming an initial gate dielectric layer on the surfaces of the P-type device region and the N-type device region; forming a first dipole layer on the surface of the initial gate dielectric layer in the third threshold voltage region; forming a second dipole layer on the surface of the first dipole layer and the surface of the initial gate dielectric layer in the second threshold voltage region; forming a third dipole layer on the surfaces of the second dipole layer, the surface of the initial gate dielectric layer in the first threshold voltage region, the surface of the initial gate dielectric layer in the fourth threshold voltage region, the surface of the initial gate dielectric layer in the fifth threshold voltage region, and the surface of the initial gate dielectric layer in the sixth threshold voltage region, with N-type polarized particles in the first dipole layer, the second dipole layer, and the third dipole layer; forming a fourth dipole layer on the surface of the third dipole layer in the sixth threshold voltage region; forming a fifth dipole layer on the surface of the third dipole layer in the fifth threshold voltage region; forming a sixth dipole layer on the surfaces of the third dipole layer in the fourth threshold voltage region, the surface of the fourth dipole layer, and the surface of the fifth dipole layer, with P-type polarized particles in the fourth dipole layer, the fifth dipole layer, and the sixth dipole layer; performing an annealing process to drive the N-type polarized particles in the first dipole layer, the second dipole layer, and the third dipole layer to migrate into the initial gate dielectric layer, and drive the P-type polarized particles in the fourth dipole layer, the fifth dipole layer, and the sixth dipole layer to migrate into the initial gate dielectric layer, forming a first gate dielectric layer on the first threshold voltage region, a second gate dielectric layer on the second threshold voltage region, a third gate dielectric layer on the third threshold voltage region, a fourth gate dielectric layer on the fourth threshold voltage region, a fifth gate dielectric layer on the fifth threshold voltage region, and a sixth gate dielectric layer on the sixth threshold voltage region, with different contents of N-type polarized particles in the first gate dielectric layer, the second gate dielectric layer, and the third gate dielectric layer, and different contents of P-type polarized particles in the fourth gate dielectric layer, the fifth gate dielectric layer, and the sixth gate dielectric layer; after the annealing process, removing the first dipole layer, the second dipole layer, the third dipole layer, the fourth dipole layer, the fifth dipole layer, and the sixth dipole layer; after removing the first dipole layer, the second dipole layer, the third dipole layer, the fourth dipole layer, the fifth dipole layer, and the sixth dipole layer, forming a first gate electrode layer on the surface of the first gate dielectric layer, a second gate electrode layer on the surface of the second gate dielectric layer, a third gate electrode layer on the surface of the third gate dielectric layer, a fourth gate electrode layer on the surface of the fourth gate dielectric layer, a fifth gate electrode layer on the surface of the fifth gate dielectric layer, and a sixth gate electrode layer on the surface of the sixth gate dielectric layer.

[0016] Optionally, the process parameters of the annealing process include an annealing temperature range of 400°C to 1000°C and an annealing time of 0.001 s to 600 s.

[0017] Optionally, the material of the first dipole layer includes lanthanum oxide, the material of the second dipole layer includes lanthanum oxide, and the material of the third dipole layer includes lanthanum oxide.

[0018] Optionally, the material of the fourth dipole layer includes aluminum oxide, the material of the fifth dipole layer includes aluminum oxide, and the material of the sixth dipole layer includes aluminum oxide.

[0019] Optionally, the material of the initial gate dielectric layer includes a high-K dielectric material, and the high-K dielectric material includes: lanthanum oxide, cerium oxide, or hafnium oxide.

[0020] Optionally, the method for forming the first dipole layer and the second dipole layer includes: forming an initial first dipole layer on the surface of the initial gate dielectric layer; removing the initial first dipole layer in the second threshold voltage region by using a first patterning to expose the surface of the initial gate dielectric layer in the second threshold voltage region, thereby forming a first intermediate dipole layer; forming an initial second dipole layer on the surface of the first intermediate dipole layer and the surface of the initial gate dielectric layer in the second threshold voltage region; removing the initial second dipole layer and the first intermediate dipole layer in the first threshold voltage region, the fourth threshold voltage region, the fifth threshold voltage region, and the sixth threshold voltage region by using a second patterning until the surface of the initial gate dielectric layer in the first threshold voltage region, the fourth threshold voltage region, the fifth threshold voltage region, and the sixth threshold voltage region is exposed, and forming a first dipole layer on the surface of the initial gate dielectric layer in the third threshold voltage region; forming a second dipole layer on the surface of the first dipole layer and the surface of the second threshold voltage region.

[0021] Optionally, the method for forming the fourth dipole layer, the fifth dipole layer, and the sixth dipole layer includes: forming an initial fourth dipole layer on the surface of the third dipole layer; patterning and removing the initial fourth dipole layer in the fifth threshold voltage region to expose the third dipole layer in the fifth threshold voltage region, thereby forming a fourth intermediate dipole layer; forming an initial fifth dipole layer on the surface of the fourth intermediate dipole layer and the third dipole layer; removing the initial fifth dipole layer and the fourth intermediate dipole layer on the surface of the fourth threshold voltage region until the third dipole layer on the surface of the second threshold voltage region is exposed, thereby forming a fifth intermediate dipole layer; forming an initial sixth dipole layer on the surface of the fifth intermediate dipole layer and the surface of the third dipole layer; patterning and removing the initial sixth dipole layer, the fifth intermediate dipole layer, and the fourth intermediate dipole layer in the third threshold voltage region, the second threshold voltage region, and the first threshold voltage region to form the sixth dipole layer, the fifth dipole layer, and the fourth dipole layer.

[0022] Optionally, the method for forming the substrate includes: providing a substrate; etching a part of the thickness of the substrate to form fins.

[0023] Optionally, before forming the initial gate dielectric layer, the following steps are further included: forming a first dummy gate structure across the fin on the surface of the substrate in the first threshold voltage region, forming a second dummy gate structure across the fin on the surface of the substrate in the second threshold voltage region, forming a third dummy gate structure across the fin on the surface of the substrate in the third threshold voltage region, forming a fourth dummy gate structure across the fin on the surface of the substrate in the fourth threshold voltage region, forming a fifth dummy gate structure across the fin on the surface of the substrate in the fifth threshold voltage region, forming a sixth dummy gate structure across the fin on the surface of the substrate in the sixth threshold voltage region; forming a first source / drain doping layer in the fin on both sides of the first dummy gate structure, forming a second source / drain doping layer in the fin on both sides of the second dummy gate structure, forming a third source / drain doping layer in the fin on both sides of the third dummy gate structure, forming a fourth source / drain doping layer in the fin on both sides of the fourth dummy gate structure, forming a fifth source / drain doping layer in the fin on both sides of the fifth dummy gate structure, forming a sixth source / drain doping layer in the fin on both sides of the sixth dummy gate structure; removing the first dummy gate structure to form a first gate groove, removing the second dummy gate structure to form a second gate groove, removing the third dummy gate structure to form a third gate groove, removing the fourth dummy gate structure to form a fourth gate groove, removing the fifth dummy gate structure to form a fifth gate groove, removing the sixth dummy gate structure to form a sixth gate groove; forming an initial gate dielectric layer at the bottom of the first gate groove, the bottom of the second gate groove, the bottom of the third gate groove, the bottom of the fourth gate groove, the bottom of the fifth gate groove, and the bottom of the sixth gate groove respectively.

[0024] Optionally, the materials of the first gate layer, the second gate layer, the third gate layer, the fourth gate layer, the fifth gate layer, and the sixth gate layer are metal materials

[0025] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0026] In the semiconductor structure of the technical solution of the present invention, the substrate includes a P-type device region and an N-type device region. The N-type device region includes a first threshold voltage region, a second threshold voltage region, and a third threshold voltage region. The P-type device region includes a fourth threshold voltage region, a fifth threshold voltage region, and a sixth threshold voltage region. The first gate structure is located in the first threshold voltage region, the second gate structure is located in the second threshold voltage region, the third gate junction is located in the third threshold voltage region, the fourth gate structure is located in the fourth threshold voltage region, the fifth gate structure is located in the fifth threshold voltage region, and the sixth gate structure is located in the sixth threshold voltage region. The contents of N-type polarization particles in the first gate dielectric layer, the second gate dielectric layer, and the third gate dielectric layer are different, so as to realize the voltage regulation of the first threshold voltage region, the second threshold voltage region, and the third threshold voltage region. The contents of P-type polarization particles in the fourth gate dielectric layer, the fifth gate dielectric layer, and the sixth gate dielectric layer are different, so as to realize the voltage regulation of the fourth threshold voltage region, the fifth threshold voltage region, and the sixth threshold voltage region. On the one hand, the voltage regulation of the six threshold voltage regions is realized. On the other hand, this voltage regulation method does not require an additional thickness of the work function layer to be realized, so it can better adapt to the formation of gate structures with smaller critical dimensions, further increasing the openness of the device and having a wide range of applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figures 1 to 8 FIG. is a schematic diagram of the structures of each step of a semiconductor structure and a method for forming the same according to an embodiment of the present invention. DETAILED DESCRIPTION

[0028] As in the background art, the performance of existing multi-threshold voltage fin field effect transistors.

[0029] Currently, titanium nitride and titanium aluminide are used as the work functions of N-type devices and P-type devices. Titanium nitride can reduce the threshold voltage of P-type devices and increase the threshold voltage of N-type devices. Titanium aluminide can increase the threshold voltage of P-type devices and reduce the threshold voltage of N-type devices. Therefore, the threshold voltages of N-type devices and P-type devices are determined by the thicknesses of titanium nitride and titanium aluminide.

[0030] Generally, N-type devices and P-type devices have different thicknesses of titanium nitride and the same thickness of titanium aluminide. Since N-type devices and P-type devices have different thicknesses of titanium nitride, subsequent different threshold voltages are caused. At the same time, for P-type devices, the thickness of titanium nitride cannot be too thick. Then, as the critical dimension of the gate structure becomes smaller and smaller, the space reserved for the formation of the work function becomes smaller and smaller, resulting in the performance of the finally formed transistor not meeting the actual process requirements.

[0031] On this basis, the present invention provides a semiconductor structure. The substrate includes a P-type device region and an N-type device region. The N-type device region includes a first threshold voltage region, a second threshold voltage region, and a third threshold voltage region. The P-type device region includes a fourth threshold voltage region, a fifth threshold voltage region, and a sixth threshold voltage region. A first gate structure is located in the first threshold voltage region, a second gate structure is located in the second threshold voltage region, a third gate junction is located in the third threshold voltage region, a fourth gate structure is located in the fourth threshold voltage region, a fifth gate structure is located in the fifth threshold voltage region, and a sixth gate structure is located in the sixth threshold voltage region. The contents of N-type polarization particles in the first gate dielectric layer, the second gate dielectric layer, and the third gate dielectric layer are different, so as to realize the voltage regulation of the first threshold voltage region, the second threshold voltage region, and the third threshold voltage region. The contents of P-type polarization particles in the fourth gate dielectric layer, the fifth gate dielectric layer, and the sixth gate dielectric layer are different, so as to realize the voltage regulation of the fourth threshold voltage region, the fifth threshold voltage region, and the sixth threshold voltage region. On the one hand, the voltage regulation of six threshold voltage regions is realized. On the other hand, this voltage regulation method does not require an additional thickness work function layer to achieve, so it can better adapt to the formation of gate structures with smaller critical dimensions, further increasing the openness of the device and having a wide range of applications.

[0032] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following specifically describes the specific embodiments of the present invention with reference to the accompanying drawings.

[0033] Figures 1 to 8 It is a schematic structural diagram of each step of a semiconductor structure and its forming method in an embodiment of the present invention.

[0034] First, please refer to Figure 1 , and provide a substrate, which includes a P-type device region and an N-type device region.

[0035] In this embodiment, the N-type device region includes a first threshold voltage region I, a second threshold voltage region II, and a third threshold voltage region III, and the P-type device region includes a fourth threshold voltage region IV, a fifth threshold voltage region V, and a sixth threshold voltage region VI.

[0036] In this embodiment, the first threshold voltage region I is used to form a first standard threshold voltage (SVT_N), the second threshold voltage region II is used to form a first low threshold voltage (LVT_N), the third threshold voltage region III is used to form a first ultra-low threshold voltage (ULVT_N), the fourth threshold voltage region IV is used to form a second standard threshold voltage (SVT_P), the fifth threshold voltage region V is used to form a second low threshold voltage (LVT_P), and the sixth threshold voltage region VI is used to form a second ultra-low threshold voltage (ULVT_P).

[0037] In this embodiment, the method for forming the substrate includes: providing a substrate 100; etching a part of the thickness of the substrate 100 to form fin portions 101.

[0038] In this embodiment, an isolation structure 102 covering part of the sidewalls of the fin portions 101 is further formed on the surface of the substrate 100.

[0039] Please continue to refer to Figure 1 , a first dummy gate structure 103 spanning the fin portions 101 is formed on the surface of the substrate 100 in the first threshold voltage region I, a second dummy gate structure 104 spanning the fin portions 101 is formed on the surface of the substrate 100 in the second threshold voltage region II, a third dummy gate structure 105 spanning the fin portions 101 is formed on the surface of the substrate 100 in the third threshold voltage region III, a fourth dummy gate structure 106 spanning the fin portions 101 is formed on the surface of the substrate 100 in the fourth threshold voltage region IV, a fifth dummy gate structure 107 spanning the fin portions 101 is formed on the surface of the substrate 100 in the fifth threshold voltage region V, and a sixth dummy gate structure 108 spanning the fin portions 101 is formed on the surface of the substrate 100 in the sixth threshold voltage region VI; a first source / drain doping layer 109 is formed in the fin portions 101 on both sides of the first dummy gate structure 103, a second source / drain doping layer 110 is formed in the fin portions 101 on both sides of the second dummy gate structure 104, a third source / drain doping layer 111 is formed in the fin portions 101 on both sides of the third dummy gate structure 105, a fourth source / drain doping layer 112 is formed in the fin portions 101 on both sides of the fourth dummy gate structure 106, a fifth source / drain doping layer 113 is formed in the fin portions 101 on both sides of the fifth dummy gate structure 107, and a sixth source / drain doping layer 114 is formed in the fin portions 101 on both sides of the sixth dummy gate structure 108.

[0040] In this embodiment, a first sidewall 115 is formed on the sidewall of the first dummy gate structure 103, a second sidewall 116 is formed on the sidewall of the second dummy gate structure 104, a third sidewall 117 is formed on the sidewall of the third dummy gate structure 105, a fourth sidewall 118 is formed on the sidewall of the fourth dummy gate structure 106, a fifth sidewall 119 is formed on the sidewall of the fifth dummy gate structure 107, and a sixth sidewall 120 is formed on the sidewall of the sixth dummy gate structure 108.

[0041] Please refer to Figure 2 , the first dummy gate structure 103 is removed to form a first gate groove 121, the second dummy gate structure 104 is removed to form a second gate groove 122, the third dummy gate structure 105 is removed to form a third gate groove 123, the fourth dummy gate structure 106 is removed to form a fourth gate groove 124, the fifth dummy gate structure 107 is removed to form a fifth gate groove 125, and the sixth dummy gate structure 108 is removed to form a sixth gate groove 126.

[0042] In this embodiment, before removing the first dummy gate structure 103, the second dummy gate structure 104, the third dummy gate structure 105, the fourth dummy gate structure 106, the fifth dummy gate structure 107, and the sixth dummy gate structure 108, a dielectric layer 134 is formed on the substrate 100, and the top surface of the dielectric layer 134 is flush with the tops of the first dummy gate structure 103, the second dummy gate structure 104, the third dummy gate structure 105, the fourth dummy gate structure 106, the fifth dummy gate structure 107, and the sixth dummy gate structure 108.

[0043] Please continue to refer to Figure 2 , an initial gate dielectric layer 127 is formed on the surfaces of the P-type device region and the N-type device region.

[0044] In this embodiment or, the initial gate dielectric layer 127 is formed at the bottoms of the first gate groove 121, the second gate groove 122, the third gate groove 123, the fourth gate groove 124, the fifth gate groove 125, and the sixth gate groove 126 respectively.

[0045] In this embodiment, the material of the initial gate dielectric layer 127 includes a high-K dielectric material, and the high-K dielectric material includes: lanthanum oxide, cerium oxide, or hafnium oxide.

[0046] Please refer to Figure 3 , a first dipole layer 128 is formed on the surface of the initial gate dielectric layer 127 in the third threshold voltage region III, and a second dipole layer 129 is formed on the surface of the first dipole layer 128 and the surface of the initial gate dielectric layer 127 in the second threshold voltage region II.

[0047] In this embodiment, the material of the first dipole layer 128 includes lanthanum oxide, and the material of the second dipole layer 129 includes lanthanum oxide.

[0048] In this embodiment, the formation method of the first dipole layer 128 and the second dipole layer 129 includes: forming an initial first dipole layer (not shown in the figure) on the surface of the initial gate dielectric layer 127; using a first patterning to remove the initial first dipole layer (not shown in the figure) in the second threshold voltage region II, exposing the surface of the initial gate dielectric layer 127 in the second threshold voltage region II, and forming a first intermediate dipole layer; forming an initial second dipole layer 129 on the surface of the first intermediate dipole layer and the surface of the initial gate dielectric layer 127 in the second threshold voltage region II; using a second patterning to remove the initial second dipole layer 129 and the first intermediate dipole layer in the first threshold voltage region I, the fourth threshold voltage region IV, the fifth threshold voltage region V, and the sixth threshold voltage region VI until the surface of the initial gate dielectric layer 127 on the surfaces of the first threshold voltage region I, the fourth threshold voltage region IV, the fifth threshold voltage region V, and the sixth threshold voltage region VI is exposed, and forming a first dipole layer 128 on the surface of the initial gate dielectric layer 127 on the surface of the third threshold voltage region III; forming a second dipole layer 129 on the surface of the first dipole layer 128 and the surface of the second threshold voltage region II.

[0049] Please refer to Figure 4 , a third dipole layer 130 is formed on the surface of the second dipole layer 129, the surface of the initial gate dielectric layer 127 in the first threshold voltage region I, the surface of the initial gate dielectric layer 127 in the fourth threshold voltage region IV, the surface of the initial gate dielectric layer 127 in the fifth threshold voltage region V, and the surface of the initial gate dielectric layer 127 in the sixth threshold voltage region VI. The first dipole layer 128, the second dipole layer 129, and the third dipole layer 130 contain N-type polarized particles.

[0050] In this embodiment, the material of the third dipole layer 130 includes lanthanum oxide.

[0051] Please refer to Figure 5 , a fourth dipole layer 131 is formed on the surface of the third dipole layer 130 in the sixth threshold voltage region VI, a fifth dipole layer 132 is formed on the surface of the third dipole layer 130 in the fifth threshold voltage region V, and a sixth dipole layer 133 is formed on the surface of the third dipole layer 130 in the fourth threshold voltage region IV, the surface of the fourth dipole layer 131, and the surface of the fifth dipole layer 132. The fourth dipole layer 131, the fifth dipole layer 132, and the sixth dipole layer 133 contain P-type polarized particles.

[0052] In this embodiment, the material of the fourth dipole layer 131 includes aluminum oxide, the material of the fifth dipole layer 132 includes aluminum oxide, and the material of the sixth dipole layer 133 includes aluminum oxide.

[0053] In this embodiment, the formation method of the fourth dipole layer 131, the fifth dipole layer 132, and the sixth dipole layer includes: forming an initial fourth dipole layer on the surface of the third dipole layer 130; patterning and removing the initial fourth dipole layer in the fifth threshold voltage region V to expose the third dipole layer 130 in the fifth threshold voltage region V, thereby forming a fourth intermediate dipole layer; forming an initial fifth dipole layer 132 on the surfaces of the fourth intermediate dipole layer and the third dipole layer 130; removing the initial fifth dipole layer and the fourth intermediate dipole layer on the surface of the fourth threshold voltage region IV until the third dipole layer 130 on the surface of the second threshold voltage region II is exposed, thereby forming a fifth intermediate dipole layer; forming an initial sixth dipole layer on the surfaces of the fifth intermediate dipole layer and the third dipole layer 130; patterning and removing the initial sixth dipole layer, the fifth intermediate dipole layer, and the fourth intermediate dipole layer in the third threshold voltage region III, the second threshold voltage region II, and the first threshold voltage region I, thereby forming the sixth dipole layer 133, the fifth dipole layer 132, and the fourth dipole layer 131.

[0054] Please refer to Figure 6 , perform an annealing process to drive the N-type polarized particles in the first dipole layer 128, the second dipole layer 129, and the third dipole layer 130 to migrate into the initial gate dielectric layer 127, and drive the P-type polarized particles in the fourth dipole layer 131, the fifth dipole layer 132, and the sixth dipole layer 133 to migrate into the initial gate dielectric layer 127.

[0055] In this embodiment, the process parameters of the annealing process include an annealing temperature range of 400°C to 1000°C and an annealing time of 0.001 s to 600 s.

[0056] Please refer to Figure 7 , after the annealing process, remove the first dipole layer 128, the second dipole layer 129, the third dipole layer 130, the fourth dipole layer 131, the fifth dipole layer 132, and the sixth dipole layer 133.

[0057] In this embodiment, a first gate dielectric layer 135 is formed on the first threshold voltage region I, a second gate dielectric layer 136 is formed on the second threshold voltage region II, a third gate dielectric layer 137 is formed on the third threshold voltage region III, a fourth gate dielectric layer 138 is formed on the fourth threshold voltage region IV, a fifth gate dielectric layer 139 is formed on the fifth threshold voltage region V, and a sixth gate dielectric layer 140 is formed on the sixth threshold voltage region VI. The contents of N-type polarized particles in the first gate dielectric layer 135, the second gate dielectric layer 136, and the third gate dielectric layer 137 are different, and the contents of P-type polarized particles in the fourth gate dielectric layer 138, the fifth gate dielectric layer 139, and the sixth gate dielectric layer 140 are different.

[0058] In this embodiment, the concentration range of N-type polarized particles in the first gate dielectric layer 135 is 1*10 11cm -2 ~1 * 10 16 cm -2 、 the concentration range of N - type polarization particles in the second gate dielectric layer 136 is 1 * 10 11 cm -2 ~1 * 10 16 cm -2 , and the concentration range of N - type polarization particles in the third gate dielectric layer 137 is 1 * 10 11 cm -2 ~1 * 10 16 cm -2 .

[0059] In this embodiment, the concentration range of P - type polarization particles in the third gate dielectric layer 137 is 1 * 10 11 cm -2 ~1 * 10 16 cm -2 、 the concentration range of P - type polarization particles in the fourth gate dielectric layer 138 is 1 * 10 11 cm -2 ~1 * 10 16 cm -2 , and the concentration range of P - type polarization particles in the sixth gate dielectric layer 140 is 1 * 10 11 cm -2 ~1 * 10 16 cm -2 .

[0060] Please refer to Figure 8 , a first gate layer 141' is formed on the surface of the first gate dielectric layer 135, a second gate layer 142' is formed on the surface of the second gate dielectric layer 136, a third gate layer 143' is formed on the surface of the third gate dielectric layer 137, a fourth gate layer 144' is formed on the surface of the fourth gate dielectric layer 138, a fifth gate layer 145' is formed on the surface of the fifth gate dielectric layer 139, and a sixth gate layer 146' is formed on the surface of the sixth gate dielectric layer 140.

[0061] In this embodiment, the first gate dielectric layer 135 and the first gate layer 141' constitute the first gate structure 141, the second gate dielectric layer 136 and the second gate layer 142' constitute the second gate structure 142, the third gate dielectric layer 137 and the third gate layer 143' constitute the third gate structure 143, the fourth gate dielectric layer 138 and the fourth gate layer 144' constitute the fourth gate structure 144, the fifth gate dielectric layer 139 and the fifth gate layer 145' constitute the fifth gate structure 145, and the sixth gate dielectric layer 140 and the sixth gate layer 146' constitute the sixth gate structure 146.

[0062] In this embodiment, on the one hand, the first dipole layer 128, the second dipole layer 129, the third dipole layer 130, the fourth dipole layer 131, the fifth dipole layer 132, and the sixth dipole layer 133 are simultaneously used to perform different particle doping effects on the initial gate dielectric layer 127, so that the contents of N-type polarized particles in the first gate dielectric layer 135, the second gate dielectric layer 136, and the third gate dielectric layer 137 are different, and the contents of P-type polarized particles in the fourth gate dielectric layer 138, the fifth gate dielectric layer 139, and the sixth gate dielectric layer 140 are different, realizing voltage regulation in six threshold voltage regions. On the other hand, after the gate dielectric layer is formed by this voltage regulation method, a gate electrode layer is directly formed on the surface of the gate dielectric layer, without the need for an additional thickness work function layer to achieve, so that it can better adapt to the formation of gate electrode structures with smaller critical dimensions, further increasing the openness of the device and having a wider scope of application.

[0063] Correspondingly, the present invention also provides a semiconductor structure by using the above method. Please refer to Figure 8 , including: providing a substrate, the substrate includes a P-type device region and an N-type device region, the N-type device region includes a first threshold voltage region I, a second threshold voltage region II, and a third threshold voltage region III, the P-type device region includes a fourth threshold voltage region IV, a fifth threshold voltage region V, and a sixth threshold voltage region VI; a first gate electrode structure 141 on the substrate in the first threshold voltage region I, the first gate electrode structure 141 includes a first gate dielectric layer 135, and a first gate electrode layer 141' on the surface of the first gate dielectric layer 135; a second gate electrode structure 142 on the substrate in the second threshold voltage region II, the second gate electrode structure 142 includes a second gate dielectric layer 136, and a second gate electrode layer 142' on the surface of the second gate dielectric layer 136; a third gate electrode structure 143 on the substrate in the third threshold voltage region III, the third gate electrode structure 143 includes a third gate dielectric layer 137, and a third gate electrode layer 143' on the surface of the third gate dielectric layer 137, and the contents of N-type polarized particles in the first gate dielectric layer 135, the second gate dielectric layer 136, and the third gate dielectric layer 137 are different; a fourth gate electrode structure 144 on the substrate in the fourth threshold voltage region IV, the fourth gate electrode structure 144 includes a fourth gate dielectric layer 138, and a fourth gate electrode layer 144' on the surface of the fourth gate dielectric layer 138; a fifth gate electrode structure 145 on the substrate in the fifth threshold voltage region V, the fifth gate electrode structure 145 includes a fifth gate dielectric layer 139, and a fifth gate electrode layer 145' on the surface of the fifth gate dielectric layer 139; a sixth gate electrode structure 146 on the substrate in the sixth threshold voltage region VI, the sixth gate electrode structure 146 includes a sixth gate dielectric layer 140, and a sixth gate electrode layer 146' on the surface of the sixth gate dielectric layer 140, and the contents of P-type polarized particles in the fourth gate dielectric layer 138, the fifth gate dielectric layer 139, and the sixth gate dielectric layer 140 are different.

[0064] In this embodiment, by simultaneously utilizing the different particle doping effects of the first dipole layer 128, the second dipole layer 129, the third dipole layer 130, the fourth dipole layer 131, the fifth dipole layer 132, and the sixth dipole layer 133 on the initial gate dielectric layer 127, the contents of N-type polarized particles in the first gate dielectric layer 135, the second gate dielectric layer 136, and the third gate dielectric layer 137 are made different, and the contents of P-type polarized particles in the fourth gate dielectric layer 138, the fifth gate dielectric layer 139, and the sixth gate dielectric layer 140 are made different to achieve voltage regulation in six threshold voltage regions. On the other hand, the gate layer is located on the surface of the gate dielectric layer to form a gate structure, without the need for an additional thickness work function layer, thus being more adaptable to the formation of gate structures with smaller critical dimensions, further increasing the openness of the device and having a wider range of applications.

[0065] In this embodiment, the N-type polarized particles include lanthanum.

[0066] In this embodiment, the P-type polarized particles include aluminum.

[0067] In this embodiment, the concentration range of N-type polarized particles in the first gate dielectric layer 135 is 1×10 11 cm -2 ~1×10 16 cm -2 ; the concentration range of N-type polarized particles in the second gate dielectric layer 136 is 1×10 11 cm -2 ~1×10 16 cm -2 ; and the concentration range of N-type polarized particles in the third gate dielectric layer 137 is 1×10 11 cm -2 ~1×10 16 cm -2 .

[0068] In this embodiment, the concentration range of P-type polarized particles in the third gate dielectric layer 137 is 1×10 11 cm -2 ~1×10 16 cm -2 ; the concentration range of P-type polarized particles in the fourth gate dielectric layer 138 is 1×10 11 cm -2 ~1×10 16 cm -2 ; and the concentration range of P-type polarized particles in the sixth gate dielectric layer 140 is 1×10 11 cm -2 ~1×10 16 cm -2 .

[0069] In this embodiment, the materials of the first gate dielectric layer 135, the second gate dielectric layer 136, the third gate dielectric layer 137, the fourth gate dielectric layer 138, the fifth gate dielectric layer 139, and the sixth gate dielectric layer 140 include high-k dielectric materials, and the high-k dielectric materials include: lanthanum oxide, cerium oxide, or hafnium oxide.

[0070] In this embodiment, the materials of the first gate layer 141’, the second gate layer 142’, the third gate layer 143’, the fourth gate layer 144’, the fifth gate layer 145’, and the sixth gate layer 146’ include metal materials.

[0071] In this embodiment, the substrate includes: a substrate 100; a fin 101 located on the surface of the substrate 100, and the first gate structure 141, the second gate structure 142, the third gate structure 143, the fourth gate structure 144, the fifth gate structure 145, and the sixth gate structure 146 straddle the fin 101.

[0072] In this embodiment, it further includes: a first source / drain doping layer 109 in the fin 101 on both sides of the first gate structure 141, a second source / drain doping layer 110 in the fin 101 on both sides of the second gate structure 142, a third source / drain doping layer 111 in the fin 101 on both sides of the third gate structure 143, a fourth source / drain doping layer 112 in the fin 101 on both sides of the fourth gate structure 144, a fifth source / drain doping layer 113 in the fin 101 on both sides of the fifth gate structure 145, and a sixth source / drain doping layer 114 in the fin 101 on both sides of the sixth gate structure 146.

[0073] In this embodiment, it further includes: an isolation structure 102 located on the surface of the substrate 100 and covering a part of the sidewalls of the fin 101.

[0074] In this embodiment, it further includes: a dielectric layer 134 located on the surface of the substrate 100, and the top surface of the dielectric layer 134 is flush with the top surfaces of the first gate structure 141, the second gate structure 142, the third gate structure 143, the fourth gate structure 144, the fifth gate structure 145, and the sixth gate structure 146.

[0075] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, Including: Providing a substrate, the substrate including a P-type device region and an N-type device region, the N-type device region including a first threshold voltage region, a second threshold voltage region, and a third threshold voltage region, the P-type device region including a fourth threshold voltage region, a fifth threshold voltage region, and a sixth threshold voltage region; A first gate structure on the substrate in the first threshold voltage region, the first gate structure including a first gate dielectric layer and a first gate layer on the surface of the first gate dielectric layer; A second gate structure on the substrate in the second threshold voltage region, the second gate structure including a second gate dielectric layer and a second gate layer on the surface of the second gate dielectric layer; A third gate structure on the substrate in the third threshold voltage region, the third gate structure including a third gate dielectric layer and a third gate layer on the surface of the third gate dielectric layer, the contents of N-type polarization particles in the first gate dielectric layer, the second gate dielectric layer, and the third gate dielectric layer being different; A fourth gate structure on the substrate in the fourth threshold voltage region, the fourth gate structure including a fourth gate dielectric layer and a fourth gate layer on the surface of the fourth gate dielectric layer; A fifth gate structure on the substrate in the fifth threshold voltage region, the fifth gate structure including a fifth gate dielectric layer and a fifth gate layer on the surface of the fifth gate dielectric layer; A sixth gate structure on the substrate in the sixth threshold voltage region, the sixth gate structure including a sixth gate dielectric layer and a sixth gate layer on the surface of the sixth gate dielectric layer, the contents of P-type polarization particles in the fourth gate dielectric layer, the fifth gate dielectric layer, and the sixth gate dielectric layer being different.

2. The semiconductor structure according to claim 1, characterized in that, The N-type polarization particles include lanthanum.

3. The semiconductor structure according to claim 1, characterized in that, The P-type polarization particles include aluminum.

4. The semiconductor structure according to claim 1, wherein, The concentration range of N-type polarization particles in the first gate dielectric layer is 1×10 11 cm -2 ~1×10 16 cm -2 、The concentration range of N-type polarization particles in the second gate dielectric layer is 1×10 11 cm -2 ~1×10 16 cm -2 ,and the concentration range of N-type polarization particles in the third gate dielectric layer is 1×10 11 cm -2 ~1×10 16 cm -2 。 5. The semiconductor structure according to claim 1, characterized in that The concentration range of P-type polarization particles in the third gate dielectric layer is 1×10 11 cm -2 ~1×10 16 cm -2 、The concentration range of P-type polarization particles in the fourth gate dielectric layer is 1×10 11 cm -2 ~1×10 16 cm -2 ,and the concentration range of P-type polarization particles in the sixth gate dielectric layer is 1×10 11 cm -2 ~1×10 16 cm -2 .

6. The semiconductor structure according to claim 1, wherein, The materials of the first gate dielectric layer, the second gate dielectric layer, the third gate dielectric layer, the fourth gate dielectric layer, the fifth gate dielectric layer, and the sixth gate dielectric layer include high-K dielectric materials, and the high-K dielectric materials include: lanthanum oxide, cerium oxide, or hafnium oxide.

7. The semiconductor structure according to claim 1, wherein The substrate includes: a substrate; fins on the surface of the substrate, and the first gate structure, the second gate structure, the third gate structure, the fourth gate structure, the fifth gate structure, and the sixth gate structure straddle the fins.

8. The semiconductor structure according to claim 7, wherein Further including: A first source-drain doping layer in the fins on both sides of the first gate structure, a second source-drain doping layer in the fins on both sides of the second gate structure, a third source-drain doping layer in the fins on both sides of the third gate structure, a fourth source-drain doping layer in the fins on both sides of the fourth gate structure, a fifth source-drain doping layer in the fins on both sides of the fifth gate structure, and a sixth source-drain doping layer in the fins on both sides of the sixth gate structure.

9. A method for forming a semiconductor structure, characterized in that, Including: Providing a substrate, the substrate including a P-type device region and an N-type device region, the N-type device region including a first threshold voltage region, a second threshold voltage region, and a third threshold voltage region, the P-type device region including a fourth threshold voltage region, a fifth threshold voltage region, and a sixth threshold voltage region; An initial gate dielectric layer is formed on the surfaces of the P-type device region and the N-type device region; A first dipole layer is formed on the surface of the initial gate dielectric layer in the third threshold voltage region; A second dipole layer is formed on the surface of the first dipole layer and the surface of the initial gate dielectric layer in the second threshold voltage region; A third dipole layer is formed on the surface of the second dipole layer, the surface of the initial gate dielectric layer in the first threshold voltage region, the surface of the initial gate dielectric layer in the fourth threshold voltage region, the surface of the initial gate dielectric layer in the fifth threshold voltage region, and the surface of the initial gate dielectric layer in the sixth threshold voltage region. The first dipole layer, the second dipole layer, and the third dipole layer contain N-type polarization particles; A fourth dipole layer is formed on the surface of the third dipole layer in the sixth threshold voltage region; A fifth dipole layer is formed on the surface of the third dipole layer in the fifth threshold voltage region; A sixth dipole layer is formed on the surface of the third dipole layer in the fourth threshold voltage region, the surface of the fourth dipole layer, and the surface of the fifth dipole layer. The fourth dipole layer, the fifth dipole layer, and the sixth dipole layer contain P-type polarization particles; An annealing treatment is performed to drive the N-type polarization particles in the first dipole layer, the second dipole layer, and the third dipole layer to migrate into the initial gate dielectric layer, and drive the P-type polarization particles in the fourth dipole layer, the fifth dipole layer, and the sixth dipole layer to migrate into the initial gate dielectric layer. A first gate dielectric layer is formed on the first threshold voltage region, a second gate dielectric layer is formed on the second threshold voltage region, a third gate dielectric layer is formed on the third threshold voltage region, a fourth gate dielectric layer is formed on the fourth threshold voltage region, a fifth gate dielectric layer is formed on the fifth threshold voltage region, and a sixth gate dielectric layer is formed on the sixth threshold voltage region. The contents of N-type polarization particles in the first gate dielectric layer, the second gate dielectric layer, and the third gate dielectric layer are different, and the contents of P-type polarization particles in the fourth gate dielectric layer, the fifth gate dielectric layer, and the sixth gate dielectric layer are different; After the annealing treatment, the first dipole layer, the second dipole layer, the third dipole layer, the fourth dipole layer, the fifth dipole layer, and the sixth dipole layer are removed; After removing the first dipole layer, the second dipole layer, the third dipole layer, the fourth dipole layer, the fifth dipole layer, and the sixth dipole layer, a first gate electrode layer is formed on the surface of the first gate dielectric layer, a second gate electrode layer is formed on the surface of the second gate dielectric layer, a third gate electrode layer is formed on the surface of the third gate dielectric layer, a fourth gate electrode layer is formed on the surface of the fourth gate dielectric layer, a fifth gate electrode layer is formed on the surface of the fifth gate dielectric layer, and a sixth gate electrode layer is formed on the surface of the sixth gate dielectric layer.

10. The method for forming a semiconductor structure according to claim 9, wherein, The process parameters of the annealing treatment include an annealing temperature range of 400°C to 1000°C and an annealing time of 0.001 s to 600 s.

11. The method for forming a semiconductor structure according to claim 9, wherein, The material of the first dipole layer includes lanthanum oxide, the material of the second dipole layer includes lanthanum oxide, and the material of the third dipole layer includes lanthanum oxide.

12. The method for forming a semiconductor structure as claimed in claim 9, wherein, The material of the fourth dipole layer includes aluminum oxide, the material of the fifth dipole layer includes aluminum oxide, and the material of the sixth dipole layer includes aluminum oxide.

13. The method for forming a semiconductor structure according to claim 9, wherein, The material of the initial gate dielectric layer includes a high-K dielectric material, and the high-K dielectric material includes: lanthanum oxide, cerium oxide or hafnium oxide.

14. The method for forming a semiconductor structure according to claim 9, wherein, The forming method of the first dipole layer and the second dipole layer includes: forming an initial first dipole layer on the surface of the initial gate dielectric layer; removing the initial first dipole layer in the second threshold voltage region by using a first patterning to expose the surface of the initial gate dielectric layer in the second threshold voltage region, and forming a first intermediate dipole layer; forming an initial second dipole layer on the surface of the first intermediate dipole layer and the surface of the initial gate dielectric layer in the second threshold voltage region; removing the initial second dipole layer and the first intermediate dipole layer in the first threshold voltage region, the fourth threshold voltage region, the fifth threshold voltage region and the sixth threshold voltage region by using a second patterning until the surface of the initial gate dielectric layer in the first threshold voltage region, the fourth threshold voltage region, the fifth threshold voltage region and the sixth threshold voltage region is exposed, and forming the first dipole layer on the surface of the initial gate dielectric layer in the third threshold voltage region; forming the second dipole layer on the surface of the first dipole layer and the surface in the second threshold voltage region.

15. The method for forming a semiconductor structure according to claim 14, wherein, The forming method of the fourth dipole layer, the fifth dipole layer and the sixth dipole layer includes: forming an initial fourth dipole layer on the surface of the third dipole layer; patterning and removing the initial fourth dipole layer in the fifth threshold voltage region to expose the third dipole layer in the fifth threshold voltage region, and forming a fourth intermediate dipole layer; forming an initial fifth dipole layer on the surface of the fourth intermediate dipole layer and the third dipole layer; removing the initial fifth dipole layer and the fourth intermediate dipole layer on the surface of the fourth threshold voltage region until the third dipole layer on the surface of the second threshold voltage region is exposed, and forming a fifth intermediate dipole layer; forming an initial sixth dipole layer on the surface of the fifth intermediate dipole layer and the third dipole layer; patterning and removing the initial sixth dipole layer, the fifth intermediate dipole layer and the fourth intermediate dipole layer in the third threshold voltage region, the second threshold voltage region and the first threshold voltage region to form the sixth dipole layer, the fifth dipole layer and the fourth dipole layer.

16. The method for forming a semiconductor structure according to claim 9, wherein The forming method of the substrate includes: providing a substrate; etching a part of the thickness of the substrate to form fins.

17. The method for forming a semiconductor structure according to claim 16, wherein, Before forming the initial gate dielectric layer, the following steps are further included: forming a first dummy gate structure across the fin on the surface of the substrate in the first threshold voltage region, forming a second dummy gate structure across the fin on the surface of the substrate in the second threshold voltage region, forming a third dummy gate structure across the fin on the surface of the substrate in the third threshold voltage region, forming a fourth dummy gate structure across the fin on the surface of the substrate in the fourth threshold voltage region, forming a fifth dummy gate structure across the fin on the surface of the substrate in the fifth threshold voltage region, and forming a sixth dummy gate structure across the fin on the surface of the substrate in the sixth threshold voltage region; forming a first source / drain doping layer in the fins on both sides of the first dummy gate structure, forming a second source / drain doping layer in the fins on both sides of the second dummy gate structure, forming a third source / drain doping layer in the fins on both sides of the third dummy gate structure, forming a fourth source / drain doping layer in the fins on both sides of the fourth dummy gate structure, forming a fifth source / drain doping layer in the fins on both sides of the fifth dummy gate structure, and forming a sixth source / drain doping layer in the fins on both sides of the sixth dummy gate structure; removing the first dummy gate structure to form a first gate groove, removing the second dummy gate structure to form a second gate groove, removing the third dummy gate structure to form a third gate groove, removing the fourth dummy gate structure to form a fourth gate groove, removing the fifth dummy gate structure to form a fifth gate groove, and removing the sixth dummy gate structure to form a sixth gate groove; forming the initial gate dielectric layer at the bottom of the first gate groove, the bottom of the second gate groove, the bottom of the third gate groove, the bottom of the fourth gate groove, the bottom of the fifth gate groove, and the bottom of the sixth gate groove respectively.

18. The method for forming a semiconductor structure according to claim 9, wherein The materials of the first gate layer, the second gate layer, the third gate layer, the fourth gate layer, the fifth gate layer, and the sixth gate layer are metal materials.

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