Nitride CMOS device based on non-polar m plane and preparation method thereof
By etching grooves in the GaN layer and depositing the AlGaN layer to form a heterojunction, the problems of leakage current and low-temperature downloading fluid freezing effects of traditional Si-based CMOS at high temperature and high pressure are solved, and high-performance nitride CMOS devices are realized, suitable for high-temperature, high-pressure, and high-frequency and high-power applications.
Patent Information
- Application Number
- CN202510548529.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-28
- Publication Date
- 2025-08-01
AI Technical Summary
Traditional Si-based CMOS has leakage current increase and low-temperature loading reamer freezing effects in high-temperature and high-pressure environments, and nitride-based CMOS is difficult to produce 2DEG and 2DHG on the same GaN layer at the same time, and the doping efficiency is low, resulting in insufficient performance of the device in high-temperature, high-pressure, high-frequency and high-power occasions.
Using a non-polar m-face nitride CMOS device structure, a GaN/AlGaN heterojunction is formed to generate 2DEG and 2DHG as n-type and p-type conductive channels, using polarization effect to achieve high mobility and high conductivity.
CMOS devices with high mobility and high conductivity are suitable for high temperature, high voltage, high frequency and high power occasions, with a larger bandwidth, higher breakdown electric field and higher radiation resistance.
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Figure CN120417480A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of semiconductors, and particularly relates to a nitride CMOS device based on a non-polar m-plane and a preparation method thereof. Background Art
[0002] CMOS (Complementary Metal Oxide Semiconductor) is an integrated circuit technology based on field effect transistors. Its core structure is a pair of complementary transistors, namely an N-type MOS transistor (NMOS) and a P-type MOS transistor (PMOS). When the NMOS and PMOS transistors work simultaneously in a circuit, they can achieve low-power, high-speed logic functions. As the cornerstone of modern electronic devices, CMOS technology has a wide range of applications covering various devices from smartphones to data centers.
[0003] Traditional CMOS is generally based on Si. However, due to the small bandgap of Si material, in a high-temperature and high-pressure environment, Si-based CMOS enables carriers to obtain sufficient energy to jump to the conduction band, resulting in an increase in leakage current, making the component unable to turn off normally, and in severe cases, it may lead to component failure. In a low-temperature environment, due to the carrier freeze-out effect caused by impurity ionization, the concentration of electrons or holes gradually decreases, affecting the normal operation of the semiconductor. In addition, the Si-based CMOS circuit design is complex, with large parasitic inductance and relatively low overall operating speed.
[0004] Compared with silicon, nitrides (such as GaN) as the third-generation semiconductor materials have a larger bandgap, higher breakdown electric field, higher electron saturation velocity, and higher radiation resistance, and are more suitable for high-temperature, high-pressure, high-frequency, and high-power applications. At the same time, nitrides have a unique polarization effect. Taking GaN and AlGaN as examples, GaN mainly exists in the wurtzite structure under normal temperature and pressure. The lattice mismatch and thermal mismatch existing in the heterojunction composed of GaN material and its ternary alloy A1GaN material can also generate a piezoelectric polarization electric field. Through the spontaneous and piezoelectric polarization electric fields, a high-density and high-mobility 2DEG (dimensional electron gas) and 2DHG (dimensional hole gas) can be induced at the heterojunction interface, which has unique advantages for preparing CMOS devices
[0005] However, the conductive channels of conventional nitride-based CMOS are horizontal, and it is impossible to generate 2DEG and 2DHG simultaneously on the same GaN layer. The p-channel in CMOS generally needs to use a GaN / AlGaN / p-GaN double heterojunction to achieve. In addition, when conventional nitride-based CMOS is doped with n-type and p-type impurities, the activation energy of impurity ionization is relatively high, the doping efficiency is low, and it is difficult to achieve doping by ion implantation, resulting in difficulties in applying the n-well and p-well processes to nitride-based CMOS materials. Summary of the Invention
[0006] To solve the above problems existing in the prior art, the present invention provides a nitride CMOS device based on the non-polar m-plane and a preparation method thereof. The technical problems to be solved by the present invention are achieved through the following technical solutions:
[0007] In a first aspect, the present invention proposes a nitride CMOS device based on the non-polar m-plane, including: a substrate, a non-polar m-plane GaN layer, an AlGaN layer, a drain electrode, a gate electrode, and a source electrode; wherein,
[0008] The GaN layer is located on the substrate; and a groove is etched in the middle of the GaN layer;
[0009] The AlGaN layer is disposed on the left and right sidewalls of the groove to form a double heterojunction with the GaN layer; wherein, the AlGaN layer on the left sidewall of the groove forms a GaN / AlGaN heterojunction with the adjacent GaN layer, and generates 2DEG on the GaN side to serve as the n-type conductive channel of the device; the AlGaN layer on the right sidewall of the groove forms an AlGaN / GaN heterojunction with the adjacent GaN layer, and generates 2DHG on the GaN side to serve as the p-type conductive channel of the device;
[0010] The drain electrode is disposed on the GaN layer at the bottom of the groove;
[0011] The gate electrode and the source electrode are disposed on the AlGaN layer.
[0012] In an embodiment of the present invention, the substrate is made of diamond material.
[0013] In an embodiment of the present invention, the thickness of the GaN layer is 0.1 - 50 μm; the etching depth of the groove is 0.01 - 5 μm.
[0014] In an embodiment of the present invention, the width of the AlGaN layer is 3 - 100 nm; and the Al component in the AlGaN is 0.1 - 1.
[0015] In one embodiment of the present invention, the thickness of the drain electrode is 0.01 - 1 μm, and the material is a multi-layer metal of Ti / Al / Ni / Au; the thickness of the source electrode and the gate electrode is 0.01 - 1 μm, the width is 1 - 250 nm, and the material is a double-layer metal of Ni / Au.
[0016] Second, the present invention proposes a preparation method of a nitride CMOS device based on a non-polar m-plane, including:
[0017] Provide a substrate and perform pretreatment;
[0018] Epitaxially grow a non-polar m-plane GaN layer on the pretreated substrate;
[0019] Etch the GaN layer to form a groove in the middle of the GaN layer;
[0020] Epitaxially grow AlGaN layers on the left and right sidewalls of the groove;
[0021] Fabricate a drain electrode on the GaN layer at the bottom of the groove;
[0022] Fabricate a gate electrode and a source electrode on the AlGaN layer, thus completing the device preparation.
[0023] In one embodiment of the present invention, providing a substrate and performing pretreatment includes:
[0024] Provide a diamond substrate;
[0025] Put the diamond substrate into a container filled with acetone solution, and then put the container into an ultrasonic cleaning tank for cleaning for 10 - 50 min;
[0026] Take out the cleaned diamond substrate and put it into a drying oven for drying treatment at a temperature of 50 - 90 °C;
[0027] Put the dried diamond substrate into a dilute hydrochloric acid solution and soak it for 10 - 200 s;
[0028] Take out the soaked diamond substrate and put it into a drying oven for drying treatment again at a temperature of 50 - 150 °C.
[0029] In one embodiment of the present invention, growing an epitaxial non-polar m-plane GaN layer on the pretreated substrate includes:
[0030] Put the pretreated substrate into the reaction chamber, keep the temperature of the reaction chamber at 900 - 1100 °C, keep the pressure of the reaction chamber at 10 - 50 Torr, and simultaneously introduce a nitrogen source with a flow rate of 1500 - 3300 sccm and a gallium source with a flow rate of 10 - 90 sccm, and use the MOCVD process to grow a non-polar m-plane GaN layer with a thickness of 0.1 - 50 μm on the substrate.
[0031] In one embodiment of the present invention, the GaN layer is etched to form a groove in the middle of the GaN layer, including:
[0032] Maintain the temperature of the reaction chamber at 900 - 1100 °C, maintain the pressure of the reaction chamber at 10 - 50 Torr, and use dry etching technology to etch a groove with a depth of 0.01 - 5 μm on the non-polar m-plane GaN layer.
[0033] In one embodiment of the present invention, an AlGaN layer is epitaxially grown on the left and right sidewalls of the groove, including:
[0034] Maintain the temperature of the reaction chamber at 900 - 1100 °C, maintain the pressure of the reaction chamber at 10 - 50 Torr, and simultaneously introduce a nitrogen source with a flow rate of 1500 - 3300 sccm, a gallium source with a flow rate of 10 - 90 sccm, and an aluminum source with a flow rate of 50 - 200 sccm. Use the MOCVD process to grow an AlGaN layer with a width of 3 - 100 nm and an Al composition of 0.1 - 1 on the left and right sidewalls of the groove, so as to form a double heterojunction with the GaN layers on the left and right sides, and respectively form a 2DEG and a 2DHG with high concentration and high mobility on the surface of the heterojunction.
[0035] Advantages of the present invention:
[0036] The nitride-based CMOS device based on the non-polar m-plane provided by the present invention uses a groove to etch GaN, and AlGaN is deposited on the two sidewalls in the groove, which can make the 2DEG and 2DHG appear simultaneously in the GaN layer, serving as the n-type and p-type conductive channels of the CMOS. Compared with the traditional nitride-based CMOS, a CMOS device with high mobility and high conductivity is realized; the CMOS device adopting this structure has a larger bandgap width, a higher breakdown electric field, a higher electron saturation velocity, and a higher radiation resistance, and is more suitable for high-temperature, high-pressure, high-frequency, and high-power occasions.
[0037] The following will further describe the present invention in detail with reference to the drawings and embodiments. Description of the Drawings [[ID=
[23] ]
[0038] Figure 1 is a schematic structural diagram of a nitride-based CMOS device based on the non-polar m-plane provided by an embodiment of the present invention;
[0039] Figure 2 is a schematic flow diagram of a preparation method of a nitride-based CMOS device based on the non-polar m-plane provided by an embodiment of the present invention;
[0040] Figure 3 [[ID=3
[34] ]is a schematic process diagram of preparing a nitride-based CMOS device based on the non-polar m-plane provided by an embodiment of the present invention. Detailed implementation manners
[0041] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.
[0042] The first aspect of the present invention provides a nitride CMOS device based on a non-polar m-plane. Please refer to Figure 1 , Figure 1 which is a schematic structural diagram of a nitride CMOS device based on a non-polar m-plane provided by an embodiment of the present invention. The device includes: a substrate, a non-polar m-plane GaN layer, an AlGaN layer, a drain electrode, a gate electrode, and a source electrode; wherein,
[0043] the GaN layer is located on the substrate; and a groove is etched in the middle of the GaN layer;
[0044] the AlGaN layer is disposed on the left and right sidewalls of the groove to form a double heterojunction with the GaN layer; wherein, the AlGaN layer on the left sidewall of the groove forms a GaN / AlGaN heterojunction with the adjacent GaN layer, and generates 2DEG on the GaN side to serve as the n-type conductive channel of the device; the AlGaN layer on the right sidewall of the groove forms an AlGaN / GaN heterojunction with the adjacent GaN layer, and generates 2DHG on the GaN side to serve as the p-type conductive channel of the device;
[0045] the drain electrode is disposed on the GaN layer at the bottom of the groove;
[0046] the gate electrode and the source electrode are disposed on the AlGaN layer.
[0047] In this embodiment, the substrate is made of diamond material, which can improve the heat dissipation ability of the device.
[0048] Optionally, as an implementation manner, the thickness range of the GaN layer is 0.1-50 μm, preferably 25 μm, and the etching depth range of the groove is 0.01-5 μm, preferably 5 μm.
[0049] Optionally, as an implementation manner, the width range of the AlGaN layer in this embodiment is 3-100 nm, preferably 25 nm; and the Al component in the AlGaN is 0.1-1, preferably 0.8.
[0050] In addition, in this embodiment, the thickness of the drain electrode ranges from 0.01 to 1 μm, preferably 1 μm, and the material is a Ti / Al / Ni / Au multi-layer metal; the thickness of the source electrode and the gate electrode ranges from 0.01 to 1 μm, preferably 1 μm, the width ranges from 1 to 250 nm, preferably 200 nm, and the material is a Ni / Au double-layer metal.
[0051] The nitride CMOS device based on the non-polar m-plane provided by the present invention uses groove etching for GaN, and AlGaN is deposited on two sidewalls in the groove. Due to the existence of the polarization effect perpendicular to the growth direction, 2DEG and 2DHG simultaneously appear in the GaN layers at the AlGaN / GaN heterojunction interfaces on the two sidewalls, respectively, serving as the electron and hole conducting channels of the CMOS, that is, the n-type and p-type conducting channels. Compared with the traditional nitride-based CMOS, a CMOS device with high mobility and high conductivity is achieved; the CMOS device adopting this structure has a larger bandgap width, a higher breakdown electric field, a higher electron saturation velocity, and a higher radiation resistance, and is more suitable for high-temperature, high-pressure, high-frequency, and high-power applications.
[0052] Specifically, group III nitrides such as gallium nitride usually exist in a hexagonal wurtzite structure, and its crystal planes mainly include the c-plane, the m-plane, and the a-plane; among them, the c-plane is a polar plane (such as (0001)), and the polarization direction is perpendicular to the surface; the m-plane is a non-polar plane, corresponding to the {10-10} crystal plane and perpendicular to the a-axis; the a-plane is a non-polar plane, corresponding to the {11-20} crystal plane and perpendicular to the m-axis. In Figure 1 GaN grows along the m-plane, and the c-plane perpendicular to the m-plane is the polar plane of GaN. When AlGaN grows along the polar direction of GaN, due to the polarization effect, two-dimensional electron gas or two-dimensional hole gas will be generated due to different stacking directions.
[0053] In the wurtzite crystal structures of GaN and AlGaN, the polarization direction is determined by the lattice polarity: Ga plane (
[0001] direction): the spontaneous polarization direction is opposite to the material growth direction; N plane ([000-1] direction): the spontaneous polarization direction is reversed and the same as the material growth direction. Generally, the spontaneous polarization is stronger than the piezoelectric polarization, and the influence of the piezoelectric polarization effect can be ignored.
[0054] Such as Figure 1As shown, the polar direction of GaN should be the N-face polarity. The spontaneous polarization direction of the right AlGaN layer is upward (N-face polarity), and the spontaneous polarization direction of GaN is also upward (N-face polarity), forming an AlGaN / GaN heterojunction (N-face growth). Since the AlGaN has a higher Al composition, its spontaneous polarization intensity is greater than that of GaN, resulting in the appearance of negative polarization charges (uncompensated polarization charge difference) at the AlGaN / GaN interface. Due to the principle of electrical neutrality, the negative polarization charges will attract holes, causing the valence band on the GaN side to bend upward, forming a hole potential well and accumulating 2DHG on the GaN side. On the left side, the stacking direction is different, forming a GaN / AlGaN heterojunction (N-face polarity), which will generate positive polarization charges at the interface, causing the conduction band on the GaN side to bend downward, forming an electron potential well and generating the opposite 2DEG on the GaN side.
[0055] The GaN-based CMOS implemented based on this technology is easier to integrate, without the need to grow additional layer structures, and the high-performance GaN-based CMOS devices and circuits with high mobility, high conductivity, and high switching frequency can be realized by using the 2DHG and 2DEG induced by the polarization effect.
[0056] Based on the same inventive concept, the second aspect of the present invention also provides a method for preparing a nitride CMOS device based on the non-polar m-plane. Please refer jointly to Figure 2 and Figure 3 , Figure 2 is a schematic flow chart of the method for preparing a nitride CMOS device based on the non-polar m-plane provided by the embodiments of the present invention, Figure 3 is a schematic process diagram of the process for preparing a nitride CMOS device based on the non-polar m-plane provided by the embodiments of the present invention. The method for preparing a nitride CMOS device based on the non-polar m-plane provided by the present invention mainly includes the following steps:
[0057] Step 1: Provide a substrate and perform pre-treatment.
[0058] Specifically, first, provide a diamond substrate.
[0059] Then, place the diamond substrate into a container filled with acetone solution, and then place the container into an ultrasonic cleaning tank for cleaning for 10 - 50 min, preferably 30 min.
[0060] Next, take out the cleaned diamond substrate and place it in a drying oven for drying at a temperature of 50 - 90 °C. Among them, the drying temperature is preferably 70 °C.
[0061] After that, soak the dried diamond substrate in a dilute hydrochloric acid solution for 10 - 200 s, preferably 50 s.
[0062] Finally, take out the soaked diamond substrate and put it into a drying oven, and perform drying treatment again at a temperature of 50 - 150 °C, preferably 120 °C.
[0063] Thus, the pretreatment of the substrate is completed.
[0064] Step 2: Epitaxially grow a non-polar m-plane GaN layer on the pretreated substrate.
[0065] Specifically, put the pretreated substrate into the reaction chamber, keep the temperature of the reaction chamber at 900 - 1100 °C, preferably 1050 °C, keep the pressure of the reaction chamber at 10 - 50 Torr, preferably 40 Torr, and simultaneously introduce a nitrogen source with a flow rate of 1500 - 3300 sccm and a gallium source with a flow rate of 10 - 90 sccm, and use the MOCVD process to grow a non-polar m-plane GaN layer with a thickness of 25 μm on the substrate, as shown in Figure (a) of Figure 3 Among them. The flow rate of the nitrogen source is preferably 3000 sccm, and the flow rate of the gallium source is preferably 70 sccm.
[0066] Step 3: Etch the GaN layer to form a groove in the middle of the GaN layer.
[0067] Specifically, keep the temperature of the reaction chamber at 900 - 1100 °C, preferably 1050 °C, keep the pressure of the reaction chamber at 10 - 50 Torr, preferably 40 Torr, and use dry etching technology to etch a groove with a depth of 0.01 - 5 μm on the non-polar m-plane GaN layer, as shown in Figure (b) of Figure 3 Among them.
[0068] Step 4: Epitaxially grow AlGaN layers on the left and right sidewalls of the groove.
[0069] Specifically, keep the temperature of the reaction chamber at 900 - 1100 °C, preferably 1050 °C, keep the pressure of the reaction chamber at 10 - 50 Torr, preferably 40 Torr, and simultaneously introduce a nitrogen source with a flow rate of 1500 - 3300 sccm, a gallium source with a flow rate of 10 - 90 sccm, and an aluminum source with a flow rate of 50 - 200 sccm, and use the MOCVD process to grow AlGaN layers with a width of 3 - 100 nm and an Al component of 0.1 - 1 on the left and right sidewalls of the groove, so as to form a double heterojunction with the GaN layers on the left and right sides, and respectively form 2DEG and 2DHG with high concentration and high mobility on the surface of the heterojunction, as shown in Figure (c) of Figure 3 Among them. The flow rate of the nitrogen source is preferably 3000 sccm, the flow rate of the gallium source is preferably 70 sccm, and the flow rate of the aluminum source is preferably 150 sccm.
[0070] Step 5: Fabricate a drain electrode on the GaN layer at the bottom of the groove.
[0071] Specifically, the Ti / Al / Ni / Au multi-layer metal electrodes are deposited on the GaN layer in the groove by using electron beam evaporation technology, where the thickness of the metal Ti is 30 nm, the thickness of the metal Al is 60 nm, the thickness of the metal Ni is 30 nm, and the thickness of the metal Au is 90 nm; and rapid thermal annealing is performed for 2 min in an N2 atmosphere at a temperature of 950 °C to complete the fabrication of the drain electrode (D), as shown in Figure 3 Figure (d) in
[0072] Step 6: Fabricate the gate electrode and the source electrode on the AlGaN layer, thereby completing the device fabrication.
[0073] Specifically, the Ni / Au double-layer structure is deposited on the AlGaN layers on both sides by using electron beam evaporation technology, where the thickness of the metal Ni is 60 nm and the thickness of the metal Au is 80 nm, and rapid annealing is performed at a temperature of 750 °C for 3 min to obtain the metal gate electrode (G) and the source electrode (S), as shown in Figure 3 Figure (e) in
[0074] Thus, the fabrication of the nitride-based CMOS device based on the non-polar m-plane is completed.
[0075] In the present invention, GaN is etched by using a groove, and AlGaN is deposited on the two sidewalls in the groove, which can enable the 2DEG and 2DHG to appear simultaneously in the GaN layer, serving as the n-type and p-type conductive channels of the CMOS. Compared with the traditional nitride-based CMOS, high mobility and high conductivity can be achieved.
[0076] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention.
[0077] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more unless otherwise specifically defined.
[0078] In the present invention, unless otherwise clearly specified or limited, the first feature being "on" or "under" the second feature may include direct contact between the first and second features, or may include contact between the first and second features not directly but through additional features therebetween. Moreover, the first feature being "above", "over" and "on top of" the second feature includes the first feature being directly above and obliquely above the second feature, or merely indicating that the horizontal height of the first feature is higher than that of the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly below and obliquely below the second feature, or merely indicating that the horizontal height of the first feature is less than that of the second feature.
[0079] In the description of this specification, the description with reference to terms such as "an embodiment", "some embodiments", "example", "specific example", or "some examples", etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.
[0080] The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can still be made, and all should be regarded as belonging to the protection scope of the present invention.
Claims
1. A nitride CMOS device based on non-polar m-plane, characterized in that, Including: A substrate, a non-polar m-plane GaN layer, an AlGaN layer, a drain electrode, a gate electrode, and a source electrode; wherein, The GaN layer is located on the substrate; and a groove is etched in the middle of the GaN layer; The AlGaN layer is disposed on the left and right sidewalls of the groove to form a double heterojunction with the GaN layer; wherein, the AlGaN layer on the left sidewall of the groove forms a GaN / AlGaN heterojunction with the adjacent GaN layer, and generates 2DEG on the GaN side to serve as the n-type conductive channel of the device; the AlGaN layer on the right sidewall of the groove forms an AlGaN / GaN heterojunction with the adjacent GaN layer, and generates 2DHG on the GaN side to serve as the p-type conductive channel of the device; The drain electrode is disposed on the GaN layer at the bottom of the groove; The gate electrode and the source electrode are disposed on the AlGaN layer.
2. The nitride CMOS device based on the non-polar m-plane according to claim 1, wherein The substrate is made of diamond material.
3. The nitride CMOS device based on the non-polar m-plane according to claim 1, wherein The thickness of the GaN layer is 0.1 - 50 μm, and the etching depth of the groove is 0.01 - 5 μm.
4. The nitride CMOS device based on the non-polar m-plane according to claim 1, characterized in that, The width of the AlGaN layer is 3 - 100 nm; and the Al component in AlGaN is 0.1 - 1.
5. The nitride CMOS device based on the non-polar m-plane according to claim 1, wherein The thickness of the drain electrode is 0.01 - 1 μm, and the material is a multi-layer metal of Ti / Al / Ni / Au; the thickness of the source electrode and the gate electrode is 0.01 - 1 μm, the width is 1 - 250 nm, and the material is a double-layer metal of Ni / Au.
6. A method for fabricating a nitride CMOS device based on a non-polar m-plane, characterized in that, Including: Providing a substrate and performing pre-treatment; Epitaxially growing a non-polar m-plane GaN layer on the pre-treated substrate; Etching the GaN layer to form a groove in the middle of the GaN layer; Epitaxially growing an AlGaN layer on the left and right sidewalls of the groove; Fabricating a drain electrode on the GaN layer at the bottom of the groove; Fabricating a gate electrode and a source electrode on the AlGaN layer, thereby completing the device preparation.
7. The manufacturing method of a nitride CMOS device based on a non-polar m-plane according to claim 6, characterized in that, Providing a substrate and performing pre-treatment, including: Providing a diamond substrate; Placing the diamond substrate into a container filled with acetone solution, and then placing the container into an ultrasonic cleaning tank for cleaning for 10 - 50 min; Taking out the cleaned diamond substrate and placing it into a drying oven for drying treatment at a temperature of 50 - 90 °C; Placing the dried diamond substrate into a dilute hydrochloric acid solution for soaking for 10 - 200 s; Taking out the soaked diamond substrate and placing it into a drying oven for drying treatment again at a temperature of 50 - 150 °C.
8. The manufacturing method of a nitride CMOS device based on a non-polar m-plane according to claim 6, characterized in that, Epitaxially growing a non-polar m-plane GaN layer on the pre-treated substrate, including: Placing the pre-treated substrate into a reaction chamber, maintaining the temperature of the reaction chamber at 900 - 1100 °C, maintaining the pressure of the reaction chamber at 10 - 50 Torr, and simultaneously introducing a nitrogen source with a flow rate of 1500 - 3300 sccm and a gallium source with a flow rate of 10 - 90 sccm, and growing a non-polar m-plane GaN layer with a thickness of 0.1 - 50 μm on the substrate by using the MOCVD process.
9. The manufacturing method of the nitride CMOS device based on the non-polar m-plane according to claim 6, characterized in that Etching the GaN layer to form a groove in the middle of the GaN layer, including: Maintain the temperature of the reaction chamber at 900 - 1100 °C, maintain the pressure of the reaction chamber at 10 - 50 Torr, and use dry etching technology to etch a groove with a depth of 0.01 - 5 μm on the non-polar m-plane GaN layer.
10. The manufacturing method of the nitride CMOS device based on non-polar m-plane according to claim 6, characterized in that Epitaxially grow an AlGaN layer on the left and right sidewalls of the groove, including: Maintain the temperature of the reaction chamber at 900 - 1100 °C, maintain the pressure of the reaction chamber at 10 - 50 Torr, and simultaneously introduce a nitrogen source with a flow rate of 1500 - 3300 sccm, a gallium source with a flow rate of 10 - 90 sccm, and an aluminum source with a flow rate of 50 - 200 sccm. Use the MOCVD process to grow an AlGaN layer with a width of 3 - 100 nm and an Al composition of 0.1 - 1 on the sidewalls on both sides of the groove to form a double heterojunction with the GaN layers on the left and right, and respectively form a 2DEG and a 2DHG with high concentration and high mobility on the surface of the heterojunction.