Display device and forming method thereof

Abstract

The embodiment of the invention relates to a display device and a manufacturing method thereof. The display device may include: a substrate including a first region and a second region; a buffer layer on the substrate; a first semiconductor pattern disposed in the first region and on the buffer layer; a second semiconductor pattern disposed in the second region and on the buffer layer; a first gate insulating layer disposed on the first semiconductor pattern in a portion of the first region and covering at least a portion of an upper surface of the first semiconductor pattern; and a second gate insulating layer disposed on the first gate insulating layer, the second semiconductor pattern, and the buffer layer. According to the embodiments of the present disclosure, it is possible to prevent interface contamination that may occur when setting a driving circuit for driving a display panel.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority of Korean Patent Application No. 10 - 2024 - 0015199, filed on January 31, 2024, which is incorporated herein by reference in its entirety for all purposes as if fully set forth herein. Technical field

[0003] The present disclosure relates to a display device and a method of manufacturing the same. Background art

[0004] With the development of the information society, display devices for displaying images are required to be lighter and thinner. A display device may include, in addition to a display panel for implementing an image, a driving circuit for driving the display panel located around the display panel. As the display device becomes lighter and thinner, there may be a case where the driving circuit is disposed within a part of the display panel.

[0005] However, during the process of arranging the driving circuit for driving the display panel within the display panel, contamination may occur at the interface between components at the position where the driving circuit is placed within the panel, which may lead to a decrease in the reliability of the display device.

[0006] In addition, since various buffer layers are also provided when the driving circuit is placed in the display panel, the current characteristics of the device for providing an image display function may deteriorate, which may cause a brightness defect in the display device and may limit the process freedom of other components in the display panel. Summary of the invention

[0007] Embodiments of the present disclosure may provide a display device and a method of manufacturing the same, which can prevent interface contamination that may occur when a driving circuit for driving a display panel is provided.

[0008] Embodiments of the present disclosure may provide a display device and a method of manufacturing the same, which can prevent a brightness defect of the display device when a driving circuit for driving a display panel is provided.

[0009] Embodiments of the present disclosure may provide a display device and a method of manufacturing the same, which can ensure the process freedom of other components in the display panel when a driving circuit for driving a display panel is provided.

[0010] Embodiments of the present disclosure may provide a display device, including: a substrate including a first region and a second region; a buffer layer on the substrate; a first semiconductor pattern disposed in the first region and on the buffer layer; a second semiconductor pattern disposed in the second region and on the buffer layer; a first gate insulating layer on the first semiconductor pattern in a part of the first region and covering at least a part of an upper surface of the first semiconductor pattern; and a second gate insulating layer on the first gate insulating layer, the second semiconductor pattern, and the buffer layer.

[0011] Embodiments of the present disclosure may provide a display device, including: a substrate including a first region and a second region; a first transistor disposed in the first region and including a first semiconductor pattern, a first gate electrode, a first source electrode, and a first drain electrode; a second transistor disposed in the second region and including a second semiconductor pattern, a second gate electrode, a second source electrode, and a second drain electrode; a first gate insulating layer between the first gate electrode and the first semiconductor pattern in a partial region of the first region; and a second gate insulating layer between the first gate insulating layer and the first gate electrode, wherein the first gate insulating layer overlaps with the first semiconductor pattern, and the second gate insulating layer is disposed between the second gate electrode and the second semiconductor pattern.

[0012] Embodiments of the present disclosure may provide a method of manufacturing a display device, including: forming a first semiconductor pattern in a first region on a substrate, and forming a first gate insulating layer on at least a part of the first semiconductor pattern; forming a second semiconductor pattern in a second region on the substrate; and forming a second gate insulating layer on the first gate insulating layer and the second semiconductor pattern.

[0013] According to embodiments of the present disclosure, a display device and a method of manufacturing the same can be provided, which can prevent interface contamination that may occur when a driving circuit for driving a display panel is provided.

[0014] According to embodiments of the present disclosure, a display device and a method of manufacturing the same can be provided, which can prevent brightness defects of the display device when a driving circuit for driving a display panel is provided.

[0015] According to embodiments of the present disclosure, a display device and a method of manufacturing the same can be provided, which can ensure a process freedom degree of other components in the display panel when a driving circuit for driving a display panel is provided.

[0016] According to embodiments of the present disclosure, a display device and a method of manufacturing the same can be provided, which can achieve process optimization by preventing surface contamination when a driving circuit for driving a display panel is provided and eliminating a need for an additional process for removing surface contamination. Description of the Drawings

[0017] Figure 1 Shows the configuration of a display device according to an embodiment of the present disclosure.

[0018] Figure 2 Shows a sub-pixel and a peripheral circuit of a display device according to an embodiment of the present disclosure.

[0019] Figure 3 Is a circuit diagram of a sub-pixel of a display device according to an embodiment of the present disclosure.

[0020] Figure 4 Shows an example of a cross-sectional structure of a display device according to an embodiment of the present disclosure.

[0021] Figure 5 Is Figure 4 An enlarged view of part A of

[0022] Figure 6 Shows another example of a cross-sectional structure of a display device according to an embodiment of the present disclosure.

[0023] Figure 7A And Figure 7B Is Figure 6 An enlarged view of part B of

[0024] Figure 8 And Figure 9 Show Figure 7A Another example of the structure shown in

[0025] Figure 10A And Figure 10B Shows an example of a method of manufacturing a display device according to an embodiment of the present disclosure. Detailed Description

[0026] In the following description of examples or embodiments of the present disclosure, reference will be made to the accompanying drawings, in which specific examples or embodiments that can be implemented are shown by way of example, and the same reference numerals and symbols may be used in the drawings to represent the same or similar components, even if they are shown in different drawings from each other. Further, in the following description of examples or embodiments of the present disclosure, when it is determined that the description may make the subject matter in some embodiments of the present disclosure less clear, the detailed description of well-known functions and components incorporated herein will be omitted. Terms such as "including", "having", "containing", "constituting", "consisting of", and "formed of" used herein are generally intended to allow the addition of other components, unless these terms are used together with the term "only". As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0027] In this disclosure, terms such as "first", "second", "A", "B", "(A)", or "(B)" may be used to describe elements of the present disclosure. Each of these terms is not used to define the nature, order, sequence, quantity, etc. of the element, but is only used to distinguish the corresponding element from other elements.

[0028] When it is mentioned that a first element is "connected or coupled to" a second element, "in contact with or overlapping" the second element, etc., it should be understood that the first element can not only be "directly connected or coupled to" the second element or "in direct contact with or overlapping" the second element, but also a third element can be "inserted" between the first and second elements, or the first and second elements can be "connected or coupled", "in contact with or overlapping", etc. with each other through a fourth element. Here, the second element may include at least one of two or more elements that are "connected or coupled", "in contact with or overlapping", etc. with each other.

[0029] When using time - relative terms such as "after", "subsequently", "next", "before", etc. to describe a process or operation of an element or configuration, or a process or step in an operation, process, or manufacturing method, these terms can be used to describe a non - continuous or non - sequential process or operation, unless the terms "directly" or "immediately" are used together.

[0030] In addition, when referring to any dimension, relative size, etc., even if the relevant description is not specified, the numerical value or corresponding information (e.g., level, range, etc.) of the element or feature should be considered to include the tolerance or error range that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.). In addition, the term "may" fully encompasses all meanings of the term "can".

[0031] Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0032] Figure 1 The configuration of a display device according to an embodiment of the present disclosure is shown.

[0033] Reference Figure 1 , the display device 100 may include an image processor 120, a degradation compensation unit 160, a memory 170, a timing controller 130, a data driver 150, and a power supply unit 180. In addition, the display device 100 may include a display panel 110, and the data driver 150 and the gate driver 140 are formed on the display panel 110.

[0034] In addition to the image data provided from the outside, the image processor 120 may also output drive signals for driving various devices. For example, the drive signals output from the image processor 120 may include a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, and a clock signal.

[0035] The degradation compensation unit 160 may calculate a degradation compensation gain value of a sub-pixel SP of the display panel based on a sensed voltage Vsen provided from the data driver 150, may calculate a dimming weight value based on the calculated degradation compensation gain value, may modulate the input image data Idata of each sub-pixel SP in the current frame based on the calculated degradation compensation gain value and the dimming weight value, and may then provide the modulated image data Mdata to the timing controller 130.

[0036] The timing controller 130 may receive the image data modulated from the degradation compensation unit 160 and a driving signal. The timing controller 130 may generate and output a gate timing control signal GDC for controlling the operation timing of the gate driver 140 and a data timing control signal DDC for controlling the operation timing of the data driver 150 based on the driving signal input from the image processor 120.

[0037] In addition, the timing controller 130 may control the operation timings of the gate driver 140 and the data driver 150 to obtain at least one sensed voltage Vsen from each sub-pixel SP to provide to the degradation compensation unit 160.

[0038] The gate driver 140 may output a scan signal to the display panel 110 in response to the gate timing control signal GDC provided from the timing controller 130. The gate driver 140 may output the scan signal through a plurality of gate lines GL1 to GLm. The gate driver 140 may be formed in the form of an integrated circuit (IC), but is not limited thereto. Specifically, the gate driver 140 may be formed in an in-panel gate (GIP) structure formed by directly stacking thin film transistors on a substrate inside the display device 100. The GIP structure may include a plurality of circuits, such as a shift register and a level shifter.

[0039] The data driver 150 may output a data voltage to the display panel 110 in response to the data timing control signal DDC input from the timing control unit 130. The data driver 150 may sample and latch the digital data signal DATA provided from the timing controller 130 and convert it into an analog data voltage based on a gamma voltage.

[0040] The data driver 150 may output the data voltage through a plurality of data lines DL1 to DLn.

[0041] In addition, the data driver 140 may provide the sensed voltage Vsen input from the display panel 110 to the degradation compensation unit 160 through a sensed voltage readout line.

[0042] In this case, the data driver 150 may be mounted on the display panel 110 in the form of an integrated circuit (IC), or may be directly formed on the display panel 110, but is not limited thereto.

[0043] The power supply unit 180 may output and supply a high potential driving voltage EVDD and a low potential driving voltage EVSS to the display panel 110. The high potential driving voltage VDD and the low potential driving voltage EVSS may be supplied to the display panel 110 through power lines. In this case, the voltage output from the power supply unit 180 may be output to the data driver 150 or the gate driver 140, and may be used to drive the data driver 150 or the gate driver 140.

[0044] The display panel 110 may display an image in response to the data voltage and the scan signal provided from the data driver 150 and the gate driver 140 that may be provided in the non-display area NA, and the power supplied from the power supply unit 180.

[0045] The display area AA of the display panel 110 may include a plurality of sub-pixels SP and display an actual image. The sub-pixels SP may include red sub-pixels, green sub-pixels, and blue sub-pixels, or may include white (W) sub-pixels, red (R) sub-pixels, green (G) sub-pixels, and blue (B) sub-pixels. In this case, the W, R, G, and B sub-pixels SP may all be formed to have the same area, but may also be formed to have different areas.

[0046] The memory 170 may store a look-up table of the degradation compensation gain, and may also store the degradation compensation timing information of the organic light emitting devices of the sub-pixels SP. In this case, the degradation compensation timing of the organic light emitting devices may be based on the number of times or the driving time of the organic light emitting display panel.

[0047] Figure 2 The sub-pixels and the peripheral circuits of the display device according to an embodiment of the present disclosure are shown.

[0048] Reference Figure 2 , one sub-pixel SP may be connected to the gate line GL1, the data line DL1, the sense voltage readout line SRL1, and the power line PL1. The arrangement of the sub-pixels SP and the number of transistors and capacitors may be determined according to the circuit configuration.

[0049] Figure 3 Is a circuit diagram of the sub-pixels of the display device according to an embodiment of the present disclosure.

[0050] Reference Figure 3, the display device 100 may include a gate line GL, a data line DL, a power line PL, and a sensing line SL, which intersect each other to define sub-pixels SP. Each sub-pixel SP may include a driving thin film transistor DT, a light emitting device ED, a storage capacitor Cst, a first switching thin film transistor ST1, and a second switching thin film transistor ST2.

[0051] The light emitting device ED may include an anode electrode connected to a second node N2, a cathode electrode connected to an input terminal of a low potential driving voltage EVSS, and an organic emission layer located between the anode electrode and the cathode electrode.

[0052] The driving thin film transistor DT may control a current Id flowing through the light emitting device ED according to a gate-source voltage Vgs. The driving thin film transistor DT may include a gate electrode connected to a first node N1, a drain electrode connected to the power line PL to provide a high potential driving voltage EVDD, and a source electrode connected to the second node N2.

[0053] The storage capacitor Cst may be connected between the first node N1 and the second node N2.

[0054] When driving the display panel 110, the first switching thin film transistor ST1 may apply a data voltage Vdata charged in the data line DL to the first node N1 in response to a gate signal SCAN to turn on the driving thin film transistor DT. The first switching thin film transistor ST1 may include a gate electrode connected to the gate line GL to input a scan signal SCAN, a drain electrode connected to the data line DL to input a data voltage Vdata, and a source electrode connected to the first node N1.

[0055] The second switching thin film transistor ST2 may switch a current between the second node N2 and a sensing voltage readout line SRL in response to a sensing signal SEN, thereby charging a source voltage of the second node N2 into a sensing capacitor Cx of the sensing voltage readout line SRL. The second switching thin film transistor ST2 may switch a current between the second node N2 and the sensing voltage readout line SRL in response to a sensing signal SEN when driving the display panel 110, thereby resetting the source voltage of the driving thin film transistor DT to an initialization voltage Vpre. In this case, the gate electrode of the second switching thin film transistor ST2 may be connected to the sensing line SL, the drain electrode may be connected to the second node N2, and the source electrode may be connected to the sensing voltage readout line SRL.

[0056] Meanwhile, during Figure 3Among them, an organic light-emitting display device having a 3T1C structure including three thin-film transistors and one storage capacitor has been described as an example. However, the organic light-emitting display device according to the present disclosure is not limited thereto and can be applied to various structures such as 4T1C, 5T1C, 6T1C, 7T1C, and 8T1C.

[0057] Figure 4 An example of a cross-sectional structure of a display device according to an embodiment of the present disclosure is shown.

[0058] Reference Figure 4 , a driving thin-film transistor DT, a first thin-film transistor GT1, and a second thin-film transistor GT2 may be provided on the substrate 400.

[0059] The substrate 400 may be divided into a display area AA where sub-pixels SP are provided and a non-display area NA located outside the display area AA. The driving thin-film transistor DT may be located in the display area AA on the substrate 400, and the first thin-film transistor GT1 and the second thin-film transistor GT2 may be located in the non-display area NA on the substrate 400.

[0060] The first thin-film transistor GT1 and the second thin-film transistor GT2 may be any one of a plurality of thin-film transistors constituting a gate driver. Specifically, they may be provided in a GIP area, which is an area for setting a gate driver, in the non-display area NA.

[0061] Hereinafter, a cross-sectional structure of a display device including the first thin-film transistor GT1, the second thin-film transistor GT2, and the driving thin-film transistor DT will be described.

[0062] A plurality of buffer layers 410 may be provided on the substrate 400. The buffer layer 410 may be a single layer or multiple layers. If the buffer layer 410 is multiple layers, the buffer layer 410 may include a first buffer layer 411 and a second buffer layer 412 provided on the first buffer layer 411.

[0063] The buffer layer 410 may function to block various types of defects leaking from the substrate 400 and may be made of silicon nitride or silicon oxide.

[0064] A capacitor may be provided in the area where the buffer layer 410 is provided. The capacitor may include a first capacitor electrode 413 and a second capacitor electrode 414.

[0065] The first buffer layer 411 may be disposed between the first capacitor electrode 413 and the second capacitor electrode 414. The first capacitor electrode 413 and the second capacitor electrode 414 may be formed as a single layer or multiple layers of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), tungsten (W), or an alloy thereof, but are not limited thereto.

[0066] The barrier layer 415 may be disposed on the first buffer layer 411. The barrier layer 415 may be disposed between the first buffer layer 411 and the second buffer layer 412, and may be disposed under the second semiconductor pattern 441.

[0067] The barrier layer 415 may be formed as a single layer or multiple layers of one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), tungsten (W), or an alloy thereof. The barrier layer 415 may prevent the semiconductor pattern from malfunctioning when light incident from outside the display device irradiates the semiconductor pattern.

[0068] The above-mentioned first capacitor electrode 413 may serve the same function as the barrier layer 415.

[0069] The plurality of gate insulating layers 420 and the first semiconductor pattern 431 of the first thin film transistor GT1 may be disposed on the buffer layer 410.

[0070] The plurality of gate insulating layers 420 may include a first gate insulating layer 421 and a second gate insulating layer 422 disposed on the first gate insulating layer 421.

[0071] The first gate insulating layer 421 may be used to insulate the first semiconductor pattern 431 from the first gate electrode 434, and may also be used to insulate the first semiconductor pattern 431 from the second semiconductor pattern 441.

[0072] The first gate insulating layer 421 or the second gate insulating layer 422 may be formed of an insulating inorganic material such as silicon nitride or silicon oxide. In addition, the first gate insulating layer 421 may contain some fluorine F.

[0073] The first semiconductor pattern 431 may be made of an oxide and may have a high mobility. For example, the first semiconductor pattern 431 may be a bilayer or trilayer containing indium zinc oxide (IZO). If the first semiconductor pattern 431 is a bilayer, it may be (F)IZO / IGZO, and if it is a trilayer, it may be IGZO / (F)IZO / IGZO.

[0074] However, embodiments of the present disclosure are not necessarily limited thereto, and the first semiconductor pattern 431 may be made of amorphous silicon (a-Si) or polycrystalline semiconductor. However, the case where the first semiconductor pattern 431 is made of an oxide is exemplified herein.

[0075] The first semiconductor pattern 431 may include a first channel region where a channel is formed when the first thin film transistor GT1 is driven. The first semiconductor pattern 431 may include a first source region and a first drain region, and the first source region and the first drain region are made conductive through a doping process on both sides of the first channel region. The first source region may refer to the portion of the first semiconductor pattern 431 connected to the first source electrode 432, and the first drain region may refer to the portion of the first semiconductor pattern 431 connected to the first drain electrode 433.

[0076] The semiconductor pattern of the second thin film transistor GT2 and the second semiconductor pattern 441 of the driving thin film transistor DT may be disposed on the first gate insulating layer 421.

[0077] The second semiconductor pattern 441 may be made of an oxide and may have a low mobility. As an example, the second semiconductor pattern 441 may include indium gallium zinc oxide (IGZO).

[0078] However, it is not necessarily limited thereto, and the second semiconductor pattern 441 may be made of amorphous silicon (a-Si) or polycrystalline semiconductor. However, the case where the second semiconductor pattern 441 is made of an oxide is exemplified.

[0079] The second semiconductor pattern 441 may include a second channel region where a channel is formed when the driving thin film transistor DT is driven. The second semiconductor pattern 441 may include a second source region and a second drain region, and the second source region and the second drain region are made conductive through a doping process on both sides of the second channel region. The second source region may refer to the portion of the second semiconductor pattern 441 connected to the second source electrode 442, and the second drain region may refer to the portion of the second semiconductor pattern 441 connected to the second drain electrode 443.

[0080] The second gate insulating layer 422 may be disposed on the second semiconductor pattern 441.

[0081] An interlayer insulating layer 450, the first gate electrode 434 of the first thin film transistor GT1, the gate electrode of the second thin film transistor GT2, and the second gate electrode 444 of the driving thin film transistor DT may be disposed on the second gate insulating layer 422.

[0082] The interlayer insulating layer 450 may be formed of an insulating material such as silicon nitride or silicon oxide.

[0083] The first gate electrode 434 of the first thin film transistor GT1, the gate electrode of the second thin film transistor GT2, and the second gate electrode 444 of the driving thin film transistor DT may be disposed on the same layer.

[0084] The first gate electrode 434 of the first thin film transistor GT1, the gate electrode of the second thin film transistor GT2, and the second gate electrode 444 of the driving thin film transistor DT may be formed as a single layer or multiple layers made of one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), tungsten (W), or an alloy thereof, but is not limited thereto.

[0085] On the interlayer insulating layer 450, a planarization layer 460, the first source electrode 432 and the first drain electrode 433 of the first thin film transistor GT1, the second source electrode 442, the second drain electrode 443, and the gate line electrode 445 of the driving thin film transistor DT may be disposed.

[0086] In addition, the source electrode, the drain electrode, and the first connection electrode 451 of the second thin film transistor GT2 may be disposed on the interlayer insulating layer 450.

[0087] The first source electrode 432 and the first drain electrode 433 of the first thin film transistor GT1 may be electrically connected to the first semiconductor pattern 431 through holes penetrating the interlayer insulating layer 450, the second gate insulating layer 422, and the first gate insulating layer 421.

[0088] The second source electrode 442 and the second drain electrode 443 of the driving thin film transistor DT may be electrically connected to the second semiconductor pattern 441 through holes penetrating the interlayer insulating layer 450 and the second gate insulating layer 422, and may be electrically connected to the blocking layer 415 through holes penetrating the interlayer insulating layer 450, the second gate insulating layer 422, the first gate insulating layer 421, and the second buffer layer 412.

[0089] In addition, the second source electrode 442 may be electrically connected to the second semiconductor pattern 441 through a hole penetrating the interlayer insulating layer 450 and the second gate insulating layer 422.

[0090] The gate line electrode 445 may be electrically connected to the second gate electrode 444 and may be used as a wiring for supplying a gate voltage to the second gate electrode 444.

[0091] The first connection electrode 451 may be electrically connected to the first capacitor electrode 413 through holes penetrating the interlayer insulating layer 450, the second gate insulating layer 422, the first gate insulating layer 421, the second buffer layer 412, and the first buffer layer 411. The first connection electrode 451 may electrically connect the second connection electrode 452 and the first capacitor electrode 413.

[0092] The planarization layer 460 may include a first planarization layer 461 and a second planarization layer 462 disposed on the first planarization layer 461. The planarization layer 461.

[0093] The planarization layer 460 may protect various thin film transistors disposed therebelow and may alleviate or planarize steps caused by various patterns.

[0094] The planarization layer 460 may be formed of at least one organic insulating material, such as BCB (benzocyclobutene), acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, but is not limited thereto.

[0095] The second connection electrode 452 may be disposed between the first planarization layer 461 and the second planarization layer 462.

[0096] The second connection electrode 452 may electrically connect the first connection electrode 451 and the anode electrode 470.

[0097] The first capacitor electrode 413 may be electrically connected to the anode electrode 470 through the first connection electrode 451 and the second connection electrode 452.

[0098] The first source electrode 432, the first drain electrode 433, the second source electrode 442, the second drain electrode 443, the first connection electrode 451, and the second connection electrode 452 may be made of the same material. For example, each electrode may be made of a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti). However, it is not limited thereto.

[0099] The anode electrode 470 may be disposed on the second planarization layer 462.

[0100] In Figure 4 it is shown that the anode electrode 470 is only connected to the first capacitor electrode 413 in the non-display area NA, but the anode electrode 470 may be electrically connected to the source electrode 442 of the driving thin film transistor DT in the display area AA.

[0101] The bank layer 480 may be disposed on the anode electrode 470 and the second planarization layer 462. The bank layer 480 may further include spacers.

[0102] The bank layer 480 may have an opening area on the anode electrode 470.

[0103] Figure 5 is Figure 4 an enlarged view of part A of.

[0104] Reference Figure 5 As described above, the display device may include a plurality of gate insulating layers 420.

[0105] Specifically, among the plurality of gate insulating layers 420, the first gate insulating layer 421 may be disposed on the first semiconductor pattern 431 and may be disposed in the entire region including the display area AA and the non-display area NA. In addition, the first gate insulating layer 421 may be located between the first semiconductor pattern 431 and the second semiconductor pattern 441.

[0106] In this case, as Figure 5 shown, in order to dispose the first gate insulating layer 421 on the first semiconductor pattern 431, it is necessary to first form the first semiconductor pattern 431 on the buffer layer 410 and then deposit the first gate insulating layer 421. That is, it is necessary to first perform the process of forming the first semiconductor pattern 431.

[0107] The process of forming the first semiconductor pattern 431 may include depositing an oxide layer (e.g., (F)IZO / IGZO or IGZO / (F)IZO / IGZO) on the entire buffer layer 410, and then applying a photoresist (PR) on the oxide layer and patterning the oxide layer by exposure and etching.

[0108] However, in the process of patterning the oxide layer, photoresist residues may remain on the upper portion of the oxide layer, which may cause contamination of the upper interface of the oxide layer. In addition, since oxygen is removed from the upper interface of the oxide layer, an oxygen compensation process is required. However, due to the oxygen compensation process, the characteristics of the transistor may deteriorate.

[0109] In addition, in the case where the first gate insulating layer 421 is located between the first semiconductor pattern 431 and the second semiconductor pattern 441, since the first gate insulating layer 421 contains a large amount of oxygen, a large number of traps may appear at the interface of the second semiconductor pattern 441. As a result, the second semiconductor pattern 441 may deteriorate, which may cause a problem that the current characteristics of the driving thin film transistor DT may deteriorate.

[0110] In addition, since the second gate insulating layer 422 is disposed on the first gate insulating layer 421 in all regions on the substrate, when forming the second gate insulating layer 422, the forming conditions may be restricted so as not to affect the insulating characteristics of the first gate insulating layer 421.

[0111] A solution to the above problems will be described below with reference to the accompanying drawings.

[0112] Figure 6 Another example of the cross-sectional structure of a display device according to an embodiment of the present disclosure is shown. Figure 7A and Figure 7B is Figure 6 an enlarged view of part B of

[0113] Figure 6 , Figure 7A and Figure 7B The cross-sectional structure of the display device shown in Figure 4 and Figure 5 is the same as the cross-sectional structure of the display device described in

[0114] Reference Figure 6 and Figure 7A , the first gate insulating layer 421 may be disposed in a part of the non-display area NA.

[0115] Specifically, as Figure 6 shown, the first gate insulating layer 421 may be disposed on the upper surface US of the first semiconductor pattern 431 included in the GIP area of the non-display area NA.

[0116] In an embodiment, the first gate insulating layer 421 may be formed in three layers, including a first layer 421a, a second layer 421b disposed on the first layer 421a, and a third layer 421c disposed on the second layer 421b.

[0117] The first layer 421a and the third layer 421c of the first gate insulating layer 421 may include SiOx, and the second layer 421b may include SiNx:F or SiOx:F.

[0118] The width W1 of each of the layers 421a, 421b, 421c of the first gate insulating layer 421 may be equal to or greater than the width W2 of the upper surface US of the first semiconductor pattern 431.

[0119] Since the second layer 421b of the first gate insulating layer 421 includes SiN:F or SiO:F without hydrogen, the first semiconductor pattern 431 can be partially prevented from becoming conductive by hydrogen.

[0120] In Figure 7A , the case where the first gate insulating layer 421 is three layers is shown, but the embodiments of the present disclosure are not necessarily limited thereto, and the first gate insulating layer 421 may be a single layer or a double layer.

[0121] If the first gate insulating layer 421 is a single layer, the first gate insulating layer 421 may include SiOx, SiN:F or SiO:F.

[0122] If the first gate insulating layer 421 is a double layer, at least one of the double layers may include SiN:F or SiO:F. Figure 6 ,Figure 7A and Figure 7B The first gate insulating layer 421 shown in Figure 7B can be formed by depositing it over the entire surface of the first semiconductor pattern 431, and then applying a photoresist, performing exposure, and etching. In this case, the process of forming the first gate insulating layer 421 and the process of forming the first semiconductor pattern 431 can be performed together.

[0123] A detailed description of the process of forming the first gate insulating layer 421 on the upper surface US of the first semiconductor pattern 431 and the process of forming the first semiconductor pattern 431 will be described later with reference to Figure 10A and Figure 10B . Figure 10A and Figure 10B Figure 10B

[0124] When the first gate insulating layer 421 is formed to be disposed on the upper surface US of the first semiconductor pattern 431, the first gate insulating layer 421 may not be disposed in the display area AA. That is, the first gate insulating layer 421 may not be disposed on the second semiconductor pattern 441 of the driving thin film transistor DT.

[0125] Although Figure 6 shows a structure in which the first gate insulating layer 421 is formed only on the first semiconductor pattern 431 of the first thin film transistor GT1, the embodiment is not necessarily limited thereto, and the first gate insulating layer 421 may also be disposed only on the semiconductor pattern of the second thin film transistor GT2. However, for the sake of convenience of explanation, hereinafter, a structure in which the first gate insulating layer 421 is formed only on the first semiconductor pattern 431 of the first thin film transistor GT1 will be described as an example.

[0126] Since the first gate insulating layer 421 is disposed only in the region on the first semiconductor pattern 431 of the first thin film transistor GT1 located in the GIP region, the semiconductor pattern of the second thin film transistor GT2 and the second semiconductor pattern 441 of the driving thin film transistor DT can be disposed on the buffer layer 410.

[0127] That is, the first semiconductor pattern 431 of the first thin film transistor GT1, the semiconductor pattern of the second thin film transistor GT2, and the second semiconductor pattern 441 of the driving thin film transistor DT can be disposed on the same layer.

[0128] The second gate insulating layer 422 can be disposed on the first gate insulating layer 421, the semiconductor pattern of the second thin film transistor GT2, and the second semiconductor pattern 441 of the driving thin film transistor DT.

[0129] Referring to Figure 6 and Figure 7A , the second gate insulating layer 422 can be formed as a single layer. Figure 6 and Figure 7A Figure 7A

[0130] When the second gate insulating layer 422 is a single layer, the second gate insulating layer 422 may include SiOx, SiNx:F, or SiOx:F. If the second gate insulating layer 422 includes SiN:F or SiO:F without hydrogen, it is possible to partially prevent the first semiconductor pattern 431 from becoming conductive due to hydrogen.

[0131] Reference Figure 7B , the second gate insulating layer 422 may be formed as a double layer including a first layer 422a and a second layer 422b disposed on the first layer 422a.

[0132] The first layer 422a of the second gate insulating layer 422 may include SiNx:F or SiOx:F, and the second layer 422b may include SiOx. Alternatively, the first layer 422a of the second gate insulating layer 422 may include SiOx, and the second layer 422b may include SiNx:F or SiOx:F.

[0133] The first layer 422a of the second gate insulating layer 422 may block oxygen flowing out from the second layer 422b from flowing into the second semiconductor pattern 441. As Figure 6 , Figure 7A and Figure 7B shown, when the first gate insulating layer 421 is disposed only on the upper surface US of the first semiconductor pattern 431, the side surface (e.g., the first side surface SS1 or the second side surface SS2) of the first semiconductor pattern 431 may contact the second gate insulating layer 422. In some embodiments, both the first side surface SS1 and the second side surface SS2 of the first semiconductor pattern 431 may contact the second gate insulating layer 422.

[0134] The second gate insulating layer 422 may be formed along the steps of the underlying layer such that the second gate insulating layer 422 may be formed to be higher in the region where the first gate insulating layer 421 is disposed than in the region where the first gate insulating layer 421 is not disposed.

[0135] As Figure 7A and Figure 7B shown, if the thickness of the first gate insulating layer 421 is 'd', the vertical height of the upper surface of the second gate insulating layer 422 disposed on the region where the first gate insulating layer 421 is disposed may be greater by a value of 'd' than the vertical height of the upper surface of the second gate insulating layer 422 disposed on the region where the first gate insulating layer 421 is not disposed.

[0136] The first gate electrode 434 of the first thin film transistor GT1, the gate electrode of the second thin film transistor GT2, and the second gate electrode 444 of the driving thin film transistor DT may be disposed on the second gate insulating layer 422.

[0137] The first gate electrode 434 of the first thin film transistor GT1, the gate electrode of the second thin film transistor GT2, and the second gate electrode 444 of the driving thin film transistor DT may be formed on the same layer. However, since the upper surface of the second gate insulating layer 422 is formed to be higher in the region where the first gate insulating layer 421 is provided, the height of the upper surface of the first gate electrode 434 of the first thin film transistor GT1 may be greater than the height of the upper surfaces of the gate electrode of the second thin film transistor GT2 and the second gate electrode 444 of the driving thin film transistor DT by the thickness of the first gate insulating layer 421.

[0138] That is, the distance from the first semiconductor pattern 431 to the first gate electrode 434 may be greater than the distance from the second semiconductor pattern 441 to the second gate electrode 444 by the thickness of the first gate insulating layer 421.

[0139] The interlayer insulating layer 450 may be provided on the second gate insulating layer 422, the first gate electrode 434, and the second gate electrode 444.

[0140] The thickness of the interlayer insulating layer 450 may be smaller by the thickness of the first gate insulating layer 421 in the region where the first gate insulating layer 421 is provided than in the region where the first gate insulating layer 421 is not provided.

[0141] That is, the height of the upper surface of the interlayer insulating layer 450 may be the same in the region where the first gate insulating layer 421 is provided and in the region where the first gate insulating layer 421 is not provided.

[0142] Another example of the structure in which the first gate insulating layer 421 is provided will be described below.

[0143] Figure 8 and Figure 9 shows Figure 7A another example of the structure shown in

[0144] Figure 8 The cross-sectional structure shown in Figure 7A and Figure 7B is the same as the cross-sectional structure described with reference to Figure 8 except that the first gate insulating layer 421 not only covers the upper surface US of the first semiconductor pattern 431 but also covers the side surfaces SS1, SS2 of the first semiconductor pattern 431. Therefore, redundant explanations will be omitted. That is, the first gate insulating layer 421 shown in

[0145] is shown as a three-layer structure, but is not limited thereto, and may be a single-layer or double-layer structure.

[0145] Referring to Figure 8 the first gate insulating layer 421 may be provided to cover the upper surface US and the side surfaces SS1, SS2 of the first semiconductor pattern 431 of the first thin film transistor GT1.

[0146] The second gate insulating layer 422 may be disposed on the first gate insulating layer 421 and the second semiconductor pattern 441.

[0147] In Figure 8 it is shown as a single layer, but is not limited thereto, and may be a double layer. For example, the second gate insulating layer 422 may include a first layer and a second layer on the first layer, as described above with reference to Figure 7B described.

[0148] Here, the first layer may include SiNx:F or SiOx:F, and the second layer 422b may include SiOx. Alternatively, the first layer 422a of the second gate insulating layer 422 may include SiOx, and the second layer 422b may include SiNx:F or SiOx:F.

[0149] Since the first gate insulating layer 421 is disposed to cover the upper surface and the side surface of the first semiconductor pattern 431, the first semiconductor pattern 431 may not contact the second gate insulating layer 422.

[0150] The first gate insulating layer 421 may be formed by depositing over the entire surface of the first semiconductor pattern 431, and then applying a photoresist, performing exposure, and etching. In this case, the process of forming the first gate insulating layer 421 may be performed after the process of forming the first semiconductor pattern 431.

[0151] A detailed description of the process of forming the first semiconductor pattern 431 and the process of forming the first gate insulating layer 421 to cover the upper surface and the side surface of the first semiconductor pattern 431 will be described later with reference to Figure 10A and Figure 10B described.

[0152] Since Figure 9 the cross-sectional structure shown is the same as the cross-sectional structure described with reference to Figure 8 [[ID=^31]]described, except that the first gate insulating layer 421 is disposed not only on the first semiconductor pattern 431 but also on the second semiconductor pattern 441 of the driving thin film transistor DT, a repetitive description will be omitted. That is, Figure 8 the first gate insulating layer 421 shown is exemplified as a triple layer, but is not limited thereto, and may be a single layer or a double layer. Referring to Figure 9 the first gate insulating layer 421 may be disposed to cover the upper surface USS and the side surfaces (e.g., the third side surface SS3, the fourth side surface SS4) of the second semiconductor pattern 441 of the driving thin film transistor DT provided in the display area AA.

[0153] The second gate insulating layer 422 may be disposed on the first gate insulating layer 421 on the first semiconductor pattern 431 and on the first gate insulating layer 421 on the second semiconductor pattern 441.

[0154] In Figure 9 , the second gate insulating layer 422 is shown as a single layer, but is not limited thereto and may be a double layer. As referred to above with reference to Figure 7B the second gate insulating layer 422 may include a first layer and a second layer on the first layer.

[0155] Here, the first layer may include SiNx:F or SiOx:F, and the second layer 422b may include SiOx. Alternatively, the first layer 422a of the second gate insulating layer 422 may include SiOx, and the second layer 422b may include SiNx:F or SiOx:F.

[0156] Since the first gate insulating layer 421 is disposed to cover the upper surface USS and the side surfaces SS3, SS4 of the second semiconductor pattern 441, the second semiconductor pattern 441 may not contact the second gate insulating layer 422.

[0157] Figure 9 A structure is shown in which the first gate insulating layer 421 covers the upper surface US and the side surfaces SS1, SS2 of the first semiconductor pattern 431 and the upper surface USS and the side surfaces SS3, SS4 of the second semiconductor pattern 441, but is not necessarily limited thereto. The first gate insulating layer 421 may only cover the upper surface US of the first semiconductor pattern 431 and the upper surface USS of the second semiconductor pattern 441.

[0158] In this case, the second gate insulating layer 422 may contact the side surface of the first semiconductor pattern 431 and the side surface of the second semiconductor pattern 441. The second gate insulating layer 422 is shown as a single layer, but may also be a double layer, and at least one layer may include SiNx:F or SiOx:F.

[0159] The first gate insulating layer 421 formed on the second semiconductor pattern 431 may be a layer formed in the same manner as the first gate insulating layer 421 formed on the first semiconductor pattern 431. In this case, the process of forming the first gate insulating layer 421 may be performed after the process of forming the second semiconductor pattern 441.

[0160] The first gate insulating layer 421 disposed on the second semiconductor pattern 441 may have the same thickness as the first gate insulating layer 421 disposed on the first semiconductor pattern 441, but is not limited thereto.

[0161] If the first gate insulating layer 421 disposed on the second semiconductor pattern 441 has the same thickness as the first gate insulating layer 421 disposed on the first semiconductor pattern 441, the height of the upper surface of the second gate insulating layer 422 may be the same in the region where the first semiconductor pattern 431 is disposed and in the region where the second semiconductor pattern 441 is disposed.

[0162] Accordingly, the height of the upper surface of the first gate electrode 434 of the first thin film transistor GT1 and the height of the upper surface of the second gate electrode 444 of the driving thin film transistor DT may be the same.

[0163] Hereinafter, a method of manufacturing a display device will be described with reference to Figures 6 to 9 the method of manufacturing a display device described above.

[0164] Figure 10A and Figure 10B FIGS. illustrate examples of a method of manufacturing a display device according to an embodiment of the present disclosure.

[0165] With reference to Figure 10A , a buffer layer 410 may be formed on a substrate.

[0166] With reference to Figure 10A <Case 1> of, a first oxide layer 1000 may be formed on the buffer layer 410.

[0167] The first oxide layer 1000 may be made of the same material as the first semiconductor pattern 431. That is, as described above, the first oxide layer 1000 may be a bilayer or a trilayer including IZO. If the first semiconductor pattern 431 is a bilayer, it may be (F)IZO / IGZO, and if the first semiconductor pattern 431 is a trilayer, it may be IGZO / (F)IZO / IGZO. However, it is not limited thereto.

[0168] The first oxide layer 1000 may be deposited on the buffer layer 410 in a display area AA and a non-display area NA.

[0169] A first insulating material layer 1010 may be formed on the first oxide layer 1000.

[0170] The first insulating material layer 1010 may be formed of an insulating inorganic material (e.g., silicon nitride or silicon oxide). In addition, the first insulating material layer 1010 may contain some fluorine (F).

[0171] A photoresist (not shown) may be applied on the first insulating material layer 1010.

[0172] After applying the photoresist (not shown), exposure may be performed using an etching mask (hereinafter referred to as a first etching mask) to form the first semiconductor pattern 431.

[0173] After exposure and development, an etching process can be performed.

[0174] The etching process can be a process of removing the exposed portions. However, it is not limited thereto, and depending on the type of photoresist, it can be a process of removing the unexposed areas.

[0175] The first insulating material layer 1010 and the first oxide layer 1000 can be etched together. Specifically, the etching can be performed in the order of first removing the first insulating material layer 1010 and then removing the first oxide layer 1000.

[0176] The first insulating material layer 1010 can be etched using a dry etching process, and the first oxide layer 1000 can be etched using a wet etching process. However, it is not necessarily limited thereto.

[0177] Removing a portion of the first insulating material layer 1010 through the etching process can form the first gate insulating layer 421. Here, the first gate insulating layer 421 can be a three-layer including a first layer 421a, a second layer 421b, and a third layer 421c, but is not limited thereto.

[0178] Reference Figure 10A to <Case 1>, the first gate insulating layer 421 can be located on the upper surface of the first semiconductor pattern 431 in a partial area within the non-display area NA.

[0179] After forming the first gate insulating layer 421, the first oxide layer 1000 can be removed through an etching process to form the first semiconductor pattern 431.

[0180] The first semiconductor pattern 431 can have a greater width in the horizontal direction than the first gate insulating layer 421, but is not necessarily limited thereto.

[0181] As described above, the first gate insulating layer 421 and the first semiconductor pattern 431 can be formed using a first etching mask (i.e., one mask).

[0182] In addition, since the first semiconductor pattern 431 is etched after forming the first gate insulating layer 421 on the first semiconductor pattern 431, the process of directly applying photoresist on the first oxide layer 1000 and patterning it through exposure and etching can be omitted.

[0183] That is, during the process of patterning the oxide layer, problems such as residues such as photoresist remaining on the top of the oxide layer do not occur.

[0184] Reference Figure 10A to <Case 2> in, the first semiconductor pattern 431 can be formed on the buffer layer 410.

[0185] The first semiconductor pattern 431 may be formed before the formation of the first insulating material layer 1010. Specifically, the first semiconductor pattern 431 may be formed by a process of depositing a first oxide layer over the entire surface as in <Case 1>, then applying a photoresist to the first oxide layer, and performing exposure and etching using a first etching mask.

[0186] The first semiconductor pattern 431 may be formed in the non-display area NA, particularly in the GIP area.

[0187] The first insulating material layer 1010 may be formed over the first semiconductor pattern 431 and the buffer layer 410.

[0188] The first insulating material layer 1010 may be disposed in the entire area including the display area AA and the non-display area NA.

[0189] A photoresist (not shown) may be applied over the first insulating material layer 1010.

[0190] After applying the photoresist (not shown), exposure may be performed using an etching mask (hereinafter referred to as the second etching mask) to form the first gate insulating layer 421.

[0191] After exposure and development, an etching process may be performed.

[0192] Here, the etching process may be a process of removing a part of the first insulating material layer 1010.

[0193] By removing a part of the first insulating material layer 1010 through the etching process, the first gate insulating layer 421 may be formed.

[0194] In the process of forming the first gate insulating layer 421, the area of the portion exposed by the second etching mask, that is, the area of the portion removed through the etching process, may be smaller than the area of the portion exposed by the first etching mask in the process of forming the first gate insulating layer 421 in <Case 1>.

[0195] That is, since the portion of the first insulating material layer 1010 remaining after etching in <Case 2> is larger than that in <Case 1>, the first gate insulating layer 421 in <Case 2> may cover not only the upper surface of the first semiconductor pattern 431 but also its side surface, which is different from the first gate insulating layer 421 in <Case 1>.

[0196] Reference Figure 10B to <Case 1> and <Case 2>, the second semiconductor pattern 441 may be formed over the buffer layer 410 in the display area AA.

[0197] During the process of forming the second semiconductor pattern 441, an etching mask (hereinafter referred to as the third etching mask) can be used to form the second semiconductor pattern 441.

[0198] The second semiconductor pattern 441 can be formed through a process of depositing a second oxide layer (not shown) on the entire surface, applying a photoresist to the second oxide layer, and performing exposure and etching using the third etching mask.

[0199] The second semiconductor pattern 441 can be formed in the display area AA.

[0200] The second insulating material layer 1020 can be formed on the second semiconductor pattern 441, the first gate insulating layer 421, and the buffer layer 410. The second insulating material layer 1020 is shown as a single layer, but is not necessarily limited thereto, and can also be formed as a double layer.

[0201] The second insulating material layer 1020 can be formed in the entire area including the display area AA and the non-display area NA. In this case, since the first gate insulating layer 421 is formed in the non-display area NA, the second insulating material layer 1020 can be formed higher in the area where the first semiconductor pattern 431 is provided.

[0202] The second insulating material layer 1020 can be made of the same material as the first insulating material layer 1010, but is not limited thereto.

[0203] The second insulating material layer 1020 can be used to insulate the semiconductor pattern from the gate electrode of the transistor.

[0204] As described above with reference to Figures 6 to 1 0, if the first gate insulating layer 421 is only provided on the upper surface of the first semiconductor pattern 431 in the non-display area NA, specifically, if the first semiconductor pattern 431 and the first gate insulating layer 421 are co-deposited and then immediately etched, the process of applying a photoresist to the first oxide layer 1000 to form the first semiconductor pattern 431, exposure, and etching can be omitted.

[0205] That is to say, the process of directly applying a photoresist on the first oxide layer 1000 can be omitted, thereby preventing photoresist residues from remaining on the top of the oxide layer and contaminating the interface during the patterning process. In addition, since there is no problem of oxygen separating from the upper interface of the oxide layer, a separate oxygen compensation process may not be required.

[0206] In addition, if the first gate insulating layer 421 is only located in the non-display area NA, the second semiconductor pattern 441 is no longer disposed on the first gate insulating layer 421, which can prevent deterioration of the second semiconductor pattern 441 due to a large amount of oxygen contained in the first gate insulating layer 421, thereby preventing a decrease in the current characteristics of the driving thin film transistor DT and resulting brightness defects of the display device.

[0207] Furthermore, since the first gate insulating layer 421 is only disposed on the first semiconductor pattern 431 in the non-display area NA, that is, since the first gate insulating layer 421 is only disposed in a very local area, the conditions for forming the second gate insulating layer 422 are hardly restricted, thereby increasing the degree of freedom of the process for forming the second gate insulating layer 422.

[0208] In addition, if the first gate insulating layer 421 not only covers the upper surface of the first semiconductor pattern 431 but also covers the side surface of the first semiconductor pattern 431, deterioration of the first semiconductor pattern 431 due to the wet etching process performed when forming the second semiconductor pattern 441 can be prevented, thereby preventing deterioration of the performance of the first thin film transistor GT1.

[0209] The embodiments of the present disclosure described above are briefly described as follows.

[0210] According to an embodiment of the present disclosure, a display device may be provided, including: a substrate including a first region and a second region; a buffer layer on the substrate; a first semiconductor pattern disposed in the first region and on the buffer layer; a second semiconductor pattern disposed in the second region and on the buffer layer; a first gate insulating layer disposed on the first semiconductor pattern in a part of the first region and covering at least a part of the upper surface of the first semiconductor pattern; and a second gate insulating layer disposed on the first gate insulating layer, the second semiconductor pattern, and the buffer layer.

[0211] In the display device according to an embodiment of the present disclosure, the first gate insulating layer may cover the entire upper surface of the first semiconductor pattern.

[0212] In the display device according to an embodiment of the present disclosure, the first gate insulating layer may cover the entire upper surface and the side surface of the first semiconductor pattern.

[0213] In the display device according to an embodiment of the present disclosure, the first semiconductor pattern and the second semiconductor pattern may be disposed on the same layer.

[0214] The display device according to an embodiment of the present disclosure may further include a first gate electrode on the first semiconductor pattern and a second gate electrode on the second semiconductor pattern. The distance between the first gate electrode and the first semiconductor pattern may be greater than the distance between the second gate electrode and the second semiconductor pattern.

[0215] In the display device according to an embodiment of the present disclosure, the first gate insulating layer may be disposed in at least a portion of the region on the second semiconductor pattern.

[0216] The display device according to an embodiment of the present disclosure may further include a first gate electrode on the first semiconductor pattern and a second gate electrode on the second semiconductor pattern. The distance between the first gate electrode and the first semiconductor pattern may be equal to the distance between the second gate electrode and the second semiconductor pattern.

[0217] In the display device according to an embodiment of the present disclosure, the first gate insulating layer may cover the entire upper surface and side surface of the second semiconductor pattern.

[0218] In the display device according to an embodiment of the present disclosure, at least one of the first gate insulating layer or the second gate insulating layer disposed on the second semiconductor pattern may include at least some fluorine.

[0219] In the display device according to an embodiment of the present disclosure, the second gate insulating layer may have the same thickness in the first region and the second region.

[0220] In the display device according to an embodiment of the present disclosure, the first semiconductor pattern may include a high-mobility oxide, and the second semiconductor pattern may include a low-mobility oxide.

[0221] In the display device according to an embodiment of the present disclosure, the first region may be a non-display region, and the second region may be a display region. The first semiconductor pattern and the first gate insulating layer may be located in the region where the gate driving circuit is located in the non-display region.

[0222] In the display device according to an embodiment of the present disclosure, at least one of the first gate insulating layer or the second gate insulating layer may include at least some fluorine.

[0223] According to an embodiment of the present disclosure, a display device may be provided, including: a substrate including a first region and a second region; a first transistor disposed in the first region and including a first semiconductor pattern, a first gate electrode, a first source electrode, and a first drain electrode; a second transistor disposed in the second region and including a second semiconductor pattern, a second gate electrode, a second source electrode, and a second drain electrode; a first gate insulating layer disposed between the first gate electrode and the first semiconductor pattern in a partial region of the first region; and a second gate insulating layer disposed between the first gate insulating layer and the first gate electrode. In this case, the first gate insulating layer may overlap with the first semiconductor pattern, and the second gate insulating layer may be disposed between the second gate electrode and the second semiconductor pattern.

[0224] In the display device according to an embodiment of the present disclosure, the first gate insulating layer may cover the entire upper surface of the first semiconductor pattern.

[0225] In the display device according to an embodiment of the present disclosure, the first gate insulating layer may cover the entire upper surface and side surface of the first semiconductor pattern.

[0226] In the display device according to an embodiment of the present disclosure, the first semiconductor pattern and the second semiconductor pattern may be disposed on the same layer.

[0227] In the display device according to an embodiment of the present disclosure, the distance between the first gate electrode and the first semiconductor pattern may be greater than the distance between the second gate electrode and the second semiconductor pattern.

[0228] In the display device according to an embodiment of the present disclosure, the first gate insulating layer may be disposed in at least a partial region on the second semiconductor pattern.

[0229] In the display device according to an embodiment of the present disclosure, the distance between the first gate electrode and the first semiconductor pattern may be equal to the distance between the second gate electrode and the second semiconductor pattern.

[0230] In the display device according to an embodiment of the present disclosure, the first gate insulating layer may cover the entire upper surface and side surface of the second semiconductor pattern.

[0231] In the display device according to an embodiment of the present disclosure, at least one of the first gate insulating layer or the second gate insulating layer disposed on the second semiconductor pattern may include at least some fluorine.

[0232] According to an embodiment of the present disclosure, a method of manufacturing a display device may be provided, including: forming a first semiconductor pattern in a first region on a substrate, and forming a first gate insulating layer on at least a part of the first semiconductor pattern; forming a second semiconductor pattern in a second region on the substrate; and forming a second gate insulating layer on the first gate insulating layer and the second semiconductor pattern.

[0233] In the method of manufacturing a display device according to an embodiment of the present disclosure, the step of forming a first semiconductor pattern in a first region on a substrate and forming a first gate insulating layer on at least a part of the first semiconductor pattern may include: forming a first oxide layer on the substrate and forming a first insulating material layer on the first oxide layer; and etching the first oxide layer and the first insulating material layer using one etching mask.

[0234] In the method of manufacturing a display device according to an embodiment of the present disclosure, the step of forming a first semiconductor pattern in a first region on a substrate and forming a first gate insulating layer on at least a part of the first semiconductor pattern may include: forming a first oxide layer on the substrate, and then etching the first oxide layer; and forming a first insulating material layer after etching the first oxide layer, and etching the first insulating material layer.

[0235] The above description is provided to enable those skilled in the art to make and use the technical idea of the present disclosure, and is provided in the context of a specific application and its requirements. Those skilled in the art will readily understand various modifications, additions, and substitutions to the embodiments, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present disclosure. The above description and the drawings provide only examples of the technical idea of the present disclosure for illustrative purposes. That is, the disclosed embodiments are intended to illustrate the scope of the technical idea of the present disclosure.

Claims

1. A display device, comprising: A substrate, which includes a first region and a second region; A buffer layer, which is located on the substrate; A first semiconductor pattern, which is disposed in the first region and on the buffer layer; A second semiconductor pattern, which is disposed in the second region and on the buffer layer; A first gate insulating layer, which is located on the first semiconductor pattern in a part of the first region and covers at least a part of the upper surface of the first semiconductor pattern; And A second gate insulating layer, which is located on the first gate insulating layer, the second semiconductor pattern, and the buffer layer.

2. The display device according to claim 1, wherein, The first gate insulating layer completely covers the upper surface of the first semiconductor pattern.

3. The display device according to claim 1, wherein, The first gate insulating layer completely covers the upper surface and the side surface of the first semiconductor pattern.

4. The display device according to claim 1, wherein, The first semiconductor pattern and the second semiconductor pattern are disposed on the same layer.

5. The display device according to claim 1, further comprising: A first gate electrode on the first semiconductor pattern; And A second gate electrode on the second semiconductor pattern, Wherein, the distance between the first gate electrode and the first semiconductor pattern is greater than the distance between the second gate electrode and the second semiconductor pattern.

6. The display device according to claim 1, wherein, The first gate insulating layer is disposed in at least a part of the region on the second semiconductor pattern.

7. The display device according to claim 6, further comprising: A first gate electrode on the first semiconductor pattern; And A second gate electrode on the second semiconductor pattern, Wherein, the distance between the first gate electrode and the first semiconductor pattern is equal to the distance between the second gate electrode and the second semiconductor pattern.

8. The display device according to claim 6, wherein, The first gate insulating layer completely covers the upper surface and the side surface of the second semiconductor pattern.

9. The display device according to claim 6, wherein, At least one of the first gate insulating layer or the second gate insulating layer disposed on the second semiconductor pattern includes at least some fluorine.

10. The display device according to claim 1, wherein, The second gate insulating layer has the same thickness in the first region and the second region.

11. The display device according to claim 1, wherein, The first semiconductor pattern includes a high-mobility oxide, and the second semiconductor pattern includes a low-mobility oxide.

12. The display device according to claim 1, wherein, The first region is a non-display region, and the second region is a display region, Wherein, the first semiconductor pattern and the first gate insulating layer are located in the region where the gate driving circuit is located in the non-display region.

13. The display device according to claim 1, wherein, At least one of the first gate insulating layer or the second gate insulating layer includes at least some fluorine.

14. The display device according to claim 1 or 6, wherein, The first gate insulating layer includes three layers or two layers, and at least one layer includes fluorine.

15. A display device, comprising: A substrate, which includes a first region and a second region; A first transistor, which is disposed in the first region and includes a first semiconductor pattern, a first gate electrode, a first source electrode, and a first drain electrode; A second transistor, which is disposed in the second region and includes a second semiconductor pattern, a second gate electrode, a second source electrode, and a second drain electrode; A first gate insulating layer, which is disposed between the first gate electrode and the first semiconductor pattern in a part of the first region; and A second gate insulating layer is disposed between the first gate insulating layer and the first gate electrode, wherein the first gate insulating layer overlaps with the first semiconductor pattern, and wherein the second gate insulating layer is disposed between the second gate electrode and the second semiconductor pattern.

16. The display device according to claim 15, wherein, The first gate insulating layer completely covers the upper surface of the first semiconductor pattern.

17. The display device according to claim 15, wherein, The first gate insulating layer completely covers the upper surface and the side surface of the first semiconductor pattern.

18. The display device according to claim 15, wherein, The first semiconductor pattern and the second semiconductor pattern are disposed on the same layer.

19. The display device according to claim 15, wherein, The distance between the first gate electrode and the first semiconductor pattern is greater than the distance between the second gate electrode and the second semiconductor pattern.

20. The display device according to claim 15, wherein, The first gate insulating layer is disposed in at least a partial region on the second semiconductor pattern.

21. The display device according to claim 20, wherein, The distance between the first gate electrode and the first semiconductor pattern is equal to the distance between the second gate electrode and the second semiconductor pattern.

22. The display device according to claim 20, wherein, The first gate insulating layer completely covers the upper surface and the side surface of the second semiconductor pattern.

23. The display device according to claim 20, wherein, At least one of the first gate insulating layer or the second gate insulating layer disposed on the second semiconductor pattern includes at least some fluorine.

24. A method of manufacturing a display device, comprising: forming a first semiconductor pattern in a first region on a substrate and forming a first gate insulating layer on at least a part of the first semiconductor pattern; forming a second semiconductor pattern in a second region on the substrate; and forming a second gate insulating layer on the first gate insulating layer and the second semiconductor pattern.

25. The method according to claim 24, wherein Forming a first semiconductor pattern in a first region on a substrate and forming a first gate insulating layer on at least a part of the first semiconductor pattern includes: forming a first oxide layer on the substrate and forming a first insulating material layer on the first oxide layer; and etching both the first oxide layer and the first insulating material layer using an etching mask.

26. The method according to claim 24, wherein, Forming a first semiconductor pattern in a first region on a substrate and forming a first gate insulating layer on at least a part of the first semiconductor pattern includes: forming a first oxide layer on the substrate; etching the first oxide layer; forming a first insulating material layer after etching the first oxide layer; and etching the first insulating material layer.

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