Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. The display panel is provided with a first source and drain electrode layer and a second source and drain electrode layer; a first clock signal line, a second clock signal line, a third clock signal line, a first high-potential signal line, a second high-potential signal line, a first low-potential signal line, a second low-potential signal line, a third low-potential signal line, a first reset control line and a second reset control line are connected in sequence. And at least one of the second reset control line and the low-frequency signal line is arranged on the second source-drain electrode layer, so that the number of wires in the first source-drain electrode layer can be reduced, the transverse space occupied by the first source-drain electrode layer is reduced, the space occupied by the gate drive circuit is reduced, and the frame of the display panel is reduced.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and in particular, to a display panel and a display device. Background Art

[0002] OLED (Organic Light-Emitting Diode) display devices are widely used in various fields because of their light weight, wide viewing angle, low power consumption, fast response speed, low temperature resistance, high luminous efficiency, and the ability to fabricate curved flexible display screens. In order to reduce the number of driving chips, reduce the bezel, and lower costs, a gate driving circuit is used to replace the gate driving chip to drive the pixel circuit. Specifically, the gate driving circuit includes a thin-film transistor setting area and a signal trace area. Thin-film transistors are provided in the thin-film transistor setting area, and signal traces are provided in the signal trace area. The signal traces are connected to the thin-film transistors through connection lines. However, in actual use, it is found that the gate driving circuit occupies a large space. However, as the resolution of the OLED display device increases, the number of stages of the gate driving circuit increases, resulting in a decrease in the longitudinal space that the gate driving circuit can occupy and an increase in the lateral space occupied by the gate driving circuit, resulting in a large bezel of the display panel.

[0003] Therefore, there is a technical problem in the current display device that the lateral space occupied by the thin-film transistor setting area and the signal trace area in the gate driving circuit is large, resulting in a large bezel of the display device. Summary of the Invention

[0004] Embodiments of the present application provide a display panel and a display device to solve the technical problem that the lateral space occupied by the thin-film transistor setting area and the signal trace area in the gate driving circuit of the current display device is large, resulting in a large bezel of the display device.

[0005] To achieve the above object, according to the first aspect of the present application, a display panel is provided, which includes:

[0006] Multiple rows of pixels, where the pixels include light-emitting devices and pixel driving circuits;

[0007] The multi-stage gate driving circuit is electrically connected to the corresponding pixel driving circuit respectively. Each stage of the gate driving circuit includes a first type of gate circuit, a second type of gate circuit, and a third type of gate circuit arranged along a first direction. The first type of gate circuit is electrically connected to at least a first clock signal line, a second clock signal line, a first high potential signal line, a first low potential signal line, a second low potential signal line, a first reset control line, and a low-frequency signal line. The second type of gate circuit is electrically connected to at least the first high potential signal line, the second low potential signal line, a third clock signal line of the display panel, and a second reset control line of the display panel. The third type of gate circuit is electrically connected to at least the first high potential signal line, a second high potential signal line, the second low potential signal line, and a third low potential signal line;

[0008] Wherein, the display panel further includes a substrate, an active layer, a first gate layer, a first source-drain layer, and a second source-drain layer arranged in sequence. At least one of the first clock signal line, the second clock signal line, the third clock signal line, the first high potential signal line, the second high potential signal line, the first low potential signal line, the second low potential signal line, the third low potential signal line, the first reset control line, the second reset control line, and the low-frequency signal line is arranged on the second source-drain layer.

[0009] According to a second aspect of the present application, a display device is provided. The display device includes the display panel as described in any one of the above embodiments.

[0010] An embodiment of the present application provides a display panel and a display device. By providing a first source-drain layer and a second source-drain layer, at least one of the first clock signal line, the second clock signal line, the third clock signal line, the first high potential signal line, the second high potential signal line, the first low potential signal line, the second low potential signal line, the third low potential signal line, the first reset control line, the second reset control line, and the low-frequency signal line is arranged on the second source-drain layer, which can reduce the number of traces in the first source-drain layer, thereby reducing the lateral space occupied by the first source-drain layer, further reducing the space occupied by the gate driving circuit, and reducing the border of the display panel. Description of the Drawings

[0011] Figure 1 It is a schematic diagram of a display device for comparison.

[0012] Figure 2 It is a plan view of the display panel provided by the embodiment of the present application.

[0013] Figure 3 It is a cross-sectional view of the display panel provided by the embodiment of the present application.

[0014] Figure 4 The circuit diagram of the pixel driving circuit provided by the embodiment of the present application.

[0015] Figure 5 The circuit diagram of the first type of gate circuit provided by the embodiment of the present application.

[0016] Figure 6 The circuit diagram of the second type of gate circuit provided by the embodiment of the present application.

[0017] Figure 7 The circuit diagram of the third type of gate circuit provided by the embodiment of the present application.

[0018] Figure 8 The stacked diagram of the light-shielding layer, active layer, first gate layer, first source-drain layer, and second source-drain layer of the display panel provided by the embodiment of the present application.

[0019] Figure 9 For Figure 8 The exploded view of the light-shielding layer of the display panel in

[0020] Figure 10 For Figure 8 The exploded view of the active layer of the display panel in

[0021] Figure 11 For Figure 8 The exploded view of the first gate layer of the display panel in

[0022] Figure 12 For Figure 8 The exploded view of the first source-drain layer of the display panel in

[0023] Figure 13 For Figure 8 The exploded view of the second source-drain layer of the display panel in

[0024] Figure 14 For Figure 8 The stacked diagram of the light-shielding layer and the active layer of the display panel in

[0025] Figure 15 For Figure 8 The stacked diagram of the light-shielding layer, active layer, and first gate layer of the display panel in

[0026] Figure 16 For Figure 8 The stacked diagram of the light-shielding layer, active layer, first gate layer, and first source-drain layer of the display panel in

[0027] Figure 17 For Figure 8 The stacked diagram of the light-shielding layer and the first via hole of the display panel in

[0028] Figure 18 ForFigure 8 Stacked diagram of the light-shielding layer and the first source-drain layer in

[0029] Figure 19 is Figure 8 Stacked diagram of the first gate layer and the second via hole in

[0030] Figure 20 is Figure 8 Stacked diagram of the first gate layer and the first source-drain layer in

[0031] Figure 21 is Figure 8 Stacked diagram of the first source-drain layer and the third via hole in

[0032] Figure 22 is Figure 8 Stacked diagram of the first source-drain layer and the third via hole and the fourth via hole in

[0033] Figure 23 is Figure 8 Stacked diagram of the first source-drain layer and the second source-drain layer in

[0034] Figure 24 is Figure 8 Partial enlarged view of the corresponding area of the first type of gate circuit of the display panel in

[0035] Figure 25 is Figure 24 Exploded view of the light-shielding layer of the display panel in

[0036] Figure 26 is Figure 24 Exploded view of the active layer of the display panel in

[0037] Figure 27 is Figure 24 Exploded view of the first gate layer of the display panel in

[0038] Figure 28 is Figure 24 Exploded view of the first source-drain layer of the display panel in

[0039] Figure 29 is Figure 24 Exploded view of the second source-drain layer of the display panel in

[0040] Figure 30 is Figure 8 Partial enlarged view of the corresponding area of the second type of gate circuit of the display panel in

[0041] Figure 31 is Figure 30 Exploded view of the light-shielding layer of the display panel in

[0042] Figure 32For Figure 30 Exploded view of the active layer of the display panel in

[0043] Figure 33 For Figure 30 Exploded view of the first gate layer of the display panel in

[0044] Figure 34 For Figure 30 Exploded view of the first source-drain layer of the display panel in

[0045] Figure 35 For Figure 30 Exploded view of the second source-drain layer of the display panel in

[0046] Figure 36 For Figure 8 Partially enlarged view of the corresponding area of the third type of gate circuit of the display panel in

[0047] Figure 37 For Figure 36 Exploded view of the light-shielding layer of the display panel in

[0048] Figure 38 For Figure 36 Exploded view of the active layer of the display panel in

[0049] Figure 39 For Figure 36 Exploded view of the first gate layer of the display panel in

[0050] Figure 40 For Figure 36 Exploded view of the first source-drain layer of the display panel in

[0051] Figure 41 For Figure 36 Exploded view of the second source-drain layer of the display panel in Detailed implementation mode

[0052] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the protection scope of the present application.

[0053] In the description of the present application, it should be noted that unless otherwise clearly specified and defined, the terms "installation", "connection", "connection", and "electrical connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or communication with each other; it can be directly connected, or indirectly connected through an intermediate medium, and can be the communication inside two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific situations.

[0054] In order to illustrate the principle of the technical problem generated in the embodiment of the present application, some comparative display devices are provided. It can be understood that these comparative display devices cannot be regarded as the prior art in the embodiment of the present application. As Figure 1 shown, the comparative display device 1 includes a pixel circuit 11 and a gate circuit 12. The gate circuit 12 will respectively set a wiring area 121 and a transistor area 122. A signal wiring 121a is set in the wiring area 121, and a thin-film transistor 122a is set in the transistor area 122. By extending the signal wiring 121a from the wiring area 121 into the transistor area 122 and connecting it to the corresponding transistor 122a, the normal operation of the gate circuit 12 is realized. However, since the signal wiring 121a and the source and drain electrodes of the transistor are arranged on the same layer, in order to avoid short circuits between the unconnected signal wiring and the source and drain electrodes of the transistor, the signal wiring needs to be spaced from the source and drain electrodes of the transistor, resulting in the need to separately set the wiring area 121 and the transistor area 122. The wiring area 121 needs to occupy a large space, and when the signal wiring 121a extends into the transistor area 122, each transistor needs to occupy more space to avoid the unconnected signal wiring 121a, resulting in a large space occupied by the gate circuit 12. Therefore, the current display device has a technical problem that the lateral space occupied by the thin-film transistor setting area and the signal wiring area in the gate driving circuit is large, resulting in a large border of the display device.

[0055] The embodiment of the present application provides a display panel and a display device to solve the above technical problems.

[0056] Based on the problem that the wiring area and the transistor area in the comparative display device need to be separately set, resulting in both the wiring area and the transistor area occupying a large space, the embodiment of the present application adjusts aspects such as the setting position of the signal line, the setting film layer of the signal line, and the arrangement method of the signal line, and / or adjusts aspects such as the setting position of the transistor, the arrangement method of the transistor, and the design of the transistor structure, so as to reduce the occupied space of the gate driving circuit 22 and reduce the border of the display panel 2.

[0057] Figure 1 Schematic diagram of a comparative display device.Figure 2 A plan view of a display panel provided by an embodiment of the present application. Figure 3 A cross-sectional view of a display panel provided by an embodiment of the present application. Figure 4 A circuit diagram of a pixel driving circuit provided by an embodiment of the present application. Figure 5 A circuit diagram of a first type of gate circuit provided by an embodiment of the present application. Figure 6 A circuit diagram of a second type of gate circuit provided by an embodiment of the present application. Figure 7 A circuit diagram of a third type of gate circuit provided by an embodiment of the present application. Figure 8 A stacked diagram of a light-shielding layer, an active layer, a first gate layer, a first source-drain layer, and a second source-drain layer of a display panel provided by an embodiment of the present application. Figure 9 For Figure 8 An exploded view of the light-shielding layer of the display panel in Figure 10 For Figure 8 An exploded view of the active layer of the display panel in Figure 11 For Figure 8 An exploded view of the first gate layer of the display panel in Figure 12 For Figure 8 An exploded view of the first source-drain layer of the display panel in Figure 13 For Figure 8 An exploded view of the second source-drain layer of the display panel in Figure 14 For Figure 8 A stacked diagram of the light-shielding layer and the active layer of the display panel in Figure 15 For Figure 8 A stacked diagram of the light-shielding layer, the active layer, and the first gate layer of the display panel in

[0058] Figure 16 For Figure 8 A stacked diagram of the light-shielding layer, the active layer, the first gate layer, and the first source-drain layer of the display panel in Figure 17 For Figure 8 A stacked diagram of the light-shielding layer and the first via of the display panel in Figure 18 For Figure 8 A stacked diagram of the light-shielding layer and the first source-drain layer in Figure 19 For Figure 8 A stacked diagram of the first gate layer and the second via in Figure 20 For Figure 8 A stacked diagram of the first gate layer and the first source-drain layer in Figure 21 For Figure 8 A stacked diagram of the first source-drain layer and the third via in Figure 22 For Figure 8 A stacked diagram of the first source-drain layer, the third via, and the fourth via in Figure 23 For Figure 8 A stacked diagram of the first source-drain layer and the second source-drain layer in Figure 24for Figure 8 A local enlarged view of the area corresponding to the first type of gate circuit of the display panel. Figure 25 for Figure 24 Exploded view of the light-shielding layer of the display panel. Figure 26 for Figure 24 An exploded view of the active layer of the display panel. Figure 27 for Figure 24 An exploded view of the first gate layer of the display panel. Figure 28 for Figure 24 Exploded view of the first source and drain layer of the display panel. Figure 29 for Figure 24 An exploded view of the second source and drain layer of the display panel. Figure 30 for Figure 8 A local enlarged view of the area corresponding to the second type of gate circuit of the display panel. Figure 31 for Figure 30 Exploded view of the light-shielding layer of the display panel. Figure 32 for Figure 30 An exploded view of the active layer of the display panel. Figure 33 for Figure 30 An exploded view of the first gate layer of the display panel. Figure 34 for Figure 30 Exploded view of the first source and drain layer of the display panel. Figure 35 for Figure 30 An exploded view of the second source and drain layer of the display panel. Figure 36 for Figure 8 A local enlarged view of the area corresponding to the third type of gate circuit of the display panel. Figure 37 for Figure 36 Exploded view of the light-shielding layer of the display panel. Figure 38 for Figure 36 An exploded view of the active layer of the display panel. Figure 39 for Figure 36 An exploded view of the first gate layer of the display panel. Figure 40 for Figure 36 Exploded view of the first source and drain layer of the display panel. Figure 41 for Figure 36 An exploded view of the second source and drain layer of the display panel.

[0059] like Figure 2 As shown, an embodiment of the present application provides a display panel 2, which includes a display area 201 and a non-display area 202. A plurality of pixels 23 are provided in the display area 201, and the pixels 23 include a light-emitting device LED and a pixel driving circuit 21 for driving the light-emitting device LED. A multi-stage gate driving circuit 22 is provided in the non-display area 202. The multi-stage gate driving circuit 22 can be arranged along the second direction Y, and the gate driving circuit 22 outputs a scanning signal to the pixel driving circuit 21.

[0060] Specifically, as Figure 2 shown, the non-display area 202 can be arranged to surround the display area 201. However, the embodiments of the present application are not limited thereto. The non-display area 202 can be arranged on one side, both sides or three sides of the display area 201, and the non-display area 202 can be bent to the back of the display area 201. The non-display area 202 can include an upper border area, a lower border area, a left border area and a right border area. The gate driving circuit 22 can be arranged in the left border area and / or the right border area, and the gate driving circuit 22 can be arranged along the first direction X on one side or both sides of the display area 201.

[0061] As Figure 3 shown, as a specific structure of the display panel 2 in the embodiments of the present application, the display panel 2 includes a substrate 211, a light-shielding layer 212, a buffer layer 213, a semiconductor layer 214, a first gate insulating layer 215, an active layer 216, a second gate insulating layer 217, a first gate layer 218, a third gate insulating layer 232, a second gate layer 225, a first interlayer insulating layer 219, a first source-drain layer 221, a passivation layer 222, a first planarization layer 224, a second source-drain layer 223, a second planarization layer 226, a third planarization layer 227, a pixel electrode layer 228, a first pixel definition layer 229, a second pixel definition layer 231, a light-emitting functional layer and a common electrode layer which are arranged in sequence.

[0062] Specifically, the material of the semiconductor layer 214 includes an oxide semiconductor, specifically a metal oxide, and more specifically indium gallium zinc oxide.

[0063] Specifically, the material of the active layer 216 can include one of a silicon semiconductor and an oxide semiconductor, specifically low-temperature polycrystalline silicon or a metal oxide, specifically Ln-IZO (indium zinc oxide doped with lanthanide elements), IGZTO (indium gallium zinc tin oxide).

[0064] Specifically, as Figure 3 shown, Figure 3 shows that the display panel 2 includes a semiconductor layer 214 and an active layer 216. However, the embodiments of the present application are not limited thereto. The display panel 2 can include only one of the semiconductor layer 214 and the active layer 216.

[0065] Specifically, as Figure 3 shown, Figure 3 shows that the display panel includes two gate layers. However, the embodiments of the present application are not limited thereto. The display panel can include one gate layer or three gate layers.

[0066] Specifically, as Figure 3 shown, Figure 3As shown, the display panel 2 includes a first source-drain layer 221 and a second source-drain layer 223, but the embodiments of the present application are not limited thereto. The display panel 2 may include a first source-drain layer 221, a second source-drain layer 223, and a third source-drain layer.

[0067] Specifically, as Figure 3 shown, Figure 3 As shown, the light-shielding layer 212 is only disposed in the display area 201, but the embodiments of the present application are not limited thereto. The light-shielding layer 212 may be disposed in the non-display area 202.

[0068] Specifically, as Figure 3 shown, Figure 3 As shown, the transistors in the display area 201 all use the semiconductor layer 214 as the active part, and the transistors in the non-display area 202 all use the active layer 216 as the active part. However, the embodiments of the present application are not limited thereto. Some transistors in the display area 201 may use the semiconductor layer 214 as the active part, and some transistors in the display area 201 may use the active layer 216 as the active part. Similarly, some transistors in the non-display area 202 may use the semiconductor layer 214 as the active part, and some transistors in the non-display area 202 may use the active layer 216 as the active part.

[0069] Specifically, as Figure 3 shown, Figure 3 Taking the display panel 2 as an organic light-emitting diode display panel 2 as an example for illustration, but the embodiments of the present application are not limited thereto. The display panel 2 may be a liquid crystal display panel 2 or other types of display panels 2.

[0070] Specifically, as Figures 5 to 7 shown, each stage of the gate driving circuit 22 includes a first type of gate circuit 22a, a second type of gate circuit 22b, and a third type of gate circuit 22c.

[0071] As Figures 2 to 41As shown in the figure, an embodiment of the present application provides a display panel 2. The display panel 2 includes multiple rows of pixels 23 and a multi-stage gate driving circuit 22. The pixel 23 includes a light-emitting device LED and a pixel driving circuit 21. The multi-stage gate driving circuit 22 is electrically connected to the corresponding pixel driving circuit 21 respectively. Each stage of the gate driving circuit 22 includes a first type of gate circuit 22a, a second type of gate circuit 22b, and a third type of gate circuit 22c arranged along the first direction X. The first type of gate circuit 22a is electrically connected to at least a first clock signal line CKA, a second clock signal line CKB, a first high-potential signal line VGH1, a first low-potential signal line VGL1, a second low-potential signal line VGL2, a first reset control line VST1, and a low-frequency signal line LC. The second type of gate circuit 22b is electrically connected to at least the first high-potential signal line VGH1, the second low-potential signal line VGL2, a third clock signal line CKC of the display panel, and a second reset control line VST2 of the display panel. The third type of gate circuit 22c is electrically connected to at least the first high-potential signal line VGH1, a second high-potential signal line VGH2, the second low-potential signal line VGL2, and a third low-potential signal line VGL3.

[0072] Wherein, the display panel 2 further includes a substrate 211, an active layer 216, a first gate layer 218, a first source-drain layer 221, and a second source-drain layer 223 arranged in sequence. At least one of the first clock signal line CKA, the second clock signal line CKB, the third clock signal line CKC, the first high-potential signal line VGH1, the second high-potential signal line VGH2, the first low-potential signal line VGL1, the second low-potential signal line VGL2, the third low-potential signal line VGL3, the first reset control line VST1, the second reset control line VST2, and the low-frequency signal line LC is disposed on the second source-drain layer 223.

[0073] An embodiment of the present application provides a display panel 2. By providing the first source-drain layer 221 and the second source-drain layer 223, at least one of the first clock signal line CKA, the second clock signal line CKB, the third clock signal line CKC, the first high-potential signal line VGH1, the second high-potential signal line VGH2, the first low-potential signal line VGL1, the second low-potential signal line VGL2, the third low-potential signal line VGL3, the first reset control line VST1, the second reset control line VST2, and the low-frequency signal line LC is disposed on the second source-drain layer 223, the number of traces in the first source-drain layer can be reduced, thereby reducing the lateral space occupied by the first source-drain layer, further reducing the space occupied by the gate driving circuit, and reducing the border of the display panel.

[0074] Specifically, compared with the comparative display device where the source, drain, and each signal trace of the transistor are formed in the first source-drain layer, each signal trace, the source and drain of the transistor all need to occupy the lateral space of the first source-drain layer, and each signal trace needs to wind around when connected to the source and drain of the transistor, further occupying the lateral space, resulting in a larger width of the first source-drain layer, and further resulting in a larger border of the gate driving circuit. In the embodiment of the present application, by arranging at least part of the signal lines in the second source-drain layer, the number of traces in the first source-drain layer is reduced, the lateral space occupied by the first source-drain layer is reduced, and the signal lines in the second source-drain layer can overlap with the traces in the first source-drain layer or the source and drain of the transistor in the thickness direction, reducing the occupied space of the connection lines, reducing the space occupied by the gate driving circuit, and reducing the border of the display panel.

[0075] In some embodiments, as [[ID= shown, at least one of the first reset control line VST1, the low-frequency signal line LC, the first clock signal line CKA, the second clock signal line CKB, the first low-potential signal line VGL1, and the second low-potential signal line VGL2 is arranged in the second source-drain layer 223. By arranging at least one of the first reset control line VST1, the low-frequency signal line LC, the first clock signal line CKA, the second clock signal line CKB, the first low-potential signal line VGL1, and the second low-potential signal line VGL2 in the second source-drain layer 223, the lateral space occupied by the signal lines electrically connected to the first type of gate circuit can be reduced, and the border of the display panel can be reduced.

[0076] Specifically, compared with the comparative display device where each signal line connected to the first type of gate circuit 22a needs to be arranged in the first source-drain layer and needs to extend from the trace area to the transistor area, resulting in a larger occupied lateral space, in the embodiment of the present application, by arranging the signal lines connected to the first type of gate circuit 22a in the second source-drain layer, the width of the first source-drain layer is reduced, and the distance between the signal lines arranged in the second source-drain layer and the connected transistors can be shortened, thereby reducing the occupied space of the connection lines, reducing the occupied space of the gate driving circuit, and reducing the border of the display panel.

[0077] In some embodiments, as ​ shown, the first reset control line VST1 is arranged in the second source-drain layer 223. By arranging the first reset control line VST1 in the second source-drain layer 223, the first reset control line VST1 does not need to occupy the lateral space of the first source-drain layer 221, reducing the lateral space occupied by the gate driving circuit 22 and reducing the border of the display panel.

[0078] In some embodiments, as​ , ​ , ​ As shown in ​ , the first type of gate circuit 22a includes a first pull-up control module 311. There is a gap between the projection of the first reset control line VST1 on the substrate 211 and the projection of the first pull-up control module 311 on the substrate 211. By making there be a gap between the projection of the first reset control line VST1 on the substrate and the projection of the first pull-up control module 311 on the substrate 211, the first reset control line VST1 can be prevented from affecting the signal lines and transistors in the first type of gate circuit 22a, and space can be reserved for other signal lines.

[0079] Specifically, the above embodiment takes the case where there is a gap between the projection of the first reset control line VST1 on the substrate 211 and the projection of the first pull-up control module 311 on the substrate 211 as an example for illustration, but the embodiments of the present application are not limited thereto. The projection of the first reset control line VST1 on the substrate 211 may overlap with each module in the first type of gate circuit 22a. For example, the projection of the first reset control line VST1 on the substrate 211 overlaps with the projection of the first pull-up control module 311 on the substrate 211, or the projection of the first reset control line VST1 on the substrate 211 overlaps with the projection of the first reset module 317 on the substrate 211.

[0080] In some embodiments, as ​ , ​ , ​ shown, the first type of gate circuit 22a includes a first reset module 317, and the first reset module 317 is electrically connected to the first reset control line VST1;

[0081] Among them, the first source-drain layer 221 includes a first source connection line LD1. There is a gap between the projection of the first reset control line VST1 on the substrate 211 and the projection of the first reset module 317 on the substrate 211, and the first reset control line VST1 is connected to the first reset module 317 through the first source connection line LD1. By making there be a gap between the projection of the first reset control line VST1 on the substrate 211 and the projection of the first reset module 317 on the substrate 211, the first reset control line VST1 can be prevented from affecting the signal lines and transistors in the first type of gate circuit 22a, and space can be reserved for other signal lines. Moreover, since the first reset control line VST1 is connected to the first reset module 317 through the first source connection line LD1, normal connection between the first reset control line VST1 and the first reset module can be achieved.

[0082] In some embodiments, as ​As shown, the low-frequency signal line LC is disposed in the second source-drain layer 223. By disposing the low-frequency signal line LC in the second source-drain layer 223, the low-frequency signal line LC does not need to occupy the lateral space of the first source-drain layer 221, reducing the lateral space occupied by the gate driving circuit 22 and reducing the border of the display panel.

[0083] In some embodiments, as ​ , ​ , ​ shown, the first type of gate circuit 22a includes a first inverter module 315, and the low-frequency signal line LC is electrically connected to the first inverter module 315; the projection of the low-frequency signal line LC on the substrate 211 overlaps with the projection of the first inverter module 315 on the substrate 211. By making the projection of the low-frequency signal line LC on the substrate 211 overlap with the projection of the first inverter module 315 on the substrate 211, the signals of the signal lines and transistors in the first type of gate circuit 22a are not affected, and space can be reserved for other signal lines.

[0084] In some embodiments, as ​ shown, the first clock signal line CKA is disposed in the second source-drain layer 223. By disposing the first clock signal line CKA in the second source-drain layer 223, the first clock signal line CKA does not need to occupy the lateral space of the first source-drain layer 221, reducing the lateral space occupied by the gate driving circuit 22 and reducing the border of the display panel.

[0085] Specifically, it can be understood that each clock signal line in the display panel 2 will include multiple clock lines. The multiple clock lines will occupy a large space in the first source-drain layer, and the multiple clock lines disposed outside the transistor region and connected to the transistor by extending into the transistor region will further occupy space, resulting in a large lateral occupied space of the gate driving circuit 22 and a large border of the display panel 2. In the embodiments of the present application, by disposing the first clock signal line CKA in the second source-drain layer 223, the lateral space occupied by the clock signal line can be reduced, and the border of the display panel 2 can be reduced.

[0086] In some embodiments, as ​ , ​ , ​As shown, the first type of gate circuit 22a includes a first pull-up control module 311, and the projection of the first clock signal line CKA on the substrate 211 overlaps with the projection of the first pull-up control module 311 on the substrate 211. By making the projection of the first clock signal line CKA on the substrate 211 overlap with the projection of the first pull-up control module 311 on the substrate 211, the first clock signal line does not need to occupy extra space, reducing the space occupied by the gate driving circuit and reducing the border of the display panel 2.

[0087] Specifically, as ​ , ​ shown, the first clock signal line CKA may include a first clock first line CKA1, a first clock second line CKA2, a first clock third line CKA3, and a first clock fourth line CKA4. Every four levels of the first type of gate circuit 22a are connected to these four first clock signal lines CKA in a cycle. For example, the first-level to fourth-level first type of gate circuits 22a are respectively connected to the first clock first line CKA1, the first clock second line CKA2, the first clock third line CKA3, and the first clock fourth line CKA4. The fifth-level to eighth-level first type of gate circuits 22a are respectively connected to the first clock first line CKA1, the first clock second line CKA2, the first clock third line CKA3, and the first clock fourth line CKA4. Similarly, the clock signal lines connected to other levels of the first type of gate circuit 22a can be determined.

[0088] Specifically, the first clock fourth line CKA4, the first clock third line CKA3, the first clock second line CKA2, and the first clock first line CKA1 are arranged in sequence along the first direction.

[0089] Specifically, the above embodiment is described by taking the first clock signal line CKA including four clock lines as an example, but the embodiments of the present application are not limited thereto. The first clock signal line CKA may include other numbers of clock lines, for example, it may include 8 clock lines.

[0090] Specifically, among every four levels of the first type of gate circuit 22a, the positions of the connections between each level of the first type of gate circuit 22a and the first clock signal line CKA are different.

[0091] In some embodiments, as ​ shown, the second clock signal line CKB is disposed on the second source-drain layer 223. By making the second clock signal line CKB disposed on the second source-drain layer 223, the second clock signal line CKB does not need to occupy the lateral space of the first source-drain layer 221, reducing the lateral space occupied by the gate driving circuit 22 and reducing the border of the display panel.

[0092] Specifically, it can be understood that each clock signal line in the display panel 2 includes multiple clock lines. The multiple clock lines will occupy a large space in the first source-drain layer. Moreover, when the multiple clock lines are arranged outside the transistor region and connected to the transistors by extending into the transistor region, it will further occupy space, resulting in a large lateral occupied space of the gate driving circuit 22 and a large border of the display panel 2. In the embodiment of the present application, by arranging the second clock signal line CKB in the second source-drain layer 223, the lateral space occupied by the clock signal line can be reduced, and the border of the display panel 2 can be reduced.

[0093] In some embodiments, such as ​ , ​ , ​ shown, the first type of gate circuit 22a includes a first pull-up module 312, and the projection of the second clock signal line CKB on the substrate 211 overlaps with the projection of the first pull-up module 312 on the substrate 211. By making the projection of the second clock signal line CKB on the substrate 211 overlap with the projection of the first pull-up module 312 on the substrate 211, the second clock signal line CKB does not need to occupy additional space, and the second clock signal line is convenient to be connected to the first pull-up module 312, reducing the occupied space of the connection line, reducing the occupied space of the gate driving circuit, and reducing the border of the display panel 2.

[0094] Specifically, the second clock signal line CKB includes a first group of sub-lines CKBi and a second group of sub-lines CKBj, and the projection of the first group of sub-lines CKBi on the substrate 211 overlaps with the projection of the first pull-up module 312 on the substrate 211.

[0095] Specifically, the second clock signal line CKB may include a second clock first line CKB1, a second clock second line CKB2, a second clock third line CKB3, a second clock fourth line CKB4, a second clock fifth line CKB5, a second clock sixth line CKB6, a second clock seventh line CKB7, and a second clock eighth line CKB8. The second clock first line CKB1, the second clock third line CKB3, the second clock fifth line CKB5, and the second clock seventh line CKB7 in the second clock signal line CKB serve as a first group of sub-lines CKBi, and the second clock second line CKB2, the second clock fourth line CKB4, the second clock sixth line CKB6, and the second clock eighth line CKB8 serve as a second group of sub-lines CKBj. The second pull-up transistors T22j of every four levels of the first type of gate circuits 22a are connected to the first group of sub-lines CKBi in a cyclic manner, and the third pull-up transistors T23j of every four levels of the first type of gate circuits 22a are connected to the second group of sub-lines CKBj in a cyclic manner. For example, the second pull-up transistors T22j of the first-level to fourth-level first type of gate circuits 22a are respectively connected to the second clock first line CKB1, the second clock third line CKB3, the second clock fifth line CKB5, and the second clock seventh line CKB7, and the third pull-up transistors T23j of the first-level to fourth-level first type of gate circuits 22a are respectively connected to the second clock second line CKB2, the second clock fourth line CKB4, the second clock sixth line CKB6, and the second clock eighth line CKB8; the second pull-up transistors T22j of the fifth-level to eighth-level first type of gate circuits 22a are respectively connected to the second clock first line CKB1, the second clock third line CKB3, the second clock fifth line CKB5, and the second clock seventh line CKB7, and the third pull-up transistors T23j of the fifth-level to eighth-level first type of gate circuits 22a are respectively connected to the second clock second line CKB2, the second clock fourth line CKB4, the second clock sixth line CKB6, and the second clock eighth line CKB8; similarly, the clock signal lines connected to the first type of gate circuits 22a at other levels can be determined.

[0096] Specifically, the second clock seventh line CKB7, the second clock fifth line CKB5, the second clock third line CKB3, and the second clock first line CKB1 are arranged in sequence along a first direction.

[0097] Specifically, the second clock eighth line CKB8, the second clock sixth line CKB6, the second clock fourth line CKB4, and the second clock second line CKB2 are arranged in sequence along a first direction.

[0098] Specifically, in the above embodiments, the second clock signal line CKB is taken as an example of including eight clock lines, but the embodiments of the present application are not limited thereto. The second clock signal line CKB may include other numbers of clock lines, for example, it may include 4 clock lines or 16 clock lines.

[0099] Specifically, among every four levels of the first type of gate circuits 22a, the positions of the connections of the second pull-up transistors T22j of each level of the first type of gate circuits 22a to the first group of sub-lines CKBi are different.

[0100] Specifically, among every four levels of the first type of gate circuits 22a, the positions of the connections of the third pull-up transistors T23j of each level of the first type of gate circuits 22a to the second group of sub-lines CKBj are different.

[0101] In some embodiments, as ​ shown, the first low-potential signal line VGL1 is disposed on the second source-drain layer 223. By disposing the first low-potential signal line VGL1 on the second source-drain layer 223, the first low-potential signal line VGL1 does not need to occupy the lateral space of the first source-drain layer 221, reducing the lateral space occupied by the gate driving circuit 22 and reducing the border of the display panel.

[0102] In some embodiments, as ​ 、 ​ 、 ​ shown, the first type of gate circuit 22a includes a first inverting module 315 and a first pull-up module 312. The first inverting module 315 and the first pull-up module 312 are electrically connected to a first pull-up node Q1[n]. The projection of the first low-potential signal line VGL1 on the substrate 211 is located between the projection of the first inverting module 315 on the substrate 211 and the projection of the first pull-up module 312 on the substrate 211. By disposing the first low-potential signal line between the projection of the first inverting module 315 on the substrate 211 and the projection of the first pull-up module 312 on the substrate 211, the first low-potential signal line VGL1 does not need to occupy additional space, and the first low-potential signal line does not affect the normal operation of the first pull-up module.

[0103] In some embodiments, as ​ shown, the second low-potential signal line VGL2 is disposed on the second source-drain layer 223. By disposing the second low-potential signal line VGL2 on the second source-drain layer 223, the second low-potential signal line VGL2 does not need to occupy the lateral space of the first source-drain layer 221, reducing the lateral space occupied by the gate driving circuit 22 and reducing the border of the display panel.

[0104] In some embodiments, as ​ 、​ , ​ As shown in ​ , the first type of gate circuit 22a includes a first pull-up module 312. The projection of the second low-potential signal line VGL2 on the substrate 211 overlaps with the projection of the first pull-up module 312 on the substrate 211. By making the projection of the second low-potential signal line VGL2 on the substrate 211 overlap with the projection of the first pull-up module 312 on the substrate 211, the second low-potential signal line VGL2 does not need to occupy additional space, reducing the lateral space occupied by the gate driving circuit 22 and reducing the border of the display panel.

[0105] In some embodiments, as ​ shown, the second reset control line VST2 is disposed on the second source-drain layer 223. By making the second reset control line VST2 disposed on the second source-drain layer 223, the second reset control line VST2 does not need to occupy the lateral space of the first source-drain layer 221, reducing the lateral space occupied by the gate driving circuit 22 and reducing the border of the display panel.

[0106] In some embodiments, as ​ , ​ , ​ shown, the second type of gate circuit 22b includes a second reset module 327. The second reset module 327 is electrically connected to the second reset control line VST2. The projection of the second reset control line VST2 on the substrate 211 is located between the projection of the first type of gate circuit 22a on the substrate 211 and the projection of the second reset module 327 on the substrate 211. By making the projection of the second reset control line VST2 on the substrate 211 located between the projection of the first type of gate circuit 22a on the substrate 211 and the projection of the second reset module 327 on the substrate 211, the second reset control line VST2 does not need to occupy additional lateral space, reducing the lateral space occupied by the gate driving circuit 22 and reducing the border of the display panel. Moreover, the distance between the second reset control line VST2 and the second reset module 327 is small, and the length of the connection line between the second reset control line VST2 and the second reset module 327 is small or even no connection line needs to be provided, further reducing the space occupied by the second reset control line VST2 and reducing the border of the display panel.

[0107] In some embodiments, as ​As shown, at least one of the third clock signal line CKC, the first high potential signal line VGH1, the second high potential signal line VGH2, and the third low potential signal line VGL3 is disposed on the second source-drain layer 223. By disposing at least one of the third clock signal line CKC, the first high potential signal line VGH1, the second high potential signal line VGH2, and the third low potential signal line VGL3 on the second source-drain layer 223, the lateral space occupied by the signal lines electrically connected to the gate driving circuit can be reduced, and the border of the display panel can be reduced.

[0108] Specifically, compared with the related display device in which each signal line connected to the gate driving circuit needs to be disposed on the first source-drain layer and needs to extend from the routing area to the transistor area, resulting in a relatively large lateral space occupied, in the embodiment of the present application, by disposing the signal lines connected to the gate driving circuit on the second source-drain layer, the width of the first source-drain layer is reduced, and the distance between the signal lines disposed on the second source-drain layer and the connected transistors can be shortened, thereby reducing the space occupied by the connection lines, reducing the space occupied by the gate driving circuit, and reducing the border of the display panel.

[0109] In some embodiments, as ​ shown, the first high potential signal line VGH1 is disposed on the second source-drain layer 223. By disposing the first high potential signal line VGH1 on the second source-drain layer 223, the first high potential signal line VGH1 does not need to occupy the lateral space of the first source-drain layer 221, reducing the lateral space occupied by the gate driving circuit 22 and reducing the border of the display panel.

[0110] In some embodiments, as ​ 、 ​ 、 ​ shown, the third type of gate circuit 22c includes a third pull-up control module 331, and there is an overlap between the projection of the first high potential signal line VGH1 on the substrate 211 and the projection of the third pull-up control module 331 on the substrate 211. By making the projection of the first high potential signal line VGH1 on the substrate 211 overlap with the projection of the third pull-up control module 331 on the substrate 211, the first high potential signal line VGH1 does not need to occupy additional space, reducing the lateral space occupied by the gate driving circuit 22 and reducing the border of the display panel, and the first high potential signal line VGH1 can be directly connected to the third pull-up control module, reducing the length of the connection line, further reducing the occupied space, and reducing the border of the display panel.

[0111] In some embodiments, as ​As shown, the third clock signal line CKC is disposed on the second source-drain layer 223. By disposing the third clock signal line CKC on the second source-drain layer 223, the third clock signal line CKC does not need to occupy the lateral space of the first source-drain layer 221, reducing the lateral space occupied by the gate driving circuit 22 and reducing the border of the display panel.

[0112] Specifically, it can be understood that each clock signal line in the display panel 2 includes multiple clock lines. The multiple clock lines will occupy a large space of the first source-drain layer, and the multiple clock lines disposed outside the transistor region and connected to the transistor by extending into the transistor region will further occupy space, resulting in a large lateral occupied space of the gate driving circuit 22 and a large border of the display panel 2. In the embodiment of the present application, by disposing the third clock signal line CKC on the second source-drain layer 223, the lateral space occupied by the clock signal line can be reduced, and the border of the display panel 2 can be reduced.

[0113] In some embodiments, as ​ 、 ​ 、 ​ shown, the third type of gate circuit 22c includes a third pull-up control module 331, and there is an overlap between the projection of the third clock signal line CKC on the substrate 211 and the projection of the third pull-up control module 331 on the substrate 211. By making the projection of the third clock signal line CKC on the substrate 211 overlap with the projection of the third pull-up control module 331 on the substrate 211, the first clock signal line does not need to occupy additional space, reducing the space occupied by the gate driving circuit and reducing the border of the display panel 2.

[0114] Specifically, the third clock signal line CKC may include a third clock first line CKC1, a third clock second line CKC2, a third clock third line CKC3, and a third clock fourth line CKC4. Every four levels of the second type of gate circuit 22b are cyclically connected to these four third clock signal lines CKC. For example, the first-level to fourth-level second type of gate circuits 22b are respectively connected to the third clock first line CKC1, the third clock second line CKC2, the third clock third line CKC3, and the third clock fourth line CKC4. The fifth-level to eighth-level second type of gate circuits 22b are respectively connected to the third clock first line CKC1, the third clock second line CKC2, the third clock third line CKC3, and the third clock fourth line CKC4. Similarly, the clock signal lines connected to other levels of the second type of gate circuit 22b can be determined.

[0115] Specifically, the third clock fourth line CKC4, the third clock third line CKC3, the third clock second line CKC2, and the third clock first line CKC1 are arranged in sequence along the first direction.

[0116] Specifically, in the above embodiments, the third clock signal line CKC includes four clock lines as an example for illustration, but the embodiments of the present application are not limited thereto. The third clock signal line CKC may include other numbers of clock lines, for example, it may include eight clock lines.

[0117] Specifically, in every four-stage second type of gate circuit 22b, the positions of the connections between each stage of the second type of gate circuit 22b and the third clock signal line CKC are different.

[0118] In some embodiments, as ​ shown, the second high potential signal line VGH2 is disposed on the second source-drain layer 223. By disposing the second high potential signal line VGH2 on the second source-drain layer 223, the second high potential signal line VGH2 does not need to occupy the lateral space of the first source-drain layer 221, reducing the lateral space occupied by the gate driving circuit 22 and reducing the border of the display panel.

[0119] In some embodiments, as ​ , ​ , ​ shown, the third type of gate circuit 22c includes a third pull-up module 332. The third pull-up module 332 is electrically connected to the second high potential signal line VGH2, and there is an overlap between the projection of the second high potential signal line VGH2 on the substrate 211 and the projection of the third pull-up module 332 on the substrate 211. By making there be an overlap between the projection of the second high potential signal line VGH2 on the substrate 211 and the projection of the third pull-up module 332 on the substrate 211, the second high potential signal line VGH2 does not need to occupy extra space, reducing the space occupied by the gate driving circuit, reducing the border of the display panel 2, and the second high potential signal line VGH2 can be directly connected to the third pull-up module 332, shortening the length of the connection line or even eliminating the connection line, further reducing the space occupied by the second high potential signal line VGH2 and reducing the border of the display panel.

[0120] In some embodiments, as ​ shown, the third low potential signal line VGL3 is disposed on the second source-drain layer 223. By disposing the third low potential signal line VGL3 on the second source-drain layer 223, the third low potential signal line VGL3 does not need to occupy the lateral space of the first source-drain layer 221, reducing the lateral space occupied by the gate driving circuit 22 and reducing the border of the display panel.

[0121] In some embodiments, as ​ , ​ , ​As shown, the third type of gate circuit 22c includes a third pull-down module 333. The third pull-down module 333 is electrically connected to the third low-potential signal line VGL3. The projection of the third low-potential signal line VGL3 on the substrate 211 overlaps with the projection of the third pull-down module 333 on the substrate 211. By making the projection of the third low-potential signal line VGL3 on the substrate 211 overlap with the projection of the third pull-down module 333 on the substrate 211, the third low-potential signal line VGL3 does not need to occupy extra space, reducing the space occupied by the gate driving circuit and reducing the border of the display panel 2. Moreover, the third low-potential signal line VGL3 can be directly connected to the third pull-down module 333, shortening the length of the connection line or even eliminating the connection line, further reducing the space occupied by the third low-potential signal line VGL3 and reducing the border of the display panel.

[0122] In some embodiments, as ​ shown, the first clock signal line CKA, the second clock signal line CKB, the third clock signal line CKC, the first high-potential signal line VGH1, the second high-potential signal line VGH2, the first low-potential signal line VGL1, the second low-potential signal line VGL2, the third low-potential signal line VGL3, the first reset control line VST1, the second reset control line VST2, and the low-frequency signal line LC are all disposed in the second source-drain layer. By disposing the first clock signal line CKA, the second clock signal line CKB, the third clock signal line CKC, the first high-potential signal line VGH1, the second high-potential signal line VGH2, the first low-potential signal line VGL1, the second low-potential signal line VGL2, the third low-potential signal line VGL3, the first reset control line VST1, the second reset control line VST2, and the low-frequency signal line LC in the second source-drain layer, the lateral space occupied by the gate driving circuit can be further reduced, and the border of the display panel can be reduced.

[0123] Specifically, the second clock signal line CKB includes a first group of sub-lines CKBi and a second group of sub-lines CKBj.

[0124] Specifically, the first reset control line VST1, the low-frequency signal line LC, the first clock signal line CKA, the first low-potential signal line VGL1, the first group of sub-lines CKBi, the second low-potential signal line VGL2, the second reset control line VST2, the second group of sub-lines CKBj, the first high-potential signal line VGH1, the third clock signal line CKC, the second high-potential signal line VGH2, and the third low-potential signal line VGL3 are arranged along the first direction X.

[0125] In some embodiments, as ​As shown, the first type of gate circuit 22a includes a first pull-up module 312. The second clock signal line CKB includes a first group of sub-lines CKBi and a second group of sub-lines CKBj. The first pull-up module 312 includes:

[0126] A first pull-up transistor T21j, the first electrode of the first pull-up transistor T21j is electrically connected to the first clock signal line CKA, and the second electrode of the first pull-up transistor T21j is electrically connected to the stage transmission signal terminal Cout[n] of the first type of gate circuit 22a at this stage;

[0127] A second pull-up transistor T22j, the first electrode of the second pull-up transistor T22j is electrically connected to the first group of sub-lines CKBi, and the second electrode of the second pull-up transistor T22j is electrically connected to the first signal output terminal Gn[m] of another stage of the first type of gate circuit 22a;

[0128] A third pull-up transistor T23j, the first electrode of the third pull-up transistor T23j is electrically connected to the second group of sub-lines CKBj, and the second electrode of the third pull-up transistor T23j is electrically connected to the first signal output terminal Gn[n] of the first type of gate circuit 22a at this stage. By making a first type of gate circuit 22a at one stage have the first signal output terminals of two stages of the first type of gate circuit, the first type of gate circuit at one stage can occupy the space of two stages of the first type of gate circuit, thereby shortening the horizontal space occupied by the first type of gate circuit and reducing the border.

[0129] Specifically, in the embodiment of the present application, the first signal output terminal Gn[m] of another stage of the first type of gate circuit 22a can be the first signal output terminals of the lower stages of the first type of gate circuit 22a. For example, the first signal output terminal Gn[m] of another stage of the first type of gate circuit 22a can be the first signal output terminal of the next stage of the first type of gate circuit 22a. Taking n as 3 as an example, then m can be 4; however, the embodiment of the present application is not limited thereto. The first signal output terminal Gn[m] of another stage of the first type of gate circuit 22a can be the first signal output terminals of the next two stages of the first type of gate circuit 22a or the first signal output terminals of other stages of the first type of gate circuit 22a.

[0130] Specifically, it can be understood that, compared with the case where the first type of gate circuit in the comparative display device has only one first signal output terminal, each stage of the first type of gate circuit is connected to a corresponding first signal output terminal. In the embodiment of the present application, the first type of gate circuit of one stage has two first signal output terminals. Accordingly, the first type of gate circuit can be shortened by half. Accordingly, the first signal output terminals connected to each first type of gate circuit can be arranged in sequence. For example, the two first signal output terminals of the first stage of the first type of gate circuit can be regarded as the first signal output terminal of the first stage of the first type of gate circuit and the first signal output terminal of the second stage of the first type of gate circuit in the comparative display device. Similarly, the first signal output terminals of other stages of the first type of gate circuit can be determined.

[0131] Specifically, the gate driving circuit includes a plurality of transistors (such as a first pull-up control transistor and a first pull-up transistor), and the pixel driving circuit includes a plurality of transistors (such as a driving transistor and a switching transistor).

[0132] In some embodiments, the mobility of at least one transistor in the gate driving circuit 22 is greater than the mobility of the transistors in the pixel driving circuit 21; thereby, the size of the transistors in the gate driving circuit can be reduced, thereby reducing the occupied space of the gate driving circuit 22 and reducing the border.

[0133] Specifically, when making the mobility of at least one transistor in the gate driving circuit 22 greater than the mobility of the transistors in the pixel driving circuit 21, for example, making the mobility of the first inverter transistor in the gate driving circuit 22 greater than the mobility of the initialization transistor in the pixel driving circuit 21. However, the embodiments of the present application are not limited thereto. The mobility of other transistors in the gate driving circuit can be made greater than the mobility of the transistors in the pixel driving circuit, or the mobility of multiple transistors in the gate driving circuit can be greater than the mobility of the transistors in the pixel driving circuit.

[0134] Specifically, the materials of the active parts of the transistors in the gate driving circuit can be the same, the materials of the active parts of the transistors in the pixel driving circuit can be the same, and the mobility of the active parts of the transistors in the gate driving circuit is made greater than the mobility of the transistors in the pixel driving circuit.

[0135] Specifically, the mobility of the active parts of the transistors in the gate driving circuit can be greater than 20. For example, the materials of the active parts of the transistors in the gate driving circuit are Ln-IZO (indium zinc oxide doped with lanthanide elements) and IGZTO (indium gallium zinc tin oxide), and the material of the active part of the transistor in the pixel driving circuit is indium gallium zinc oxide, so that the area of the transistors in the gate driving circuit can be relatively small.

[0136] Specifically, to improve the performance of the transistor, the area of the transistor is generally made larger. For example, when indium gallium zinc oxide is used as the material of the active part, the channel width of the transistor needs to be 1000 and the length needs to be 5 to meet the electrical requirements of the transistor. In the embodiments of the present application, by making the mobility of the transistor in the gate driving circuit greater than the mobility of the transistor in the pixel driving circuit, the area of the transistor can be reduced, still meeting the electrical requirements, reducing the occupied area of the transistor, and reducing the border of the display panel.

[0137] Meanwhile, to more clearly illustrate the structure of each film layer of the display panel, ​ is provided, as ​ shown, the positions of the structures in the light-shielding layer 212 and the relative positional relationship between the structures can be seen; as ​ shown, the positions of the structures in the active layer 216 and the relative positional relationship between the structures can be seen; as ​ shown, the positions of the structures in the first gate layer 218 and the relative positional relationship between the structures can be seen; as ​ shown, the positions of the structures in the first source-drain layer 221 and the relative positional relationship between the structures can be seen; as ​ shown, the positions of the structures in the second source-drain layer 223 and the relative positional relationship between the structures can be seen.

[0138] Meanwhile, to illustrate the corresponding relationship between different film layers, ​ is provided, as ​ shown, the relative positional relationship between the light-shielding layer 212 and the active layer 216 can be seen; as ​ shown, the relative positional relationship between the light-shielding layer 212, the active layer 216 and the first gate layer 218 can be seen; as ​ shown, the relative positional relationship between the light-shielding layer 212, the active layer 216, the first gate layer 218 and the first source-drain layer 221 can be seen; as ​ shown, the relative positional relationship between the light-shielding layer 212, the active layer 216, the first gate layer 218, the first source-drain layer 221 and the second source-drain layer 223 can be seen; as ​ shown, the relative positional relationship between the light-shielding layer 212 and the first via 411 can be seen. The first via 411 refers to the via connecting the first source-drain layer 221 and the light-shielding layer 212, including the via of the buffer layer 213; as ​ shown, the relative positional relationship between the light-shielding layer 212 and the first source-drain layer 221 and the connecting position thereof can be seen; as ​ shown, the relative positional relationship between the first gate layer 218 and the second via 412 can be seen. The second via 412 refers to the via of the first interlayer insulating layer 219 and the third gate insulating layer 232;​ As shown, the relative positional relationship between the first gate layer 218 and the first source / drain layer 221 and the connection positions thereof can be seen; as ​ shown, the relative positional relationship between the first source / drain layer 221 and the third via 413 can be seen. The third via 413 refers to the via in the passivation layer 222; as ​ shown, the relative positional relationship between the first source / drain layer 221, the third via 413 and the fourth via 414 can be seen. The fourth via 414 refers to the via in the first planarization layer 224; as ​ shown, the relative positional relationship between the first source / drain layer 221 and the second source / drain layer 223 and the connection positions thereof can be seen.

[0139] In some embodiments, as ​ shown, the first type of gate circuit 22a includes a first pull-up control module 311, a first pull-up module 312, a first pull-down module 313, a first pull-down maintenance module 314, a first inverting module 315, a first negative bias protection module 316 and a first reset module 317. The first pull-up control module 311 and the first pull-up module 312 are electrically connected to a first pull-up node Q1[n]. The first pull-down module 313 is electrically connected to the first pull-up node Q1[n] and a first signal output terminal Gn[n] of the first type of gate circuit 22a at the same stage. The first pull-down maintenance module 314 is electrically connected between the first pull-up node Q1[n] and a first low potential signal line VGL1. The first inverting module 315 is electrically connected to the first pull-up node Q1[n], the first low potential signal line VGL1 and a low-frequency signal line LC. The first negative bias protection module 316 is electrically connected between a first high potential signal line VGH1 and the first pull-up node Q1[n]. The first reset module 317 is electrically connected between the first pull-up node Q1[n] and the first low potential signal line VGL1.

[0140] In some embodiments, as ​ 、 ​As shown, at least two of the first pull-up control module 311, the first pull-up module 312, the first pull-down module 313, the first pull-down maintenance module 314, the first inverter module 315, the first negative bias protection module 316, and the first reset module 317 are arranged along the second direction, and the included angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees. By arranging at least two of the first pull-up control module 311, the first pull-up module 312, the first pull-down module 313, the first pull-down maintenance module 314, the first inverter module 315, the first negative bias protection module 316, and the first reset module 317 along the second direction, the lateral space occupied by the first type of gate circuit 22a can be shortened, thereby reducing the lateral space occupied by the gate drive circuit 22 and reducing the border of the display panel 2.

[0141] Specifically, compared with the horizontal arrangement of each module in the comparative display device, in the embodiment of the present application, by arranging at least two modules in the first type of gate circuit 22a along the second direction, the lateral space occupied by the first type of gate circuit 22a can be reduced, the lateral space occupied by the gate drive circuit 22 can be reduced, and the border of the display panel 2 can be reduced.

[0142] In some embodiments, as ​ 、 ​ shown, a part of the first pull-up control module 311, a part of the first inverter module 315, the first negative bias protection module 316, and the first reset module 317 are arranged along the second direction Y. By arranging a part of the first pull-up control module 311, a part of the first inverter module 315, the first negative bias protection module 316, and the first reset module 317 along the second direction Y, the lateral space occupied by the first pull-up control module 311, the first inverter module 315, the first negative bias protection module 316, and the first reset module 317 can be reduced, the lateral space occupied by the first type of gate circuit 22a can be reduced, the lateral space occupied by the gate drive circuit 22 can be reduced, and thus the border of the display panel 2 can be reduced.

[0143] Specifically, as ​ shown, it can be seen that in the second direction, a part of the first inverter module 315, the first reset module 317, the first negative bias protection module 316, and a part of the first pull-up control module 311 are arranged along the second direction.

[0144] In some embodiments, as ​ 、 ​As shown, another part of the first pull-up control module 311, another part of the first inverter module 315, and another part of the first pull-down maintenance module 314 are arranged along the second direction Y. By arranging another part of the first pull-up control module 311, another part of the first inverter module 315, and another part of the first pull-down maintenance module 314 along the second direction Y, the lateral space occupied by the first type of gate circuit 22a can be reduced, the lateral space occupied by the gate driving circuit 22 can be reduced, and thus the border of the display panel 2 can be reduced.

[0145] Specifically, as ​ shown, it can be seen that along the second direction Y, another part of the first inverter module 315, the first pull-down maintenance module 314, and another part of the first pull-up control module 311 are arranged in sequence, and the first pull-down maintenance module 314 is arranged between the first inverter module 315 and the first pull-up control module 311.

[0146] In some embodiments, as ​ 、 ​ shown, another part of the first pull-up control module 311, another part of the first inverter module 315, and a part of the first pull-down module 313 are arranged along the second direction Y, and the first reset module 317, the first pull-down maintenance module 314, and a part of the first pull-down module 313 are arranged along the first direction X. By arranging another part of the first pull-up control module 311, another part of the first inverter module 315, and a part of the first pull-down module 313 along the second direction Y, the lateral space occupied by the gate driving circuit 22 can be further reduced, and thus the border of the display panel 2 can be reduced.

[0147] Specifically, as ​ shown, it can be seen that another part of the first inverter module 315, a part of the first pull-down module 313, and another part of the first pull-up control module 311 are arranged in sequence along the second direction.

[0148] Specifically, as ​ shown, a part of the first inverter module 315 and a part of the first pull-up control module 311 are arranged along the second direction, and another part of the first inverter module 315 and another part of the first pull-up control module 311 are arranged along the second direction.

[0149] In some embodiments, as ​ 、 ​As shown, a part of the first pull-up module 312 and another part of the first pull-down module 313 are arranged along the second direction Y. By arranging a part of the first pull-up module 312 and another part of the first pull-down module 313 along the second direction Y, the lateral space occupied by the gate driving circuit 22 can be further reduced, thereby reducing the border of the display panel 2.

[0150] Specifically, as ​ shown, it can be seen that a part of the first pull-up module 312 and another part of the first pull-down module 313 are arranged in sequence along the second direction Y.

[0151] In some embodiments, as ​ 、 ​ shown, the first pull-up control module 311 includes a first pull-up control transistor T11j, a second pull-up control transistor T12j, and a third pull-up control transistor T81j. The gate T11jG of the first pull-up control transistor T11j is electrically connected to the stage transmission output terminal Cout[n - 2] of the upper two-stage first type of gate circuit 22a. The first electrode T11jS of the first pull-up control transistor T11j is electrically connected to the first high-potential signal line VGH1. The second electrode T11jD of the first pull-up control transistor T11j is electrically connected to the first electrode T12jS of the second pull-up control transistor T12j. The gate T12jG of the second pull-up control transistor T12j is electrically connected to the stage transmission output terminal Cout[n - 2] of the upper two-stage first type of gate circuit 22a. The second electrode T12jD of the second pull-up control transistor T12j is electrically connected to the first pull-up node Q1[n]. The gate T81jG of the third pull-up control transistor T81j is electrically connected to the first high-potential signal line VGH1. The first electrode T81jS of the third pull-up control transistor T81j is electrically connected to the first high-potential signal line VGH1. The second electrode T81jD of the third pull-up control transistor T81j is electrically connected to the second electrode T11jD of the first pull-up control transistor T11j;

[0152] Among them, in each stage of the gate driving circuit 22, the first pull-up control transistor T11j and the second pull-up control transistor T12j are arranged in sequence along the second direction, and the first pull-up control transistor T11j and the third pull-up control transistor T81j are arranged in sequence along the first direction. By arranging the first pull-up control transistor T11j and the second pull-up control transistor T12j in sequence along the second direction, the space occupied by the first pull-up control module 311 can be reduced, thereby reducing the border of the display panel 2.

[0153] In some embodiments, as ​ 、​ As shown, the third pull-up control transistor T81j includes a first pull-up control sub-transistor T81j1 and a second pull-up control sub-transistor T81j2. The gate T81j2G of the second pull-up control sub-transistor T81j2 and the first electrode T81j2S of the second pull-up control sub-transistor T81j2 are electrically connected to the first high-potential signal line VGH1. The second electrode T81j2D of the second pull-up control sub-transistor T81j2 is electrically connected to the first electrode of the first pull-up control sub-transistor T81j1. The gate T81j1G of the first pull-up control sub-transistor T81j1 is electrically connected to the first high-potential signal line VGH1. The second electrode T81j1D of the first pull-up control sub-transistor T81j1 is electrically connected to the second electrode T11jD of the first pull-up control transistor T11j;

[0154] Wherein, the first pull-up control sub-transistor T81j1 and the second pull-up control sub-transistor T81j2 are arranged along the second direction. By making the third pull-up control transistor T81j include the first pull-up control sub-transistor T81j1 and the second pull-up control sub-transistor T81j2, the performance of the third pull-up control transistor T81j can be improved, and the first pull-up control sub-transistor T81j1 and the second pull-up control sub-transistor T81j2 are arranged along the first direction, which can reduce the lateral area occupied by the third pull-up control transistor T81j and reduce the border of the display panel 2.

[0155] Specifically, the first pull-up control sub-transistor T81j1 and the second pull-up control sub-transistor T81j2 can be regarded as two independent transistors, or can be regarded as two sub-transistors in the third pull-up control transistor T81j. Similarly, the other sub-transistors can also refer to the above description and will not be elaborated in the following embodiments.

[0156] Specifically, when a transistor has multiple sub-transistors, the first electrode of the transistor is the electrode connected to the signal line. For example, the third pull-up control transistor T81j includes the first pull-up control sub-transistor T81j1 and the second pull-up control sub-transistor T81j2. Since the first electrode T81j2S of the second pull-up control sub-transistor T81j2 is electrically connected to the first high-potential signal line VGH1, the first electrode T81jS of the third pull-up control transistor T81j is the first electrode T81j2S of the second pull-up control sub-transistor T81j2. Similarly, the first electrodes of other transistors can be determined.

[0157] Specifically, the multi-stage gate drive circuit 22 includes a multi-stage first-class gate circuit 22a. In the first-stage first-class gate circuit 22a, the gate T11jG of the first pull-up control transistor T11j can be connected to the start signal line. In other stages of the first-class gate circuit 22a, the gate T11jG of the first pull-up control transistor T11j and the gate T12jG of the second pull-up control transistor T12j are connected to the first signal output ends of the two upper stages of the first-class gate circuit 22a, and the first electrode T11jS of the first pull-up control transistor T11j and the first electrode T12jS of the second pull-up control transistor T12j are electrically connected to the first high-potential signal line VGH1.

[0158] In some embodiments, as ​ 、 ​ As shown, the first pull-down module 313 includes a first pull-down transistor T31j, a second pull-down transistor T32j, a third pull-down transistor T33j and a fourth pull-down transistor T41j, the gate T31jG of the first pull-down transistor T31j is electrically connected to the first pull-down node QB1[n], the first electrode T31jS of the first pull-down transistor T31j is electrically connected to the first low-potential signal line VGL1, the second electrode T31jD of the first pull-down transistor T31j is electrically connected to the stage transmission output terminal Cout[n] of the first-type gate circuit 22a of this stage, the gate T32jG of the second pull-down transistor T32j is electrically connected to the first pull-down node QB1[n], the first electrode T32jS of the second pull-down transistor T32j is electrically connected to the second low-potential signal line VGL2, and the second electrode T32jD of the second pull-down transistor T32j is electrically connected to another The first signal output terminal Gn[m] of the first-stage first-type gate circuit 22a is electrically connected, the gate T33jG of the third pull-down transistor T33j is electrically connected to the first pull-down node QB1[n], the first electrode T33jS of the third pull-down transistor T33j is electrically connected to the second low-potential signal line VGL2, and the second electrode T33jD of the third pull-down transistor T33j is electrically connected to the first signal output terminal Gn[n] of the first-stage first-type gate circuit 22a of the current stage; the gate T41jG of the fourth pull-down transistor T41j is electrically connected to the stage transmission output terminal Cout[n+2] of the first-stage first-type gate circuit 22a of the next two stages, the first electrode T41jS of the fourth pull-down transistor T41j is electrically connected to the first low-potential signal line VGL1, and the second electrode T41jD of the fourth pull-down transistor T41j is electrically connected to the first pull-up node Q1[n].

[0159] Among them, the first pull-down transistor T31j and the fourth pull-down transistor T41j are arranged along the second direction, and the second pull-down transistor T32j and the third pull-down transistor T33j are arranged along the second direction. By arranging the first pull-down transistor T31j and the fourth pull-down transistor T41j along the second direction, and the second pull-down transistor T32j and the third pull-down transistor T33j along the second direction, the space occupied by the first pull-down module 313 can be reduced, and the border of the display panel 2 can be reduced.

[0160] In some embodiments, such as ​ , ​ shown, the fourth pull-down transistor T41j includes a first pull-down sub-transistor T41j1 and a second pull-down sub-transistor T41j2. The gate T41j2G of the second pull-down sub-transistor T41j2 is electrically connected to the stage transmission output terminal Cout[n + 2] of the next two stages of the first type of gate circuit 22a. The first electrode T41j2S of the second pull-down sub-transistor T41j2 is electrically connected to the first low-potential signal line VGL1. The second electrode T41j2D of the second pull-down sub-transistor T41j2 is electrically connected to the first electrode T41j1S of the first pull-down sub-transistor T41j1 at a first internal node N1[n]. The gate T41j1G of the first pull-down sub-transistor T41j1 is electrically connected to the stage transmission output terminal Cout[n + 2] of the next two stages of the first type of gate circuit 22a. The second electrode T41j1D of the first pull-down sub-transistor T41j1 is electrically connected to the first pull-up node Q1[n];

[0161] Among them, the first pull-down sub-transistor T41j1 and the second pull-down sub-transistor T41j2 are arranged along the second direction. By making the fourth pull-down transistor T41j include the first pull-down sub-transistor T41j1 and the second pull-down sub-transistor T41j2, the performance of the fourth pull-down transistor T41j can be improved, and since the first pull-down sub-transistor T41j1 and the second pull-down sub-transistor T41j2 are arranged along the second direction, the lateral area occupied by the fourth pull-down transistor T41j can be reduced, and the border of the display panel 2 can be reduced.

[0162] In some embodiments, such as ​ , ​As shown, the first inverter module 315 includes a first inverter transistor T51j, a second inverter transistor T52j, a third inverter transistor T53j, a fourth inverter transistor T54j, and a fifth inverter transistor T55j. The gate T51jG of the first inverter transistor T51j and the first electrode T51jS of the first inverter transistor T51j are electrically connected to the low-frequency signal line LC. The second electrode T51jD of the first inverter transistor T51j is electrically connected to the second electrode T52jD of the second inverter transistor T52j. The gate T52jG of the second inverter transistor T52j is electrically connected to the first pull-up node Q1[n]. The first electrode T52jS of the second inverter transistor T52j is electrically connected to the first low-potential signal line VGL1. The gate T53jG of the third inverter transistor T53j is electrically connected to the second electrode T51jD of the first inverter transistor T51j. The first electrode T53jS of the third inverter transistor T53j is electrically connected to the low-frequency signal line LC. The second electrode T53jD of the third inverter transistor T53j is electrically connected to the first pull-down node QB1[n]. The gate T54jG of the fourth inverter transistor T54j is electrically connected to the first pull-up node Q1[n]. The first electrode T54jS of the fourth inverter transistor T54j is electrically connected to the first low-potential signal line VGL1. The second electrode T54jD of the fourth inverter transistor T54j is electrically connected to the first pull-down node QB1[n]. The gate T55jG of the fifth inverter transistor T55j is electrically connected to the stage transmission output Cout[n - 2] of the upper two-stage first type of gate circuit 22a. The first electrode T55jS of the fifth inverter transistor T55j is electrically connected to the first low-potential signal line VGL1. The second electrode T55jD of the fifth inverter transistor T55j is electrically connected to the first pull-down node QB1[n];

[0163] Among them, the first inverter transistor T51j and the second inverter transistor T52j are arranged along the second direction, the third inverter transistor T53j and the fourth inverter transistor T54j are arranged along the second direction, and the second inverter transistor T52j, the fourth inverter transistor T54j, and the fifth inverter transistor T55j are arranged along the first direction. By arranging the first inverter transistor T51j and the second inverter transistor T52j along the second direction, and arranging the third inverter transistor T53j and the fourth inverter transistor T54j along the second direction, the lateral space occupied by the first inverter module 315 can be reduced, thereby reducing the border of the display panel 2.

[0164] In some embodiments, such as ​ 、 ​As shown, the first inverter transistor T51j includes a first inverter sub-transistor T51j1 and a second inverter sub-transistor T51j2. The gate T51j1G of the first inverter sub-transistor T51j1 and the first electrode T51j1S of the first inverter sub-transistor T51j1 are electrically connected to the low-frequency signal line LC. The second electrode T51j1D of the first inverter sub-transistor T51j1 is electrically connected to the first electrode of the second inverter sub-transistor T51j2. The gate T51j2G of the second inverter sub-transistor T51j2 is electrically connected to the low-frequency signal line LC. The second electrode T51j2D of the second inverter sub-transistor T51j2 is electrically connected to the second electrode T52jD of the second inverter transistor T52j;

[0165] Wherein, the first inverter sub-transistor T51j1 and the second inverter sub-transistor T51j2 are arranged along a first direction. By making the first inverter transistor T51j include the first inverter sub-transistor T51j1 and the second inverter sub-transistor T51j2, the performance of the first inverter transistor T51j can be improved.

[0166] In some embodiments, as ​ 、 ​ shown, the first pull-down maintaining module 314 includes a first pull-down maintaining transistor T42j. The gate T42jG of the first pull-down maintaining transistor T42j is electrically connected to the first pull-down node QB1[n] of the first type of gate circuit. The first electrode T42jS of the first pull-down maintaining transistor T42j is electrically connected to the first low-potential signal line VGL1. The second electrode T42jD of the first pull-down maintaining transistor T42j is electrically connected to the first pull-up node Q1[n];

[0167] Wherein, in a second direction, the first pull-down maintaining transistor T42j is arranged between the fourth inverter transistor T54j and the second pull-up control transistor T12j; thereby, the lateral space occupied by the first pull-down maintaining transistor T42j arranged between the fourth inverter transistor T54j and the second pull-up control transistor T12j can be reduced, and the border of the display panel 2 can be reduced.

[0168] In some embodiments, as ​ 、 ​As shown, the first pull-down holding transistor T42j includes a first pull-down holding sub-transistor T42j1 and a second pull-down holding sub-transistor T42j2. The gate T42j2G of the second pull-down holding sub-transistor T42j2 is electrically connected to the first pull-down node QB1[n]. The first electrode T42j2S of the second pull-down holding sub-transistor T42j2 is electrically connected to the first low potential signal line VGL1. The second electrode T42j2D of the second pull-down holding sub-transistor T42j2 is electrically connected to the first electrode T42j1S of the first pull-down holding sub-transistor T42j1 at a first internal node N1[n]. The gate T42j1G of the first pull-down holding sub-transistor T42j1 is electrically connected to the first pull-down node QB1[n]. The second electrode of the first pull-down holding sub-transistor T42j1 is electrically connected to the first pull-up node Q1[n].

[0169] Wherein, the first pull-down holding sub-transistor T42j1 and the second pull-down holding sub-transistor T42j2 are arranged along a second direction. By making the first pull-down holding transistor T42j include the first pull-down holding sub-transistor T42j1 and the second pull-down holding sub-transistor T42j2, the performance of the first pull-down holding transistor T42j can be improved. And since the first pull-down holding sub-transistor T42j1 and the second pull-down holding sub-transistor T42j2 are arranged along the second direction, the lateral space occupied by the first pull-down holding transistor T42j can be reduced, and the border of the display panel 2 can be reduced.

[0170] In some embodiments, as ​ 、 ​ shown, the first reset module 317 includes a first reset transistor T43j. The gate T43jG of the first reset transistor T43j is electrically connected to the first reset control line VST1 of the display panel. The first electrode T43jS of the first reset transistor T43j is electrically connected to the first low potential signal line VGL1. The second electrode T43jD of the first reset transistor T43j is electrically connected to the first pull-up node Q1[n].

[0171] Wherein, the first reset transistor T43j is arranged between the second inverter transistor T52j and the third pull-up control transistor T81j. By making the first reset transistor T43j arranged between the second inverter transistor T52j and the third pull-up control transistor T81j, the lateral space occupied by the first reset transistor T43j, the second inverter transistor T52j and the third pull-up control transistor T81j is reduced, thereby reducing the border of the display panel 2.

[0172] In some embodiments, as ​ 、 ​As shown, the first reset transistor T43j includes a first reset sub-transistor T43j1 and a second reset sub-transistor T43j2. The gate T43j1G of the second reset sub-transistor T43j2 is electrically connected to the first reset control line VST1. The first electrode of the second reset sub-transistor T43j2 is electrically connected to the first low potential signal line VGL1. The second electrode T43j1D of the first reset sub-transistor T43j1 is electrically connected to the first electrode T43j1S of the first reset sub-transistor T43j1 at the first internal node N1[n]. The gate T43j1G of the first reset sub-transistor T43j1 is electrically connected to the first reset control line VST1. The second electrode T43j1D of the first reset sub-transistor T43j1 is electrically connected to the first pull-up node Q1[n].

[0173] Wherein, the first reset sub-transistor T43j1 and the second reset sub-transistor T43j2 are arranged along the second direction. By making the first reset transistor T43j include the first reset sub-transistor T43j1 and the second reset sub-transistor T43j2, the performance of the first reset transistor T43j can be improved. And the first reset sub-transistor T43j1 and the second reset sub-transistor T43j2 are arranged along the second direction, which can reduce the lateral space occupied by the first reset transistor T43j and reduce the border of the display panel 2.

[0174] In some embodiments, as ​ 、 ​ shown, the first negative bias prevention module 316 includes a first negative bias prevention transistor T71j. The gate T71jG of the first negative bias prevention transistor T71j is electrically connected to the first pull-up node Q1[n]. The first electrode T71jS of the first negative bias prevention transistor T71j is electrically connected to the first high potential signal line VGH1. The second electrode T71jD of the first negative bias prevention transistor T71j is electrically connected to the first internal node N1[n].

[0175] Wherein, the first negative bias prevention transistor T71j is arranged along the second direction between the first reset transistor T43j and the third pull-up control transistor T81j. By making the first negative bias prevention transistor T71j be arranged along the second direction between the first reset transistor T43j and the third pull-up control transistor T81j, the lateral area occupied by the first negative bias prevention module 316 can be reduced, and the border of the display panel 2 can be reduced.

[0176] In some embodiments, as ​ 、 ​As shown, the first negative-bias protection transistor T71j includes a first negative-bias protection sub-transistor T71j1 and a second negative-bias protection sub-transistor T71j2. The gate T71j2G of the second negative-bias protection sub-transistor T71j2 is electrically connected to the first pull-up node Q1[n]. The first electrode T71j2S of the second negative-bias protection sub-transistor T71j2 is electrically connected to the first high-potential signal line. The second electrode T71j2D of the second negative-bias protection sub-transistor T71j2 is electrically connected to the first electrode of the first negative-bias protection sub-transistor T71j1. The gate T71j1G of the first negative-bias protection sub-transistor T71j1 is electrically connected to the first pull-up node Q1[n]. The second electrode T71j1D of the first negative-bias protection sub-transistor T71j1 is electrically connected to the first internal node N1[n].

[0177] Wherein, the first negative-bias protection sub-transistor T71j1 and the second negative-bias protection sub-transistor T71j2 are arranged along the second direction. By making the first negative-bias protection transistor T71j include the first negative-bias protection sub-transistor T71j1 and the second negative-bias protection sub-transistor T71j2, the performance of the first negative-bias protection transistor T71j can be improved. Moreover, since the first negative-bias protection sub-transistor T71j1 and the second negative-bias protection sub-transistor T71j2 are arranged along the second direction, the lateral space occupied by the first negative-bias protection transistor T71j can be reduced, and the border of the display panel 2 can be decreased.

[0178] In some embodiments, such as ​ 、 ​ 、 ​As shown, the second clock signal line CKB includes a first group of sub-lines CKBi and a second group of sub-lines CKBj. The first pull-up module 312 includes a first pull-up transistor T21j, a second pull-up transistor T22j, and a third pull-up transistor T23j. The gate T21jG of the first pull-up transistor T21j is electrically connected to the first pull-up node Q1[n]. The first electrode T21jS of the first pull-up transistor T21j is electrically connected to the first clock signal line CKA. The second electrode T21jD of the first pull-up transistor T21j is electrically connected to the stage output terminal Cout[n] of the first type of gate circuit 22a at this stage. The gate T22jG of the second pull-up transistor T22j is electrically connected to the first pull-up node Q1[n]. The first electrode T22jS of the second pull-up transistor T22j is electrically connected to the first group of sub-lines CKBi. The second electrode T22jD of the second pull-up transistor T22j is electrically connected to the first signal output terminal Gn[m] of another stage of the first type of gate circuit 22a. The gate T23jG of the third pull-up transistor T23j is electrically connected to the first pull-up node Q1[n]. The first electrode T23jS of the third pull-up transistor T23j is electrically connected to the second group of sub-lines CKBj. The second electrode T23jD of the third pull-up transistor T23j is electrically connected to the first signal output terminal Gn[n] of the first type of gate circuit 22a at this stage;

[0179] Wherein, the first pull-up transistor T21j and the second pull-down transistor T32j are arranged along the second direction Y. The second pull-up transistor T22j and the third pull-up transistor T23j are arranged along the second direction Y. The first pull-up transistor T21j and the second pull-up transistor T22j are arranged along the first direction X. By arranging the first pull-up transistor T21j and the second pull-down transistor T32j along the second direction Y, and arranging the second pull-up transistor T22j and the third pull-up transistor T23j along the second direction Y, the lateral area occupied by the first pull-down module and the first pull-up module can be reduced, and the border of the display panel 2 can be reduced.

[0180] In some embodiments, as ​ 、 ​ shown, the first inverter transistor T51j, the second inverter transistor T52j, the first reset transistor T43j, the first negative-bias protection transistor T71j, and the third pull-up control transistor T81j are arranged along the second direction Y;

[0181] The third inverter transistor T53j, the fourth inverter transistor T54j, the fourth pull-down transistor T42j, the second pull-up control transistor T12j, and the first pull-up control transistor T11j are arranged along the second direction;

[0182] The fifth inverter transistor T55j, the first pull-down transistor T31j, the fourth pull-down transistor T41j, the second pull-up control transistor T12j, and the first pull-up control transistor T11j are arranged along the second direction Y;

[0183] The second inverter transistor T52j, the fourth inverter transistor T54j, the fifth inverter transistor T55j, the first pull-up transistor T21j, and the second pull-up transistor T22j are arranged along the first direction X; such that different transistors can be arranged along the second direction, reducing the lateral space occupied by the first type of gate circuit and reducing the border of the display panel.

[0184] In some embodiments, as ​ shown, the first type of gate circuit 22a further includes a first capacitor C1. One plate of the first capacitor C1 is electrically connected to the first pull-up node Q1[n], and the other plate of the first capacitor C1 is electrically connected to the stage transmission output Cout[n] of the first type of gate circuit 22a of this stage.

[0185] Specifically, the first capacitor includes a first plate of the first capacitor and a second plate of the first capacitor. The first plate of the first capacitor includes a first part of the first plate of the first capacitor and a second part of the first plate of the first capacitor.

[0186] In some embodiments, as ​ 、 ​ shown, the display panel 2 includes a light-shielding layer 212. The light-shielding layer includes a first light-shielding connection line LS1, a second light-shielding connection line LS2, the stage transmission output Cout[n] of the first type of gate circuit 22a of this stage, and a first part C1a1 of the first plate C1a of the first capacitor C1.

[0187] In some embodiments, as ​ 、 ​As shown, the display panel 2 includes an active layer 216, and the active layer 216 includes the active part T11jA of the first pull-up control transistor T11j, the active part T12jA of the second pull-up control transistor T12j, the active part T81jA of the third pull-up control transistor T81j, the active part T21jA of the first pull-up transistor T21j, the active part T22jA of the second pull-up transistor T22j, the active part T23jA of the third pull-up transistor T23j, the active part T31jA of the first pull-down transistor T31j, the active part T32jA of the second pull-down transistor T32j, the active part T33jA of the third pull-down transistor T33j, the active part T41jA of the fourth pull-down transistor T41j, the active part T42jA of the first pull-down maintenance transistor T42j, the active part T51jA of the first inverter transistor T51j, the active part T52jA of the second inverter transistor T52j, the active part T53jA of the third inverter transistor T53j, the active part T54jA of the fourth inverter transistor T54j, the active part T55jA of the fifth inverter transistor T55j, the active part T43jA of the first reset transistor T43j, and the active part T71jA of the first negative-bias protection transistor T71j;

[0188] Among them, the active part T51jA of the first inverter transistor T51j, the active part T52jA of the second inverter transistor T52j, the active part T43jA of the first reset transistor T43j, the active part T71jA of the first negative-bias protection transistor T71j, and the active part T81jA of the third pull-up control transistor T81j are arranged in sequence along the second direction Y;

[0189] The active part T53jA of the third inverter transistor T53j, the active part T54jA of the fourth inverter transistor T54j, the active part T42jA of the first pull-down maintenance transistor T42j, the active part T12jA of the second pull-up control transistor T12j, and the active part T11jA of the first pull-up control transistor T11j are arranged in sequence along the second direction Y;

[0190] The active part T55jA of the fifth inverter transistor T55j, the active part T31jA of the first pull-down transistor T31j, the active part T41jA of the fourth pull-down transistor T41j, the active part T12jA of the second pull-up control transistor T12j, and the active part T11jA of the first pull-up control transistor T11j are arranged in sequence along the second direction Y;

[0191] The active part T21jA of the first pull-up transistor T21j, the active part T33jA of the third pull-down transistor T33j, and the active part T32jA of the second pull-down transistor T32j are arranged in sequence along the second direction.

[0192] The active part T22jA of the second pull-up transistor T22j and the active part T23jA of the third pull-up transistor T23j are arranged in sequence along the second direction;

[0193] The active part T52jA of the second inverter transistor T52j, the active part T54jA of the fourth inverter transistor T54j, the active part T55jA of the fifth inverter transistor T55j, the active part T21jA of the first pull-up transistor T21j, and the active part T22jA of the second pull-up transistor T22j are arranged in sequence along the first direction.

[0194] Specifically, as ​ shown, the active part T81jA of the third pull-up control transistor T81j includes the active part T81j1A of the first pull-up control sub-transistor T81j1 and the active part T81j2A of the second pull-up control sub-transistor T81j2, and the active part T81j1A of the first pull-up control sub-transistor T81j1 and the active part T81j2A of the second pull-up control sub-transistor T81j2 are arranged in sequence along the second direction.

[0195] Specifically, as ​ shown, the active part T41jA of the fourth pull-down transistor T41j includes the active part T41j1A of the first pull-down sub-transistor T41j1 and the active part T41j2A of the second pull-down sub-transistor T41j2, and the active part T41j1A of the first pull-down sub-transistor T41j1 and the active part T41j2A of the second pull-down sub-transistor T41j2 are arranged along the second direction.

[0196] Specifically, as ​ shown, the active part T42jA of the first pull-down holding transistor T42j includes the active part T42j1A of the first pull-down holding sub-transistor T42j1 and the active part T42j2A of the second pull-down holding sub-transistor T42j2, and the active part T42j1A of the first pull-down holding sub-transistor T42j1 and the active part T42j2A of the second pull-down holding sub-transistor T42j2 are arranged along the second direction.

[0197] Specifically, as ​ shown, the active part T43jA of the first reset transistor T43j includes the active part T43j1A of the first reset sub-transistor T43j1 and the active part T43j2A of the second reset sub-transistor T43j2, and the active part T43j1A of the first reset sub-transistor T43j1 and the active part T43j2A of the second reset sub-transistor T43j2 are arranged along the second direction.

[0198] Specifically, as ​As shown, the active part T51jA of the first inverter transistor T51j includes the active part T51j1A of the first inverter sub-transistor T51j1 and the active part T51j2A of the second inverter sub-transistor T51j2. The active part T51j1A of the first inverter sub-transistor T51j1 and the active part T51j2A of the second inverter sub-transistor T51j2 are arranged along a first direction.

[0199] Specifically, as ​ shown, the active part T71jA of the first negative-bias protection transistor T71j includes the active part T71j1A of the first negative-bias protection sub-transistor T71j1 and the active part T71j2A of the second negative-bias protection sub-transistor T71j2. The active part T71j1A of the first negative-bias protection sub-transistor T71j1 and the active part T71j2A of the second negative-bias protection sub-transistor T71j2 are arranged along the first direction.

[0200] In some embodiments, as ​ 、 ​ shown, the display panel 2 includes a first gate layer 218. The first gate layer 218 includes the gate T11jG of the first pull-up control transistor T11j, the gate T12jG of the second pull-up control transistor T12j, the gate T81jG of the third pull-up control transistor T81j, the gate T21jG of the first pull-up transistor T21j, the gate T22jG of the second pull-up transistor T22j, the gate T23jG of the third pull-up transistor T23j, the gate T31jG of the first pull-down transistor T31j, the gate T32jG of the second pull-down transistor T32j, the gate T33jG of the third pull-down transistor T33j, the gate T41jG of the fourth pull-down transistor T41j, the gate T42jG of the first pull-down holding transistor T42j, the gate T51jG of the first inverter transistor T51j, the gate T52jG of the second inverter transistor T52j, the gate T53jG of the third inverter transistor T53j, the gate T54jG of the fourth inverter transistor T54j, the gate T55jG of the fifth inverter transistor T55j, the gate T43jG of the first reset transistor T43j, the gate T71jG of the first negative-bias protection transistor T71j, the second electrode plate C1b of the first capacitor C1, and the first gate connection line LE1;

[0201] Among them, the gate T51jG of the first inverter transistor T51j, the gate T52jG of the second inverter transistor T52j, the gate T43jG of the first reset transistor T43j, the gate T71jG of the first negative-bias protection transistor T71j, and the gate T81jG of the third pull-up control transistor T81j are arranged along the first direction Y;

[0202] The gates T53jG of the third inverter transistor T53j, the gates T54jG of the fourth inverter transistor T54j, the gates T42jG of the first pull-down maintenance transistor T42j, the gates T12jG of the second pull-up control transistor T12j, and the gates T11jG of the first pull-up control transistor T11j are arranged along the second direction Y;

[0203] The gates T55jG of the fifth inverter transistor T55j, the gates T31jG of the first pull-down transistor T31j, the gates T41jG of the fourth pull-down transistor T41j, the gates T12jG of the second pull-up control transistor T12j, and the gates T11jG of the first pull-up control transistor T11j are arranged along the second direction Y;

[0204] The gates T21jG of the first pull-up transistor T21j, a part of the second electrode plate C1b of the first capacitor C1, the gates T33jG of the third pull-down transistor T33j, and the gates T32jG of the second pull-down transistor T32j are arranged in sequence along the second direction Y;

[0205] The gates T22jG of the second pull-up transistor T22j and the gates T23jG of the third pull-up transistor T23j are arranged in sequence along the second direction Y;

[0206] The gates T52jG of the second inverter transistor T52j, the gates T54jG of the fourth inverter transistor T54j, the gates T55jG of the fifth inverter transistor T55j, the gates T21jG of the first pull-up transistor T21j, another part of the second electrode plate C1b of the first capacitor C1, and the gates T22jG of the second pull-up transistor T22j are arranged in sequence along the first direction X.

[0207] Specifically, as ​ shown, the gate T81jG of the third pull-up control transistor T81j includes the gate T81j1G of the first pull-up control sub-transistor T81j1 and the gate T81j2G of the second pull-up control sub-transistor T81j2, and the gate T81j1G of the first pull-up control sub-transistor T81j1 and the gate T81j2G of the second pull-up control sub-transistor T81j2 are arranged in sequence along the second direction.

[0208] Specifically, as ​ shown, the gate T41jG of the fourth pull-down transistor T41j includes the gate T41j1G of the first pull-down sub-transistor T41j1 and the gate T41j2G of the second pull-down sub-transistor T41j2, and the gate T41j1G of the first pull-down sub-transistor T41j1 and the gate T41j2G of the second pull-down sub-transistor T41j2 are arranged along the second direction.

[0209] Specifically, as ​As shown, the gate T42jG of the first pull-down holding transistor T42j includes the gate T42j1G of the first pull-down holding sub-transistor T42j1 and the gate T42j2G of the second pull-down holding sub-transistor T42j2. The gate T42j1G of the first pull-down holding sub-transistor T42j1 and the gate T42j2G of the second pull-down holding sub-transistor T42j2 are arranged along the second direction.

[0210] Specifically, as ​ shown, the gate T43jG of the first reset transistor T43j includes the gate T43j1G of the first reset sub-transistor T43j1 and the gate T43j1G of the second reset sub-transistor T43j2. The gate T43j1G of the first reset sub-transistor T43j1 and the gate T43j1G of the second reset sub-transistor T43j2 are arranged along the second direction.

[0211] Specifically, as Figure 27 shown, the gate T51jG of the first inverter transistor T51j includes the gate T51j1G of the first inverter sub-transistor T51j1 and the gate T51j2G of the second inverter sub-transistor T51j2. The gate T51j1G of the first inverter sub-transistor T51j1 and the gate T51j2G of the second inverter sub-transistor T51j2 are arranged along the first direction.

[0212] Specifically, as Figure 27 shown, the gate T71jG of the first negative-bias protection transistor T71j includes the gate T71j1G of the first negative-bias protection sub-transistor T71j1 and the gate T71j2G of the second negative-bias protection sub-transistor T71j2. The gate T71j1G of the first negative-bias protection sub-transistor T71j1 and the gate T71j2G of the second negative-bias protection sub-transistor T71j2 are arranged along the first direction.

[0213] In some embodiments, as Figure 24 、 Figure 28As shown, the display panel 2 includes a first source-drain layer 221, and the first source-drain layer 221 includes the first electrode T11jS of the first pull-up control transistor T11j, the first electrode T12jS of the second pull-up control transistor T12j, the first electrode T81jS of the third pull-up control transistor T81j, the first electrode T21jS of the first pull-up transistor T21j, the first electrode T22jS of the second pull-up transistor T22j, the first electrode T23jS of the third pull-up transistor T23j, the first electrode T31jS of the first pull-down transistor T31j, the first electrode T32jS of the second pull-down transistor T32j, the first electrode T33jS of the third pull-down transistor T33j, the first electrode T41jS of the fourth pull-down transistor T41j, the first electrode T42jS of the first pull-down holding transistor T42j, the first electrode T51jS of the first inverter transistor T51j, the first electrode T52jS of the second inverter transistor T52j, the first electrode T53jS of the third inverter transistor T53j, the first electrode T54jS of the fourth inverter transistor T54j, the first electrode T55jS of the fifth inverter transistor T55j, the first electrode T43jS of the first reset transistor T43j, the first electrode T71jS of the first negative-bias protection transistor T71j, the second electrode T11jD of the first pull-up control transistor T11j, the second electrode T12jD of the second pull-up control transistor T12j, the second electrode T81jD of the third pull-up control transistor T81j, the second electrode T21jD of the first pull-up transistor T21j, the second electrode T22jD of the second pull-up transistor T22j, the second electrode T23jD of the third pull-up transistor T23j, the second electrode T31jD of the first pull-down transistor T31j, the second electrode T32jD of the second pull-down transistor T32j, the second electrode T33jD of the third pull-down transistor T33j, the second electrode T41jD of the fourth pull-down transistor T41j, the second electrode T42jD of the first pull-down holding transistor T42j, the second electrode T51jD of the first inverter transistor T51j, the second electrode T52jD of the second inverter transistor T52j, the second electrode T53jD of the third inverter transistor T53j, the second electrode T54jD of the fourth inverter transistor T54j, the second electrode T55jD of the fifth inverter transistor T55j, the second electrode T43jD of the first reset transistor T43j, the second electrode T71jD of the first negative-bias protection transistor T71j, the second part C1a2 of the first plate C1a of the first capacitor C1, the first source connection line LD1, the second source connection line LD2, the third source connection line LD3, the fourth source connection line LD4, and the fifth source connection line LD5;

[0214] Among them, the first electrodes T51jS of the first inverter transistor T51j, the first electrodes T52jS of the second inverter transistor T52j, the first electrodes T43jS of the first reset transistor T43j, the first electrodes T71jS of the first negative bias protection transistor T71j, and the first electrodes T81jS of the third pull-up control transistor T81j are arranged in sequence along the second direction Y;

[0215] The first electrodes T53jS of the third inverter transistor T53j, the first electrodes T54jS of the fourth inverter transistor T54j, the first electrodes T42jS of the first pull-down maintenance transistor T42j, the first electrodes T12jS of the second pull-up control transistor T12j, and the first electrodes T11jS of the first pull-up control transistor T11j are arranged in sequence along the second direction Y;

[0216] The first electrodes T55jS of the fifth inverter transistor T55j, the first electrodes T31jS of the first pull-down transistor T31j, the first electrodes T41jS of the fourth pull-down transistor T41j, the first electrodes T12jS of the second pull-up control transistor T12j, and the first electrodes T11jS of the first pull-up control transistor T11j are arranged in sequence along the second direction Y;

[0217] The first electrodes T21jS of the first pull-up transistor T21j, the first electrodes T33jS of the third pull-down transistor T33j, and the first electrodes T32jS of the second pull-down transistor T32j are arranged in sequence along the second direction Y;

[0218] The first electrodes T22jS of the second pull-up transistor T22j and the first electrodes T23jS of the third pull-up transistor T23j are arranged in sequence along the second direction Y;

[0219] The first electrodes T52jS of the second inverter transistor T52j, the first electrodes T54jS of the fourth inverter transistor T54j, the first electrodes T55jS of the fifth inverter transistor T55j, the first electrodes T21jS of the first pull-up transistor T21j, and the first electrodes T22j of the second pull-up transistor T22j are arranged in sequence along the first direction;

[0220] The second source connection line LD2 connects the gate T55jG of the fifth inverter transistor T55j and the stage transmission signal terminal Cout[n-2] of the upper two stages of the first type of gate circuit 22a. The third source connection line LD3 connects the gate T32jG of the second pull-down transistor T32j and the first shielding connection line LS1. The first shielding connection line LS1 connects the second electrode T55jD of the fifth inverter transistor T55j. The fourth source connection line LD4 connects the gate T41jG of the fourth pull-down transistor T41j and the stage transmission signal terminal Cout[n+2] of the lower two stages of the first type of gate circuit 22a. The second shielding connection line LS2 connects the first electrode T55jS of the fourth inverter transistor T54j and the first electrode T31jS of the first pull-down transistor T31j.

[0221] Specifically, in the circuit diagram of the embodiment of the present application, in order to illustrate the connection relationship of each transistor, each transistor has a gate, a first electrode, and a second electrode. However, in the actual design process, in order to reduce the occupied space of the transistor, the electrodes of some transistors are formed by the same structure. For example, the first electrode of the first pull-up control sub-transistor T81j1 and the second electrode T81j2D of the second pull-up control sub-transistor T81j2 can be formed by the same structure. Therefore, in the figure, the second electrode T81j2D of the second pull-up control sub-transistor T81j2 is marked. It can be understood that this structure is also the first electrode of the first pull-up control sub-transistor T81j1. Similarly, the structures of the electrodes of other transistors can be determined.

[0222] Specifically, as Figures 24 to 29 shown, the first part C1a1 of the first plate C1a of the first capacitor C1 is connected to the second part C1a2 of the first plate C1a of the first capacitor C1.

[0223] Specifically, as Figures 24 to 29 shown, the first plate of the first capacitor C1 includes the first part of the first plate of the first capacitor C1 and the second part of the first plate of the first capacitor C1.

[0224] Specifically, as Figure 28 shown, the first source-drain layer 221 includes the first electrode of the first pull-up control sub-transistor T81j1, the second electrode T81j1D of the first pull-up control sub-transistor T81j1, the first electrode T81j2S of the second pull-up control sub-transistor T81j2, and the second electrode T81j2D of the second pull-up control sub-transistor T81j2. The first electrode T81j2S of the second pull-up control sub-transistor T81j2, the second electrode T81j2D of the second pull-up control sub-transistor T81j2, and the second electrode T81j1D of the first pull-up control sub-transistor T81j1 are arranged in sequence along the second direction.

[0225] Specifically, asFigure 28 As shown, the first source-drain layer 221 includes the first electrode T41j1S of the first pull-down sub-transistor T41j1, the second electrode T41j1D of the first pull-down sub-transistor T41j1, the first electrode T41j2S of the second pull-down sub-transistor T41j2, and the second electrode T41j2D of the second pull-down sub-transistor T41j2. The second electrode T41j2D of the second pull-down sub-transistor T41j2, the first electrode T41j2S of the second pull-down sub-transistor T41j2, and the second electrode T41j1D of the first pull-down sub-transistor T41j1 are arranged in sequence along the second direction.

[0226] Specifically, as Figure 28 As shown, the first source-drain layer 221 includes the first electrode T42j1S of the first pull-down holding sub-transistor T42j1, the second electrode of the first pull-down holding sub-transistor T42j1, the first electrode T42j2S of the second pull-down holding sub-transistor T42j2, and the second electrode T42j2D of the second pull-down holding sub-transistor T42j2. The second electrode T42j2D of the second pull-down holding sub-transistor T42j2, the first electrode T42j2S of the second pull-down holding sub-transistor T42j2, and the first electrode T42j1S of the first pull-down holding sub-transistor T42j1 are arranged in sequence along the second direction.

[0227] Specifically, as Figure 28 As shown, the first source-drain layer 221 includes the first electrode T43j1S of the first reset sub-transistor T43j1, the second electrode T43j1D of the first reset sub-transistor T43j1, the first electrode of the second reset sub-transistor T43j2, and the second electrode T43j1D of the second reset sub-transistor T43j2. The second electrode T43j1D of the second reset sub-transistor T43j2, the first electrode of the second reset sub-transistor T43j2, and the second electrode T43j1D of the first reset sub-transistor T43j1 are arranged in sequence along the second direction.

[0228] Specifically, as Figure 28 As shown, the first source-drain layer 221 includes the first electrode T51j1S of the first inverter sub-transistor T51j1, the second electrode T51j1D of the first inverter sub-transistor T51j1, the first electrode of the second inverter sub-transistor T51j2, and the second electrode T51j2D of the second inverter sub-transistor T51j2. The first electrode T51j1S of the first inverter sub-transistor T51j1, the second electrode T51j1D of the first inverter sub-transistor T51j1, and the second electrode T51j2D of the second inverter sub-transistor T51j2 are arranged in sequence along the first direction.

[0229] Specifically, as Figure 28As shown, the first source-drain layer 221 includes the first electrode of the first negative-bias-proof transistor T71j1, the second electrode T71j1D of the first negative-bias-proof transistor T71j1, the first electrode T71j2S of the second negative-bias-proof transistor T71j2, and the second electrode T71j2D of the second negative-bias-proof transistor T71j2. The first electrode T71j2S of the second negative-bias-proof transistor T71j2, the second electrode T71j2D of the second negative-bias-proof transistor T71j2, and the second electrode T71j1D of the first negative-bias-proof transistor T71j1 are arranged in sequence along the first direction.

[0230] In some embodiments, as Figure 24 、 Figure 29 shown, the second clock signal line CKB includes a first group of sub-lines CKBi and a second group of sub-lines CKBj. The display panel 2 includes a second source-drain layer 223. The second source-drain layer 223 includes a first reset control line VST1, a low-frequency control line LC, a first clock signal line CKA, a first low-potential signal line VGL1, a second clock signal line CKB, and a second low-potential signal line VGL2;

[0231] The first reset control line VST1, the low-frequency control line LC, the first clock signal line CKA, the first low-potential signal line VGL1, the first group of sub-lines CKBi, the second low-potential signal line VGL2, and the second group of sub-lines CKBj are arranged along the first direction X;

[0232] The first reset control line VST1 is connected to the gate T43jG of the first reset transistor T43j through the first source connection line LD1. The second low-potential signal line VGL2 is connected to the first gate connection line LE1 through the fifth source connection line LD5. The first gate connection line LE1 is connected to the first electrode T32jS of the second pull-down transistor T32j.

[0233] In some embodiments, as Figure 6 、 Figure 30As shown, the second type of gate circuit 22b includes a second pull-up control module 321, a second pull-up module 322, a second pull-down module 323, a second pull-down maintenance module 324, a second inverter module 325, a second negative-bias protection module 326, and a second reset module 327. The second pull-up control module 321 is electrically connected to the second pull-up module 322 at a second pull-up node Q2[n]. The second pull-down module 323 is electrically connected to the second pull-up node Q2[n] and a second signal output terminal INI[n] of the second type of gate circuit 22b at this stage. The second pull-down maintenance module 324 is electrically connected between the second pull-up node Q2[n] and a second low-potential signal line VGL2. The second inverter module 325 is electrically connected to the second pull-up node Q2[n], the second low-potential signal line VGL2, and a low-frequency signal line LC. The second negative-bias protection module 326 is electrically connected between a first high-potential signal line VGH1 and the second pull-up node Q2[n]. The second reset module 327 is electrically connected between the second pull-up node Q2[n] and the second low-potential signal line VGL2.

[0234] In some embodiments, as Figure 6 、 Figure 30 shown, at least two of the second pull-up control module 321, the second pull-up module 322, the second pull-down module 323, the second pull-down maintenance module 324, the second inverter module 325, the second negative-bias protection module 326, and the second reset module 327 are arranged along a second direction, and the included angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees. By arranging at least two of the second pull-up control module 321, the second pull-up module 322, the second pull-down module 323, the second pull-down maintenance module 324, the second inverter module 325, the second negative-bias protection module 326, and the second reset module 327 along the second direction, the lateral space occupied by the second type of gate circuit 22b can be shortened, thereby reducing the lateral space occupied by the gate driving circuit 22 and reducing the border of the display panel 2.

[0235] Specifically, compared with the horizontal arrangement of each module in the comparative display device, in the embodiment of the present application, by arranging at least two modules in the second type of gate circuit 22b along the second direction, the lateral space occupied by the second type of gate circuit 22b can be reduced, the lateral space occupied by the gate driving circuit 22 can be reduced, and the border of the display panel 2 can be reduced.

[0236] In some embodiments, as Figure 6 、 Figure 30As shown, a part of the second pull-up control module 321, a part of the second inverting module 325, the second negative-bias protection module 326, and the second reset module 327 are arranged along the second direction Y. By arranging a part of the second pull-up control module 321, a part of the second inverting module 325, the second negative-bias protection module 326, and the second reset module 327 along the second direction Y, the lateral space occupied by the second pull-up control module 321, the second inverting module 325, the second negative-bias protection module 326, and the second reset module 327 can be reduced, the lateral space occupied by the second type of gate circuit 22b can be reduced, and the lateral space occupied by the gate driving circuit 22 can be reduced, thereby reducing the border of the display panel 2.

[0237] Specifically, as Figure 30 shown, it can be seen that in the second direction, a part of the second inverting module 325, the second reset module 327, the second negative-bias protection module 326, and a part of the second pull-up control module 321 are arranged along the second direction Y.

[0238] In some embodiments, as Figure 6 、 Figure 30 shown, another part of the second pull-up control module 321, another part of the second inverting module 325, and the second pull-down maintaining module 324 are arranged along the second direction Y. By arranging another part of the second pull-up control module 321, another part of the second inverting module 325, and the second pull-down maintaining module 324 along the second direction Y, the lateral space occupied by the second pull-up control module 321, the second inverting module 325, and the second pull-down maintaining module 324 can be reduced, the lateral space occupied by the second type of gate circuit 22b can be reduced, and the lateral space occupied by the gate driving circuit 22 can be reduced, thereby reducing the border of the display panel 2.

[0239] Specifically, as Figure 30 shown, it can be seen that another part of the second pull-up control module 321, the second pull-down maintaining module 324, and another part of the second inverting module 325 are arranged in sequence along the second direction Y.

[0240] In some embodiments, as Figure 6 、 Figure 30 shown, another part of the second pull-up control module 321, another part of the second inverting module 325, and the second pull-down module 323 are arranged along the second direction Y, and the second reset module 327, the second pull-down maintaining module 324, a part of the second pull-down module 323, and the second pull-up module 322 are arranged along the first direction X.

[0241] In some embodiments, asFigure 6 , Figures 30 to 35 As shown in Figures 30 to 35 , the second pull-up control module 321 includes a fourth pull-up control transistor T11i, a fifth pull-up control transistor T12i, and a sixth pull-up control transistor T81i. The gate T11iG of the fourth pull-up control transistor T11i is electrically connected to the second signal output terminal INI[n - 2] of the second type of gate circuit 22b of the previous two levels. The first electrode T11iS of the fourth pull-up control transistor T11i is electrically connected to the first high potential signal line VGH1. The second electrode T11iD of the fourth pull-up control transistor T11i is electrically connected to the first electrode T12iS of the fifth pull-up control transistor T12i. The gate T12iG of the fifth pull-up control transistor T12i is electrically connected to the second signal output terminal INI[n - 2] of the second type of gate circuit 22b of the previous two levels. The second electrode T12iD of the fifth pull-up control transistor T12i is electrically connected to the second pull-up node Q2[n]. The gate T81iG of the sixth pull-up control transistor T81i is electrically connected to the first high potential signal line VGH1. The first electrode T81iS of the sixth pull-up control transistor T81i is electrically connected to the first high potential signal line VGH1. The second electrode T81iD of the sixth pull-up control transistor T81i is electrically connected to the second electrode T11iD of the fourth pull-up control transistor T11i;

[0242] Among them, the fourth pull-up control transistor T11i and the fifth pull-up control transistor T12i are arranged along the second direction Y, and the sixth pull-up control transistor T81i and the fourth pull-up control transistor T11i are arranged along the first direction X. By arranging the fourth pull-up control transistor T11i and the fifth pull-up control transistor T12i along the second direction Y, the space occupied by the second pull-up control module 321 can be reduced, thereby reducing the border of the display panel 2.

[0243] In some embodiments, such as Figure 6 , Figures 30 to 35As shown, the sixth pull-up control transistor T81i includes a third pull-up control sub-transistor T81i1 and a fourth pull-up control sub-transistor T81i2. The gate T81i2G of the fourth pull-up control sub-transistor T81i2 and the first electrode T81i2S of the fourth pull-up control sub-transistor T81i2 are electrically connected to the first high-potential signal line VGH1. The second electrode T81i2D of the fourth pull-up control sub-transistor T81i2 is electrically connected to the first electrode of the third pull-up control sub-transistor T81i1. The gate T81i1G of the third pull-up control sub-transistor T81i1 is electrically connected to the first high-potential signal line VGH1. The second electrode T81i1D of the third pull-up control sub-transistor T81i1 is electrically connected to the second electrode T11iD of the fourth pull-up control transistor T11i;

[0244] Wherein, the third pull-up control sub-transistor T81i1 and the fourth pull-up control sub-transistor T81i2 are arranged along the second direction. By making the sixth pull-up control transistor T81i include the third pull-up control sub-transistor T81i1 and the fourth pull-up control sub-transistor T81i2, the performance of the sixth pull-up control transistor T81i can be improved. And the third pull-up control sub-transistor T81i1 and the fourth pull-up control sub-transistor T81i2 are arranged along the first direction, which can reduce the lateral area occupied by the sixth pull-up control transistor T81i and reduce the border of the display panel 2.

[0245] Specifically, the third pull-up control sub-transistor T81i1 and the fourth pull-up control sub-transistor T81i2 can be regarded as two independent transistors, or can be regarded as two sub-transistors in the sixth pull-up control transistor T81i. Similarly, for other sub-transistors, the above description can be referred to and will not be elaborated in the following embodiments.

[0246] Specifically, when a transistor has multiple sub-transistors, the first electrode of the transistor is the electrode connected to the signal line. For example, the sixth pull-up control transistor T81i includes the third pull-up control sub-transistor T81i1 and the fourth pull-up control sub-transistor T81i2. Since the first electrode T81i2S of the fourth pull-up control sub-transistor T81i2 is electrically connected to the first high-potential signal line VGH1, the first electrode T81iS of the sixth pull-up control transistor T81i is the first electrode T81i2S of the fourth pull-up control sub-transistor T81i2. Similarly, the first electrodes of other transistors can be determined.

[0247] Specifically, the multi-stage gate driving circuit 22 includes a multi-stage second type of gate circuit 22b. Inside the first-stage second type of gate circuit 22b, the gate T11iG of the fourth pull-up control transistor T11i can be connected to the start signal line. Inside the second type of gate circuit 22b of other stages, the gate T11iG of the fourth pull-up control transistor T11i and the gate T12iG of the fifth pull-up control transistor T12i are electrically connected to the second signal output terminal INI[n - 2] of the second type of gate circuit 22b of the previous two stages. The first electrode T11iS of the fourth pull-up control transistor T11i and the first electrode T12iS of the fifth pull-up control transistor T12i are electrically connected to the first high-potential signal line VGH1.

[0248] In some embodiments, as Figure 6 , Figures 30 to 35 shown, the second pull-down module 323 includes a fifth pull-down transistor T31i and a sixth pull-down transistor T41i. The gate T31iG of the fifth pull-down transistor T31i is electrically connected to the second pull-down node QB2[n]. The first electrode T31iS of the fifth pull-down transistor T31i is electrically connected to the second low-potential signal line VGL2. The second electrode T31iD of the fifth pull-down transistor T31i is electrically connected to the second signal output terminal INI[n] of the second type of gate circuit 22b of this stage. The gate T41iG of the sixth pull-down transistor T41i is electrically connected to the second signal output terminal INI[n + 2] of the second type of gate circuit 22b of the next two stages. The first electrode T41iS of the sixth pull-down transistor T41i is connected to the second low-potential signal line VGL2. The second electrode T41iD of the sixth pull-down transistor T41i is electrically connected to the second pull-up node Q2[n].

[0249] Wherein, the fifth pull-down transistor T31i and the sixth pull-down transistor T41i are arranged along the second direction Y. By arranging the fifth pull-down transistor T31i and the sixth pull-down transistor T41i along the second direction, the space occupied by the second pull-down module 323 can be reduced, and the border of the display panel 2 can be reduced.

[0250] In some embodiments, as Figure 6 , Figures 30 to 35As shown, the sixth pull-down transistor T41i includes a third pull-down sub-transistor T41i1 and a fourth pull-down sub-transistor T41i2. The gate T41i2G of the fourth pull-down sub-transistor T41i2 is electrically connected to the second signal output terminal INI[n + 2] of the next two-stage second type of gate circuit 22b. The first electrode T41i2S of the fourth pull-down sub-transistor T41i2 is electrically connected to the second low-potential signal line VGL2. The second electrode T41i2D of the fourth pull-down sub-transistor T41i2 is electrically connected to the first electrode T41i1S of the third pull-down sub-transistor T41i1 at the second internal node N2[n]. The gate T41i1G of the third pull-down sub-transistor T41i1 is electrically connected to the second signal output terminal INI[n + 2] of the next two-stage second type of gate circuit 22b. The second electrode T41i1D of the third pull-down sub-transistor T41i1 is electrically connected to the second pull-up node Q2[n].

[0251] Wherein, the third pull-down sub-transistor T41i1 and the fourth pull-down sub-transistor T41i2 are arranged along the second direction Y. By making the sixth pull-down transistor T41i include the third pull-down sub-transistor T41i1 and the fourth pull-down sub-transistor T41i2, the performance of the sixth pull-down transistor T41i can be improved. Moreover, since the third pull-down sub-transistor T41i1 and the fourth pull-down sub-transistor T41i2 are arranged along the second direction, the lateral area occupied by the sixth pull-down transistor T41i can be reduced, and the border of the display panel 2 can be decreased.

[0252] In some embodiments, such as Figure 6 、 Figures 30 to 35As shown, the second inverter module 325 includes a sixth inverter transistor T51i, a seventh inverter transistor T52i, an eighth inverter transistor T53i, a ninth inverter transistor T54i, and a tenth inverter transistor T55i. The gate T51iG and the first electrode T51iS of the sixth inverter transistor T51i are electrically connected to the low-frequency signal line LC. The second electrode T51iD of the sixth inverter transistor T51i is electrically connected to the second electrode T52iD of the seventh inverter transistor T52i. The gate T52iG of the seventh inverter transistor T52i is electrically connected to the second pull-up node Q2[n]. The first electrode T52iS of the seventh inverter transistor T52i is electrically connected to the second low-potential signal line VGL2. The gate T53iG of the eighth inverter transistor T53i is electrically connected to the second electrode T51iD of the sixth inverter transistor T51i. The first electrode T53iS of the eighth inverter transistor T53i is electrically connected to the low-frequency signal line LC. The second electrode T53iD of the eighth inverter transistor T53i is electrically connected to the second pull-down node QB2[n]. The gate T54iG of the ninth inverter transistor T54i is electrically connected to the second pull-up node Q2[n]. The first electrode T54iS of the ninth inverter transistor T54i is electrically connected to the second low-potential signal line VGL2. The second electrode T54iD of the ninth inverter transistor T54i is electrically connected to the second pull-down node QB2[n]. The gate T55iG of the tenth inverter transistor T55i is electrically connected to the second signal output terminal INI[n - 2] of the upper two-stage second type gate circuit 22b. The first electrode T55iS of the tenth inverter transistor T55i is electrically connected to the second low-potential signal line VGL2. The second electrode T55iD of the tenth inverter transistor T55i is electrically connected to the second pull-down node QB2[n];

[0253] Among them, the sixth inverter transistor T51i and the seventh inverter transistor T52i are arranged along the second direction Y. The eighth inverter transistor T53i and the ninth inverter transistor T54i are arranged along the second direction Y. The sixth inverter transistor T51i, the eighth inverter transistor T53i, and the tenth inverter transistor T55i are arranged along the first direction X. By arranging the sixth inverter transistor T51i and the seventh inverter transistor T52i along the second direction, and the eighth inverter transistor T53i and the ninth inverter transistor T54i along the second direction, the lateral space occupied by the second inverter module 325 can be reduced, thereby reducing the border of the display panel 2.

[0254] In some embodiments, such as Figure 6 、 Figures 30 to 35As shown, the sixth inverter transistor T51i includes a third inverter sub-transistor T51i1 and a fourth inverter sub-transistor T51i2. The gate T51i1G of the third inverter sub-transistor T51i1 and the first electrode T51i1S of the third inverter sub-transistor T51i1 are electrically connected to the low-frequency signal line LC. The second electrode T51i1D of the third inverter sub-transistor T51i1 is electrically connected to the first electrode of the fourth inverter sub-transistor T51i2. The gate T51i2G of the fourth inverter sub-transistor T51i2 is electrically connected to the low-frequency signal line LC. The second electrode T51i2D of the fourth inverter sub-transistor T51i2 is electrically connected to the second electrode T52iD of the seventh inverter transistor T52i;

[0255] Wherein, the third inverter sub-transistor T51i1 and the fourth inverter sub-transistor T51i2 are arranged along the first direction X. By making the sixth inverter transistor T51i include the third inverter sub-transistor T51i1 and the fourth inverter sub-transistor T51i2, the performance of the sixth inverter transistor T51i can be improved.

[0256] In some embodiments, as Figure 6 、 Figures 30 to 35 shown, the sixth inverter transistor T51i and the sixth pull-up control transistor T81i are arranged along the second direction Y. The eighth inverter transistor T53i and the fifth pull-up control transistor T12i are arranged along the second direction Y. The tenth inverter transistor T55i and the fifth pull-down transistor T31i are arranged along the second direction Y. Thereby, the lateral space occupied by the second inverter module 325, the second pull-up control module 321 and the second pull-down module 323 can be reduced, and the border of the display panel 2 can be reduced.

[0257] In some embodiments, as Figure 6 、 Figures 30 to 35 shown, the second pull-down maintenance module 324 includes a second pull-down maintenance transistor T42i. The gate T42iG of the second pull-down maintenance transistor T42i is electrically connected to the second pull-down node QB2[n]. The first electrode T42iS of the second pull-down maintenance transistor T42i is electrically connected to the second low-potential signal line VGL2. The second electrode T42iD of the second pull-down maintenance transistor T42i is electrically connected to the second pull-up node Q2[n];

[0258] Wherein, in the second direction, the second pull-down maintenance transistor T42i is arranged between the ninth inverter transistor T54i and the fifth pull-up control transistor T12i. Thereby, the lateral space occupied by the second pull-down maintenance transistor T42i, the ninth inverter transistor T54i and the fifth pull-up control transistor T12i can be reduced, and the border of the display panel 2 can be reduced.

[0259] In some embodiments, as Figure 6 , Figures 30 to 35 shown, the second pull-down holding transistor T42i includes a third pull-down holding sub-transistor T42i1 and a fourth pull-down holding sub-transistor T42i2. The gate T42i2G of the fourth pull-down holding sub-transistor T42i2 is electrically connected to the second pull-down node QB2[n]. The first electrode T42i2S of the fourth pull-down holding sub-transistor T42i2 is electrically connected to the second low potential signal line VGL2. The second electrode T42i2D of the fourth pull-down holding sub-transistor T42i2 is electrically connected to the first electrode T42i1S of the third pull-down holding sub-transistor T42i1 at a second internal node N2[n]. The gate of the third pull-down holding sub-transistor T42i1 is electrically connected to the second pull-down node QB2[n]. The second electrode of the third pull-down holding sub-transistor T42i1 is electrically connected to the second pull-up node Q2[n];

[0260] Wherein, the third pull-down holding sub-transistor T42i1 and the fourth pull-down holding sub-transistor T42i2 are arranged along the second direction Y. By making the second pull-down holding transistor T42i include the third pull-down holding sub-transistor T42i1 and the fourth pull-down holding sub-transistor T42i2, the performance of the second pull-down holding transistor T42i can be improved. Moreover, since the third pull-down holding sub-transistor T42i1 and the fourth pull-down holding sub-transistor T42i2 are arranged along the second direction, the lateral space occupied by the second pull-down holding transistor T42i can be reduced, and the border of the display panel 2 can be reduced.

[0261] In some embodiments, as Figure 6 , Figures 30 to 35 shown, the second reset module 327 includes a second reset transistor T43i. The gate T43iG of the second reset transistor T43i is electrically connected to the second reset control line VST2. The first electrode T43iS of the second reset transistor T43i is electrically connected to the second low potential signal line VGL2. The second electrode T43iD of the second reset transistor T43i is electrically connected to the second pull-up node Q2[n];

[0262] Wherein, in the second direction Y, the second reset transistor T43i is arranged on a side of the seventh inverter transistor T52i away from the sixth inverter transistor T51i. By arranging the second reset transistor T43i on the side of the seventh inverter transistor T52i away from the sixth inverter transistor T51i, the lateral space occupied by the second reset transistor T43i and the second inverter module 325 is reduced, thereby reducing the border of the display panel 2, and the second reset transistor T43i is convenient to be connected to the second reset control line VST2.

[0263] In some embodiments, asFigure 6 , Figures 30 to 35 As shown, the second reset transistor T43i includes a third reset sub-transistor T43i1 and a fourth reset sub-transistor T43i2. The gate T43i1G of the fourth reset sub-transistor T43i2 is electrically connected to the second reset control line VST2. The first electrode of the fourth reset sub-transistor T43i2 is electrically connected to the second low potential signal line VGL2. The second electrode T43i1D of the third reset sub-transistor T43i1 is electrically connected to the first electrode T43i1S of the third reset sub-transistor T43i1 at the second internal node N2[n]. The gate T43i1G of the third reset sub-transistor T43i1 is electrically connected to the second reset control line VST2. The second electrode T43i1D of the third reset sub-transistor T43i1 is electrically connected to the second pull-up node Q2[n];

[0264] Wherein, the third reset sub-transistor T43i1 and the fourth reset sub-transistor T43i2 are arranged along the second direction. By making the second reset transistor T43i include the third reset sub-transistor T43i1 and the fourth reset sub-transistor T43i2, the performance of the second reset transistor T43i can be improved. And the third reset sub-transistor T43i1 and the fourth reset sub-transistor T43i2 are arranged along the second direction, which can reduce the lateral space occupied by the second reset transistor T43i and reduce the border of the display panel 2.

[0265] In some embodiments, as Figure 6 , Figures 30 to 35 shown, the second negative bias prevention module 326 includes a second negative bias prevention transistor T61i. The gate T61iG of the second negative bias prevention transistor T61i is electrically connected to the second pull-up node Q2[n]. The first electrode T61iS of the second negative bias prevention transistor T61i is electrically connected to the first high potential signal line VGH1. The second electrode T61iD of the second negative bias prevention transistor T61i is electrically connected to the second internal node N2[n];

[0266] Wherein, the second negative bias prevention transistor T61i is arranged along the second direction Y between the seventh inverter transistor T52i and the sixth pull-up control transistor T81i. By making the second negative bias prevention transistor T61i arranged along the second direction Y between the seventh inverter transistor T52i and the sixth pull-up control transistor T81i, the lateral area occupied by the second negative bias prevention module 326 can be reduced, and the border of the display panel 2 can be reduced.

[0267] In some embodiments, as Figure 6 , Figures 30 to 35As shown, the second negative-bias protection transistor T61i includes a third negative-bias protection sub-transistor T61i1 and a fourth negative-bias protection sub-transistor T61i2. The gate T61i2G of the fourth negative-bias protection sub-transistor T61i2 is electrically connected to the second pull-up node Q2[n]. The first electrode T61i2S of the fourth negative-bias protection sub-transistor T61i2 is electrically connected to the first high-potential signal line. The second electrode T61i2D of the fourth negative-bias protection sub-transistor T61i2 is electrically connected to the first electrode of the third negative-bias protection sub-transistor T61i1. The gate T61i1G of the third negative-bias protection sub-transistor T61i1 is electrically connected to the second pull-up node Q2[n]. The second electrode T61i1D of the third negative-bias protection sub-transistor T61i1 is electrically connected to the second internal node N2[n].

[0268] Wherein, the third negative-bias protection sub-transistor T61i1 and the fourth negative-bias protection sub-transistor T61i2 are arranged along the second direction. By making the second negative-bias protection transistor T61i include the third negative-bias protection sub-transistor T61i1 and the fourth negative-bias protection sub-transistor T61i2, the performance of the second negative-bias protection transistor T61i can be improved. Moreover, since the third negative-bias protection sub-transistor T61i1 and the fourth negative-bias protection sub-transistor T61i2 are arranged along the second direction, the lateral space occupied by the second negative-bias protection transistor T61i can be reduced, and the border of the display panel 2 can be decreased.

[0269] In some embodiments, as Figure 6 、 Figures 30 to 35 shown, the second pull-up module 322 includes a fourth pull-up transistor T21i. The gate T21iG of the fourth pull-up transistor T21i is electrically connected to the second pull-up node Q2[n]. The first electrode T21iS of the fourth pull-up transistor T21i is electrically connected to the third clock signal line CKC. The second electrode T21iD of the fourth pull-up transistor T21i is electrically connected to the second signal output terminal INI[n] of the second type of gate circuit 22b at this stage.

[0270] Wherein, the fourth pull-up transistor T21i and the tenth inverter transistor T55i are arranged along the first direction X.

[0271] In some embodiments, as Figure 6 、 Figures 30 to 35 shown, the second type of gate circuit 22b further includes a second capacitor C2. One plate of the second capacitor C2 is electrically connected to the second pull-up node Q2[n], and the other plate of the second capacitor C2 is electrically connected to the second signal output terminal INI[n] of the second type of gate circuit 22b at this stage.

[0272] Specifically, the second capacitor C2 includes a first electrode plate C2a of the second capacitor C2 and a second electrode plate C2b of the second capacitor C2. The first electrode plate C2a of the second capacitor C2 includes a first part C2a1 of the first electrode plate C2a of the second capacitor C2 and a second part C2a2 of the first electrode plate C2a of the second capacitor C2.

[0273] In some embodiments, as Figure 30 , Figure 31 shown, the display panel 2 includes a light-shielding layer 212. The light-shielding layer 212 includes a third light-shielding connection line LS3, a second signal output terminal INI[n] of the second type of gate circuit 22b of this stage, and a first part C2a1 of the first electrode plate C2a of the second capacitor C2, which are arranged in sequence along the first direction X.

[0274] In some embodiments, as Figure 30 , Figure 32 shown, the display panel 2 includes an active layer 216. The active layer 216 includes an active part T11iA of the fourth pull-up control transistor T11i, an active part T12iA of the fifth pull-up control transistor T12i, an active part T81iA of the sixth pull-up control transistor T81i, an active part T21iA of the fourth pull-up transistor T21i, an active part T31iA of the fifth pull-down transistor T31i, an active part T41iA of the sixth pull-down transistor T41i, an active part T42iA of the second pull-down maintenance transistor T42i, an active part T51iA of the sixth inverter transistor T51i, an active part T52iA of the seventh inverter transistor T52i, an active part T53iA of the eighth inverter transistor T53i, an active part T54iA of the ninth inverter transistor T54i, an active part T55iA of the tenth inverter transistor T55i, an active part T43iA of the second reset transistor T43i, and an active part T61iA of the second negative-bias protection transistor T61i;

[0275] Among them, the active part T51iA of the sixth inverter transistor T51i, the active part T52iA of the seventh inverter transistor T52i, the active part T61iA of the second negative-bias protection transistor T61i, and the active part T81iA of the sixth pull-up control transistor T81i are arranged in sequence along the second direction Y;

[0276] The active part T51iA of the sixth inverter transistor T51i, the active part T52iA of the seventh inverter transistor T52i, and the active part T43iA of the second reset transistor T43i are arranged in sequence along the second direction Y;

[0277] The active part T53iA of the eighth inverter transistor T53i, the active part T54iA of the ninth inverter transistor T54i, the active part T42iA of the second pull-down maintenance transistor T42i, the active part T12iA of the fifth pull-up control transistor T12i, and the active part T11iA of the fourth pull-up control transistor T11i are arranged in sequence along the second direction Y;

[0278] The active part T55iA of the tenth inverter transistor T55i, the active part T31iA of the fifth pull-down transistor T31i, the active part T41iA of the sixth pull-down transistor T41i, the active part T12iA of the fifth pull-up control transistor T12i, and the active part T11iA of the fourth pull-up control transistor T11i are arranged in sequence along the second direction;

[0279] The active part T51iA of the sixth inverter transistor T51i, the active part T53iA of the eighth inverter transistor T53i, the active part T55iA of the tenth inverter transistor T55i, and the active part T21iA of the fourth pull-up transistor T21i are arranged in sequence along the first direction X.

[0280] Specifically, as Figure 32 shown, the active part T81iA of the sixth pull-up control transistor T81i includes the active part T81i1A of the third pull-up control sub-transistor T81i1 and the active part T81i2A of the fourth pull-up control sub-transistor T81i2, and the active part T81i1A of the third pull-up control sub-transistor T81i1 and the active part T81i2A of the fourth pull-up control sub-transistor T81i2 are arranged in sequence along the second direction.

[0281] Specifically, as Figure 32 shown, the active part T41iA of the sixth pull-down transistor T41i includes the active part T41i1A of the third pull-down sub-transistor T41i1 and the active part T41i2A of the fourth pull-down sub-transistor T41i2, and the active part T41i1A of the third pull-down sub-transistor T41i1 and the active part T41i2A of the fourth pull-down sub-transistor T41i2 are arranged along the second direction.

[0282] Specifically, as Figure 32 shown, the active part T42iA of the second pull-down maintenance transistor T42i includes the active part of the third pull-down maintenance sub-transistor T42i1 and the active part T42i2A of the fourth pull-down maintenance sub-transistor T42i2, and the active part of the third pull-down maintenance sub-transistor T42i1 and the active part T42i2A of the fourth pull-down maintenance sub-transistor T42i2 are arranged along the second direction.

[0283] Specifically, as Figure 32As shown, the active part T43iA of the second reset transistor T43i includes the active part T43i1A of the third reset sub-transistor T43i1 and the active part T43i1A of the fourth reset sub-transistor T43i2. The active part T43i1A of the third reset sub-transistor T43i1 and the active part T43i1A of the fourth reset sub-transistor T43i2 are arranged along the second direction.

[0284] Specifically, as Figure 32 shown, the active part T51iA of the sixth inverter transistor T51i includes the active part T51i1A of the third inverter sub-transistor T51i1 and the active part T51i2A of the fourth inverter sub-transistor T51i2. The active part T51i1A of the third inverter sub-transistor T51i1 and the active part T51i2A of the fourth inverter sub-transistor T51i2 are arranged along the first direction.

[0285] Specifically, as Figure 32 shown, the active part T61iA of the second negative-bias protection transistor T61i includes the active part T61i1A of the third negative-bias protection sub-transistor T61i1 and the active part T61i2A of the fourth negative-bias protection sub-transistor T61i2. The active part T61i1A of the third negative-bias protection sub-transistor T61i1 and the active part T61i2A of the fourth negative-bias protection sub-transistor T61i2 are arranged along the second direction.

[0286] In some embodiments, as Figure 30 、 Figure 33 shown, the display panel 2 includes a gate layer 218, and the gate layer 218 includes the gate T11iG of the fourth pull-up control transistor T11i, the gate T12iG of the fifth pull-up control transistor T12i, the gate T81iG of the sixth pull-up control transistor T81i, the gate T21iG of the fourth pull-up transistor T21i, the gate T31iG of the fifth pull-down transistor T31i, the gate T41iG of the sixth pull-down transistor T41i, the gate T42iG of the second pull-down holding transistor T42i, the gate T51iG of the sixth inverter transistor T51i, the gate T52iG of the seventh inverter transistor T52i, the gate T53iG of the eighth inverter transistor T53i, the gate T54iG of the ninth inverter transistor T54i, the gate T55iG of the tenth inverter transistor T55i, the gate T43iG of the second reset transistor T43i, the gate T61iG of the second negative-bias protection transistor T61i, and the second electrode plate C2b of the second capacitor C2;

[0287] Among them, the gate T51iG of the sixth inverter transistor T51i, the gate T52iG of the seventh inverter transistor T52i, the gate T61iG of the second negative-bias protection transistor T61i, and the gate T81iG of the sixth pull-up control transistor T81i are arranged in sequence along the second direction Y;

[0288] The gate T51iG of the sixth inverter transistor T51i, the gate T52iG of the seventh inverter transistor T52i, and the gate T43iG of the second reset transistor T43i are arranged in sequence along the second direction Y;

[0289] The gate T53iG of the eighth inverter transistor T53i, the gate T54iG of the ninth inverter transistor T54i, the gate T42iG of the second pull - down maintenance transistor T42i, the gate T12iG of the fifth pull - up control transistor T12i, and the gate T11iG of the fourth pull - up control transistor T11i are arranged in sequence along the second direction Y;

[0290] The gate T55iG of the tenth inverter transistor T55i, the gate T31iG of the fifth pull - down transistor T31i, the gate T41iG of the sixth pull - down transistor T41i, the gate T12iG of the fifth pull - up control transistor T12i, and the gate T11iG of the fourth pull - up control transistor T11i are arranged in sequence along the second direction;

[0291] A part of the gate T11iG of the fourth pull - up transistor T11i and the second plate C2b of the second capacitor C2 are arranged in sequence along the second direction Y;

[0292] The gate T51iG of the sixth inverter transistor T51i, the gate T53iG of the eighth inverter transistor T53i, the gate T55iG of the tenth inverter transistor T55i, the gate T21iG of the fourth pull - up transistor T21i, and another part of the second plate C2b of the second capacitor C2 are arranged in sequence along the first direction X.

[0293] Specifically, as Figure 33 shown, the gate T81iG of the sixth pull - up control transistor T81i includes the gate T81i1G of the third pull - up control sub - transistor T81i1 and the gate T81i2G of the fourth pull - up control sub - transistor T81i2, and the gate T81i1G of the third pull - up control sub - transistor T81i1 and the gate T81i2G of the fourth pull - up control sub - transistor T81i2 are arranged in sequence along the second direction.

[0294] Specifically, as Figure 33 shown, the gate T41iG of the sixth pull - down transistor T41i includes the gate T41i1G of the third pull - down sub - transistor T41i1 and the gate T41i2G of the fourth pull - down sub - transistor T41i2, and the gate T41i1G of the third pull - down sub - transistor T41i1 and the gate T41i2G of the fourth pull - down sub - transistor T41i2 are arranged along the second direction.

[0295] Specifically, as Figure 33As shown, the gate T42iG of the second pull-down holding transistor T42i includes the gate of the third pull-down holding sub-transistor T42i1 and the gate T42i2G of the fourth pull-down holding sub-transistor T42i2, and the gate of the third pull-down holding sub-transistor T42i1 and the gate T42i2G of the fourth pull-down holding sub-transistor T42i2 are arranged along a second direction.

[0296] Specifically, as Figure 33 shown, the gate T43iG of the second reset transistor T43i includes the gate T43i1G of the third reset sub-transistor T43i1 and the gate T43i1G of the fourth reset sub-transistor T43i2, and the gate T43i1G of the third reset sub-transistor T43i1 and the gate T43i1G of the fourth reset sub-transistor T43i2 are arranged along a second direction.

[0297] Specifically, as Figure 33 shown, the gate T51iG of the sixth inverter transistor T51i includes the gate T51i1G of the third inverter sub-transistor T51i1 and the gate T51i2G of the fourth inverter sub-transistor T51i2, and the gate T51i1G of the third inverter sub-transistor T51i1 and the gate T51i2G of the fourth inverter sub-transistor T51i2 are arranged along a first direction.

[0298] Specifically, as Figure 33 shown, the gate T61iG of the second negative-bias protection transistor T61i includes the gate T61i1G of the third negative-bias protection sub-transistor T61i1 and the gate T61i2G of the fourth negative-bias protection sub-transistor T61i2, and the gate T61i1G of the third negative-bias protection sub-transistor T61i1 and the gate T61i2G of the fourth negative-bias protection sub-transistor T61i2 are arranged along a second direction.

[0299] In some embodiments, such as Figure 30 、 Figure 34As shown, the display panel 2 includes a first source-drain layer 221. The first source-drain layer 221 includes the first electrode T11iS of the fourth pull-up control transistor T11i, the first electrode T12iS of the fifth pull-up control transistor T12i, the first electrode T81iS of the sixth pull-up control transistor T81i, the first electrode T21iS of the fourth pull-up transistor T21i, the first electrode T31iS of the fifth pull-down transistor T31i, the first electrode T41iS of the sixth pull-down transistor T41i, the first electrode T42iS of the second pull-down holding transistor T42i, the first electrode T51iS of the sixth inverter transistor T51i, the first electrode T52iS of the seventh inverter transistor T52i, the first electrode T53iS of the eighth inverter transistor T53i, the first electrode T54iS of the ninth inverter transistor T54i, the first electrode T55iS of the tenth inverter transistor T55i, the first electrode T43iS of the second reset transistor T43i, the first electrode T61iS of the second negative-bias protection transistor T61i, the second part C2a2 of the first plate C2a of the second capacitor C2, the sixth source connection line LD6, the seventh source connection line LD7, and the eighth source connection line LD8;

[0300] Among them, the first electrode T51iS of the sixth inverter transistor T51i, the first electrode T52iS of the seventh inverter transistor T52i, the first electrode T61iS of the second negative-bias protection transistor T61i, and the first electrode T81iS of the sixth pull-up control transistor T81i are arranged in sequence along the second direction Y;

[0301] The first electrode T51iS of the sixth inverter transistor T51i, the first electrode T52iS of the seventh inverter transistor T52i, and the first electrode T43iS of the second reset transistor T43i are arranged in sequence along the second direction Y;

[0302] The first electrode T53iS of the eighth inverter transistor T53i, the first electrode T54iS of the ninth inverter transistor T54i, the first electrode T42iS of the second pull-down maintenance transistor T42i, the first electrode T12iS of the fifth pull-up control transistor T12i, and the first electrode T11iS of the fourth pull-up control transistor T11i are arranged in sequence along the second direction Y;

[0303] The first electrode T55iS of the tenth inverter transistor T55i, the first electrode T31iS of the fifth pull-down transistor T31i, the first electrode T41iS of the sixth pull-down transistor T41i, the first electrode T12iS of the fifth pull-up control transistor T12i, and the first electrode T11iS of the fourth pull-up control transistor T11i are arranged in sequence along the second direction;

[0304] The first electrode T51iS of the sixth inverter transistor T51i, the first electrode T53iS of the eighth inverter transistor T53i, the first electrode T55iS of the tenth inverter transistor T55i, and the first electrode T21iS of the fourth pull-up transistor T21i are arranged in sequence along the first direction X;

[0305] The third shielding connection line LS3 connects the first electrode T41iS of the sixth pull-down transistor T41i and the first electrode T55iS of the tenth inverter transistor T55i. The seventh source connection line LD7 connects the gate T55iG of the tenth inverter transistor T55i and the second signal output terminal INI[n - 2] of the upper two-stage second type gate circuit 22b. The eighth source connection line LD8 connects the gate T41iG of the sixth pull-down transistor T41i and the second signal output terminal INI[n + 2] of the lower two-stage second type gate circuit 22b.

[0306] Specifically, in the circuit diagram of the embodiment of the present application, in order to illustrate the connection relationship of each transistor, each transistor has a gate, a first electrode, and a second electrode. However, in the actual design process, in order to reduce the occupied space of the transistor, the electrodes of some transistors are formed by the same structure. For example, the first electrode of the third pull-up control sub-transistor T81i1 and the second electrode T81i2D of the fourth pull-up control sub-transistor T81i2 can be formed by the same structure. Therefore, only the second electrode T81i2D of the fourth pull-up control sub-transistor T81i2 is marked in the figure. It can be understood that this structure is also the first electrode of the third pull-up control sub-transistor T81i1. Similarly, the structures of the electrodes of other transistors can be determined.

[0307] Specifically, as Figures 30 to 35 shown, the first part C2a1 of the first plate C2a of the second capacitor C2 is connected to the second part C2a2 of the first plate C2a of the second capacitor C2.

[0308] Specifically, as Figure 34 shown, the first source-drain layer 221 includes the first electrode of the third pull-up control sub-transistor T81i1, the second electrode T81i1D of the third pull-up control sub-transistor T81i1, the first electrode T81i2S of the fourth pull-up control sub-transistor T81i2, and the second electrode T81i2D of the fourth pull-up control sub-transistor T81i2. The first electrode T81i2S of the fourth pull-up control sub-transistor T81i2, the second electrode T81i2D of the fourth pull-up control sub-transistor T81i2, and the second electrode T81i1D of the third pull-up control sub-transistor T81i1 are arranged in sequence along the second direction Y.

[0309] Specifically, as Figure 34 shown, the first source-drain layer 221 includes the first electrode of the third pull-down sub-transistor T41i1, the second electrode T41i1D of the third pull-down sub-transistor T41i1, the first electrode T41i2S of the fourth pull-down sub-transistor T41i2, and the second electrode T41i2D of the fourth pull-down sub-transistor T41i2. The first electrode T41i2S of the fourth pull-down sub-transistor T41i2, the second electrode T41i2D of the fourth pull-down sub-transistor T41i2, and the second electrode T41i1D of the third pull-down sub-transistor T41i1 are arranged in sequence along the second direction Y.

[0310] Specifically, as Figure 34 shown, the first source-drain layer 221 includes the first electrode of the third pull-down maintenance sub-transistor T42i1, the second electrode T42i1D of the third pull-down maintenance sub-transistor T42i1, the first electrode T42i2S of the fourth pull-down maintenance sub-transistor T42i2, and the second electrode T42i2D of the fourth pull-down maintenance sub-transistor T42i2. The first electrode T42i2S of the fourth pull-down maintenance sub-transistor T42i2, the second electrode T42i2D of the fourth pull-down maintenance sub-transistor T42i2, and the second electrode T42i1D of the third pull-down maintenance sub-transistor T42i1 are arranged in sequence along the second direction Y.

[0311] Specifically, as Figure 34 shown, the first source-drain layer 221 includes the first electrode of the third reset sub-transistor T43i1, the second electrode T43i1D of the third reset sub-transistor T43i1, the first electrode T43i2S of the fourth reset sub-transistor T43i2, and the second electrode T43i1D of the fourth reset sub-transistor T43i2. The first electrode T43i2S of the fourth reset sub-transistor T43i2, the second electrode T43i1D of the fourth reset sub-transistor T43i2, and the second electrode T43i1D of the third reset sub-transistor T43i1 are arranged in sequence along the second direction Y.

[0312] Specifically, as Figure 34As shown, the first source-drain layer 221 includes the first electrode T51i1S of the third inverter sub-transistor T51i1, the second electrode T51i1D of the third inverter sub-transistor T51i1, the first electrode of the fourth inverter sub-transistor T51i2, and the second electrode T51i2D of the fourth inverter sub-transistor T51i2. The first electrode T51i1S of the third inverter sub-transistor T51i1, the second electrode T51i1D of the third inverter sub-transistor T51i1, and the second electrode T51i2D of the fourth inverter sub-transistor T51i2 are arranged in sequence along the first direction X.

[0313] Specifically, as Figure 34 shown, the first source-drain layer 221 includes the first electrode of the third negative-bias protection sub-transistor T61i1, the second electrode T61i1D of the third negative-bias protection sub-transistor T61i1, the first electrode T61i2S of the fourth negative-bias protection sub-transistor T61i2, and the second electrode T61i2D of the fourth negative-bias protection sub-transistor T61i2. The first electrode T61i2S of the fourth negative-bias protection sub-transistor T61i2, the second electrode T61i2D of the fourth negative-bias protection sub-transistor T61i2, and the second electrode T61i1D of the third negative-bias protection sub-transistor T61i1 are arranged in sequence along the second direction Y.

[0314] In some embodiments, as Figure 30 、 Figure 35 shown, the second clock signal line CKB includes a first group of sub-lines CKBi and a second group of sub-lines CKBj. The display panel 2 includes a second source-drain layer 223. The second source-drain layer 223 includes a second reset control line VST2 and the second group of sub-lines CKBj that are arranged in sequence along the first direction X.

[0315] The second reset control line VST2 is connected to the gate T43iG of the second reset transistor T43i through the sixth source connection line LD6.

[0316] In some embodiments, as Figure 7As shown in the figure, the third type of gate circuit 22c includes a third pull-up control module 331, a third pull-up module 332, a third pull-down module 333, a third pull-down maintenance module 334, a third inverter module 335, and a third negative bias protection module 336. The third pull-up control module 331 is electrically connected to the third pull-up module 332 at a third pull-up node Q3[n] of the third type of gate circuit. The third pull-down module 333 is electrically connected to the third pull-up node Q3[n] and a third signal output terminal REF[n] of the current-stage third type of gate circuit 22c. The third pull-down maintenance module 334 is electrically connected between the third pull-up node Q3[n] and a second low-potential signal line VGL2 of the display panel. The third inverter module 335 is electrically connected to the third pull-up node Q3[n], a first high-potential signal line VGH1 of the display panel, the second low-potential signal line VGL2, a first signal output terminal Gn[n - 1] of the previous-stage first type of gate circuit 22a, a second signal output terminal INI[n] of the current-stage second type of gate circuit 22b, and a second signal output terminal INI[n + 1] of the next-stage second type of gate circuit 22b. The third negative bias protection module 336 is electrically connected between the first high-potential signal line VGH1 and the third pull-up node Q3[n].

[0317] In some embodiments, as Figure 7 , Figure 36 shown, at least two of the third pull-up control module 331, the third pull-up module 332, the third pull-down module 333, the third pull-down maintenance module 334, the third inverter module 335, and the third negative bias protection module 336 are arranged along a second direction, and the included angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees. By arranging at least two of the third pull-up control module 331, the third pull-up module 332, the third pull-down module 333, the third pull-down maintenance module 334, the third inverter module 335, and the third negative bias protection module 336 along the second direction, the lateral space occupied by the third type of gate circuit 22c can be shortened, thereby reducing the lateral space occupied by the gate driving circuit 22 and reducing the border of the display panel 2.

[0318] Specifically, compared with the horizontal arrangement of each module in the comparative display device, by arranging at least two modules in the third type of gate circuit 22c along the second direction in the embodiments of the present application, the lateral space occupied by the third type of gate circuit 22c can be reduced, the lateral space occupied by the gate driving circuit 22 can be reduced, and the border of the display panel 2 can be reduced.

[0319] In some embodiments, as Figure 7 , Figure 36As shown, a part of the third inverting module 335 and the third pull-up control module 331 are arranged along the second direction Y. By arranging a part of the third inverting module 335 and the third pull-up control module 331 along the second direction, the lateral space occupied by a part of the third inverting module 335 and a part of the third pull-up control module 331 can be reduced, the lateral space occupied by the third type of gate circuit 22c can be reduced, and the lateral space occupied by the gate driving circuit 22 can be reduced, thereby reducing the border of the display panel 2.

[0320] Specifically, as Figure 36 shown, it can be seen that in the second direction, a part of the third inverting module 335 is located above the third pull-up control module 331.

[0321] In some embodiments, as Figure 7 、 Figure 36 shown, another part of the third inverting module 335, the third pull-down maintenance module 334, and a part of the third pull-down module 333 are arranged along the second direction Y. By arranging another part of the third inverting module 335, the third pull-down maintenance module 334, and a part of the third pull-down module 333 along the second direction Y, the lateral space occupied by another part of the third inverting module 335, the third pull-down maintenance module 334, and the third pull-down module 333 can be reduced, the lateral space occupied by the third type of gate circuit 22c can be reduced, and the lateral space occupied by the gate driving circuit 22 can be reduced, thereby reducing the border of the display panel 2.

[0322] Specifically, as Figure 36 shown, it can be seen that in the second direction, another part of the third inverting module 335, the third pull-down maintenance module 334, and a part of the third pull-down module 333 are arranged in sequence along the second direction Y.

[0323] In some embodiments, as Figure 7 、 Figure 36 shown, the third pull-up module 332 and the third negative-bias protection module 336 are arranged along the second direction Y;

[0324] Another part of the third inverting module 335, the third pull-up module 332, and the third pull-down module 333 are arranged along the first direction X. By arranging the third pull-up module 332 and the third negative-bias protection module 336 along the second direction Y, the lateral space occupied by the third pull-up module 332 and the third negative-bias protection module 336 can be reduced, the lateral space occupied by the third type of gate circuit 22c can be reduced, and the lateral space occupied by the gate driving circuit 22 can be reduced, thereby reducing the border of the display panel 2.

[0325] Specifically, asFigure 36 As shown, it can be seen that in the second direction, the third pull-up module 332 is located above the third negative bias prevention module 336 .

[0326] In some embodiments, as Figure 7 、 Figures 36 to 41 As shown, the third inverting module 335 includes an eleventh inverting transistor T51r, a twelfth inverting transistor T52r, a thirteenth inverting transistor T53r, a fourteenth inverting transistor T54r, a fifteenth inverting transistor T55r, and a sixteenth inverting transistor T56r. The gate T51rG of the eleventh inverting transistor T51r and the first electrode T51rS of the eleventh inverting transistor T51r are electrically connected to the first signal output terminal Gn[n-1] of the first type gate circuit 22a of the previous stage. The second electrode T51rD of the eleventh inverting transistor T51r is electrically connected to the gate T51rG of the eleventh inverting transistor T51r and the first electrode T51rS of the eleventh inverting transistor T51r are electrically connected to the first signal output terminal Gn[n-1] of the first type gate circuit 22a of the previous stage. The second electrode T52rD of the inverter transistor T52r is electrically connected, the gate T52rG of the twelfth inverter transistor T52r is electrically connected to the second signal output terminal INI[n] of the second-type gate circuit 22b of this stage, the first electrode T52rS of the twelfth inverter transistor T52r is electrically connected to the second low-potential signal line VGL2, the gate T53rG of the thirteenth inverter transistor T53r is electrically connected to the second electrode T51rD of the eleventh inverter transistor T51r, and the first electrode T53rS of the thirteenth inverter transistor T53r is electrically connected to the first high-potential signal line VG H1 is electrically connected, a gate T54rG of the fourteenth inverter transistor T54r is electrically connected to the second electrode T51rD of the eleventh inverter transistor T51r, a first electrode T54rS of the fourteenth inverter transistor T54r is electrically connected to the first high potential signal line VGH1, a second electrode T54rD of the fourteenth inverter transistor T54r is electrically connected to the third pull-down node QB3[n], a gate T55rG of the fifteenth inverter transistor T55r is electrically connected to the third pull-up node Q3[n], and a first electrode T55rS of the fifteenth inverter transistor T55r is electrically connected to the first high potential signal line VGH1. 5rS is electrically connected to the second low-potential signal line VGL2, a second electrode of the fifteenth inverter transistor T55r is electrically connected to the third pull-down node QB3[n]; a gate T56rG of the sixteenth inverter transistor T56r is electrically connected to the second signal output terminal INI[n+1] of the next-stage second-type gate circuit 22b, a first electrode T56rS of the sixteenth inverter transistor T56r is electrically connected to the second low-potential signal line VGL2, and a second electrode T56rD of the sixteenth inverter transistor T56r is electrically connected to the third pull-down node QB3[n].

[0327] Among them, the eleventh inverter transistor T51r, the thirteenth inverter transistor T53r, and the twelfth inverter transistor T52r are arranged along the first direction. The eleventh inverter transistor T51r and the thirteenth inverter transistor T53r are arranged along the second direction with the fourteenth inverter transistor T54r. The twelfth inverter transistor T52r, the sixteenth inverter transistor T56r, and the fifteenth inverter transistor T55r are arranged along the second direction Y, which can reduce the lateral space occupied by the third inverter module 335, thereby reducing the border of the display panel 2.

[0328] In some embodiments, as Figure 7 , Figures 36 to 41 shown, the eleventh inverter transistor T51r includes a fifth inverter sub-transistor T51r1 and a sixth inverter sub-transistor T51r2. The gate T51r1G of the fifth inverter sub-transistor T51r1 and the first electrode T51r1S of the fifth inverter sub-transistor T51r1 are electrically connected to the first signal output terminal Gn[n-1] of the previous-stage first-type gate circuit 22a. The second electrode T51r1D of the fifth inverter sub-transistor T51r1 is electrically connected to the first electrode of the sixth inverter sub-transistor T51r2. The gate T51r2G of the sixth inverter sub-transistor T51r2 is electrically connected to the first signal output terminal Gn[n-1] of the previous-stage first-type gate circuit 22a. The second electrode T51r2D of the sixth inverter sub-transistor T51r2 is electrically connected to the second electrode T52rD of the twelfth inverter transistor T52r;

[0329] Among them, the fifth inverter sub-transistor T51r1 and the sixth inverter sub-transistor T51r2 are arranged along the first direction. By making the eleventh inverter transistor T51r include the fifth inverter sub-transistor T51r1 and the sixth inverter sub-transistor T51r2, the performance of the eleventh inverter transistor T51r can be improved.

[0330] In some embodiments, as Figure 7 , Figures 36 to 41As shown, the twelfth inverter transistor T52r includes a seventh inverter sub-transistor T52r1 and an eighth inverter sub-transistor T52r2. The gate T52r1G of the seventh inverter sub-transistor T52r1 and the first electrode T52r1S of the seventh inverter sub-transistor T52r1 are electrically connected to the second signal output terminal INI[n] of the second type gate circuit 22b of this stage. The second electrode T52r1D of the seventh inverter sub-transistor T52r1 is electrically connected to the first electrode T52r2S of the eighth inverter sub-transistor T52r2. The gate T52r2G of the eighth inverter sub-transistor T52r2 is electrically connected to the second signal output terminal INI[n] of the second type gate circuit 22b of this stage. The second electrode T52r2D of the eighth inverter sub-transistor T52r2 is electrically connected to the second electrode T51rD of the eleventh inverter transistor T51r;

[0331] Wherein, the seventh inverter sub-transistor T52r1 and the eighth inverter sub-transistor T52r2 are arranged along the first direction X. By making the twelfth inverter transistor T52r include the seventh inverter sub-transistor T52r1 and the eighth inverter sub-transistor T52r2, the performance of the twelfth inverter transistor T52r can be improved.

[0332] In some embodiments, as Figure 7 、 Figures 36 to 41 shown, the third pull-up control module 331 includes a seventh pull-up control transistor T11r and an eighth pull-up control transistor T12r. The gate T11rG of the seventh pull-up control transistor T11r is electrically connected to the second signal output terminal INI[n + 1] of the second type gate circuit 22b of the next stage. The first electrode T11rS of the seventh pull-up control transistor T11r is electrically connected to the first high potential signal line VGH1. The second electrode T11rD of the seventh pull-up control transistor T11r is electrically connected to the first electrode T12rS of the eighth pull-up control transistor T12r. The gate T12rG of the eighth pull-up control transistor T12r is electrically connected to the second signal output terminal INI[n + 1] of the second type gate circuit 22b of the next stage. The second electrode T12rD of the eighth pull-up control transistor T12r is electrically connected to the third pull-up node Q3[n];

[0333] Wherein, the fourteenth inverter transistor T54r, the eighth pull-up control transistor T12r and the seventh pull-up control transistor T11r are arranged along the second direction Y. By making the fourteenth inverter transistor T54r, the eighth pull-up control transistor T12r and the seventh pull-up control transistor T11r arranged along the second direction Y, the lateral space occupied by the third inverter module 335 and the third pull-up control module 331 can be reduced, and the border of the display panel 2 can be reduced.

[0334] In some embodiments, asFigure 7 , Figures 36 to 41 As shown in Figures 36 to 41 , the third pull-down module 333 includes a seventh pull-down transistor T31r and an eighth pull-down transistor T41r. The gate T31rG of the seventh pull-down transistor T31r is electrically connected to the third pull-down node QB3[n]. The first electrode T31rS of the seventh pull-down transistor T31r is electrically connected to the third low-potential signal line VGL3 of the display panel. The second electrode T31rD of the seventh pull-down transistor T31r is electrically connected to the third signal output terminal REF[n] of the third type of gate circuit 22c at this stage. The gate T41rG of the eighth pull-down transistor T41r is electrically connected to the first signal output terminal of the first type of gate circuit 22a at the previous stage. The first electrode T41rS of the eighth pull-down transistor T41r is connected to the second low-potential signal line VGL2. The second electrode T41rD of the eighth pull-down transistor T41r is electrically connected to the third pull-up node Q3[n].

[0335] Among them, the eighth pull-down transistor T41r and the fifteenth inverter transistor T55r are arranged along the second direction Y. By arranging the eighth pull-down transistor T41r and the fifteenth inverter transistor T55r along the second direction Y, the space occupied by the third pull-down module 333 and the third inverter module 335 can be reduced, and the border of the display panel 2 can be reduced.

[0336] In some embodiments, as Figure 7 , Figures 36 to 41 shown, the eighth pull-down transistor T41r includes a fifth pull-down sub-transistor T41r1 and a sixth pull-down sub-transistor T41r2. The gate T41r1G of the fifth pull-down sub-transistor T41r1 is electrically connected to the first signal output terminal of the first type of gate circuit 22a at the previous stage. The first electrode T41r1S of the fifth pull-down sub-transistor T41r1 is electrically connected to the second low-potential signal line VGL2. The second electrode T41r1D of the fifth pull-down sub-transistor T41r1 is electrically connected to the first electrode of the sixth pull-down sub-transistor T41r2 at the third internal node N3[n] of the third type of gate circuit. The gate T41r2G of the sixth pull-down sub-transistor T41r2 is electrically connected to the first signal output terminal of the first type of gate circuit 22a at the previous stage. The second electrode T41r2D of the sixth pull-down sub-transistor T41r2 is electrically connected to the third pull-up node Q3[n].

[0337] Among them, the fifth pull-down sub-transistor T41r1 and the sixth pull-down sub-transistor T41r2 are arranged along the second direction. By making the eighth pull-down transistor T41r include the fifth pull-down sub-transistor T41r1 and the sixth pull-down sub-transistor T41r2, the performance of the eighth pull-down transistor T41r can be improved, and since the fifth pull-down sub-transistor T41r1 and the sixth pull-down sub-transistor T41r2 are arranged along the second direction, the lateral area occupied by the eighth pull-down transistor T41r can be reduced, and the border of the display panel 2 can be reduced.

[0338] In some embodiments, as Figure 7 、 Figures 36 to 41 shown, the third pull-down sustain module 334 includes a third pull-down sustain transistor T42r. The gate T42rG of the third pull-down sustain transistor T42r is electrically connected to the third pull-down node QB3[n]. The first electrode T42rS of the third pull-down sustain transistor T42r is electrically connected to the second low potential signal line VGL2. The second electrode T42rD of the third pull-down sustain transistor T42r is electrically connected to the third pull-up node Q3[n];

[0339] Among them, in the second direction Y, the third pull-down sustain transistor T42r is arranged between the fifteenth inverter transistor T55r and the eighth pull-down transistor T41r; thus, the lateral space occupied by the third pull-down sustain transistor T42r, the fifteenth inverter transistor T55r, and the eighth pull-down transistor T41r can be reduced, and the border of the display panel 2 can be reduced.

[0340] In some embodiments, as Figure 7 、 Figures 36 to 41 shown, the third pull-down sustain transistor T42r includes a fifth pull-down sustain sub-transistor T42r1 and a sixth pull-down sustain sub-transistor T42r2. The gate T42r2G of the sixth pull-down sustain sub-transistor T42r2 is electrically connected to the third pull-down node QB3[n]. The first electrode T42r2S of the sixth pull-down sustain sub-transistor T42r2 is electrically connected to the second low potential signal line VGL2. The second electrode T42r2D of the sixth pull-down sustain sub-transistor T42r2 is electrically connected to the first electrode T42r1S of the fifth pull-down sustain sub-transistor T42r1 at a third internal node N3[n]. The gate T42r1G of the fifth pull-down sustain sub-transistor T42r1 is electrically connected to the third pull-down node QB3[n]. The second electrode T42r1D of the fifth pull-down sustain sub-transistor T42r1 is electrically connected to the third pull-up node Q3[n];

[0341] Among them, the fifth pull-down holding sub-transistor T42r1 and the sixth pull-down holding sub-transistor T42r2 are arranged along the second direction. By making the third pull-down holding transistor T42r include the fifth pull-down holding sub-transistor T42r1 and the sixth pull-down holding sub-transistor T42r2, the performance of the third pull-down holding transistor T42r can be improved, and since the fifth pull-down holding sub-transistor T42r1 and the sixth pull-down holding sub-transistor T42r2 are arranged along the second direction, the lateral space occupied by the third pull-down holding transistor T42r can be reduced, and the border of the display panel 2 can be reduced.

[0342] In some embodiments, as Figure 7 , Figures 36 to 41 shown, the third negative-bias protection module 336 includes a third negative-bias protection transistor T61r. The gate T61rG of the third negative-bias protection transistor T61r is electrically connected to the third pull-up node Q3[n]. The first electrode T61rS of the third negative-bias protection transistor T61r is electrically connected to the first high-potential signal line VGH1. The second electrode T61rD of the third negative-bias protection transistor T61r is electrically connected to the third internal node N3[n].

[0343] Among them, the third negative-bias protection transistor T61r is arranged along the first direction X on a side of the eighth pull-down transistor T41r away from the seventh pull-up control transistor T11r.

[0344] In some embodiments, as Figure 7 , Figures 36 to 41 shown, the third negative-bias protection transistor T61r includes a fifth negative-bias protection sub-transistor T61r1 and a sixth negative-bias protection sub-transistor T61r2. The gate T61r2G of the sixth negative-bias protection sub-transistor T61r2 is electrically connected to the third pull-up node Q3[n]. The first electrode T61r2S of the sixth negative-bias protection sub-transistor T61r2 is electrically connected to the first high-potential signal line. The second electrode T61r2D of the sixth negative-bias protection sub-transistor T61r2 is electrically connected to the first electrode of the fifth negative-bias protection sub-transistor T61r1. The gate T61r1G of the fifth negative-bias protection sub-transistor T61r1 is electrically connected to the third pull-up node Q3[n]. The second electrode T61r1D of the fifth negative-bias protection sub-transistor T61r1 is electrically connected to the third internal node N3[n].

[0345] Among them, the fifth negative-bias protection transistor T61r1 and the sixth negative-bias protection transistor T61r2 are arranged along the second direction. By making the third negative-bias protection transistor T61r include the fifth negative-bias protection transistor T61r1 and the sixth negative-bias protection transistor T61r2, the performance of the third negative-bias protection transistor T61r can be improved. Moreover, since the fifth negative-bias protection transistor T61r1 and the sixth negative-bias protection transistor T61r2 are arranged along the second direction, the lateral space occupied by the third negative-bias protection transistor T61r can be reduced, and the border of the display panel 2 can be decreased.

[0346] In some embodiments, as Figure 7 、 Figures 36 to 41 shown, the third pull-up module 332 includes a fifth pull-up transistor T21r. The gate T21rG of the fifth pull-up transistor T21r is electrically connected to the third pull-up node Q3[n]. The first electrode T21rS of the fifth pull-up transistor T21r is electrically connected to the second high-potential signal line VGH2 of the display panel. The second electrode T21rD of the fifth pull-up transistor T21r is electrically connected to the third signal output terminal REF[n] of the third type of gate circuit 22c at the same level.

[0347] Among them, the fifth pull-up transistor T21r and the third negative-bias protection transistor T61r are arranged along the second direction; thus, the lateral space occupied by the fifth pull-up transistor T21r and the third negative-bias protection transistor T61r can be reduced, and the border of the display panel 2 can be decreased.

[0348] In some embodiments, as Figure 7 shown, the third type of gate circuit 22c further includes a third capacitor C3. One plate of the third capacitor C3 is electrically connected to the third pull-up node Q3[n], and the other plate of the third capacitor C3 is electrically connected to the third signal output terminal REF[n] of the third type of gate circuit 22c at the same level.

[0349] Specifically, the third capacitor C3 includes a first plate C3a of the third capacitor C3 and a second plate C3b of the third capacitor C3. The first plate C3a of the third capacitor C3 includes a first part C3a1 of the first plate C3a of the third capacitor C3 and a second part C3a2 of the first plate C3a of the third capacitor C3.

[0350] In some embodiments, as Figure 7 shown, the third type of gate circuit 22c further includes a fourth capacitor C4. One plate of the fourth capacitor C4 is electrically connected to the first high-potential signal line VGH1, and the other plate of the fourth capacitor C4 is electrically connected to the second electrode T51rD of the eleventh inverter transistor T51r.

[0351] Specifically, the fourth capacitor C4 includes a first electrode plate C4a and a second electrode plate C4b of the fourth capacitor C4.

[0352] In some embodiments, as Figure 36 , Figure 37 shown, the display panel 2 includes a light-shielding layer 212, and the light-shielding layer 212 includes a first portion C3a1 of the first electrode plate C3a of the third capacitor C3, a first portion C4a1 of the first electrode plate C4a of the fourth capacitor C4, a fourth light-shielding connection line LS4, a fifth light-shielding connection line LS5, and a first signal output terminal Gn[n - 1] of the upper-level first type of gate circuit 22a;

[0353] The first portion C4a1 of the first electrode plate C4a of the fourth capacitor C4, the fourth light-shielding connection line LS4, the first signal output terminal Gn[n - 1] of the upper-level first type of gate circuit 22a, and the first portion C3a1 of the first electrode plate C3a of the third capacitor C3 are arranged along the first direction X; the fourth light-shielding connection line LS4 and the fifth light-shielding connection line LS5 are arranged along the second direction Y.

[0354] In some embodiments, as Figure 36 , Figure 38 shown, the display panel 2 includes an active layer 216, and the active layer 216 includes an active portion T11rA of the seventh pull-up control transistor T11r, an active portion T12rA of the eighth pull-up control transistor T12r, an active portion T21rA of the fifth pull-up transistor T21r, an active portion T31rA of the seventh pull-down transistor T31r, an active portion T41rA of the eighth pull-down transistor T41r, an active portion T42rA of the third pull-down maintenance transistor T42r, an active portion T51rA of the eleventh inverter transistor T51r, an active portion T52rA of the twelfth inverter transistor T52r, an active portion T53rA of the thirteenth inverter transistor T53r, an active portion T54rA of the fourteenth inverter transistor T54r, an active portion T55rA of the fifteenth inverter transistor T55r, an active portion T56rA of the sixteenth inverter transistor T56r, and an active portion T61rA of the third negative-bias protection transistor T61r;

[0355] Among them, the active portion T51rA of the eleventh inverter transistor T51r and the active portion T53rA of the thirteenth inverter transistor T53r are arranged in sequence along the second direction Y with the active portion T54rA of the fourteenth inverter transistor T54r, the active portion T11rA of the seventh pull-up control transistor T11r, and the active portion T12rA of the eighth pull-up control transistor T12r;

[0356] The active part T52rA of the twelfth inverter transistor T52r, the active part T56rA of the sixteenth inverter transistor T56r, the active part T55rA of the fifteenth inverter transistor T55r, the active part T42rA of the third pull-down maintenance transistor T42r, and the active part T41rA of the eighth pull-down transistor T41r are arranged in sequence along the second direction Y;

[0357] The active part T21rA of the fifth pull-up transistor T21r and the active part T61rA of the third negative-bias protection transistor T61r are arranged in sequence along the second direction Y;

[0358] The active part T51rA of the eleventh inverter transistor T51r, the active part T53rA of the thirteenth inverter transistor T53r, the active part T52rA of the twelfth inverter transistor T52r, the active part T21rA of the fifth pull-up transistor T21r, and the active part T31rA of the seventh pull-down transistor T31r are arranged in sequence along the first direction X.

[0359] Specifically, as Figure 38 shown, the active part T41rA of the eighth pull-down transistor T41r includes the active part T41r1A of the fifth pull-down sub-transistor T41r1 and the active part T41r2A of the sixth pull-down sub-transistor T41r2, and the active part T41r1A of the fifth pull-down sub-transistor T41r1 and the active part T41r2A of the sixth pull-down sub-transistor T41r2 are arranged along the second direction.

[0360] Specifically, as Figure 38 shown, the active part of the fifth pull-down maintenance transistor includes the active part T42r1A of the fifth pull-down maintenance sub-transistor T42r1 and the active part T42r2A of the sixth pull-down maintenance sub-transistor T42r2, and the active part T42r1A of the fifth pull-down maintenance sub-transistor T42r1 and the active part T42r2A of the sixth pull-down maintenance sub-transistor T42r2 are arranged along the second direction.

[0361] Specifically, as Figure 38 shown, the active part T51rA of the eleventh inverter transistor T51r includes the active part T51r1A of the fifth inverter sub-transistor T51r1 and the active part T51r2A of the sixth inverter sub-transistor T51r2, and the active part T51r1A of the fifth inverter sub-transistor T51r1 and the active part T51r2A of the sixth inverter sub-transistor T51r2 are arranged along the first direction.

[0362] Specifically, as Figure 38As shown, the active part T52rA of the twelfth inverter transistor T52r includes the active part T52r1A of the seventh inverter sub-transistor T52r1 and the active part T52r2A of the eighth inverter sub-transistor T52r2. The active part T52r1A of the seventh inverter sub-transistor T52r1 and the active part T52r2A of the eighth inverter sub-transistor T52r2 are arranged along the first direction.

[0363] Specifically, as Figure 38 shown, the active part T61rA of the third negative-bias protection transistor T61r includes the active part T61r1A of the fifth negative-bias protection sub-transistor T61r1 and the active part T61r2A of the sixth negative-bias protection sub-transistor T61r2. The active part T61r1A of the fifth negative-bias protection sub-transistor T61r1 and the active part T61r2A of the sixth negative-bias protection sub-transistor T61r2 are arranged along the second direction.

[0364] In some embodiments, as Figure 36 、 Figure 39 shown, the display panel 2 includes a first gate layer 218. The first gate layer 218 includes the gate T11rG of the seventh pull-up control transistor T11r, the gate T12rG of the eighth pull-up control transistor T12r, the gate T21rG of the fifth pull-up transistor T21r, the gate T31rG of the seventh pull-down transistor T31r, the gate T41rG of the eighth pull-down transistor T41r, the gate T42rG of the third pull-down maintenance transistor T42r, the gate T51rG of the eleventh inverter transistor T51r, the gate T52rG of the twelfth inverter transistor T52r, the gate T53rG of the thirteenth inverter transistor T53r, the gate T54rG of the fourteenth inverter transistor T54r, the gate T55rG of the fifteenth inverter transistor T55r, the gate T56rG of the sixteenth inverter transistor T56r, the gate T61rG of the third negative-bias protection transistor T61r, the second electrode plate C3b of the third capacitor C3, and the second electrode plate C4b of the fourth capacitor C4;

[0365] Among them, the gate T51rG of the eleventh inverter transistor T51r and the gate T53rG of the thirteenth inverter transistor T53r, the gate T54rG of the fourteenth inverter transistor T54r, the gate T11rG of the seventh pull-up control transistor T11r, and the gate T12rG of the eighth pull-up control transistor T12r are arranged in sequence along the second direction Y;

[0366] The gate T52rG of the twelfth inverter transistor T52r, the gate T56rG of the sixteenth inverter transistor T56r, the gate T55rG of the fifteenth inverter transistor T55r, the gate T42rG of the third pull-down maintenance transistor T42r, and the gate T41rG of the eighth pull-down transistor T41r are arranged in sequence along the second direction Y;

[0367] The gate T21rG of the fifth pull-up transistor T21r, the gate T61rG of the third negative-bias protection transistor T61r, and a part of the second plate C3b of the third capacitor C3 are arranged in sequence along the second direction Y;

[0368] The gate T53rG of the thirteenth inverter transistor T53r and the second plate C4b of the fourth capacitor C4 are arranged in sequence along the second direction Y;

[0369] The gate T31rG of the seventh pull-down transistor T31r and a part of the second plate C3b of the third capacitor C3 are arranged in sequence along the second direction Y;

[0370] The gate T51rG of the eleventh inverter transistor T51r, the gate T53rG of the thirteenth inverter transistor T53r, the gate T52rG of the twelfth inverter transistor T52r, the gate T21rG of the fifth pull-up transistor T21r, and the gate T31rG of the seventh pull-down transistor T31r are arranged in sequence along the first direction X.

[0371] Specifically, as Figure 39 shown, the gate T41rG of the eighth pull-down transistor T41r includes the gate T41r1G of the fifth pull-down sub-transistor T41r1 and the gate T41r2G of the sixth pull-down sub-transistor T41r2, and the gate T41r1G of the fifth pull-down sub-transistor T41r1 and the gate T41r2G of the sixth pull-down sub-transistor T41r2 are arranged along the second direction.

[0372] Specifically, as Figure 39 shown, the gate of the fifth pull-down maintenance transistor includes the gate T42r1G of the fifth pull-down maintenance sub-transistor T42r1 and the gate T42r2G of the sixth pull-down maintenance sub-transistor T42r2, and the gate T42r1G of the fifth pull-down maintenance sub-transistor T42r1 and the gate T42r2G of the sixth pull-down maintenance sub-transistor T42r2 are arranged along the second direction.

[0373] Specifically, as Figure 39 shown, the gate T51rG of the eleventh inverter transistor T51r includes the gate T51r1G of the fifth inverter sub-transistor T51r1 and the gate T51r2G of the sixth inverter sub-transistor T51r2, and the gate T51r1G of the fifth inverter sub-transistor T51r1 and the gate T51r2G of the sixth inverter sub-transistor T51r2 are arranged along the first direction.

[0374] Specifically, as Figure 39As shown, the gate T52rG of the twelfth inverter transistor T52r includes the gate T52r1G of the seventh inverter sub-transistor T52r1 and the gate T52r2G of the eighth inverter sub-transistor T52r2, and the gate T52r1G of the seventh inverter sub-transistor T52r1 and the gate T52r2G of the eighth inverter sub-transistor T52r2 are arranged along the first direction.

[0375] Specifically, as Figure 39 shown, the gate T61rG of the third negative-bias protection transistor T61r includes the gate T61r1G of the fifth negative-bias protection sub-transistor T61r1 and the gate T61r2G of the sixth negative-bias protection sub-transistor T61r2, and the gate T61r1G of the fifth negative-bias protection sub-transistor T61r1 and the gate T61r2G of the sixth negative-bias protection sub-transistor T61r2 are arranged along the first direction.

[0376] In some embodiments, Figure 36 、 Figure 40As shown, the display panel 2 includes a first source-drain layer 221. The first source-drain layer 221 includes the first electrode T11rS of the seventh pull-up control transistor T11r, the first electrode T12rS of the eighth pull-up control transistor T12r, the first electrode T21rS of the fifth pull-up transistor T21r, the first electrode T31rS of the seventh pull-down transistor T31r, the first electrode T41rS of the eighth pull-down transistor T41r, the first electrode T42rS of the third pull-down maintenance transistor T42r, the first electrode T51rS of the eleventh inverter transistor T51r, the first electrode T52rS of the twelfth inverter transistor T52r, the first electrode T53rS of the thirteenth inverter transistor T53r, the first electrode T54rS of the fourteenth inverter transistor T54r, the first electrode T55rS of the fifteenth inverter transistor T55r, the first electrode T56rS of the sixteenth inverter transistor T56r, the first electrode T61rS of the third negative-bias protection transistor T61r, the second electrode T11rD of the seventh pull-up control transistor T11r, the second electrode T12rD of the eighth pull-up control transistor T12r, the second electrode T21rD of the fifth pull-up transistor T21r, the second electrode T31rD of the seventh pull-down transistor T31r, the second electrode T41rD of the eighth pull-down transistor T41r, the second electrode T42rD of the third pull-down maintenance transistor T42r, the second electrode T51rD of the eleventh inverter transistor T51r, the second electrode T52rD of the twelfth inverter transistor T52r, the second electrode T53rD of the thirteenth inverter transistor T53r, the second electrode T54rD of the fourteenth inverter transistor T54r, the second electrode of the fifteenth inverter transistor T55r, the second electrode T56rD of the sixteenth inverter transistor T56r, the second electrode T61rD of the third negative-bias protection transistor T61r, the second part C3a2 of the first plate C3a of the third capacitor C3, the second part C4a2 of the first plate C4a of the fourth capacitor C4, and the ninth source connection line LD9;

[0377] Among them, the first electrode T51rS of the eleventh inverter transistor T51r, the first electrode T53rS of the thirteenth inverter transistor T53r, the first electrode T54rS of the fourteenth inverter transistor T54r, the first electrode T11rS of the seventh pull-up control transistor T11r, and the first electrode T12rS of the eighth pull-up control transistor T12r are arranged in sequence along the second direction Y.

[0378] The first electrode T52rS of the twelfth inverter transistor T52r, the first electrode T56rS of the sixteenth inverter transistor T56r, the first electrode T55rS of the fifteenth inverter transistor T55r, the first electrode T42rS of the third pull-down maintenance transistor T42r, and the first electrode T41rS of the eighth pull-down transistor T41r are arranged in sequence along the second direction Y;

[0379] The first electrode T21rS of the fifth pull-up transistor T21r and the first electrode T61rS of the third negative-bias protection transistor T61r are arranged in sequence along the second direction Y;

[0380] The first electrode T51rS of the eleventh inverter transistor T51r, the first electrode T53rS of the thirteenth inverter transistor T53r, the first electrode T52rS of the twelfth inverter transistor T52r, the first electrode T21rS of the fifth pull-up transistor T21r, and the first electrode T31rS of the seventh pull-down transistor T31r are arranged in sequence along the first direction X;

[0381] The fourth shielding connection line LS4 connects the first electrode T41rS of the eighth pull-down transistor T41r and the first electrode T55rS of the fifteenth inverter transistor T55r; the fifth shielding connection line LS5 connects the first electrode T11rS of the seventh pull-up control transistor T11r and the first electrode T61rS of the third negative-bias protection transistor T61r; the ninth source connection line LD9 connects the gate T41rG of the eighth pull-down transistor T41r and the first signal output terminal Gn[n - 1] of the previous-stage first-type gate circuit 22a.

[0382] Specifically, in the circuit diagram of the embodiment of the present application, in order to illustrate the connection relationship of each transistor, each transistor has a gate, a first electrode, and a second electrode. However, in the actual design process, in order to reduce the occupied space of the transistor, the electrodes of some transistors are formed by the same structure, and it can be understood that this structure can be regarded as the electrodes of two transistors. Similarly, the structures of the electrodes of other transistors can be determined.

[0383] Specifically, as Figures 36 to 41 shown, the first part C3a1 of the first plate C3a of the third capacitor C3 is connected to the second part C3a2 of the first plate C3a of the third capacitor C3.

[0384] Specifically, as Figures 36 to 41 shown, the first part C4a1 of the first plate C4a of the fourth capacitor C4 is connected to the second part C4a2 of the first plate C4a of the fourth capacitor C4.

[0385] Specifically, as Figure 40As shown, the first source-drain layer 221 includes the first electrode T41r1S of the fifth pull-down transistor T41r1, the second electrode T41r1D of the fifth pull-down transistor T41r1, the first electrode of the sixth pull-down transistor T41r2, and the second electrode T41r2D of the sixth pull-down transistor T41r2. The first electrode T41r1S of the fifth pull-down transistor T41r1, the second electrode T41r1D of the fifth pull-down transistor T41r1, and the second electrode T41r2D of the sixth pull-down transistor T41r2 are arranged in sequence along the second direction.

[0386] Specifically, as Figure 40 As shown, the first source-drain layer 221 includes the first electrode of the fifth pull-down holding transistor T42r1, the second electrode T42r1D of the fifth pull-down holding transistor T42r1, the first electrode T42r2S of the sixth pull-down holding transistor T42r2, and the second electrode T42r2D of the sixth pull-down holding transistor T42r2. The first electrode T42r2S of the sixth pull-down holding transistor T42r2, the second electrode T42r2D of the sixth pull-down holding transistor T42r2, and the second electrode T42r1D of the fifth pull-down holding transistor T42r1 are arranged in sequence along the second direction.

[0387] Specifically, as Figure 40 As shown, the first source-drain layer 221 includes the first electrode T51r1S of the fifth inverter transistor T51r1, the second electrode T51r1D of the fifth inverter transistor T51r1, the first electrode of the sixth inverter transistor T51r2, and the second electrode T51r2D of the sixth inverter transistor T51r2. The first electrode T51r1S of the fifth inverter transistor T51r1, the second electrode T51r1D of the fifth inverter transistor T51r1, and the second electrode T51r2D of the sixth inverter transistor T51r2 are arranged in sequence along the first direction.

[0388] Specifically, as Figure 40 As shown, the first source-drain layer 221 includes the first electrode T52r1S of the seventh inverter transistor T52r1, the second electrode T52r1D of the seventh inverter transistor T52r1, the first electrode of the eighth inverter transistor T52r2, and the second electrode T52r2D of the eighth inverter transistor T52r2. The first electrode T52r1S of the seventh inverter transistor T52r1, the second electrode T52r1D of the seventh inverter transistor T52r1, and the second electrode T52r2D of the eighth inverter transistor T52r2 are arranged in sequence along the first direction.

[0389] Specifically, as Figure 40As shown, the first source-drain layer 221 includes the first electrode of the fifth negative-bias protection transistor T61r1, the second electrode T61r1D of the fifth negative-bias protection transistor T61r1, the first electrode T61r2S of the sixth negative-bias protection transistor T61r2, and the second electrode T61r2D of the sixth negative-bias protection transistor T61r2. The second electrode T61r1D of the fifth negative-bias protection transistor T61r1, the second electrode T61r2D of the sixth negative-bias protection transistor T61r2, and the first electrode T61r2S of the sixth negative-bias protection transistor T61r2 are arranged in sequence along the second direction.

[0390] In some embodiments, as Figure 36 , Figure 41 shown, the display panel 2 includes a second source-drain layer 223. The second source-drain layer 223 includes a first high-potential signal line VGH1, a third clock signal line CKC, a second high-potential signal line VGH2, and a third low-potential signal line VGL3 arranged in sequence along the first direction X.

[0391] Specifically, the signals output on the first low-potential signal line VGL1, the second low-potential signal line VGL2, and the third low-potential signal line VGL3 can be different.

[0392] Specifically, the signals output on the first high-potential signal line VGH1 and the second high-potential signal line VGH2 can be different.

[0393] Specifically, in the embodiments of the present application, the first signal output terminal Gn[m] of another stage of the first type of gate circuit 22a can be the first signal output terminal of the next few stages of the first type of gate circuit 22a. For example, the first signal output terminal Gn[m] of another stage of the first type of gate circuit 22a can be the first signal output terminal of the next stage of the first type of gate circuit 22a. Taking n as 3, m can be 4. However, the embodiments of the present application are not limited thereto. The first signal output terminal Gn[m] of another stage of the first type of gate circuit 22a can be the first signal output terminal of the next two stages of the first type of gate circuit 22a or the first signal output terminal of other stages of the first type of gate circuit 22a.

[0394] Specifically, the above embodiments are described by taking some transistors including two sub-transistors as an example. However, the embodiments of the present application are not limited thereto, and each transistor can include only one sub-transistor.

[0395] Specifically, as Figure 4 shown, Figure 4A pixel driving circuit 21 of a display panel 2 is provided, which includes a driving transistor T1, a switching transistor T2, a reset transistor T3, and an initialization transistor T4. The driving transistor T1, the switching transistor T2, and the reset transistor T3 are connected to a first pixel node g, and the driving transistor T1 and the initialization transistor T4 are connected to a second pixel node s;

[0396] Wherein, the gate of the switching transistor T2 is electrically connected to the first signal output terminal Gn[n] of the first type of gate circuit 22a of the current stage, the gate of the initialization transistor T4 is electrically connected to the second signal output terminal INI[n] of the second type of gate circuit 22b of the current stage, and the gate of the reset transistor T3 is electrically connected to the third signal output terminal REF[n] of the third type of gate circuit 22c of the current stage. By electrically connecting the gate of the switching transistor, the gate of the initialization transistor, and the gate of the reset transistor to the first signal output terminal Gn[n] of the first type of gate circuit 22a of the current stage, the second signal output terminal INI[n] of the second type of gate circuit 22b of the current stage, and the third signal output terminal REF[n] of the third type of gate circuit 22c of the current stage respectively, signals can be input into the pixel driving circuit 21 through the gate driving circuit 22, so that the pixel driving circuit 21 can work normally.

[0397] Specifically, as Figure 2 shown, the display panel 2 further includes a light-emitting device LED. The gate of the driving transistor T1 is connected to the first node g, the first electrode of the driving transistor T1 is connected to the high-potential power supply line VDD, the second electrode of the driving transistor T1 is connected to the second node s, the first electrode of the switching transistor T2 is connected to the data line Vdata, the second electrode of the switching transistor T2 is connected to the first node g, the first electrode of the reset transistor T3 is connected to the reference line Vref, the second electrode of the reset transistor T3 is connected to the first node g, the first electrode of the initialization transistor T4 is connected to the initialization signal line Vini, the second electrode of the initialization transistor T4 is connected to the positive electrode of the light-emitting device LED, and the negative electrode of the light-emitting device LED is connected to the low-potential power supply line VSS.

[0398] Specifically, it can be understood that the display panel 2 includes multiple rows of sub-pixels. Correspondingly, multiple rows of pixel driving circuits 21 will be set to drive each sub-pixel. Correspondingly, multiple levels of gate driving circuits 22 will be set. Each level of gate driving circuit 22 can be connected to one or two corresponding rows of pixel driving circuits 21.

[0399] Specifically, the types of the transistors in the gate driving circuit 22 in the embodiments of the present application can be N-type transistors or P-type transistors. The types of the transistors in the pixel driving circuit 21 in the embodiments of the present application can be N-type transistors or P-type transistors.

[0400] Specifically, the active portions of the transistors in the gate driving circuit 22 in the embodiments of the present application may be formed by the active layer 216. The active portions of the transistors in the pixel driving circuit 21 in the embodiments of the present application may be formed by the semiconductor layer 214, or may be partially formed by the semiconductor layer 214 and partially formed by the active layer 216.

[0401] Specifically, the first electrode may be the source electrode and the second electrode may be the drain electrode; or the first electrode may be the drain electrode and the second electrode may be the source electrode.

[0402] Specifically, the above embodiments have described the display panel 2 in detail from aspects such as the circuit, timing, and transistor design of the display panel 2. It can be understood that when there is no conflict among the embodiments, the embodiments can be combined. For example, the first reset control line is disposed on the second source-drain layer, and the low-frequency signal line is disposed on the second source-drain layer.

[0403] Meanwhile, the embodiments of the present application provide a display device, which includes the display panel 2 as described in any one of the above embodiments.

[0404] In the description of the present application, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, "a plurality" means two or more, unless otherwise specifically defined.

[0405] In the above embodiments, each embodiment is described with emphasis. For the parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0406] Among the embodiments, embodiments, and related technical features of the present application, they can be combined and replaced with each other without conflict.

[0407] The above are only the preferred embodiments of the present application and do not impose any form of limitation on the present application. However, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still fall within the scope of the technical solution of the present application.

Claims

1. A display panel, characterized in that, Comprising: Multiple rows of pixels, each pixel including a light-emitting device and a pixel driving circuit; A multi-stage gate driving circuit, electrically connected to the corresponding pixel driving circuits respectively. Each stage of the gate driving circuit includes a first type of gate circuit, a second type of gate circuit, and a third type of gate circuit arranged along a first direction. The first type of gate circuit is electrically connected to at least a first clock signal line, a second clock signal line, a first high-potential signal line, a first low-potential signal line, a second low-potential signal line, a first reset control line, and a low-frequency signal line. The second type of gate circuit is electrically connected to at least the first high-potential signal line, the second low-potential signal line, a third clock signal line of the display panel, and a second reset control line of the display panel. The third type of gate circuit is electrically connected to at least the first high-potential signal line, a second high-potential signal line, the second low-potential signal line, and a third low-potential signal line; Wherein, the display panel further includes a substrate, an active layer, a first gate layer, a first source-drain layer, and a second source-drain layer arranged in sequence. At least one of the first clock signal line, the second clock signal line, the third clock signal line, the first high-potential signal line, the second high-potential signal line, the first low-potential signal line, the second low-potential signal line, the third low-potential signal line, the first reset control line, the second reset control line, and the low-frequency signal line is disposed on the second source-drain layer.

2. The display panel according to claim 1, wherein At least one of the first reset control line, the low-frequency signal line, the first clock signal line, the second clock signal line, the first low-potential signal line, and the second low-potential signal line is disposed on the second source-drain layer.

3. The display panel according to claim 2, wherein The first reset control line is disposed on the second source-drain layer.

4. The display panel according to claim 3, wherein The first type of gate circuit includes a first reset module, and the first reset module is electrically connected to the first reset control line; Wherein, the first source-drain layer includes a first source connection line. There is a spacing between the projection of the first reset control line on the substrate and the projection of the first reset module on the substrate, and the first reset control line is connected to the first reset module through the first source connection line.

5. The display panel according to claim 2, wherein, The low-frequency signal line is disposed on the second source-drain layer.

6. The display panel according to claim 5, wherein The first type of gate circuit includes a first inverting module, and the low-frequency signal line is electrically connected to the first inverting module; the projection of the low-frequency signal line on the substrate overlaps with the projection of the first inverting module on the substrate.

7. The display panel according to claim 2, wherein The first clock signal line is disposed on the second source-drain layer.

8. The display panel according to claim 7, wherein The first type of gate circuit includes a first pull-up control module, and the projection of the first clock signal line on the substrate overlaps with the projection of the first pull-up control module on the substrate.

9. The display panel according to claim 2, wherein, The second clock signal line is disposed on the second source-drain layer.

10. The display panel according to claim 9, wherein The first type of gate circuit includes a first pull-up module, and the projection of the second clock signal line on the substrate overlaps with the projection of the first pull-up module on the substrate.

11. The display panel according to claim 2, wherein The first low-potential signal line is disposed on the second source-drain layer.

12. The display panel according to claim 11, wherein The first type of gate circuit includes a first inverter module and a first pull-up module. The first inverter module and the first pull-up module are electrically connected to a first pull-up node. The projection of the first low-potential signal line on the substrate is located between the projection of the first inverter module on the substrate and the projection of the first pull-up module on the substrate.

13. The display panel according to claim 2, wherein The second low-potential signal line is disposed on the second source-drain layer.

14. The display panel according to claim 13, wherein The first type of gate circuit includes a first pull-up module. There is an overlap between the projection of the second low-potential signal line on the substrate and the projection of the first pull-up module on the substrate.

15. The display panel according to claim 1, characterized in that, The second reset control line is disposed on the second source-drain layer.

16. The display panel according to claim 15, characterized in that, The second type of gate circuit includes a second reset module. The second reset module is electrically connected to the second reset control line. The projection of the second reset control line on the substrate is located between the projection of the first type of gate circuit on the substrate and the projection of the second reset module on the substrate.

17. The display panel according to claim 1, wherein, At least one of the third clock signal line, the first high-potential signal line, the second high-potential signal line, and the third low-potential signal line is disposed on the second source-drain layer.

18. The display panel according to claim 17, wherein The first high-potential signal line is disposed on the second source-drain layer.

19. The display panel according to claim 18, characterized in that, The third type of gate circuit includes a third pull-up control module. There is an overlap between the projection of the first high-potential signal line on the substrate and the projection of the third pull-up control module on the substrate.

20. The display panel according to claim 17, wherein, The third clock signal line is disposed on the second source-drain layer.

21. The display panel according to claim 20, wherein The third type of gate circuit includes a third pull-up control module. There is an overlap between the projection of the third clock signal line on the substrate and the projection of the third pull-up control module on the substrate.

22. The display panel according to claim 17, wherein, The second high-potential signal line is disposed on the second source-drain layer.

23. The display panel according to claim 22, wherein, The third type of gate circuit includes a third pull-up module. The third pull-up module is electrically connected to the second high-potential signal line. There is an overlap between the projection of the second high-potential signal line on the substrate and the projection of the third pull-up module on the substrate.

24. The display panel according to claim 17, wherein The third low-potential signal line is disposed on the second source-drain layer.

25. The display panel according to claim 24, wherein The third type of gate circuit includes a third pull-down module. The third pull-down module is electrically connected to the third low-potential signal line. There is an overlap between the projection of the third low-potential signal line on the substrate and the projection of the third pull-down module on the substrate.

26. The display panel according to any one of claims 1 to 25, characterized in that, The gate driving circuit includes a plurality of transistors. The pixel driving circuit includes a plurality of transistors. The mobility of at least one transistor in the gate driving circuit is greater than the mobility of the transistors in the pixel driving circuit.

27. A display device, characterized in that, A display panel including any one of claims 1 to 26.

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