Display device

Abstract

A display device may include: a substrate; a pad electrode on the substrate; a first line on the substrate, the first line including a first metal layer and a second metal layer; an adhesive layer on the pad electrode; and a data driving circuit adjacent to the first line.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit and priority of Korean Patent Application No. 10 - 2024 - 0013717, filed on January 30, 2024, which is incorporated herein by reference in its entirety for all purposes. Technical field

[0003] Embodiments of the present invention relate to a display device. Background art

[0004] With the development of the information society, the demand for display devices that display images in various forms has been increasing. Therefore, in recent years, various display devices such as liquid crystal display devices and organic light - emitting display devices have been adopted. Summary of the invention

[0005] A display device may include a display area and a non - display area. A chip or a printed circuit board may be disposed in the non - display area of the display panel. A bonding process may be performed to connect the chip or the printed circuit board to the display panel.

[0006] When the bonding process is performed, cracks may occur in the display panel. As cracks occur, moisture may penetrate into the display panel. In addition, voltage lines may be damaged.

[0007] Embodiments of the present invention may provide a display device capable of preventing or at least reducing the occurrence of cracks in the display panel.

[0008] Embodiments of the present invention may provide a display device capable of preventing or at least reducing the bending of the display panel during the bonding process.

[0009] Embodiments of the present invention may provide a display device capable of preventing damage to voltage lines.

[0010] Embodiments of the present invention may provide a display device capable of reducing the resistance of a voltage supply line.

[0011] Embodiments of the present invention may provide a display device capable of achieving low power consumption by reducing resistance.

[0012] A display device according to an embodiment of the present invention may include: a substrate; a pad electrode on the substrate; a first line on the substrate, the first line including a first metal layer and a second metal layer; an adhesive layer on the pad electrode; and a data driving circuit adjacent to the first line.

[0013] According to an embodiment of the present invention, a display device capable of preventing or at least reducing the occurrence of cracks in the display panel may be provided.

[0014] According to an embodiment of the present invention, a display device capable of preventing or at least reducing bending of a display panel during a bonding process can be provided.

[0015] According to an embodiment of the present invention, a display device capable of preventing damage to a voltage line can be provided.

[0016] According to an embodiment of the present invention, a display device capable of reducing the resistance of a voltage supply line can be provided.

[0017] According to an embodiment of the present invention, a display device capable of achieving low power consumption by reducing resistance can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings, which are incorporated in and constitute a part of this specification, illustrate various aspects and embodiments of the present invention and, together with the description, serve to explain the principles and examples of the present invention for the purpose of providing a further understanding of the present invention.

[0019] Figure 1 is a system configuration diagram of a display device according to an embodiment of the present invention.

[0020] Figure 2 illustrates a display panel according to an embodiment of the present invention.

[0021] Figure 3 is a cross-sectional view of a display area of a display panel according to an embodiment of the present invention.

[0022] Figure 4 is a plan view of a display device according to an embodiment of the present invention.

[0023] Figure 5 illustrates, according to an embodiment of the present invention, in Figure 4 region A1.

[0024] Figure 6 is a cross-sectional view taken along line I-I' according to an embodiment of the present invention Figure 5 of.

[0025] Figures 7 to 9 illustrates, according to an embodiment of the present invention, in Figure 4 region A1.

[0026] Figures 10 to 11 illustrates, according to an embodiment of the present invention, in Figure 4 region A1.

[0027] Throughout the drawings and the detailed description, unless otherwise described, the same reference numerals should be understood to refer to the same elements, features, and structures. The dimensions, lengths, and thicknesses of layers, regions, and elements may be exaggerated for the purposes of clarity, illustration, and / or convenience. DETAILED DESCRIPTION

[0028] Now, let's refer in detail to the embodiments of the present invention, some examples of which may be shown in the accompanying drawings. In the following description, when a detailed description of a known method, function, structure, or configuration may unnecessarily obscure multiple aspects of the present invention, for the sake of brevity, its detailed description may be omitted. In addition, for the sake of brevity, repetitive descriptions may be omitted. The processes of the described processing steps and / or operations are non-limiting examples.

[0029] The order of the steps and / or operations is not limited to those set forth herein, but may be changed to occur in an order different from the order described herein, unless the steps and / or operations must occur in a specific order. In one or more examples, two consecutive operations may be performed substantially simultaneously, or depending on the functions or operations involved, the two operations may be performed in the reverse order or a different order.

[0030] Unless otherwise specified, similar reference numerals may refer to similar elements throughout, even when shown in different figures. Unless otherwise specified, the same reference numerals may be used throughout the specification and drawings to refer to the same or substantially the same elements. In one or more aspects, the same elements (or elements with the same name) in different figures may have the same or substantially the same functions and characteristics, unless otherwise specified. Only for the sake of convenience, the names of the corresponding elements used in the following description are selected, and thus these names may be different from those used in the actual product.

[0031] The advantages, features, and implementation methods of the present invention are illustrated by the embodiments described with reference to the accompanying drawings. However, the present invention may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Instead, these embodiments are examples provided to make the disclosure of the present invention thorough and complete to help those of ordinary skill in the art understand the inventive concept, rather than to limit the scope of protection of the present invention.

[0032] When describing the elements of the present invention, terms such as "first", "second", "A", "B", "(a)", or "(b)" may be used. These terms are intended to identify the corresponding elements from other elements and do not serve to define the essence, order, sequence, or quantity of the elements.

[0033] For the expression of one element (such as a layer, film, region, component, section, etc.) overlapping another element, etc., the element can not only directly contact, overlap, etc. with another element, but also indirectly overlap, etc. under the condition that one or more intermediate elements are provided or interposed between these elements, unless otherwise specified.

[0034] When describing temporal relationships, when the temporal order is described, for example, as "after", "subsequently", "next", "before", "prior", "preceding", etc., discontinuous or non-sequential situations may be included, and thus one or more other events may occur therebetween, unless more restrictive terms such as "exactly", "immediately", or "directly" are used.

[0035] The shapes, sizes (such as dimensions, lengths, widths, heights, thicknesses, positions, radii, diameters, and areas), ratios, rates, angles, quantities, number of elements, etc. (including those shown in the figures) disclosed herein are merely examples, and thus the present invention is not limited to the details shown. However, note that the relative sizes of the components shown in the figures are part of the present invention.

[0036] The term "exemplary" is used to indicate serving as an example or illustration. Embodiments are exemplary embodiments. Multiple aspects are exemplary aspects. In one or more embodiments, "embodiment", "example", "aspect", etc. should not be construed as being more excellent or more advantageous than other embodiments. Embodiments, examples, exemplary embodiments, aspects, etc. may refer to one or more embodiments, one or more examples, one or more exemplary embodiments, one or more aspects, etc., unless otherwise specified. In addition, the term "may" encompasses all meanings of the term "can".

[0037] The features of the embodiments of the present invention may be partially or wholly combined or combined with each other, and may interoperate and drive each other in various ways technically, as can be fully understood by those of ordinary skill in the art. The embodiments of the present invention may be implemented independently of each other, or may be implemented together in a mutually dependent relationship.

[0038] In the following description, various exemplary embodiments of the present invention are described in detail with reference to the accompanying drawings. Regarding the reference numerals of the elements of each figure, the same elements may be shown in other figures, and similar reference numerals may refer to similar elements, unless otherwise specified. The same or similar elements may be referred to by the same reference numeral, even if they are shown in different figures. In addition, for ease of description, the ratios, sizes, dimensions, and thicknesses of each element shown in the drawings may be different from the actual ratios, sizes, dimensions, and thicknesses. Therefore, the embodiments of the present invention are not limited to the ratios, sizes, dimensions, and thicknesses shown in the figures.

[0039] Figure 1 is a system configuration diagram of a display device 100 according to an embodiment of the present invention.

[0040] Refer to Figure 1, the display device 100 according to an embodiment of the present invention may include a display panel 110, which is a component configured to display an image, and a display driving circuit. The display driving circuit is a circuit configured to drive the display panel 110, and may include a data driving circuit 120, a gate driving circuit 130, and a display controller 140.

[0041] The display panel 110 may include a substrate 111 and a plurality of sub-pixels SP disposed on the substrate 111.

[0042] The substrate 111 of the display panel 110 may include a display area DA configured to display an image and a non-display area NDA disposed outside the display area DA.

[0043] A plurality of sub-pixels SP configured to display an image may be disposed in the display area DA, and the non-display area NDA may include a pad area that is provided along a first direction from the display area DA.

[0044] In the display panel 110 according to an embodiment of the present invention, the non-display area NDA may be smaller than the display area DA. In the present invention, the non-display area NDA may also be referred to as a "border".

[0045] For example, the non-display area NDA may include: a first non-display area disposed outside the display area DA in the first direction; a second non-display area disposed outside the display area DA in a second direction intersecting the first direction; a third non-display area disposed outside the display area DA in a direction opposite to the first direction; and a fourth non-display area disposed outside the display area DA in a direction opposite to the second direction. One or two of the first to fourth non-display areas may include a pad area to which the data driving circuit 120 is connected or joined (or attached). Among the first to fourth non-display areas, two or three non-display areas that do not include a pad area may have a very small size, but embodiments of the present invention are not limited thereto.

[0046] In another example, a boundary area between the display area DA and the non-display area NDA may be bendable, so that the non-display area NDA may be disposed below the display area. In this case, when a user views the display device 100 from a front view angle, there is no or almost no non-display area NDA visible to the user.

[0047] Various signal lines configured to drive the plurality of sub-pixels SP may be disposed on the substrate 111 of the display panel 110.

[0048] The display device 100 according to an embodiment of the present invention may be a liquid crystal display device or the like, or may be a self-luminous display device in which the display panel 110 itself emits light. When the display device 100 according to an embodiment of the present invention is a self-luminous display device, each of the plurality of sub-pixels SP may include a light-emitting device.

[0049] For example, the display device 100 according to an embodiment of the present invention may be an organic light-emitting display device, in which the light-emitting device is implemented as an organic light-emitting diode (OLED). In another example, the display device 100 according to an embodiment of the present invention may be an inorganic light-emitting display device, in which the light-emitting device is implemented as an inorganic-based light-emitting diode. In another example, the display device 100 according to an embodiment of the present invention may be a quantum dot display device, in which the light-emitting device is implemented using quantum dots that are self-luminous semiconductor crystals; or may be a micro-LED display device or a mini-LED display device. However, the embodiments of the present invention are not limited thereto.

[0050] The structure of each of the plurality of sub-pixels SP may be changed based on the type of the display device 100. For example, if the display device 100 is a self-luminous display device having self-luminous sub-pixels SP, each sub-pixel SP may include a self-luminous light-emitting device, one or more transistors, and one or more capacitors. However, the embodiments of the present invention are not limited thereto.

[0051] For example, various signal lines may include: a plurality of data lines DL configured to transmit (or transfer or provide) data signals (also referred to as data voltages or image signals); and a plurality of gate lines GL configured to transmit (or transfer or provide) gate signals (also referred to as scan signals).

[0052] For example, the plurality of data lines DL and the plurality of gate lines GL may cross each other. Each of the plurality of data lines DL may be arranged to extend in a first direction. Each of the plurality of gate lines GL may be arranged to extend in a second direction. Here, the first direction may be a column direction, and the second direction may be a row direction. Alternatively, the first direction may be a row direction, and the second direction may be a column direction. Hereinafter, for ease of explanation, a case where each of the plurality of data lines DL is arranged in the column direction and each of the plurality of gate lines GL is arranged in the row direction will be illustrated.

[0053] The data driving circuit 120 is a circuit configured to drive the plurality of data lines DL, and may output data signals to the plurality of data lines DL.

[0054] The data driving circuit 120 may receive image data DATA in digital form from the display controller 140, convert the received image data DATA into analog data signals, and output them to the plurality of data lines DL.

[0055] For example, the data driving circuit 120 may be connected to the display panel 110 by a tape automated bonding (TAB) method, or may be connected to the bonding pads of the display panel 110 using a chip on glass (COG) method or a chip on panel (COP) method, or may be implemented and connected to the display panel 110 using a chip on film (COF) method.

[0056] The data driving circuit 120 may be connected to one side (e.g., the upper side or the lower side or a portion) of the display panel 110. Depending on the driving method, the panel design method, etc., the data driving circuit 120 may be connected to both sides (e.g., the upper side and the lower side or two portions) of the display panel 110, or may be connected to two or more sides of the four sides of the display panel 110.

[0057] The data driving circuit 120 may be connected to the outside of the display area DA of the display panel 110, but optionally, the data driving circuit 120 may be disposed at the display area DA of the display panel 110.

[0058] The gate driving circuit 130 is a circuit configured to drive a plurality of gate lines GL, and may output a gate signal to the plurality of gate lines GL.

[0059] The gate driving circuit 130 may receive a first gate voltage corresponding to a turn-on level voltage and a second gate voltage corresponding to a cut-off level voltage together with various gate driving control signals GCS, and may generate a gate signal and provide the generated gate signal to the plurality of gate lines GL.

[0060] In the display device 100 according to an embodiment of the present invention, the gate driving circuit 130 may be built into the display panel 110 as a gate in panel (GIP) type. If the gate driving circuit 130 is a gate in panel type, the gate driving circuit 130 may be formed on the substrate of the display panel 110 during the manufacturing process of the display panel 110.

[0061] In the display device 100 according to an embodiment of the present invention, the gate driving circuit 130 may be disposed in the display area DA of the display panel 110. For example, the gate driving circuit 130 may be disposed in a first partial area (e.g., the left area or the right area within the display area DA) within the display area DA. In another example, the gate driving circuit 130 may be disposed in a first partial area (e.g., the left area or the right area within the display area DA) and a second partial area (e.g., the right area or the left area within the display area DA) within the display area DA.

[0062] In the present invention, the gate driving circuit 130 built into the display panel 110 as a gate in panel type may be referred to as a gate in panel circuit.

[0063] The display controller 140 may be a device configured to control the data driving circuit 120 and the gate driving circuit 130, and may control the driving timings of the plurality of data lines DL and the driving timings of the plurality of gate lines GL.

[0064] The display controller 140 may provide a data driving control signal DCS to the data driving circuit 120 to control the data driving circuit 120; and may provide a gate driving control signal GCS to the gate driving circuit 130 to control the gate driving circuit 130.

[0065] The display controller 140 may receive image data input from the host system 150, and provide the image data DATA to the data driving circuit 120 based on the input image data.

[0066] The display controller 140 may be implemented as a component separate from the data driving circuit 120, or may be integrated with the data driving circuit 120 and implemented as an integrated circuit.

[0067] The display controller 140 may be a timing controller used in display technology, or may be a control device capable of further performing other control functions in addition to performing the functions of a timing controller, or may be a control device different from a timing controller, or may be a control device other than a timing controller, or may be a circuit within a control device. The display controller 140 may be implemented using various circuits or electronic components such as an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a processor. However, embodiments of the present invention are not limited thereto.

[0068] The display controller 140 may be mounted on a printed circuit board, a flexible printed circuit, etc., and may be electrically connected to the data driving circuit 120 and the gate driving circuit 130 through the printed circuit board, the flexible printed circuit.

[0069] The display controller 140 may send / receive signals to / from the data driving circuit 120 according to one or more predetermined interfaces. For example, the interface may include a low voltage differential signaling (LVDS) interface, an embedded clock point-to-point interface (EPI), or a serial peripheral interface (SPI). However, embodiments of the present invention are not limited thereto.

[0070] In order to provide not only an image display function but also a touch sensing function, the display device 100 according to an embodiment of the present invention may include a touch sensor and a touch sensing circuit, the touch sensing circuit being configured to detect or sense whether a touch is generated by a touch object such as a finger or a pen, or detect a touch position by sensing the touch sensor.

[0071] The touch sensing circuit may include: a touch driving circuit configured to drive and sense a touch sensor to generate and output touch sensing data; and a touch controller configured to detect or sense the presence or absence of a touch or detect a touch position based on the touch sensing data.

[0072] The touch sensor may include a plurality of touch electrodes. The touch sensor may further include a plurality of touch lines electrically connecting the plurality of touch electrodes to the touch driving circuit.

[0073] The touch sensor may exist in the form of a touch panel outside the display panel 110, or may exist inside the display panel 110. If the touch sensor exists in the form of a touch panel outside the display panel 110, the touch sensor may be referred to as an external type. If the touch sensor is of the external type, the touch panel and the display panel 110 may be separately manufactured and combined during an assembly process. The external touch panel may include a touch panel substrate and a plurality of touch electrodes located on the touch panel substrate.

[0074] If the touch sensor exists inside the display panel 110, the touch sensor may be formed on the substrate SUB (see Figure 3 ) together with signal lines and electrodes for display driving during the manufacturing process of the display panel 110.

[0075] [[ID=!4]]The touch driving circuit may provide a touch driving signal to at least one of the plurality of touch electrodes and generate touch sensing data by sensing at least one of the plurality of touch electrodes.

[0076] The touch sensing circuit may perform touch sensing by a self - capacitance sensing method or a mutual - capacitance sensing method.

[0077] If the touch sensing circuit performs touch sensing by the self - capacitance sensing method, the touch sensing circuit may perform touch sensing based on the capacitance between each touch electrode and a touch object (such as a finger, a pen, etc.). According to the self - capacitance sensing method, each of the plurality of touch electrodes can be used as a driving touch electrode and a sensing touch electrode. The touch driving circuit may drive all or part (or some parts) of the plurality of touch electrodes and sense all or part (or some parts) of the plurality of touch electrodes.

[0078] If the touch sensing circuit performs touch sensing by the mutual - capacitance sensing method, the touch sensing circuit may perform touch sensing based on the capacitance between touch electrodes. According to the mutual - capacitance sensing method, the plurality of touch electrodes can be divided into driving touch electrodes and sensing touch electrodes. The touch driving circuit may drive the above - mentioned driving touch electrodes and sense the above - mentioned sensing touch electrodes.

[0079] The touch driving circuit and the touch controller included in the touch sensing circuit may be implemented as separate devices or as one device (or an integrated device). In addition, the touch driving circuit and the data driving circuit may be implemented as separate devices or as one device (or an integrated device).

[0080] The display device 100 may further include a power circuit that supplies various power sources to the display driving circuit and / or the touch sensing circuit.

[0081] The display device 100 according to an embodiment of the present invention may be a mobile terminal such as a smart phone or a tablet, or displays or TVs of various sizes, but is not limited thereto, and may be displays of various types and sizes capable of displaying information or images.

[0082] The display device 100 according to an embodiment of the present invention may further include electronic devices such as a camera (e.g., an image sensor) and a detection sensor (or a sensing sensor). For example, the detection sensor may be a sensor configured to detect an object or a human body by receiving light such as infrared light, ultrasonic light, or ultraviolet light. However, embodiments of the present invention are not limited thereto.

[0083] Figure 2 Illustrate a display panel 110 according to an embodiment of the present invention.

[0084] Refer to Figure 2 , the display panel 110 may include: a substrate 111 on which a plurality of sub-pixels SP are included; and an encapsulation layer 200 on the substrate 111. Herein, the encapsulation layer 200 may also be referred to as an encapsulation substrate or an encapsulation part, but embodiments of the present invention are not limited thereto.

[0085] Refer to Figure 2 , when the display device 100 according to an embodiment of the present invention is a self-emitting display device, each of the plurality of sub-pixels SP may include a light-emitting device ED and a sub-pixel circuit SPC configured to drive the light-emitting device ED. However, embodiments of the present invention are not limited thereto.

[0086] Refer to Figure 2 , the sub-pixel circuit SPC may include a plurality of pixel driving transistors configured to drive the light-emitting device ED and at least one capacitor. In the present invention, the sub-pixel circuit SPC may drive the light-emitting device ED by supplying a driving current to the light-emitting device ED at a predetermined (or pre-defined) timing. The light-emitting device ED may be driven by the driving current and emit light.

[0087] The plurality of pixel driving transistors may include: a driving transistor DT configured to drive the light-emitting device ED; and a scanning transistor ST that is turned on or off according to a scanning signal SC.

[0088] The driving transistor DT can supply a driving current to the light-emitting device ED.

[0089] The scanning transistor ST can be configured to control the electrical state of a corresponding node in the sub-pixel circuit SPC, or to control the state or operation of the driving transistor DT.

[0090] At least one capacitor can include a storage capacitor Cst to maintain a constant voltage during one frame.

[0091] To drive the sub-pixel SP, a data signal VDATA as an image signal and a scanning signal SC as a gate signal can be applied to the sub-pixel SP. In addition, a common pixel driving voltage including a first driving voltage VDD and a second driving voltage VSS can be applied to the sub-pixel SP to drive the sub-pixel SP.

[0092] The light-emitting device ED can include an anode AND, a light-emitting device layer EL, and a cathode CAT. The light-emitting device layer EL can be disposed between the anode AND and the cathode CAT.

[0093] In the case where the light-emitting device ED is an organic light-emitting device, the light-emitting device layer EL can include: a light-emitting layer EML; a first common layer COM1 located between the anode AND and the light-emitting layer EML; and a second common layer COM2 located between the light-emitting layer EML and the cathode CAT. The light-emitting layer EML can be disposed in each sub-pixel SP. In contrast, the first common layer COM1 and the second common layer COM2 can be commonly disposed across a plurality of sub-pixels SP. The light-emitting layer EML can be disposed in each light-emitting region, and the first common layer COM1 and the second common layer COM2 can be commonly disposed across a plurality of light-emitting regions and non-light-emitting regions. The first common layer COM1 and the second common layer COM2 can be collectively referred to as the common layer EL_COM. However, embodiments of the present invention are not limited thereto.

[0094] For example, the first common layer COM1 can include a hole injection layer HIL and a hole transport layer HTL. The second common layer COM2 can include an electron transport layer ETL and an electron injection layer EIL. The hole injection layer can inject holes from the anode AND into the hole transport layer, the hole transport layer can transport holes to the light-emitting layer EML, the electron injection layer can inject electrons from the cathode CAT into the electron transport layer, and the electron transport layer can transport electrons to the light-emitting layer EML.

[0095] For example, the cathode CAT can be electrically connected to the second common driving voltage line VSSL. The second common driving voltage VSS, which is a common pixel driving voltage, can be applied to the cathode CAT via the second common driving voltage line VSSL. The anode AND can be electrically connected to the first node N1 of the driving transistor DT of each sub-pixel SP. In the present invention, the second common driving voltage VSS can also be referred to as the base voltage VSS, and the second common driving voltage line VSSL can also be referred to as the base voltage line VSSL, but the embodiments of the present invention are not limited thereto.

[0096] For example, the anode AND can be a pixel electrode provided in each sub-pixel SP, and the cathode CAT can be a common electrode commonly provided in a plurality of sub-pixels SP. In another example, the cathode CAT can be a pixel electrode provided in each sub-pixel SP, and the anode AND can be a common electrode commonly provided in a plurality of sub-pixels SP. Hereinafter, for the sake of explanation, it is assumed that the anode AND is a pixel electrode and the cathode CAT is a common electrode.

[0097] Each light-emitting device ED can be formed by an overlapping portion of the anode AND, the light-emitting device layer EL, and the cathode CAT. A predetermined light-emitting region can be formed through each light-emitting device ED. For example, the light-emitting region of each light-emitting device ED can include an overlapping region of the anode AND, the light-emitting device layer EL, and the cathode CAT.

[0098] For example, the light-emitting device ED can be an organic light-emitting diode (OLED), an inorganic light-emitting diode, or a quantum dot light-emitting device. For example, in the case where the light-emitting device ED is an organic light-emitting diode OLED, the light-emitting device layer EL in the light-emitting device ED can include an organic light-emitting device layer EL containing an organic material.

[0099] The driving transistor DT can be a driving transistor configured to provide a driving current to the light-emitting device ED. The driving transistor DT can be connected between the first common driving voltage line VDDL and the light-emitting device ED.

[0100] The driving transistor DT can include a first node N1, a second node N2, and a third node N3.

[0101] The first node N1 of the driving transistor DT can be electrically connected to the light-emitting device ED, and the data signal VDATA can be applied to the second node N2. The driving voltage VDD from the first common driving voltage line VDDL can be provided to the third node N3.

[0102] The second node N2 may be a gate node, the first node N1 may be a source node or a drain node, and the third node N3 may be a drain node or a source node, but the embodiments of the present invention are not limited thereto. Hereinafter, for the sake of explanation, the case where the second node N2 in the driving transistor DT is a gate node, the first node N1 is a source node, and the third node N3 is a drain node will be described.

[0103] Figure 2 The scanning transistor ST in the shown sub-pixel circuit SPC may be a switching transistor, which is configured to transmit (or transfer) a data signal VDATA, which is an image signal, to the second node N2, which is the gate node of the driving transistor DT.

[0104] The scanning transistor ST may be turned on / off by a scanning signal SC, which is a kind of gate signal, applied via a scanning line SCL, which is a kind of gate line, and may control the electrical connection between the second node N2 of the driving transistor DT and the data line DL. The drain or source of the scanning transistor ST may be electrically connected to the data line DL, and the source or drain of the scanning transistor ST may be electrically connected to the second node N2 of the driving transistor DT. The gate of the scanning transistor ST may be electrically connected to the scanning line SCL.

[0105] The storage capacitor Cst may be electrically connected between the first node N1 and the second node N2 of the driving transistor DT. The storage capacitor Cst may be electrically connected to the first node N1 of the driving transistor DT. As another example, the storage capacitor Cst may include a first capacitor electrode and a second capacitor electrode. The first capacitor electrode may correspond to the first node N1 of the driving transistor DT. The second capacitor electrode may be electrically connected to the second node N2 of the driving transistor DT or may correspond to the second node N2 of the driving transistor DT.

[0106] The storage capacitor Cst may be an external capacitor specially formed outside the driving transistor DT, rather than a parasitic capacitor (such as Cgs, Cgd) that may exist as an internal capacitor between the first node N1 and the second node N2 of the driving transistor DT.

[0107] Each of the driving transistor DT and the scanning transistor ST may be an n-type transistor or a p-type transistor.

[0108] The display panel 110 may have a top-emitting structure or a bottom-emitting structure.

[0109] If the display panel 110 has a top-emitting structure, at least a part of the sub-pixel circuit SPC may overlap at least a part of the light-emitting device ED in the vertical direction. Optionally, if the display panel 110 has a bottom-emitting structure, the sub-pixel circuit SPC may not overlap the light-emitting device ED in the vertical direction.

[0110] As shown Figure 2 in FIG., the sub-pixel circuit SPC may have a 2T1C structure including two transistors DT and ST and a capacitor Cst. In some cases, the sub-pixel circuit SPC may further include one or more transistors or one or more capacitors, but the embodiments of the present invention are not limited thereto.

[0111] For example, the sub-pixel circuit SPC may have an 8T1C structure including eight transistors and a single capacitor. In another example, the sub-pixel circuit SPC may have a 6T2C structure including six transistors and two capacitors. In yet another example, the sub-pixel circuit SPC may have a 7T1C structure including seven transistors and a single capacitor. However, the embodiments of the present invention are not limited thereto.

[0112] According to the structure of the sub-pixel circuit SPC, the type and number of the gate signals and / or gate lines provided to the sub-pixel SP may be changed.

[0113] In addition, according to the structure of the sub-pixel circuit SPC, the type and number of the common pixel driving voltages provided to the sub-pixel SP may be changed.

[0114] Since the circuit elements (especially, the light-emitting device ED implemented by using an organic light-emitting diode (OLED) including an organic material) in each sub-pixel SP are vulnerable to external moisture or oxygen, the encapsulation layer 200 may be provided on the display panel 110 to prevent or at least reduce the penetration of oxygen into the circuit elements (especially, the light-emitting device ED). The encapsulation layer 200 may be configured in various shapes to prevent the light-emitting device ED from contacting moisture or oxygen.

[0115] Referring Figure 2 to FIG., in order to sense a user's touch, the display device 100 according to an embodiment of the present invention may include: a touch sensor layer TSL including a plurality of sensor electrodes; and a touch sensing circuit 210 configured to determine the presence or absence of a touch and touch coordinates by sensing the plurality of sensor electrodes.

[0116] The touch sensor layer TSL may be built in or embedded in the display panel 110. For example, the touch sensor layer TSL may be provided on the encapsulation layer 200 within the display panel 110.

[0117] In addition to the touch sensor layer TSL, the display panel 110 may further include: a plurality of touch pads to which the touch sensing circuit 210 is electrically connected; and a plurality of touch wirings TL for electrically connecting the plurality of sensor electrodes included in the touch sensor layer TSL to the plurality of touch pads connected to the touch sensing circuit 210.

[0118] Figure 3It is a cross-sectional view of a display area of a display panel according to an embodiment of the present invention.

[0119] Referring to Figure 3 , the substrate SUB may include a first substrate SUB1, an interlayer insulating film IPD, and a second substrate SUB2. The interlayer insulating film IPD may be located between the first substrate SUB1 and the second substrate SUB2. Since the substrate SUB is composed of the first substrate SUB1, the interlayer insulating film IPD, and the second substrate SUB2, moisture penetration can be prevented or at least reduced. For example, the first substrate SUB1 and the second substrate SUB2 may be polyimide (PI) substrates. The first substrate SUB1 may be referred to as a main PI substrate, and the second substrate SUB2 may be referred to as an auxiliary PI substrate, but the embodiments of the present invention are not limited thereto.

[0120] Various patterns (such as ACT, SD1, and GATE), various insulating films (such as MBUF, ABUF1, ABUF2, GI, ILD1, ILD2, and PAS0), and various metal patterns (such as TM, GM, ML1, and ML2) may be provided on the substrate SUB for configuring transistors, such as a driving transistor DRT, etc., but the embodiments of the present invention are not limited thereto.

[0121] The buffer layer MBUF may be provided on the second substrate SUB2, and the first buffer layer ABUF1 may be provided on the buffer layer MBUF.

[0122] The first metal layer ML1 and the second metal layer ML2 may be provided on the first buffer layer ABUF1. Here, the first metal layer ML1 and the second metal layer ML2 may be a light shielding layer LS configured to shield light, but are not limited thereto.

[0123] The second buffer layer ABUF2 may be provided on the first metal layer ML1 and the second metal layer ML2. The active layer ACT of the driving transistor DRT may be provided on the second buffer layer ABUF2. The active layer ACT may be a semiconductor layer, but the embodiments of the present invention are not limited thereto.

[0124] The first insulating film GI may be provided on the active layer ACT. For example, the first insulating film GI may be provided to cover the active layer ACT. The first insulating film GI may be a gate insulating film, but is not limited thereto.

[0125] The first gate GATE of the driving transistor DRT may be provided on the first gate insulating film GI. The gate material layer GM may be provided on the first insulating film GI at a position different from the formation position of the driving transistor DRT together with the first gate GATE of the driving transistor DRT.

[0126] The second insulating film ILD1 may be configured to cover the first gate GATE and the gate material layer GM. The metal pattern TM may be disposed on the second insulating film ILD1. The metal pattern TM may be disposed at a position different from the formation position of the driving transistor DRT. The third insulating film ILD2 may be configured to cover the metal pattern TM on the second insulating film ILD1. The metal pattern TM may be a metal layer, but embodiments of the present invention are not limited thereto. The second insulating film ILD1 may be an interlayer insulating film, but is not limited thereto. The third insulating film ILD2 may be an interlayer insulating film, but is not limited thereto.

[0127] Two first source-drains SD1 may be disposed on the third insulating film ILD2. One of the two first source-drains SD1 may be the source node of the driving transistor DRT, and the other may be the drain node of the driving transistor DRT. The two first source-drains SD1 may be electrically connected to one side (or a portion) and the other side (or another portion) of the active layer ACT via contact holes in the third insulating film ILD2, the second insulating film ILD1, and the first insulating film GI.

[0128] The portion of the active layer ACT overlapping the first gate GATE may be the channel region. One of the two first source-drains SD1 may be connected to one side (or a portion) of the channel region in the active layer ACT, and the other of the two first source-drains SD1 may be connected to the other side (or another portion) of the channel region in the active layer ACT.

[0129] The passivation layer PAS0 may be disposed on the two first source-drains SD1. The passivation layer PAS0 may be configured to cover the two first source-drains SD1. The planarization layers PLN1 and PLN2 may be disposed on the passivation layer PAS0. The planarization layers PLN1 and PLN2 may include a first planarization layer PLN1 and a second planarization layer PLN2, but are not limited thereto.

[0130] The first planarization layer PLN1 may be disposed on the passivation layer PAS0.

[0131] The second source-drain SD2 may be disposed on the first planarization layer PLN1. The second source-drain SD2 may be connected to one of the two first source-drains SD1 (corresponding to Figure 3 the second node of the driving transistor DRT in the sub-pixel SP) via a contact hole in the first planarization layer PLN1.

[0132] The second planarization layer PLN2 may be disposed on the second source-drain SD2. The second planarization layer PLN2 may be configured to cover the second source-drain SD2. The light-emitting device ED may be disposed on the second planarization layer PLN2.

[0133] The light-emitting device ED may include an anode AE, a light-emitting layer EL, and a cathode CE, but is not limited thereto.

[0134] The anode AE may be disposed on the second planarization layer PLN2. The anode AE may be electrically connected to the second source-drain SD2 via a contact hole in the second planarization layer PLN2.

[0135] The bank BANK may be provided to cover a part of the anode AE. A part of the bank BANK corresponding to the light-emitting area EA of the sub-pixel SP may be open.

[0136] A part of the anode AE may be exposed to the opening of the bank BANK (i.e., the opening part). The light-emitting layer EL may be disposed on the side surface of the bank BANK and the opening of the bank BANK (i.e., the opening part). All or part (or some parts) of the light-emitting layer EL may be disposed between adjacent banks BANK.

[0137] At the opening of the bank BANK, the light-emitting layer EL may contact the anode AE. The cathode CE may be disposed on the light-emitting layer EL.

[0138] The light-emitting device ED may be formed by the anode AE, the light-emitting layer EL, and the cathode CE. The light-emitting layer EL may include an organic layer, but is not limited thereto.

[0139] The encapsulation layer ENCAP may be disposed on the light-emitting device ED.

[0140] The encapsulation layer ENCAP may have a single-layer structure or a multi-layer structure. For example, as Figure 3 shown, the encapsulation layer ENCAP may include a first inorganic encapsulation layer PSA1, an organic encapsulation layer PCL, and a second inorganic encapsulation layer PAS2, but is not limited thereto.

[0141] For example, the first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 may be inorganic films, and the organic encapsulation layer PCL may be an organic film, but is not limited thereto. Among the first inorganic encapsulation layer PSA1, the organic encapsulation layer PCL, and the second inorganic encapsulation layer PAS2, the organic encapsulation layer PCL may be a planarization layer, but is not limited thereto.

[0142] The second inorganic encapsulation layer PAS2 may be disposed on the cathode CE and may be disposed closest to the light-emitting device ED. The first inorganic encapsulation layer PAS1 may be formed of an inorganic insulating material capable of low-temperature deposition. For example, the first inorganic encapsulation layer PAS1 may be silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiONx), or aluminum oxide (Al2O3), but is not limited thereto. For example, since the first inorganic encapsulation layer PAS1 is deposited in a low-temperature atmosphere, the first inorganic encapsulation layer PAS1 may prevent the light-emitting layer EL including an organic material vulnerable to a high-temperature atmosphere from being damaged during the deposition process.

[0143] The organic encapsulation layer PCL can be formed to have an area smaller than that of the first inorganic encapsulation layer PAS1. The organic encapsulation layer PCL can be formed to expose both ends of the first inorganic encapsulation layer PAS1. The organic encapsulation layer PCL can be used as a buffer to relieve the stress between each layer due to the bending of the display device 100, and the organic encapsulation layer PCL can also be used to enhance the planarization performance. For example, the organic encapsulation layer PCL can be an acrylic resin, an epoxy resin, a polyimide, a polyethylene, or a silicon oxycarbide (SiOC), and can be formed of an organic insulating material, but is not limited thereto. For example, the organic encapsulation layer PCL can be formed by an inkjet method, but is not limited thereto.

[0144] The second inorganic encapsulation layer PAS2 can be formed on the substrate SUB on which the organic encapsulation layer PCL is formed, covering the upper surfaces and side surfaces of each of the organic encapsulation layer PCL and the first inorganic encapsulation layer PAS1. The second inorganic encapsulation layer PAS2 can minimize or block the penetration of external moisture or oxygen into the first inorganic encapsulation layer PAS1 and the organic encapsulation layer PCL. For example, the second inorganic encapsulation layer PAS2 can be formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiONx), or aluminum oxide (Al2O3), but is not limited thereto.

[0145] Refer to Figure 3 , when the touch part TS is of the type built into the display panel 110, the touch part TS can be disposed on the encapsulation layer ENCAP.

[0146] The buffer film T-BUF can be disposed on the encapsulation layer ENCAP. The touch part TS can be disposed on the buffer film T-BUF. The buffer film T-BUF can be a touch buffer film, but is not limited thereto.

[0147] The touch part TS can include a touch metal TSM and a bridging metal BRG. The touch metal TSM and the bridging metal BRG can be disposed on different layers, but is not limited thereto.

[0148] The insulating film T-ILD can be disposed between the touch metal TSM and the bridging metal BRG.

[0149] For example, the touch metal TSM may include a first touch metal TSM, a second touch metal TSM, and a third touch metal TSM arranged adjacent to each other, but embodiments of the present invention are not limited thereto. In a case where the third touch metal TSM is disposed between the first touch metal TSM and the second touch metal TSM, and the first touch metal TSM and the second touch metal TSM need to be electrically connected to each other, the first touch metal TSM and the second touch metal TSM may be electrically connected to each other via a bridging metal BRG located on different layers. The bridging metal BRG may be insulated from the third touch metal TSM by an insulating film T-ILD.

[0150] When the touch part TS is formed on the display panel 110, a chemical solution (such as a developer or an etchant) used in the process or moisture from the outside may be generated. By disposing the touch part TS on the buffer film T-BUF, it is possible to prevent the chemical solution or moisture from penetrating into the light-emitting layer EL including an organic material during the manufacturing process of the touch part TS. Therefore, the buffer film T-BUF can prevent damage to the light-emitting layer EL that is vulnerable to chemicals or moisture.

[0151] The buffer film T-BUF may be formed at a low temperature below a specific temperature (for example, 100 degrees Celsius) in order to prevent or at least reduce damage to the light-emitting layer EL including an organic material vulnerable to high temperatures, and the buffer film T-BUF may be formed of an organic insulating material having a low dielectric constant of 1 to 3, but embodiments of the present invention are not limited thereto. For example, the buffer film T-BUF may be formed of an acrylic-based material, an epoxy-based material, or a siloxane-based material, but embodiments of the present invention are not limited thereto. When the display device 100 is bent, the encapsulation layer ENCAP may be damaged, and the touch metal TSM disposed on the buffer film T-BUF may be broken. However, even when the display device 100 is bent, the buffer film T-BUF formed of an organic insulating material and having a planarization property can prevent damage to the encapsulation layer ENCAP and / or rupture of the metal (such as TSM, BRG) constituting the touch part TS.

[0152] The protective layer PAC may be disposed on the touch part TS. For example, the protective layer PAC may be disposed to cover the touch part TS. The protective layer PAC may be an organic insulating film, but is not limited thereto.

[0153] Figure 4 is a plan view of a display device 100 according to an embodiment of the present invention.

[0154] Referring to Figure 4 , the substrate SUB may include a display area DA and a non-display area NDA.

[0155] The data driving circuit 120 and the gate driving circuits 130a and 130b may be disposed in the non-display area NDA.

[0156] The data driving circuit 120 can be disposed on the substrate SUB according to the chip mechanism on the panel. The data driving circuit 120 can be electrically connected to the display panel 110 via the data line DL.

[0157] The gate driving circuits 130a and 130b can be disposed on the substrate SUB. The gate driving circuits 130a and 130b can be disposed inside the display panel in the form of GIP. The gate driving circuits 130a and 130b can be disposed at the left and right ends of the display area DA on the substrate SUB, but the embodiments of the present invention are not limited thereto.

[0158] The gate driving circuits 130a and 130b can be electrically connected to the sub-pixels disposed in the display area DA via the gate lines GL. A plurality of gate lines GL can be arranged to cross a plurality of data lines DL, but the embodiments of the present invention are not limited thereto.

[0159] The plurality of gate lines GL can be scan signal lines SCL, sense signal SENL, and emission control lines EML.

[0160] When the gate line GL is the scan signal line SCL, the scan signal line SCL can be electrically connected to Figure 2 the gate node of the shown scan transistor ST.

[0161] When the gate line GL is the sense signal line SENL, the sense signal line SENL can be electrically connected to the gate node of the sense transistor. The sense transistor can be included in Figure 2 the shown sub-pixel SP, and the sense transistor can be electrically connected to the first node N1.

[0162] When the gate line GL is the emission control line EML, the emission control line EML can be electrically connected to the gate node of the emission control transistor. When the sub-pixel SP is configured as 7T1C or 8T1C, the emission control transistor can be included in the sub-pixel SP.

[0163] The display controller 140 can be disposed on the printed circuit board PCB (see Figure 5 ). The display controller 140 can control the data driving circuit 120 and the gate driving circuits 130a and 130b. The printed circuit board PCB can be bonded to the upper part of the substrate SUB.

[0164] The substrate SUB can include a bendable bending area BA. The bending area BA can be an area located between the data driving circuit 120 and the display area DA.

[0165] Figure 5 Illustrated is the first area A1 in Figure 4 according to an embodiment of the present invention. Figure 5It is a plan view of the bonding of the data driving circuit 120 and the substrate SUB according to an embodiment of the present invention. Figure 5 It is a plan view of the bonding of the data driving circuit 120 and the substrate SUB in a chip - on - film mechanism according to an embodiment of the present invention.

[0166] Refer to Figure 5 , the substrate SUB, the data driving circuit 120, and the printed circuit board PCB can be disposed in the first region A1.

[0167] The substrate SUB may include bonding pads BPAD. The printed circuit board PCB may be bonded to the substrate SUB at the bonding pads BPAD. The bonding pads BPAD may be bonding pads or connection pads, but the embodiments of the present invention are not limited thereto.

[0168] The bonding pads BPAD may be electrically connected to a plurality of gate voltage lines GVL1a and GVL1b, and plates (or plate - like portions) HVP1, LVP1a, and LVP1b. The plates HVP1, LVP1a, and LVP1b may include a first line HVP1 and a second line LVP1a or LVP1b. The bonding pads BPAD may include: a first region disposed at the outermost portion of the bonding pads BPAD; a second region disposed adjacent to the first region; and a third region electrically connected to the first line HVP1.

[0169] The second line LVP1 may be disposed at the left - most and right - most portions of the bonding pads BPAD. The second line LVP1a on the left side may be disposed at the left - most portion of the bonding pads BPAD. The second line LVP1b on the right side may be disposed at the right - most portion of the bonding pads BPAD.

[0170] The second line LVP1 may be a line configured to provide a voltage. The second line LVP1 may be a wide plate - shaped line, but the embodiments of the present invention are not limited thereto. The second line LVP1 may be a line provided with a base voltage. For example, the second line LVP1 may be a line provided with a voltage different from that of the first line HVP1, but not limited thereto. For example, the second line LVP1 may be a line provided with a low voltage, but not limited thereto. For example, the second line LVP1 may be a line provided with a low - potential driving voltage VSS, but not limited thereto.

[0171] The first line HVP1 may be disposed to be in contact with at least one or more of the bonding pads BPAD, but the embodiments of the present invention are not limited thereto. Refer to Figure 5 , the first line HVP1 may have a U - shape, but the embodiments of the present invention are not limited thereto. The first line HVP1 may include a left portion connected to the left - hand bonding pads BPAD and a right portion connected to the right - hand bonding pads BPAD.

[0172] The first high-voltage line HVP1 can be a line to which a voltage is supplied. The first high-voltage line HVP1 can be a wide plate-shaped line or a single line, but the embodiments of the present invention are not limited thereto. The first high-voltage line HVP1 can be a line to which a driving voltage is supplied. The first high-voltage line HVP1 can be a line to which a high voltage is supplied, but is not limited thereto. For example, the first high-voltage line HVP1 can be a line to which a high-potential driving voltage VDD is supplied, but is not limited thereto.

[0173] With respect to the horizontal direction, the first high-voltage line HVP1 can be disposed inside the second low-voltage line LVP1. The left portion of the first high-voltage line HVP1 can be disposed to the right of the second low-voltage line LVP1a on the left side. The right portion of the first high-voltage line HVP1 can be disposed to the left of the second low-voltage line LVP1b on the right side.

[0174] The gate voltage lines GVL1a and GVL1b can be disposed inside the first high-voltage line HVP1. The gate voltage lines GVL1a and GVL1b can be supplied with a clock signal or a start signal, but the embodiments of the present invention are not limited thereto. The second low-voltage line LVP1 can be electrically connected to the pad BPAD in the first region, and the gate voltage lines GVL1a and GVL1b can be electrically connected to the pad BPAD in the second region.

[0175] The gate voltage lines GVL1a and GVL1b can be disposed between the first high-voltage line HVP1 and the data driving circuit 120.

[0176] The gate voltage line GVL1a disposed on the left side can be arranged to extend downward from the pad BPAD and then bend to the left. The gate voltage line GVL1a disposed on the left side can be arranged to bend to the left and then extend downward again. The gate voltage line GVL1a on the left side can be disposed at the leftmost side of the first region A1.

[0177] The second low-voltage line LVP1a disposed on the left side can be disposed to the right of the gate voltage line GVL1a located on the left side, but is not limited thereto.

[0178] The gate voltage line GVL1b disposed on the right side can be arranged to extend downward from the pad BPAD and then bend to the right. The gate voltage line GVL1b disposed on the right side can be arranged to bend to the right and then extend downward again. The gate voltage line GVL1b disposed on the right side can be disposed at the rightmost side of the first region A1.

[0179] The second low-voltage line LVP1b disposed on the right side can be disposed to the left of the gate voltage line GVL1b located on the right side.

[0180] The lower portion of the first high-voltage line HVP1 can be disposed between the second low-voltage lines LVP1a and LVP1b.

[0181] The data driving circuit 120 can be disposed between the gate voltage line GVL1a located on the left side and the gate voltage line GVL1b disposed on the right side.

[0182] The data driving circuit 120 may have a rectangle elongated in the left - right direction, but embodiments of the present invention are not limited thereto.

[0183] The electrostatic discharge circuit ESD may be disposed between the lower portion of the first line HVP1 and the data driving circuit 120. The electrostatic discharge circuit ESD can prevent over - current from flowing due to static electricity.

[0184] The data driving circuit 120 may be electrically connected to a plurality of link lines LL (see Figure 6 ). The data driving circuit 120 may be electrically connected to the sub - pixels via the plurality of link lines LL.

[0185] Figure 6 is a cross - sectional view taken along the line I - I’ according to an embodiment of the present invention. Figure 5

[0186] Referring to Figure 6 , the data driving circuit 120 may be electrically connected to the pad electrode PE provided at the substrate SUB.

[0187] Referring to Figure 6 , a part of the gate voltage line GVL1b may be provided on the first insulating film GI. The substrate SUB, and the buffer layers MBUF and ABUF may be provided below the first insulating film GI. Since Figure 6 the structure of the substrate SUB, and the buffer layers MBUF and ABUF shown in Figure 3 is substantially the same as the structure of the substrate SUB, and the buffer layers MBUF and ABUF shown in

[0188] its repetitive description will be omitted or briefly given. The second insulating film ILD1 may be provided on the first insulating film GI and a part of the gate voltage line GVL1b. For example, the second insulating film ILD1 may be provided to cover the first insulating film GI and a part of the gate voltage line GVL1b.

[0189] The third insulating film ILD2 may be provided on the second insulating film ILD1. For example, the third insulating film ILD2 may be provided to cover the second insulating film ILD1.

[0190] The first planarization layer PLN1 may be provided on the third insulating film ILD2. The first planarization layer PLN1 may be provided to overlap with a part of the gate voltage line GVL1b. Figure 6 The first planarization layer PLN1 shown in Figure 3 may be formed simultaneously with the first planarization layer PLN1 shown in Figure 6 but embodiments of the present invention are not limited thereto. Figure 3The first planarization layer PLN1 shown is formed integrally, or may be arranged to be separated from Figure 3 the first planarization layer PLN1 shown.

[0191] The second planarization layer PLN2 may be arranged on the first planarization layer PLN1. For example, the second planarization layer PLN2 may be arranged to cover the first planarization layer PLN1. Referring to ​ , the left part of the first planarization layer PLN1 may have an inclined shape (or be beveled), but embodiments of the present invention are not limited thereto. Accordingly, the left part of the second planarization layer PLN2 may also have an inclined shape (or be beveled).

[0192] The buffer film T-BUF may be arranged on the second planarization layer PLN2. For example, the buffer film T-BUF may be arranged to cover the second planarization layer PLN2. ​ The buffer film T-BUF shown may be formed integrally with ​ the buffer film T-BUF shown, but embodiments of the present invention are not limited thereto.

[0193] The insulating film T-ILD may be arranged on the buffer film T-BUF. For example, the insulating film T-ILD may be arranged to cover the buffer film T-BUF. ​ The insulating film T-ILD shown may be formed integrally with ​ the insulating film T-ILD shown, but embodiments of the present invention are not limited thereto.

[0194] The connection line LL may be arranged on the second insulating film ILD1. The connection line LL may be a line for transmitting a signal. For example, the connection line LL may be a data line or a reference voltage line, but embodiments of the present invention are not limited thereto. ​ The connection line LL shown may include materials contained in ​ the gate material layer GM shown, but embodiments of the present invention are not limited thereto. ​ The connection line LL shown may be formed together with ​ the gate material layer GM shown, but embodiments of the present invention are not limited thereto.

[0195] The third insulating film ILD2 may be arranged on the connection line LL and the second insulating film ILD1. For example, the third insulating film ILD2 may be arranged to cover the connection line LL and the second insulating film ILD1.

[0196] The pad electrode PE may be arranged on the connection line LL and be separated from the connection line LL. In one embodiment, the pad electrode PE may include a first pad electrode PE1, a second pad electrode PE2, and a third pad electrode PE3.

[0197] The first pad electrode PE1 may be disposed on the third insulating film ILD2. The first pad electrode PE1 may be disposed to overlap with the connection line LL, but embodiments of the present invention are not limited thereto. ​ The illustrated first pad electrode PE1 may include the same material as ​ the illustrated first source-drain SD1, but embodiments of the present invention are not limited thereto. ​ The illustrated first pad electrode PE1 may be formed together with ​ the illustrated first source-drain SD1, but embodiments of the present invention are not limited thereto.

[0198] The second pad electrode PE2 may be disposed on the first pad electrode PE1. The second pad electrode PE2 may be disposed to cover the first pad electrode PE1. The second pad electrode PE2 may be disposed to overlap with the connection line LL. ​ The illustrated second pad electrode PE2 may include the same material as ​ the illustrated second source-drain SD2, but embodiments of the present invention are not limited thereto. ​ The illustrated second pad electrode PE2 may be formed together with ​ the illustrated second source-drain SD2, but embodiments of the present invention are not limited thereto.

[0199] The buffer film T-BUF may be disposed on the second pad electrode PE2 and the third insulating film ILD2. For example, the buffer film T-BUF may be disposed to cover the second pad electrode PE2 and the third insulating film ILD2.

[0200] The insulating film T-ILD may be disposed on the buffer film T-BUF. For example, the insulating film T-ILD may be disposed to cover the buffer film T-BUF.

[0201] In a region overlapping with the second pad electrode PE2, a part of the buffer film T-BUF and a part of the insulating film T-ILD may be etched and removed.

[0202] The third pad electrode PE3 may be electrically connected to the second pad electrode PE2 through the etched and removed part of the buffer film T-BUF. In a region overlapping with the second pad electrode PE2, the third pad electrode PE3 may be disposed to contact a part of the buffer film T-BUF and a part of the insulating film T-ILD. In a region overlapping with the second pad electrode PE2, the third pad electrode PE3 may be disposed to overlap with the second pad electrode PE2. The third pad electrode PE3 may be formed together with the touch metal TSM and / or the bridging metal BRG, but embodiments of the present invention are not limited thereto.

[0203] The adhesive layer AL can be disposed between the pad electrode PE and the data driving circuit 120. The adhesive layer AL can include conductive balls ALa and an adhesive ALb. The adhesive layer AL can be an anisotropic conductive film, but the embodiments of the present invention are not limited thereto.

[0204] The conductive balls ALa of the adhesive layer AL can have a spherical shape, but the embodiments of the present invention are not limited thereto. The conductive balls ALa can have conductivity. The conductive balls ALa can have a core and a shell structure surrounding the core. The core can include resin or the like, but the embodiments of the present invention are not limited thereto. The shell can be formed of any one of gold (Au), silver (Ag), nickel (Ni), copper (Cu), lead (Pb), and platinum (Pt) or an alloy, but the embodiments of the present invention are not limited thereto.

[0205] The adhesive ALb of the adhesive layer AL can include a resin-based material having adhesive properties, but the embodiments of the present invention are not limited thereto. The adhesive ALb of the adhesive layer AL can fix the conductive balls ALa inside the adhesive ALb. The adhesive ALb of the adhesive layer AL can connect or join the substrate SUB and the data driving circuit 120.

[0206] Referring to ​ , the data driving circuit 120 can include a first bump BP1 and a second bump BP2. The data driving circuit 120 can include a plurality of bumps. However, for ease of explanation, only the first bump BP1 and the second bump BP2 are shown, but the embodiments of the present invention are not limited thereto.

[0207] The first bump BP1 can be a bump configured to fix the position for joining the data driving circuit 120 to the substrate SUB. The first bump BP1 can be an alignment bump, but is not limited thereto. The first bump BP1 can be disposed to overlap with the first line.

[0208] The second bump BP2 can be a bump configured to transmit (or convey) signals. The second bump BP2 can be electrically connected to the pad electrode PE, and the second bump BP2 can provide signals to the pad electrode PE.

[0209] The data driving circuit 120 can be connected or joined to the substrate SUB through a bonding (or attaching) process.

[0210] The adhesive ALb of the adhesive layer AL can bond (or attach) the data driving circuit 120 and the substrate SUB so that the data driving circuit 120 and the substrate SUB do not separate or detach.

[0211] The conductive balls ALa of the adhesive layer AL can be disposed between the second bump BP2 and the pad electrode PE. The conductive balls ALa may contribute to signal transmission between the data driving circuit 120 and the pad electrode PE.

[0212] ​ Diagram of area A1 in another embodiment according to the present invention in ​ . ​ 、 8 And 9 are plan views of the data driving circuit 120 and the substrate SUB joined according to an embodiment of the present invention. ​ Diagram of the data driving circuit 120 and the substrate SUB joined by the chip-on-film mechanism.

[0213] When describing ​ , terms such as up and down, left and right, top and bottom, sides may be used. The descriptions of up and down, left and right, top and bottom, sides are based on ​ the plan view of

[0214] Referring to ​ , the substrate SUB, the data driving circuit 120, and the printed circuit board PCB may be disposed in the first area A1.

[0215] Referring to ​ , the area provided with the pad BPAD may include the first areas BPA1a and BPA1b, the second areas BPA2a and BPA2b, and the third areas BPA3a and BPA3b.

[0216] The first areas BPA1a and BPA1b may be the areas located at the left end and the right end of the pad BPAD.

[0217] The second areas BPA2a and BPA2b may be the areas disposed inside the pad BPAD compared with the first areas BPA1a and BPA1b. The second areas BPA2a and BPA2b may be disposed adjacent to the first areas BPA1a and BPA1b.

[0218] The third areas BPA3a and BPA3b may be the areas disposed inside the second areas BPA2a and BPA2b compared with the second areas BPA2a and BPA2b. The third areas BPA3a and BPA3b may be disposed adjacent to the second areas BPA2a and BPA2b.

[0219] The first areas BPA1a and BPA1b may be the areas closest to the ends of the pad BPAD, and the third areas BPA3a and BPA3b may be the areas farthest from the ends of the pad BPAD.

[0220] The second lines LVP2a and LVP2b may be electrically connected to the pads BPAD of the first areas BPA1a and BPA1b. The second lines LVP2a and LVP2b may be wide plate-like lines, but the embodiments of the present invention are not limited thereto.

[0221] Referring to ​, the second line LVP2a on the left side can be electrically connected to the pad BPAD in the first area BPA1a on the left side. The second line LVP2b on the right side can be electrically connected to the pad BPAD in the first area BPA1b on the right side.

[0222] Referring to ​ , the second line LVP2a on the left side can be in the form of a curve. The second line LVP2a on the left side can be arranged such that its middle portion bends to the right side. The second line LVP2a on the left side can include an area that overlaps with the gate voltage line GVL2a on the left side.

[0223] Referring to ​ , the second line LVP2b on the right side can be in the form of a curve. The second line LVP2b on the right side can be arranged such that its middle portion bends to the left side. The second line LVP2b on the right side can include an area that overlaps with the gate voltage line GVL2b on the right side.

[0224] The gate voltage lines GVL2a and GVL2b can be electrically connected to the pads BPAD in the second areas BPA2a and BPA2b. For example, the gate voltage lines GVL2a and GVL2b can be provided in the area between the first line HVP2 and the second lines LVP2a and LVP2b. For example, the gate voltage lines GVL2a and GVL2b can be arranged adjacent to the second lines LVP2a and LVP2b, and the second lines LVP2a and LVP2b are interposed between the gate voltage lines GVL2a and GVL2b.

[0225] Referring to ​ , the gate voltage line GVL2a on the left side can be electrically connected to the pad BPAD in the second area BPA2a on the left side. The gate voltage line GVL2b on the right side can be electrically connected to the pad BPAD in the second area BPA2b on the right side.

[0226] The gate voltage line GVL2a on the left side can be in the form of a curve. The gate voltage line GVL2a on the left side can be arranged such that its middle portion bends to the left side.

[0227] The gate voltage line GVL2b on the right side can be in the form of a curve. The gate voltage line GVL2b on the right side can be arranged such that its middle portion bends to the right side.

[0228] The first line HVP2 can be electrically connected to the pad BPAD in the third area BPA3. The first line HVP2 can have a wide plate shape, but the embodiments of the present invention are not limited thereto.

[0229] Referring to ​, where a left portion of the first line HVP2 that is connected to the pad BPAD can be electrically connected to the pad BPAD in the third region BPA3a on the left side. Among those portions where the first line HVP2 is connected to the pad BPAD, the first line HVP2 on the right side can be electrically connected to the pad BPAD in the third region BPA3b on the right side.

[0230] The first line HVP2 can be disposed closer to the data driving circuit 120 than the gate voltage lines GVL2a and GVL2b.

[0231] The first line HVP2 can have the following shape: a region where the data driving circuit 120 is to be disposed is removed from a rectangle. Accordingly, the shape of the first line HVP2 can be a U shape, but embodiments of the present invention are not limited thereto. For example, referring to ​ , the first line HVP2 can include a portion disposed below the data driving circuit 120, a portion disposed to the left of the data driving circuit 120, and a portion disposed to the right of the data driving circuit 120.

[0232] Referring to ​ , the first line HVP2 can be joined or connected to the pads BPAD in the third regions BPA3a and BPA3b, and can be disposed to extend downward from the portion joined to the pad BPAD. The first line HVP2 can be disposed adjacent to the left region LA3 and the right region LA4 of the data driving circuit 120, and can be arranged parallel to one side of the left region LA3 and the right region LA4. The substrate SUB can be bent in the left region LA3 and the right region LA4.

[0233] ​ The first line HVP2 shown can be disposed adjacent to the data driving circuit 120. For example, the first line HVP2 can be arranged to extend in a vertical direction from the portion joined to the pad BPAD. For example, the first line HVP2 can be disposed across the entire third regions BPA3a and BPA3b.

[0234] Since the first line HVP2 is arranged to extend in a vertical direction from the portion joined to the pad BPAD, a portion of the first line HVP2 adjacent to the pad BPAD can be relatively wide. Since the portion of the first line HVP2 adjacent to the pad BPAD is relatively wide, the resistance of the portion of the first line HVP2 adjacent to the pad BPAD can be reduced.

[0235] For example, since the first line HVP2 is arranged to extend in a vertical direction from the portion joined to the pad BPAD, the first line HVP2 can have a relatively small resistance in the portion adjacent to the pad BPAD. The resistance of the first line HVP2 adjacent to the pad BPAD can be relatively small, whereby power consumption can be reduced.

[0236] The data driving circuit 120 may include a first region LA1, a second region LA2, a third region LA3, and a fourth region LA4. For example, the first to fourth regions LA1 to LA4 may be first to fourth side regions, but are not limited to these terms.

[0237] The first region LA1 may be a region of the data driving circuit 120 adjacent to the pad BPAD. The first region LA1 may be an upper region or a top region of the data driving circuit 120.

[0238] The second region LA2 may be a region opposite to or facing the first region LA1. The second region LA2 may be a lower region or a bottom region of the data driving circuit 120.

[0239] The third region LA3 and the fourth region LA4 may be regions connecting the first region LA1 and the second region LA2 or located between the first region LA1 and the second region LA2. The third region LA3 and the fourth region LA4 may be a left region and a right region of the data driving circuit 120.

[0240] Each of the width of the first region LA1 and the width of the second region LA2 may be greater than each of the width of the third region LA3 and the width of the fourth region LA4.

[0241] When performing a bonding (or attaching) process, pressure may be applied from the upper part to the lower part of the data driving circuit 120. In addition, when performing a bonding (or attaching) process, heat may be applied to the data driving circuit 120. As the bonding (or attaching) process proceeds for a predetermined time, the data driving circuit 120 may be bonded to the substrate SUB.

[0242] When performing a bonding (or attaching) process, the portion of the substrate SUB overlapping with the data driving circuit 120 may be bent. Therefore, cracks may occur in the outer region of the data driving circuit 120. This may be referred to as a crack issue. Cracks may occur in the outer region of the data driving circuit 120, and cracks may also occur in the lower part of the first planarization layer ( ​ PLN1 therein). In addition, cracks may also occur in a part of the gate voltage line GVL1b provided in the lower part of the first planarization layer PLN1. As cracks occur, moisture may penetrate into the interior of the substrate SUB. In addition, as cracks occur in the line, it may be difficult to transmit signals or supply voltage. For example, cracks may occur in the gate voltage line GVL1b, so that the gate voltage line GVL1b cannot transmit signals.

[0243] Refer to ​ 、 8With respect to FIGS. 9, the data driving circuit 120 may be set to overlap a part of the first line HVP2. Since a part of the first line HVP2 is set to overlap the lower part of the data driving circuit 120, problems of cracks that may occur during the bonding process can be prevented. Therefore, problems of signal transmission or voltage supply that may occur due to cracks can be improved. Refer to ​ 、 8 With respect to FIGS. 9, the overlapping region OLA can be identified. The overlapping region OLA may be a region where a part of the first line HVP2 overlaps a part of the data driving circuit 120.

[0244] Refer to ​ With respect to FIG. 9, the overlapping region OLA may include a second region LA2, a third region LA3, and a fourth region LA4. Refer to ​ With respect to FIG. 10, the first line HVP2 may be set to overlap the data driving circuit 120 in the second region LA2, the third region LA3, and the fourth region LA4. For example, the first line HVP2 may overlap both ends of the data driving circuit 120 and may overlap the data driving circuit in the longitudinal direction. Since the first line HVP2 is set to extend in the vertical direction (or the up and down direction) from the part joined to the pad BPAD, the first line HVP2 may be set to overlap a part of the data driving circuit 120.

[0245] Refer to ​ With respect to FIG. 16, the overlapping region OLA may be the same as the second region LA2. Refer to ​ With respect to FIG. 18, the first line HVP2 may be set to overlap the data driving circuit 120 in the second region LA2. For example, the first line HVP2 may overlap the data driving circuit 120 in the longitudinal direction. Since the first line HVP2 is set to extend along the vertical direction (or the up and down direction) from the part joined to the pad BPAD, the first line HVP2 may be arranged adjacent to the data driving circuit 120.

[0246] Refer to ​ With respect to FIG. 23, the overlapping region OLA may include the third region LA3 and the fourth region LA4. Refer to ​ With respect to FIG. 25, the first line HVP2 may be set to overlap the data driving circuit 120 in the third region LA3 and the fourth region LA4. For example, the first line HVP2 may overlap both ends of the data driving circuit 120. Since the first line HVP2 is set to extend along the vertical direction (or the up and down direction) from the part joined to the pad BPAD, the first line HVP2 may be set to overlap a part of the data driving circuit 120.

[0247] When the bonding (or attaching) process is performed, the substrate SUB overlapping the outer edge of the data driving circuit 120 may bend. Therefore, cracks may occur on or inside the substrate SUB. Refer to ​Since a part of the first line HVP2 is arranged to overlap with a part of the data driving circuit 120 in the overlapping region OLA, cracks can be prevented from occurring on or inside the substrate SUB.

[0248] Refer to ​ , the first line HVP2 can have a wide plate shape. The area of the first line HVP2 can be larger than the areas of the gate voltage lines GVL2a and GVL2b. The gate voltage lines GVL2a and GVL2b can be in the form of thin lines. Since the first line HVP2 has a wide plate shape, the density of the first line HVP2 can be higher than the densities of the gate voltage lines GVL2a and GVL2b. Thus, the effect of dispersing the strain applied to the display panel 110 can be provided.

[0249] Refer to ​ , the first line HVP2 having a wide plate shape can be arranged adjacent to the data driving circuit 120. Since the first line HVP2 is arranged adjacent to the data driving circuit 120, cracks can be prevented from occurring in the voltage lines adjacent to the data driving circuit 120.

[0250] According to an embodiment of the present invention, a part of the first line HVP2 is arranged to overlap with a part of the data driving circuit 120, thereby reducing the stress and / or strain applied to the display panel 110 and preventing cracks from occurring on or inside the substrate SUB.

[0251] The first line HVP2 can have a wide plate shape. In the case of a wide plate shape, the metal density can be higher than the metal density of a thin line. According to an embodiment of the present invention, the first line HVP2 has a wide plate shape, which has a relatively high metal density compared to a thin line, thereby reducing the stress and / or strain applied to the display panel 110.

[0252] Refer to ​ [[ID=2,1]]The first line HVP2 is arranged to extend in the vertical direction (or up and down direction) from the part joined to the pad BPAD, so that the first line HVP2 can have a relatively small resistance in the part adjacent to the pad BPAD. The resistance of the first line adjacent to the pad BPAD can be relatively small, thereby reducing power consumption.

[0253] Refer to ​ , the electrostatic discharge circuit ESD can be arranged on the first line HVP2. Refer to ​ , two electrostatic discharge circuits ESD can be arranged on the first line HVP2. Although two electrostatic discharge circuits ESD are shown, it is not limited thereto. That is, two or more electrostatic discharge circuits can be included, but the embodiments of the present invention are not limited thereto.

[0254] ​The first line HVP1 shown can be set not to overlap with the electrostatic discharge circuit ESD. ​ The first line HVP2 shown can be set to overlap with the electrostatic discharge circuit ESD.

[0255] ​ The first line HVP2 shown can be disposed adjacent to the peripheral regions LA2, LA3, and LA4 of the data driving circuit 120. ​ The first line HVP1 shown can be not disposed in the region between the two electrostatic discharge circuits ESD. ​ The first line HVP2 shown can be disposed in the region between the two electrostatic discharge circuits ESD. For example, the electrostatic discharge circuit ESD can be connected between the first lines HVP2. ​ The first line HVP2 shown can be disposed adjacent to the second region LA2 of the data driving circuit 120 and can be arranged to extend in a downward direction from the second region LA2.

[0256] Since the electrostatic discharge circuit ESD is disposed on the first line HVP2, the first line HVP2 can be set to extend in a downward direction to the second region LA2 of the data driving circuit 120 and can be arranged to pass through the lower part of the electrostatic discharge circuit ESD. Refer to ​ and 9 , the first line HVP2 can be set to overlap with the data driving circuit 120 in the second region LA2 of the data driving circuit 120 and can be set to overlap with the electrostatic discharge circuit ESD in the lower part of the second region LA2. Refer to ​ , the first line HVP2 is disposed adjacent to the data driving circuit 120 in the second region LA2 of the data driving circuit 120 and can be set to overlap with the electrostatic discharge circuit ESD in the lower part of the second region LA2.

[0257] ​ is a diagram of the region A1 in ​ according to an embodiment of the present invention. ​ and 11 are cross-sectional views illustrating the data driving circuit 120 and the substrate SUB bonded by a chip-on-film mechanism.

[0258] In the description of ​ and 11 , the description of the structure that is substantially the same as the structure shown in ​ can be omitted.

[0259] The first line HVP2 can include a first source-drain SD1 and a second source-drain SD2. The first source-drain SD1 and the second source-drain SD2 can be disposed below (or under) the second planarization layer PLN2.

[0260] ​ and11 The first source-drain SD1 shown in ​ may include the same material as the first source-drain SD1 shown in ​ and 11 The first source-drain SD1 shown in ​ may be formed together with the first source-drain SD1 shown in

[0261] ​ and 11 The second source-drain SD2 shown in ​ may include the same material as the second source-drain SD2 shown in ​ and 11 The second source-drain SD2 shown in ​ may be formed together with the second source-drain SD2 shown in

[0262] Referring to ​ , the first source-drain SD1 may be disposed on the second interlayer insulating film (or the third insulating film) ILD2.

[0263] The first source-drain SD1 may be disposed to overlap with the second planarization layer PLN2. The first source-drain SD1 may be disposed closer to the data driving circuit 120 than the second planarization layer PLN2. For example, one side or the left end of the first source-drain SD1 may be disposed closer to the data driving circuit 120 than the second planarization layer PLN2. For example, the first source-drain SD1 may be a first metal layer, but is not limited thereto.

[0264] The second source-drain SD2 may be disposed on the first source-drain SD1. For example, the second source-drain SD2 may be disposed to cover the first source-drain SD1. The second source-drain SD2 may be disposed below a part of the data driving circuit 120. For example, the second source-drain SD2 may be disposed to extend further into the data driving circuit 120 than the first source-drain SD1. For example, the second source-drain SD2 may overlap with the adhesive layer AL and the data driving circuit 120. A part of the second source-drain SD2 may be disposed between the substrate SUB and the data driving circuit 120. For example, the second source-drain SD2 may be a second metal layer, but is not limited thereto.

[0265] The second source-drain SD2 may overlap with the data driving circuit 120. For example, the second source-drain SD2 may be disposed below the data driving circuit 120 and overlap with the data driving circuit 120. Therefore, when performing a bonding (or attaching) process, cracks can be prevented from appearing in the external region of the data driving circuit 120.

[0266] Referring to ​ , the first source-drain SD1 may be disposed on the second interlayer insulating film ILD2.

[0267] The second source-drain SD2 may be disposed on the first source-drain SD1 and may be disposed such that a part of the first source-drain SD1 is exposed. For example, the second source-drain SD2 may be disposed to expose the left part of the first source-drain SD1.

[0268] Referring to ​ , the first source-drain SD1 may be disposed below a part of the data driving circuit 120. A part of the first source-drain SD1 may be disposed between the substrate SUB and the data driving circuit 120.

[0269] For example, the first source-drain SD1 may be disposed below the data driving circuit 120 and may overlap with the data driving circuit 120. Accordingly, when a bonding (or attaching) process is performed, cracks may be prevented from occurring in an external region of the data driving circuit 120.

[0270] According to an embodiment of the present invention, a display device capable of preventing or at least reducing cracks from occurring in a display panel may be provided.

[0271] According to an embodiment of the present invention, a display device capable of preventing or at least reducing bending of a display panel during a bonding process may be provided.

[0272] According to an embodiment of the present invention, a display device capable of preventing or at least reducing damage to voltage lines may be provided.

[0273] According to an embodiment of the present invention, a display device capable of reducing the resistance of a line to which a voltage is supplied may be provided.

[0274] According to an embodiment of the present invention, a display device capable of achieving low power consumption by reducing resistance may be provided.

[0275] The display device according to embodiments of the present invention may be applied to mobile devices, video phones, smart watches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, curved devices, sliding devices, variable devices, electronic notebooks, e-book devices, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbook computers, workstations, navigation, automotive navigation, vehicle display devices, vehicle devices, theater devices, theater display devices, TVs, wallpaper devices, signage devices, game devices, laptop computers, monitors, cameras, camcorders, and home appliances, etc.

[0276] The embodiments of the present invention are briefly described as follows.

[0277] A display device according to an embodiment of the present invention may include: a substrate; pad electrodes on the substrate; a first line on the substrate, the first line including a first metal layer and a second metal layer; an adhesive layer on the pad electrodes; and a data driving circuit adjacent to the first line.

[0278] According to an embodiment of the present invention, the data driving circuit may overlap a part of the first line.

[0279] According to an embodiment of the present invention, the substrate may include pads that are bonded to a printed circuit board. The pads may include: a first region at the outermost part of the pads; a second region adjacent to the first region; and a third region electrically connected to the first line.

[0280] According to an embodiment of the present invention, the display device may further include: a second line electrically connected to the pads in the first region; and a gate voltage line electrically connected to the pads in the second region.

[0281] According to an embodiment of the present invention, the first line may be closer to the data driving circuit than the gate voltage line.

[0282] According to an embodiment of the present invention, the area of the first line may be larger than the area of the gate voltage line.

[0283] According to an embodiment of the present invention, the density of the first line may be greater than the density of the gate voltage line.

[0284] According to an embodiment of the present invention, the first metal layer may be on the substrate. The second metal layer may overlap a part of the data driving circuit.

[0285] According to an embodiment of the present invention, the second metal layer may be on the first metal layer.

[0286] According to an embodiment of the present invention, the first metal layer may overlap a part of the data driving circuit. The second metal layer may be on the first metal layer.

[0287] According to an embodiment of the present invention, the data driving circuit may include: a first bump overlapping the first line; and a second bump electrically connected to the pad electrode.

[0288] According to an embodiment of the present invention, the second bump may be outside the first bump.

[0289] According to an embodiment of the present invention, the data driving circuit may include: a first region adjacent to the pad; a second region facing the first region; and a third region located between the first region and the second region.

[0290] According to an embodiment of the present invention, the first line may overlap with the data driving circuit in the second region and the third region of the data driving circuit.

[0291] According to an embodiment of the present invention, the first line may overlap with the data driving circuit in the second region of the data driving circuit.

[0292] According to an embodiment of the present invention, the first line may overlap with the data driving circuit in the third region of the data driving circuit.

[0293] According to an embodiment of the present invention, the first line may be adjacent to the third region of the data driving circuit and may be parallel to one side of the third region of the data driving circuit.

[0294] According to an embodiment of the present invention, the substrate may be bent in the third region of the data driving circuit.

[0295] According to an embodiment of the present invention, the adhesive layer may include an adhesive and conductive balls in the adhesive.

[0296] According to an embodiment of the present invention, the display device may further include a controller that controls the data driving circuit. The controller may be on the printed circuit board, and the data driving circuit may be on the substrate.

[0297] According to an embodiment of the present invention, the display device may further include an electrostatic discharge circuit connected between a plurality of first lines including the first line.

[0298] According to an embodiment of the present invention, the gate voltage line may be between the first line and the data driving circuit.

[0299] According to an embodiment of the present invention, the gate voltage line on the left side may be arranged to extend downward from the pad and then bend to the left. The gate voltage line on the right side may be arranged to extend downward from the pad and then bend to the right. The second line on the left side may be on the right side of the gate voltage line on the left side. The second line on the right side may be on the left side of the gate voltage line on the right side.

[0300] According to an embodiment of the present invention, the adhesive layer may include an adhesive and conductive balls in the adhesive. The conductive balls may be between the second bump and the pad electrode.

[0301] According to an embodiment of the present invention, the gate voltage lines may be adjacent to the second lines, and the second lines may be interposed between the gate voltage lines.

[0302] According to an embodiment of the present invention, each of the width of the first region of the data driving circuit and the width of the second region of the data driving circuit may be greater than the width of the third region of the data driving circuit.

[0303] According to an embodiment of the present invention, the display device may further include an electrostatic discharge circuit between the lower portion of the first line and the data driving circuit.

[0304] According to an embodiment of the present invention, the first line may have a U shape.

[0305] According to an embodiment of the present invention, the first line may be arranged to extend in a vertical direction from a portion joined to the pad.

[0306] According to an embodiment of the present invention, the first line may be disposed across the entire third region.

[0307] It will be apparent to those of ordinary skill in the art that various modifications and variations can be made to the device of the present invention without departing from the scope of the present invention. Accordingly, the present invention is intended to cover modifications and variations of the present invention that fall within the scope of the appended claims and their equivalents.

Claims

1. A display device, comprising: a substrate; a pad electrode on the substrate; a first line on the substrate, the first line comprising a first metal layer and a second metal layer; an adhesive layer on the pad electrode; and a data driving circuit adjacent to the first line.

2. The display device according to claim 1, wherein the data driving circuit overlaps a part of the first line.

3. The display device according to claim 1, wherein the substrate comprises pads, and the pads are bonded to a printed circuit board, wherein the pads comprise: a first region at the outermost part of the pad; a second region adjacent to the first region; and a third region electrically connected to the first line.

4. The display device according to claim 3, further comprising: a second line electrically connected to the pads in the first region; and a gate voltage line electrically connected to the pads in the second region.

5. The display device according to claim 4, wherein the first line is closer to the data driving circuit than the gate voltage line.

6. The display device according to claim 4, wherein the area of the first line is larger than the area of the gate voltage line.

7. The display device according to claim 4, wherein the density of the first line is greater than the density of the gate voltage line.

8. The display device according to claim 1, wherein the first metal layer is on the substrate, and the second metal layer overlaps a part of the data driving circuit.

9. The display device according to claim 8, wherein the second metal layer is on the first metal layer.

10. The display device according to claim 1, wherein the first metal layer overlaps a part of the data driving circuit, and the second metal layer is on the first metal layer.

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