Display device and method of manufacturing same

Abstract

The invention relates to a display device and a manufacturing method thereof. The display device includes: a base substrate; a transistor disposed on the base substrate and including a semiconductor pattern and a gate electrode, the semiconductor pattern including a source region, an active region, and a drain region; a gate insulating pattern disposed on the semiconductor pattern; and a connection electrode disposed on the gate insulating pattern and electrically connected to the semiconductor pattern. A first hole extends through the transistor and is disposed adjacent to one of the source region and the drain region, the connection electrode is disposed on the same layer as the gate electrode, and the connection electrode includes a protruding pattern protruding toward the active region when viewed in a plane.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2024 - 0014725, filed with the Korean Intellectual Property Office on January 31, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] The present disclosure relates to a display device and a method of manufacturing the same. More specifically, the present disclosure relates to a display device including connection electrodes and a method of manufacturing a display device. Background art

[0004] Multimedia display devices such as televisions, mobile phones, tablet computers, computers, navigation devices, and game consoles include a display panel for displaying images. The display panel includes pixels for displaying images, and each of the pixels includes a light - emitting element that emits light and a driving element connected to the light - emitting element.

[0005] The light - emitting element and the driving element of the display panel are formed by stacking thin layers and patterning the thin layers using a mask. Since the display panel manufacturing process using a mask incurs a large cost, it is necessary to reduce the number of masks used for manufacturing a display device by simplifying the display panel manufacturing process. In addition, while simplifying the manufacturing process, it is necessary to manufacture a display panel with reliability. Summary of the invention

[0006] The present disclosure provides a display device having a simplified manufacturing process and improved display quality.

[0007] The present disclosure provides a method of manufacturing a display device.

[0008] Embodiments of the inventive concept provide a display device including: a base substrate; a transistor disposed on the base substrate and including a semiconductor pattern and a gate electrode, the semiconductor pattern including a source region, an active region, and a drain region; a gate insulating pattern disposed on the semiconductor pattern; and a connection electrode disposed on the gate insulating pattern and electrically connected to the semiconductor pattern. A first hole extends through the transistor and is disposed adjacent to one of the source region and the drain region. The connection electrode is disposed on the same layer as the gate electrode, and the connection electrode includes a protruding pattern that protrudes toward the active region when viewed in a plane.

[0009] The first holes are provided in plurality, and the protruding pattern is disposed between the plurality of first holes.

[0010] The protruding pattern includes a first protruding pattern extending from one of the source region and the drain region toward the active region in a direction parallel to a first direction.

[0011] The protruding pattern further includes a second protruding pattern extending from the first protruding pattern in a direction parallel to a second direction intersecting the first direction.

[0012] The connecting electrode is electrically connected to the source region or the drain region.

[0013] The protruding pattern is electrically connected to the active region.

[0014] The protruding pattern is directly disposed on the source region or the drain region.

[0015] The first hole does not overlap with the protruding pattern.

[0016] The protruding patterns are provided in plurality, and the plurality of protruding patterns protrude radially around a center point.

[0017] The connecting electrodes are provided in plurality, and the plurality of connecting electrodes include a first connecting electrode connected to the drain region and a second connecting electrode connected to the source region.

[0018] The display device further includes a first conductive pattern and a second conductive pattern, the first conductive pattern and the second conductive pattern are disposed between the base substrate and the transistor and are spaced apart from each other when viewed in a plane. The first conductive pattern is electrically connected to the drain region via the first connecting electrode, and the second conductive pattern is electrically connected to the source region via the second connecting electrode.

[0019] Each of the source region and the drain region includes a first portion having a first conductivity and a second portion having a second conductivity lower than the first conductivity.

[0020] The protruding pattern protrudes from the first portion.

[0021] The active region, the first portion, and the protruding pattern are electrically connected to each other.

[0022] The display device further includes a light-emitting element, the light-emitting element is disposed on the connecting electrode and includes a first electrode, a light-emitting layer, and a second electrode, the first electrode is connected to the connecting electrode. The connecting electrode electrically connects the first electrode and the transistor.

[0023] Embodiments of the inventive concept provide a display device including: a base substrate; a transistor disposed on the base substrate and including a semiconductor pattern and a gate electrode, the semiconductor pattern including a source region, an active region, and a drain region; a gate insulating pattern disposed on the semiconductor pattern; and a connecting electrode disposed on the gate insulating pattern and electrically connected to the semiconductor pattern. A first hole extends through the transistor and the first hole is adjacent to one of the source region and the drain region, the connecting electrode is disposed on the same layer as the gate electrode, the first holes are provided in plurality, and the connecting electrode includes a protruding pattern disposed between the plurality of first holes.

[0024] Embodiments of the inventive concept provide a method of manufacturing a display device. The method includes: preparing a preliminary display device including a base substrate, a preliminary semiconductor pattern, and a gate insulating pattern, the preliminary semiconductor pattern being disposed on the base substrate and including a source region, an active region, and a drain region, and the gate insulating pattern being disposed on the preliminary semiconductor pattern; forming a first opening through the gate insulating pattern to expose a first portion of the preliminary semiconductor pattern; forming a conductive layer on the gate insulating pattern; forming a second opening through the conductive layer to expose a portion of the first portion of the preliminary semiconductor pattern and forming a gate electrode and a connection electrode with the conductive layer; and forming a first hole through the preliminary semiconductor pattern adjacent to one of the source region and the drain region to form a semiconductor pattern with the preliminary semiconductor pattern. The connection electrode includes a protruding pattern protruding toward the active region when viewed in a plane.

[0025] The method further includes doping a first portion of the preliminary semiconductor pattern exposed through the first opening after forming the first opening.

[0026] Forming the gate electrode and the connection electrode includes: forming a photoresist layer on the conductive layer, defining a photolithography opening through the photoresist layer; and etching the conductive layer.

[0027] The connection electrode is disposed on the gate insulating pattern and electrically connected to the semiconductor pattern, and the connection electrode is disposed on the same layer as the gate electrode.

[0028] According to the above, the connection electrode of the display device includes a protruding pattern protruding toward the active region, and current flows through the protruding pattern. Therefore, when current flows from the active region to the source region and the drain region, the resistance is reduced, and the current flows more smoothly.

[0029] According to the above, an additional process of forming the connection electrode using a mask is not required, and the connection electrode including the same material as the gate serves as the source and the drain. Therefore, the manufacturing process is simplified and the manufacturing cost is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other advantages of the present disclosure will become readily apparent by reference to the following detailed description when considered in conjunction with the accompanying drawings.

[0031] Figure 1 is a perspective view of a display device according to an embodiment of the present disclosure.

[0032] Figure 2A is an exploded perspective view of a display device according to an embodiment of the present disclosure.

[0033] Figure 2B is a cross-sectional view of a display module according to an embodiment of the present disclosure.

[0034] Figure 3is a plan view of a display panel according to an embodiment of the present disclosure.

[0035] Figure 4 It is along Figure 3 A cross-sectional view taken along line II'.

[0036] Figure 5 is with Figure 4 The plan view corresponding to the circuit layer.

[0037] Figure 6 yes Figure 5 An enlarged plan view of area AA'.

[0038] Figure 7A It is along Figure 6 A sectional view taken along line II-II'.

[0039] Figure 7B It is along Figure 6 A cross-sectional view taken along line III-III'.

[0040] Figure 8 According to the embodiment of the present disclosure Figure 4 The plan view corresponding to the circuit layer.

[0041] Figure 9 yes Figure 8 An enlarged plan view of area BB'.

[0042] Figure 10 According to the embodiment of the present disclosure Figure 4 The plan view corresponding to the circuit layer.

[0043] Figure 11 yes Figure 10 An enlarged plan view of area CC'.

[0044] Figure 12 According to the embodiment of the present disclosure Figure 4 The plan view corresponding to the circuit layer.

[0045] Figure 13 yes Figure 12 An enlarged plan view of region DD'.

[0046] Figure 14 、 Figure 15 、 Figure 16 、 Figure 17 、 Figure 18 、 Figure 19 、 Figure 20 、 Figure 21 、 Figure 22 and Figure 23 is a cross-sectional view illustrating a method of manufacturing a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0047] In the present disclosure, it will be understood that when an element (or region, layer, or portion) is referred to as being "on," "connected to," or "coupled to" another element (or region, layer, or portion), it can be directly on, directly connected to, or directly coupled to the other element (or region, layer, or portion), or intervening elements (or regions, layers, or portions) may be present.

[0048] Like reference numerals throughout the figures denote like elements. In the figures, the thickness, proportions, and dimensions of components are exaggerated for effective description of the technical content. As used herein, the term "and / or" can include any combination and all combinations of one or more of the associated listed items.

[0049] It will be understood that although terms such as first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element discussed below may be termed a second element without departing from the teachings of the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "a," "an," and "the" are also intended to include the plural forms.

[0050] For ease of description, spatial relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures.

[0051] It will also be understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0052] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0053] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.

[0054] Figure 1 is a perspective view of a display device DD according to an embodiment of the present disclosure.

[0055] Reference Figure 1 The display device DD can be activated in response to an electrical signal and can display an image IM. The display device DD can include various embodiments to provide the image IM to a user. As an example, the display device DD can be applied to large-sized electronic devices such as televisions, outdoor billboards, etc., and medium- and small-sized electronic devices such as monitors, mobile phones, tablet computers, navigation devices, gaming machines, etc. However, these are merely examples, and as long as the concept of the present disclosure is not departed from, the display device DD can be applied to other electronic devices.

[0056] When viewed in a plane, the display device DD can have a rectangular shape having a long side extending in a first direction DR1 and a short side extending in a second direction DR2 intersecting the first direction DR1. However, the shape of the display device DD should not be limited to a rectangular shape, and the display device DD can have various shapes such as a circular shape, a polygonal shape, etc.

[0057] The display device DD can display the image IM through a display surface IS toward a third direction DR3 that is substantially perpendicular to the plane defined by the first direction DR1 and the second direction DR2. The normal direction of the display surface IS can be substantially parallel to the third direction DR3. The display surface IS through which the image IM is displayed can correspond to the front surface of the display device DD. The image IM can include a still image and a video. Figure 1 An application icon is shown as a representative example of the image IM.

[0058] In the present embodiment, the front (or upper) surface and the rear (or lower) surface of each component of the display device DD can be defined with respect to the third direction DR3. The front surface and the rear surface can be opposite to each other in the third direction DR3, and the normal direction of each of the front surface and the rear surface can be substantially parallel to the third direction DR3. The distance between the front surface and the rear surface of each component in the third direction DR3 can correspond to the thickness of the component in the third direction DR3.

[0059] In the present disclosure, the expression "when viewed in a plane" can mean a state of viewing in the third direction DR3. In the present disclosure, the expression "when viewed in a cross-section" can mean a state of viewing in the first direction DR1 or the second direction DR2. The directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 are relative to each other, and thus, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 can be changed to other directions.

[0060] Figure 1A display device DD including a flat display surface IS is shown as a representative example. However, the shape of the display surface IS of the display device DD should not be limited to this or restricted thereby, and the display surface IS may have a curved shape or a three-dimensional shape.

[0061] The display device DD can be flexible. The term "flexible" as used herein refers to the property of being able to bend, from a fully bent structure to a structure bent at the nanometer level. For example, the flexible display device DD can be a curved display device or a foldable display device. However, the present disclosure should not be limited to this or restricted thereby. According to an embodiment, the display device DD can be rigid.

[0062] The display surface IS of the display device DD can include a display portion D-DA and a non-display portion D-NDA. The display portion D-DA can be a portion that displays an image IM within the front surface of the display device DD, and a user can view the image IM through the display portion D-DA. In the present embodiment, the display portion D-DA having a quadrilateral shape in a plane is shown as a representative example. However, the display portion D-DA can have various shapes according to the design of the display device DD.

[0063] The non-display portion D-NDA can be a portion that does not display the image IM within the front surface of the display device DD. The non-display portion D-NDA can have a predetermined color and can block light. The non-display portion D-NDA can be disposed adjacent to the display portion D-DA. As an example, the non-display portion D-NDA can be disposed outside the display portion D-DA and can surround the display portion D-DA. However, this is merely an example. The non-display portion D-NDA can be defined as being adjacent to only one side of the display portion D-DA, or can be defined in the side surface rather than the front surface of the display device DD. According to an embodiment, the non-display portion D-NDA can be omitted.

[0064] According to an embodiment, the display device DD can sense an external input applied to it from the outside. The external input can include various external inputs such as pressure, temperature, light, etc. provided from the outside. The external input can include a proximity input (e.g., a hover input) applied when approaching the display device DD at a predetermined distance or in proximity, and a touch input (e.g., a touch by a user's hand or pen).

[0065] Figure 2A is an exploded perspective view of a display device DD according to an embodiment of the present disclosure. Figure 2B is a cross-sectional view of a display module DM according to an embodiment of the present disclosure.

[0066] Reference Figure 2A and Figure 2B, the display device DD may include a window WM, a display module DM, and a housing HAU. The display module DM may include a display panel DP and a light control member.

[0067] The window WM may be coupled to the housing HAU to form the appearance of the display device DD and provide an internal space for accommodating components (e.g., the display module DM) of the display device DD.

[0068] The window WM may be disposed on the display module DM. The window WM may protect the display module DM from external impacts. The front surface of the window WM may correspond to the display surface IS of the display device DD (e.g., see Figure 1 ). The front surface of the window WM may include a transmissive region TA and a border region BA.

[0069] The transmissive region TA of the window WM may be an optically transparent region. The window WM may transmit an image provided from the display module DM through the transmissive region TA, and a user may view the image. The transmissive region TA of the window WM may correspond to the display portion D-DA of the display device DD (e.g., see Figure 1 ).

[0070] The window WM may include an optically transparent insulating material. As an example, the window WM may include glass, sapphire, or a plastic material. The window WM may have a single-layer or multi-layer structure. The window WM may further include functional layers, such as an anti-fingerprint layer, a phase control layer, a hard coating, etc., disposed on an optically transparent substrate.

[0071] The border region BA of the window WM may be obtained by depositing, coating, or printing a material having a predetermined color on a transparent substrate. The border region BA of the window WM may prevent components of the display module DM that are disposed to overlap with the border region BA from being viewed from the outside. The border region BA may correspond to the non-display portion D-NDA of the display device DD (e.g., see Figure 1 ).

[0072] The display module DM may be disposed between the window WM and the housing HAU. The display module DM may display an image in response to an electrical signal. The display module DM may include a display area DA and a non-display area NDA defined adjacent to the display area DA.

[0073] The display area DA may be activated in response to an electrical signal and may display an image. The display area DA of the display module DM may overlap with the transmissive region TA of the window WM. In the present disclosure, the expression "a region / portion overlaps with another region / portion" should not be limited to meaning that "the region / portion has the same size as the other region / portion, and / or the region / portion has the same shape as the other region / portion". The image provided from the display area DA may be viewed from the outside through the transmissive region TA.

[0074] The non-display area NDA can be defined to be adjacent to the display area DA. As an example, the non-display area NDA can surround the display area DA; however, it should not be limited thereto or restricted thereby. According to an embodiment, the non-display area NDA can be defined in various shapes. A driving circuit or driving lines for driving elements disposed in the display area DA, various signal lines for supplying electrical signals to the elements, and pads can be disposed in the non-display area NDA. The non-display area NDA of the display module DM can overlap with the border area BA of the window WM, and the components of the display module DM disposed in the non-display area NDA can be prevented from being viewed from the outside through the border area BA.

[0075] The display panel DP according to an embodiment can be a light-emitting type display panel; however, it should not be particularly limited. For example, the display panel DP can be an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. The light-emitting layer of the organic light-emitting display panel can include an organic light-emitting material. The light-emitting layer of the inorganic light-emitting display panel can include an inorganic light-emitting material. The light-emitting layer of the quantum dot light-emitting display panel can include quantum dots and / or quantum rods. Hereinafter, an organic light-emitting display panel will be described as a representative example of the display panel DP.

[0076] The display panel DP can include a base substrate BS, a circuit layer DP-CL, a display element layer DP-OL, and a packaging layer TFE.

[0077] The base substrate BS can provide a base surface on which the circuit layer DP-CL is disposed. The base substrate BS can be a rigid substrate or a flexible substrate.

[0078] The circuit layer DP-CL can be disposed on the base substrate BS. The circuit layer DP-CL can include driving elements such as transistors, signal lines, and signal pads. The display element layer DP-OL can include light-emitting elements disposed to overlap with the display area DA. The light-emitting elements of the display element layer DP-OL can be electrically connected to the driving elements of the circuit layer DP-CL, and can emit light through the display area DA in response to signals from the driving elements.

[0079] The packaging layer TFE can be disposed on the display element layer DP-OL, and can package the light-emitting elements. The packaging layer TFE can include a plurality of thin layers. The thin layers of the packaging layer TFE can improve the light efficiency of the light-emitting elements, or can protect the light-emitting elements.

[0080] The sensor layer ISU can be disposed on the display panel DP. The sensor layer ISU can sense an external input applied thereto from the outside. The external input can be a user input. The external input can include various inputs provided by a part of the user's body, light, heat, a pen, pressure, etc.

[0081] The sensor layer ISU can be formed on the display panel DP through a continuous process. In this case, the sensor layer ISU can be directly disposed on the display panel DP. In the following description, the expression "the sensor layer ISU is directly disposed on the display panel DP" means that no intervening element exists between the sensor layer ISU and the display panel DP. That is to say, a separate bonding member may not be provided between the sensor layer ISU and the display panel DP.

[0082] According to an embodiment, the sensor layer ISU can be coupled to the display panel DP through a bonding member. The bonding member can include a conventional adhesive.

[0083] The housing HAU can be disposed under the display module DM and can accommodate the display module DM. The housing HAU can absorb the impact applied to the display module DM from the outside and can prevent foreign substances and moisture from entering the display module DM. Therefore, the display module DM can be protected by the housing HAU. According to an embodiment, the housing HAU can be provided in a form obtained by coupling a plurality of accommodating members.

[0084] Figure 3 is a plan view of the display panel DP according to an embodiment of the present disclosure.

[0085] Reference Figure 3 , the display panel DP can include pixels PX11 to PXnm disposed in the display area DA and signal lines electrically connected to the pixels PX11 to PXnm. The display panel DP can include a driving circuit GDC and pads PD disposed in the non-display area NDA.

[0086] Each of the pixels PX11 to PXnm can include a pixel driving circuit configured to include a light-emitting element, a plurality of transistors (e.g., a switching transistor, a driving transistor, etc.) connected to the light-emitting element, and a capacitor. Each of the pixels PX11 to PXnm can emit light in response to an electrical signal applied thereto. Figure 3 Pixels PX11 to PXnm arranged in a matrix form are shown as a representative example. However, the arrangement of the pixels PX11 to PXnm should not be limited to this or restricted thereby.

[0087] The signal lines can include scan lines SL1 to SLn and data lines DL1 to DLm. Each of the pixels PX11 to PXnm can be connected to a corresponding scan line among the scan lines SL1 to SLn and a corresponding data line among the data lines DL1 to DLm. At the same time, according to the configuration of the pixel driving circuits of the pixels PX11 to PXnm, more types of signal lines can be provided in the display panel DP.

[0088] The driving circuit GDC may include a gate driving circuit. The gate driving circuit may generate a gate signal and may sequentially output the gate signal to scan lines SL1 to SLn. The gate driving circuit may also output another control signal to the pixel driving circuits of pixels PX11 to PXnm.

[0089] The driving circuit GDC and pixels PX11 to PXnm may include a plurality of transistors formed by a process such as a low-temperature polysilicon (LTPS) process, a low-temperature polycrystalline oxide (LTPO) process, or an oxide semiconductor process.

[0090] The pads PD may be arranged in a non-display area NDA along one direction. The pads PD may be connected to a circuit board. Each of the pads PD may be connected to a corresponding signal line among the signal lines and may be connected to a corresponding pixel among pixels PX11 to PXnm via the signal line. The pads PD may be provided integrally with the signal lines; however, they are not limited thereto or thereby. According to an embodiment, the pads PD may be provided on a layer different from the signal lines and may be connected to the signal lines via contact holes.

[0091] Figure 4 is a cross-sectional view taken along line I-I' Figure 3 of.

[0092] Referring Figure 4 , the display panel DP may include a base substrate BS, a circuit layer DP-CL, a display element layer DP-OL, and a packaging layer TFE.

[0093] The circuit layer DP-CL may include a first conductive pattern CPT1 and a second conductive pattern CPT2 provided on the base substrate BS, a transistor TR, connection electrodes CNE1 and CNE2, a buffer layer BFL, a gate insulating pattern GI, and insulating layers INS1 and INS2.

[0094] The first conductive pattern CPT1 and the second conductive pattern CPT2 may be provided between the base substrate BS and the transistor TR and may be spaced apart from each other when viewed in a plane. The first conductive pattern CPT1 may be electrically connected to a drain region D-A via a first connection electrode CNE1. The second conductive pattern CPT2 may be electrically connected to a source region S-A via a second connection electrode CNE2.

[0095] Each of the first conductive pattern CPT1 and the second conductive pattern CPT2 may have a multi-layer structure. The first conductive pattern CPT1 and the second conductive pattern CPT2 may be formed of the same material and may have the same stacking structure. As an example, each of the first conductive pattern CPT1 and the second conductive pattern CPT2 may include a first pattern layer PT1 and a second pattern layer PT2 stacked on a base substrate BS along a thickness direction (i.e., in a third direction DR3), however, the present disclosure should not be limited to this or be restricted thereby. According to an embodiment, each of the first conductive pattern CPT1 and the second conductive pattern CPT2 may have a single-layer structure, or may have a multi-layer structure in which three or more pattern layers are stacked.

[0096] The first pattern layer PT1 and the second pattern layer PT2 may have different thicknesses from each other. As an example, the thickness of the first pattern layer PT1 may be less than the thickness of the second pattern layer PT2, however, the present disclosure should not be limited to this or be restricted thereby.

[0097] Each of the first pattern layer PT1 and the second pattern layer PT2 may include one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof. As an example, the first pattern layer PT1 may include titanium (Ti), and the second pattern layer PT2 may include copper (Cu), however, the present disclosure should not be limited to this or be restricted thereby.

[0098] A buffer layer BFL may be provided on the base substrate BS to cover the first conductive pattern CPT1 and the second conductive pattern CPT2. The buffer layer BFL may include at least one inorganic layer.

[0099] The transistor TR may include a semiconductor pattern SP and a gate electrode GE. The semiconductor pattern SP may be provided on the buffer layer BFL. The adhesion between the semiconductor pattern SP and the base substrate BS may be improved by the buffer layer BFL. The semiconductor pattern SP may include a semiconductor material such as polysilicon, crystalline silicon, or metal oxide.

[0100] The source region S-A, the active region A-A, and the drain region D-A of the transistor TR may be formed of the semiconductor pattern SP. The semiconductor pattern SP may have different electrical properties depending on whether it is doped or whether the metal oxide is reduced. The source region S-A and the drain region D-A of the semiconductor pattern SP having a relatively high conductivity may be used as electrodes or signal lines. The undoped portion, the portion doped with a low doping concentration, or the unreduced portion of the semiconductor pattern SP may correspond to the active region A-A having a relatively low conductivity. When viewed in a plane, the active region A-A may be provided between the source region S-A and the drain region D-A.

[0101] The drain region D-A may include a first drain region (or first portion) D-A1 and a second drain region (or second portion) D-A2. The first drain region D-A1 may have a conductivity higher than that of the second drain region D-A2. The first drain region D-A1 may have a first conductivity. The second drain region D-A2 may have a second conductivity lower than the first conductivity. The first drain region D-A1 may be doped at a higher concentration compared to the second drain region D-A2. Thus, when current flows in from the active region A-A, the current may mainly flow in through the first drain region D-A1.

[0102] The source region S-A may include a first source region (or first portion) S-A1 and a second source region (or second portion) S-A2. The first source region S-A1 may have a conductivity higher than that of the second source region S-A2. The first source region S-A1 may have a third conductivity. The second source region S-A2 may have a fourth conductivity lower than the third conductivity. The first source region S-A1 may be doped at a higher concentration compared to the second source region S-A2. Thus, when current flows in from the active region A-A, the current may mainly flow in through the first source region S-A1.

[0103] At least one hole HO may be defined through the semiconductor pattern SP in the source region S-A or the drain region D-A. The hole HO may be formed during an etching process for forming the connection electrodes CNE1 and CNE2 and the gate electrode GE. Figure 4 A structure in which the holes HO penetrate through the semiconductor pattern SP and are spaced apart from each other is shown as a representative example. Among the holes HO, when viewed in a plane, one hole HO may be surrounded by the source region S-A, and the other hole HO may be surrounded by the drain region D-A. However, the present disclosure should not be limited to this or restricted thereby. According to an embodiment, depending on the process for forming the circuit layer DP-CL, the hole HO may not penetrate through the semiconductor pattern SP.

[0104] The gate insulating pattern GI may be disposed on the buffer layer BFL. The gate insulating pattern GI may include at least one inorganic layer. The gate insulating pattern GI may include a first gate insulating pattern GI1, a second gate insulating pattern GI2, and a third gate insulating pattern GI3 that are spaced apart from each other. The first gate insulating pattern GI1 may cover the second drain region D-A2 of the drain region D-A and may be disposed above the first conductive pattern CPT1. The second gate insulating pattern GI2 may be disposed on the active region A-A. The second gate insulating pattern GI2 may correspond to the active region A-A. The third gate insulating pattern GI3 may cover the second source region S-A2 of the source region S-A.

[0105] The connection electrodes CNE1 and CNE2 may include a first connection electrode CNE1 and a second connection electrode CNE2. The first connection electrode CNE1 may be disposed on the first gate insulating pattern GI1. The first connection electrode CNE1 may be connected to the first conductive pattern CPT1 via a first contact hole CH1 defined through the buffer layer BFL and the first gate insulating pattern GI1. The first connection electrode CNE1 may be in contact with a first drain region D-A1 of the drain region D-A and may be electrically connected to the drain region D-A. The first drain region D-A1 and the first conductive pattern CPT1 may be electrically connected to each other through the first connection electrode CNE1. Since the first conductive pattern CPT1 is electrically connected to the drain region D-A through the first drain region D-A1 having a high conductivity, current transmission characteristics may be improved.

[0106] The second connection electrode CNE2 may be disposed on the third gate insulating pattern GI3. The second connection electrode CNE2 may be connected to the second conductive pattern CPT2 via a second contact hole CH2 defined through the buffer layer BFL and the third gate insulating pattern GI3. The second connection electrode CNE2 may be in contact with a first source region S-A1 of the source region S-A and may be electrically connected to the source region S-A. The source region S-A and the second conductive pattern CPT2 may be electrically connected to each other through the second connection electrode CNE2. The second connection electrode CNE2 may be connected to a power line that supplies power to the light-emitting element OL, and thus, a first voltage may be provided to the transistor TR.

[0107] The gate electrode GE may be disposed on the second gate insulating pattern GI2. When viewed in a plane, the gate electrode GE may overlap with the active region A-A, and the gate electrode GE may be spaced apart from the semiconductor pattern SP in a thickness direction, and the second gate insulating pattern GI2 may be interposed between the gate electrode GE and the semiconductor pattern SP.

[0108] When viewed in a plane, the connection electrodes CNE1 and CNE2 may be spaced apart from the gate electrode GE. The connection electrodes CNE1 and CNE2 and the gate electrode GE may have a multilayer structure in which conductive layers ML1, ML2, and ML3 including materials different from each other are stacked. The conductive layers ML1, ML2, and ML3 may include a first conductive layer ML1, a second conductive layer ML2, and a third conductive layer ML3. The first conductive layer ML1, the second conductive layer ML2, and the third conductive layer ML3 may be stacked by a sputtering process. However, the present disclosure should not be limited to this or restricted thereby.

[0109] Each of the first conductive layer ML1, the second conductive layer ML2, and the third conductive layer ML3 may include a metallic material. As an example, each of the first conductive layer ML1, the second conductive layer ML2, and the third conductive layer ML3 may include one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and indium tin oxide (ITO), or an alloy thereof. The first conductive layer ML1, the second conductive layer ML2, and the third conductive layer ML3 may include different metallic materials from each other. The second conductive layer ML2 may include a metallic material having a high conductivity, and the first conductive layer ML1 and the third conductive layer ML3 disposed under and on the second conductive layer ML2, respectively, may include metallic materials having corrosion resistance. As an example, the first conductive layer ML1 may include titanium (Ti), the second conductive layer ML2 may include copper (Cu), and the third conductive layer ML3 may include indium tin oxide (ITO). However, the present disclosure should not be limited to this or be restricted thereby.

[0110] The first conductive layer ML1, the second conductive layer ML2, and the third conductive layer ML3 may have different thicknesses from each other. As an example, among the first conductive layer ML1, the second conductive layer ML2, and the third conductive layer ML3, the second conductive layer ML2 including a metallic material having a high conductivity may have the maximum thickness. Accordingly, the connection electrodes CNE1 and CNE2 and the gate electrode GE formed of the first conductive layer ML1, the second conductive layer ML2, and the third conductive layer ML3 may have low resistance and high conductivity.

[0111] Figure 4 A structure in which the connection electrodes CNE1 and CNE2 and the gate electrode GE have a multilayer structure (e.g., a three-layer structure) is shown as a representative example. However, the present disclosure should not be limited to this or be restricted thereby. According to an embodiment, the connection electrodes CNE1 and CNE2 and the gate electrode GE may have a multilayer structure having a number of layers less than or more than three, or may have a single-layer structure.

[0112] The connection electrodes CNE1 and CNE2 and the gate electrode GE may be formed substantially simultaneously through the same process. The connection electrodes CNE1 and CNE2 and the gate electrode GE may have the same stacking structure as each other. As an example, the connection electrodes CNE1 and CNE2 and the gate electrode GE may have a three-layer structure of Ti / Cu / ITO. Since the connection electrodes CNE1 and CNE2 and the gate electrode GE are formed substantially simultaneously through the same process, the manufacturing process of the display panel DP may be simplified.

[0113] The first insulating layer INS1 can be configured to cover the connection electrodes CNE1 and CNE2 and the gate electrode GE on the gate insulating pattern GI. The second insulating layer INS2 (or insulating layer) can be disposed on the first insulating layer INS1. Each of the first insulating layer INS1 and the second insulating layer INS2 can include at least one inorganic layer or organic layer. The inorganic layer can include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. However, the present disclosure should not be limited thereto or thereby. The organic layer can include a phenol-based polymer, an acrylic-based polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a parylene-based polymer, a vinyl alcohol-based polymer, or a mixture thereof. However, the material of the organic layer should not be limited thereto or thereby.

[0114] The display element layer DP-OL can be disposed on the circuit layer DP-CL. The display element layer DP-OL can include a pixel defining layer PDL and a light emitting element OL. As an example, the light emitting element OL can include an organic light emitting element, an inorganic light emitting element, a quantum dot light emitting element, a micro LED, or a nano LED. However, the present disclosure should not be limited thereto or thereby. As long as light is generated or the amount of light is controlled according to an electrical signal, the light emitting element OL can include various embodiments.

[0115] The pixel defining layer PDL can be disposed on the second insulating layer INS2 of the circuit layer DP-CL. The pixel defining layer PDL can include a polymer resin. As an example, the pixel defining layer PDL can include a polyacrylate-based resin or a polyimide-based resin. In addition to the polymer resin, the pixel defining layer PDL can also include an inorganic material. According to an embodiment, the pixel defining layer PDL can be formed of an inorganic material. As an example, the pixel defining layer PDL can include silicon nitride (SiN x ), silicon oxide (SiO x ), or silicon oxynitride (SiO x N y ).

[0116] The pixel defining layer PDL can include a light absorbing material. The pixel defining layer PDL can include a black colorant. The black colorant can include a black pigment or a black dye. The black colorant can include carbon black, a metal material such as chromium, or an oxide thereof. However, the pixel defining layer PDL should not be limited thereto or thereby.

[0117] The light emitting element OL can include a first electrode AE, a hole transport region HCL, a light emitting layer EML, an electron transport region ECL, and a second electrode CE stacked in sequence.

[0118] The first electrode AE may be disposed on the second insulating layer INS2 of the circuit layer DP-CL. The first electrode AE may be connected to the first connection electrode CNE1 via a contact hole CHa defined through the first insulating layer INS1 and the second insulating layer INS2. Since the first electrode AE is connected to the first connection electrode CNE1, the drain region D-A may be connected to the light-emitting element OL through the first connection electrode CNE1.

[0119] The pixel defining layer PDL may be provided with a light-emitting opening PX-OP that is defined through the pixel defining layer PDL to extend to at least a part of the first electrode AE and expose the at least a part. The part of the first electrode AE exposed through the light-emitting opening PX-OP may correspond to the light-emitting region PXA. The region where the pixel defining layer PDL is provided may correspond to the non-light-emitting region NPXA. The non-light-emitting region NPXA may surround the light-emitting region PXA.

[0120] The hole transport region HCL may be disposed on the first electrode AE. The hole transport region HCL may include at least one of a hole injection layer, a hole transport layer, and an electron blocking layer. In addition, the hole transport region HCL may include a plurality of hole transport layers.

[0121] The light-emitting layer EML may be disposed on the hole transport region HCL. The light-emitting layer EML may have a single-layer structure of a single material, a single-layer structure of different materials, or a multi-layer structure including layers of different materials. According to an embodiment, the light-emitting layer EML may generate blue light as the source light. However, the present disclosure should not be limited to this or be restricted thereby. The display element layer DP-OL may include a light-emitting element OL that includes a light-emitting layer EML that emits light having wavelengths different from each other.

[0122] The light-emitting layer EML may be disposed in a pattern in a region corresponding to the light-emitting opening PX-OP. However, the present disclosure should not be limited to this or be restricted thereby. According to an embodiment, the light-emitting layer EML may be provided as a common layer overlapping the light-emitting region PXA and the non-light-emitting region NPXA.

[0123] The electron transport region ECL may be disposed on the light-emitting layer EML. The electron transport region ECL may include at least one of a hole blocking layer, an electron transport layer, and an electron injection layer. However, the present disclosure should not be limited to this or be restricted thereby.

[0124] The hole transport region HCL, the light-emitting layer EML, and the electron transport region ECL may be formed by various methods such as a vacuum deposition method, a spin coating method, a casting method, an LB (Langmuir-Blodgett) method, an inkjet printing method, a laser printing method, a LITI (laser-induced thermal imaging) method, etc.

[0125] The second electrode CE may be disposed on the electron transport region ECL. The second electrode CE may be a common electrode. That is, the second electrode CE may be provided as a common layer to overlap the entire regions of the light-emitting region PXA and the non-light-emitting region NPXA.

[0126] The encapsulation layer TFE may cover the light-emitting element OL. The encapsulation layer TFE may encapsulate the display element layer DP-OL. The encapsulation layer TFE may include at least one insulating layer. According to an embodiment, the encapsulation layer TFE may include at least one inorganic layer (hereinafter referred to as an encapsulation inorganic layer). According to an embodiment, the encapsulation layer TFE may include an encapsulation inorganic layer and at least one organic layer (hereinafter referred to as an encapsulation organic layer) disposed between the encapsulation inorganic layers.

[0127] The encapsulation inorganic layer may protect the display element layer DP-OL from moisture and oxygen, and the encapsulation organic layer may protect the display element layer DP-OL from foreign substances such as dust particles. The encapsulation inorganic layer may include silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, or aluminum oxide, however, it should not be limited thereto or thereby restricted. The encapsulation organic layer may include an acrylate-based compound, an epoxy-based compound, or the like. The encapsulation organic layer may also include a photo-polymerizable organic material, and it should not be particularly limited.

[0128] Figure 5 is a plan view corresponding to Figure 4 the circuit layer DP-CL. Specifically, Figure 5 is a plan view showing the first conductive pattern CPT1, the second conductive pattern CPT2, the semiconductor pattern SP, the gate electrode GE, the first connection electrode CNE1, and the second connection electrode CNE2.

[0129] Referring to Figure 5 , when viewed in a plane, the first conductive pattern CPT1 and the second conductive pattern CPT2 may be spaced apart from each other. The first conductive pattern CPT1 and the second conductive pattern CPT2 may be disposed on the base substrate BS (refer to Figure 4 ). When viewed in a plane, the first connection electrode CNE1 and the second connection electrode CNE2 may be spaced apart from each other. The first connection electrode CNE1 and the second connection electrode CNE2 may be disposed on the gate insulating pattern GI (refer to Figure 4 ). The first connection electrode CNE1 may be electrically connected to the first conductive pattern CPT1 via the first contact hole CH1. The second connection electrode CNE2 may be electrically connected to the second conductive pattern CPT2 via the second contact hole CH2.

[0130] The semiconductor pattern SP may overlap with the first connection electrode CNE1, the second connection electrode CNE2, and the gate electrode GE. The semiconductor pattern SP may overlap with the first conductive pattern CPT1 and the second conductive pattern CPT2. However, it should not be limited to this or restricted thereby, and the semiconductor pattern SP may have various shapes. As an example, the semiconductor pattern SP may not overlap with the second conductive pattern CPT2.

[0131] The semiconductor pattern SP may include a semiconductor material such as polysilicon, crystalline silicon, or metal oxide. The semiconductor pattern SP may include an active region A-A, a source region S-A, and a drain region D-A. The semiconductor pattern SP may have different electrical properties depending on whether it is doped or the metal oxide is reduced. The source region S-A and the drain region D-A of the semiconductor pattern SP having a relatively high conductivity may be used as electrodes or signal lines. The undoped portion, the portion doped with a low doping concentration, or the unreduced portion of the semiconductor pattern SP may correspond to the active region A-A having a relatively low conductivity. The active region A-A of the semiconductor pattern SP may overlap with the gate electrode GE of the semiconductor pattern SP. The active region A-A may have a relatively lower conductivity than the source region S-A and the drain region D-A.

[0132] At least one hole HO may be defined through the semiconductor pattern SP of the transistor TR (refer to Figure 4 ). The hole HO may be disposed adjacent to one of the source region S-A and the drain region D-A. The hole HO may be formed during an etching process for forming the connection electrodes CNE1 and CNE2 and the gate electrode GE. The hole HO may be defined as a plurality of holes. Figure 5 A structure in which the holes HO are spaced apart from each other is shown. Among the holes HO, at least one hole may be surrounded by the source region S-A, and the other holes may be surrounded by the drain region D-A. When observed in a plane, the first hole HO-1 may be respectively defined above the first protruding pattern CRP1 and the second protruding pattern CRP2 described later. When observed in a plane, the second hole HO-2 may be respectively defined below the first protruding pattern CRP1 and the second protruding pattern CRP2 described later.

[0133] The protruding patterns CRP1 and CRP2 may protrude (extend) from the connection electrodes CNE1 and CNE2 toward the active region A-A, respectively. The protruding patterns CRP1 and CRP2 may electrically connect the active region A-A to the connection electrodes CNE1 and CNE2. Since the protruding patterns CRP1 and CRP2 electrically connect the active region A-A to the connection electrodes CNE1 and CNE2, when current flows from the active region A-A to the source region S-A and the drain region D-A, the resistance may be reduced and the current may flow smoothly. This will be described in detail later.

[0134] The first connection electrode CNE1 may include a first protruding pattern CRP1 that protrudes in a first direction DR1. The first protruding pattern CRP1 may protrude from the first drain region D-A1 toward the active region A-A (i.e., toward the active region A-A) to be adjacent to the active region A-A but not overlap with the active region A-A. The first protruding pattern CRP1 may include the same material as the first connection electrode CNE1 having a high conductivity. The first protruding pattern CRP1 may overlap with the drain region D-A and may not overlap with the active region A-A.

[0135] The first protruding pattern CRP1 may be disposed between the first hole HO-1 and the second hole HO-2. When viewed in a plane, the first hole HO-1 may be defined above the first protruding pattern CRP1, and when viewed in a plane, the second hole HO-2 may be defined below the first protruding pattern CRP1. The first protruding pattern CRP1 may not overlap with the first hole HO-1 and the second hole HO-2. However, the shapes and positions of the first protruding pattern CRP1, the first hole HO-1, and the second hole HO-2 should not be limited to this or restricted thereby, and may be changed as needed. As an example, one hole may be formed to surround the first protruding pattern CRP1.

[0136] The second connection electrode CNE2 may include a second protruding pattern CRP2 that protrudes in a direction opposite to the first direction DR1. The second protruding pattern CRP2 may protrude from the first source region S-A1 toward the active region A-A (i.e., toward the active region A-A) to be adjacent to the active region A-A but not overlap with the active region A-A. The second protruding pattern CRP2 may include the same material as the second connection electrode CNE2 having a high conductivity. The second protruding pattern CRP2 may overlap with the source region S-A and may not overlap with the active region A-A.

[0137] The second protruding pattern CRP2 may be disposed between the first hole HO-1 and the second hole HO-2. The second protruding pattern CRP2 may not overlap with the first hole HO-1 and the second hole HO-2. When viewed in a plane, the first hole HO-1 may be defined above the second protruding pattern CRP2, and when viewed in a plane, the second hole HO-2 may be defined below the second protruding pattern CRP2. However, the shapes and positions of the second protruding pattern CRP2, the first hole HO-1, and the second hole HO-2 should not be limited to this or restricted thereby, and may be changed as needed.

[0138] Figure 6 is Figure 5 an enlarged plan view of the region AA'. Hereinafter, in Figure 6 the same reference numerals denote Figures 1 to 5the same components as those in, and thus, a detailed description of the same components will be omitted. In addition, the description of the first protruding pattern CRP1 can be applied to the second protruding pattern CRP2.

[0139] Reference Figure 6 , the first protruding pattern CRP1 can protrude from the first drain region D-A1 toward the active region A-A along the first direction DR1. In the absence of the first protruding pattern CRP1, the path of the current flowing from the active region A-A to the first drain region D-A1 can be restricted to the surrounding current path SCP. Since the surrounding current path SCP needs to avoid the hole HO and needs to enter the first drain region D-A1, the current path may become narrow, and thus the resistance may increase. In the present embodiment, the description is made on the premise that the surrounding current path SCP flows in the direction from the active region A-A to the drain region D-A. However, the surrounding current path SCP can flow in the direction opposite to the above-mentioned direction. The surrounding current path SCP described below can flow in the two directions as described above.

[0140] When the first protruding pattern CRP1 is disposed between the first hole HO-1 and the second hole HO-2, an additional current path CSP can be added to the path of the current flowing from the active region A-A to the first drain region D-A1 via the first protruding pattern CRP1. In the present embodiment, the description is made on the premise that the additional current path CSP flows in the direction from the active region A-A to the drain region D-A. However, the additional current path CSP can flow in the direction opposite to the above-mentioned direction. The additional current path CSP described below can flow in the two directions as described above. Since the first protruding pattern CRP1 includes the same material as the first connection electrode CNE1, the first protruding pattern CRP1 has a high conductivity, and the current can flow from the active region A-A to the first drain region D-A1 via the first protruding pattern CRP1. Therefore, compared with the case where the first protruding pattern CRP1 is not provided, the current path can be widened, and thus, the resistance can be reduced.

[0141] Figure 7A is a cross-sectional view taken along Figure 6 the line II-II'. In Figure 7A , the same reference numerals denote Figures 1 to 6 the same components as those in, and thus, a detailed description of the same components will be omitted.

[0142] Reference Figure 7A, the first gate insulating pattern GI1 may cover the second drain region D - A2. The first drain region D - A1 may be in direct contact with and electrically connected to the first protrusion pattern CRP1. The first protrusion pattern CRP1 may include a first conductive layer ML1, a second conductive layer ML2, and a third conductive layer ML3 containing the same material as the first connection electrode CNE1. The first protrusion pattern CRP1 may include the same material as the gate electrode GE. The first protrusion pattern CRP1, the first connection electrode CNE1, and the gate electrode GE may be formed by the same process.

[0143] The active region A - A may be electrically connected to the first drain region D - A1 and the first protrusion pattern CRP1. Thus, an additional current path CSP can be formed from the active region A - A through the first drain region D - A1 and the first protrusion pattern CRP1 to the first connection electrode CNE1. The additional current path CSP may have a wider current path than the surrounding current path SCP described later with reference to Figure 7B and thus the overall resistance can be reduced.

[0144] Figure 7B is a cross-sectional view taken along the line III - III' of Figure 6 . In Figure 7B , the same reference numerals denote the same elements in Figures 1 to 6 and Figure 7A , and thus, detailed descriptions of the same elements will be omitted.

[0145] Referring to Figure 6 and Figure 7B , the current path may be narrowed due to the hole HO overlapping with the first drain region D - A1. That is, the current flowing from the active region A - A may avoid the hole HO and may flow into the first drain region D - A1. Since the current path avoids the hole HO, the current path may be narrowed, and when the current flows through the surrounding current path SCP, the resistance may increase. In the process of forming the circuit layer DP - CL, the resistance of the surrounding current path SCP may increase as the size of the hole HO increases. In this case, the resistance can be reduced by the additional current path CSP (refer to Figure 7A ).

[0146] Figure 8 is a plan view corresponding to the circuit layer DP - CL of Figure 4 according to an embodiment of the present disclosure. Specifically, Figure 8 is a plan view showing the first conductive pattern CPT1, the second conductive pattern CPT2, the semiconductor pattern SP, the gate electrode GE, the first connection electrode CNE1, and the second connection electrode CNE2.

[0147] Figure 8The circuit layer DP-CL, except for the first protruding pattern CRP1, the second protruding pattern CRP2, and the hole HO, has substantially the same configuration as Figure 5 the circuit layer DP-CL.

[0148] The first protruding pattern CRP1 may include a portion protruding in the first direction DR1 and a portion extending in a direction parallel to the second direction DR2 from the portion protruding in the first direction DR1. Similarly, the second protruding pattern CRP2 may include a portion protruding in a direction opposite to the first direction DR1 and a portion extending in a direction parallel to the second direction DR2 from the portion protruding in a direction opposite to the first direction DR1. The hole HO may be defined adjacent to the first protruding pattern CRP1 and the second protruding pattern CRP2. As Figure 8 shown, three holes HO may be defined around the first protruding pattern CRP1. Three holes HO may be defined around the second protruding pattern CRP2. The shapes of the first protruding pattern CRP1 and the second protruding pattern CRP2 should not be limited to this or restricted thereby, and may be changed as needed.

[0149] Figure 9 is Figure 8 an enlarged plan view of the region BB' of Figure 9 . Hereinafter, in

[0150] reference Figure 9 , the first protruding pattern CRP1 may protrude from the first drain region D-A1 toward the active region A-A along the first direction DR1. The first protruding pattern CRP1 may include a first-first protruding pattern CRP1-1 extending in the first direction DR1, a first-second protruding pattern CRP1-2 extending in a direction opposite to the second direction DR2, and a first-third protruding pattern CRP1-3 extending in the second direction DR2. When viewed in a plane, the second hole HO-2 may be defined above the first-first protruding pattern CRP1-1, and when viewed in a plane, the third hole HO-3 may be defined below the first-first protruding pattern CRP1-1. The first hole HO-1 may be defined on the right side of the first-second protruding pattern CRP1-2 and the first-third protruding pattern CRP1-3 and may extend in the second direction DR2.

[0151] Since the first protruding pattern CRP1 includes various protruding portions, various current paths may be formed when current flows from the active region A-A to the first drain region D-A1.

[0152] The current flowing through the surrounding current path SCP can flow from the active region A-A to the first drain region D-A1 while avoiding the hole HO. The current flowing through the additional current path CSP can include a first additional current path CSP-1 and a second additional current path CSP-2. The current flowing through the additional current path CSP can pass through the first protruding pattern CRP1 and can flow into the first drain region D-A1.

[0153] The current starting to flow from the active region A-A can flow into the upper end of the first-third protruding pattern CRP1-3 through the first additional current path CSP-1. The current flowing through the first additional current path CSP-1 to the upper end of the first-third protruding pattern CRP1-3 can travel via the first-third protruding pattern CRP1-3 in a direction opposite to the second direction DR2, and then can travel via the first-first protruding pattern CRP1-1 in a direction opposite to the first direction DR1. As described above, the current flowing through the first additional current path CSP-1 can flow into the first drain region D-A1 via the first-third protruding pattern CRP1-3 and the first-first protruding pattern CRP1-1.

[0154] The current starting to flow from the active region A-A can flow into the lower end of the first-second protruding pattern CRP1-2 through the second additional current path CSP-2. The current flowing through the second additional current path CSP-2 to the lower end of the first-second protruding pattern CRP1-2 can travel through the first-second protruding pattern CRP1-2 in the second direction DR2, and then can travel through the first-first protruding pattern CRP1-1 in a direction opposite to the first direction DR1. As described above, the current flowing through the second additional current path CSP-2 can flow into the first drain region D-A1 through the first-second protruding pattern CRP1-2 and the first-first protruding pattern CRP1-1. As described above, since the first protruding pattern CRP1 includes the first-first protruding pattern CRP1-1, the first-second protruding pattern CRP1-2, and the first-third protruding pattern CRP1-3, the widths of the additional current paths CSP-1 and CSP-2 can be increased and the resistance can be reduced.

[0155] Figure 10 is a plan view corresponding to the circuit layer DP-CL of an embodiment according to the present disclosure. Specifically, Figure 4 The Figure 10 is a plan view showing the first conductive pattern CPT1, the second conductive pattern CPT2, the semiconductor pattern SP, the gate electrode GE, the first connection electrode CNE1, and the second connection electrode CNE2.

[0156] Figure 10The circuit layer DP-CL, except for the first protruding pattern CRP1, the second protruding pattern CRP2, and the holes HO, has substantially the same configuration as Figure 5 the circuit layer DP-CL.

[0157] The first protruding pattern CRP1 may include a portion protruding in the first direction DR1 and a portion extending in a direction parallel to the second direction DR2 from the portion protruding in the first direction DR1. Similarly, the second protruding pattern CRP2 may include a portion protruding in a direction opposite to the first direction DR1 and a portion extending in a direction parallel to the second direction DR2 from the portion protruding in a direction opposite to the first direction DR1. The holes HO may be disposed adjacent to the first protruding pattern CRP1 and the second protruding pattern CRP2. As Figure 10 shown, four holes HO may be disposed around the first protruding pattern CRP1, and four holes HO may be disposed around the second protruding pattern CRP2. The shapes of the first protruding pattern CRP1 and the second protruding pattern CRP2 should not be limited to this or restricted thereby, and may be changed as needed.

[0158] Figure 11 is Figure 10 an enlarged plan view of the region CC'. Hereinafter, in Figure 11 the same reference numerals denote Figure 10 the same elements in

[0159] Reference Figure 11, the first protruding pattern CRP1 can protrude from the first drain region D-A1 towards the active region A-A along the first direction DR1. The first protruding pattern CRP1 can include a first-first protruding pattern CRP1-1 extending in the first direction DR1, a first-second protruding pattern CRP1-2 extending in a direction opposite to the second direction DR2, a first-third protruding pattern CRP1-3 extending in the first direction DR1, and a first-fourth protruding pattern CRP1-4 extending in the second direction DR2. When observed in a plane, the second hole HO-2 can be defined above the first-first protruding pattern CRP1-1, and when observed in a plane, the third hole HO-3 can be defined below the first-first protruding pattern CRP1-1. When observed in a plane, the first hole HO-1 can be defined above the first-third protruding pattern CRP1-3, and when observed in a plane, the fourth hole HO-4 can be defined below the first-third protruding pattern CRP1-3. Each of the first-first protruding pattern CRP1-1, the first-second protruding pattern CRP1-2, the first-third protruding pattern CRP1-3, and the first-fourth protruding pattern CRP1-4 can be disposed between two of the first hole HO-1, the second hole HO-2, the third hole HO-3, and the fourth hole HO-4.

[0160] Since the first protruding pattern CRP1 includes various protruding portions, various current paths can be formed when current flows from the active region A-A to the first drain region D-A1.

[0161] The current flowing through the surrounding current path SCP can flow from the active region A-A into the first drain region D-A1 while avoiding the hole HO. The current flowing through the additional current path CSP can include a first additional current path CSP1, a second additional current path CSP2, and a third additional current path CSP3. The current flowing through the additional current path CSP can pass through the first protruding pattern CRP1 and can flow into the first drain region D-A1.

[0162] The current flowing from the active region A-A can travel to the first drain region D-A1 in a direction opposite to the first direction DR1 through the first additional current path CSP1 via the first to third protruding patterns CRP1-3 and the first to first protruding patterns CRP1-1. The second additional current path CSP2 can flow into the upper end of the first to fourth protruding pattern CRP1-4, travel in a direction opposite to the second direction DR2 through the first to fourth protruding pattern CRP1-4, and then travel in a direction opposite to the first direction DR1 through the first to first protruding pattern CRP1-1. The third additional current path CSP3 can flow into the lower end of the first to second protruding pattern CRP1-2, travel in the second direction DR2 through the first to second protruding pattern CRP1-2, and travel in a direction opposite to the first direction DR1 through the first to first protruding pattern CRP1-1.

[0163] As described above, the first additional current path CSP1 can flow into the first drain region D-A1 through the first to third protruding pattern CRP1-3 and the first to first protruding pattern CRP1-1. The second additional current path CSP2 can flow into the first drain region D-A1 through the first to fourth protruding pattern CRP1-4 and the first to first protruding pattern CRP1-1. The third additional current path CSP3 can flow into the first drain region D-A1 through the first to second protruding pattern CRP1-2 and the first to first protruding pattern CRP1-1. As described above, since the first protruding pattern CRP1 includes the first to first protruding pattern CRP1-1, the first to second protruding pattern CRP1-2, the first to third protruding pattern CRP1-3, and the first to fourth protruding pattern CRP1-4, the widths of the additional current paths CSP1, CSP2, and CSP3 can be increased and the resistance can be reduced.

[0164] Figure 12 is a plan view corresponding to the circuit layer DP-CL of Figure 4 according to an embodiment of the present disclosure. Specifically, Figure 12 is a plan view showing the first conductive pattern CPT1, the second conductive pattern CPT2, the semiconductor pattern SP, the gate electrode GE, the first connection electrode CNE1, and the second connection electrode CNE2.

[0165] Figure 12 The circuit layer DP-CL of Figure 5 has substantially the same configuration as the circuit layer DP-CL of

[0166] The first protruding pattern CRP1 can be set to multiple and can protrude radially outward around the center point. Similarly, the second protruding pattern CRP2 can be set to multiple and can protrude radially outward around the center point. The hole HO can be arranged adjacent to the first protruding pattern CRP1 and the second protruding pattern CRP2. As Figure 12 shown, four holes HO can be arranged around the first protruding pattern CRP1, and four holes HO can be arranged around the second protruding pattern CRP2. The shapes of the first protruding pattern CRP1 and the second protruding pattern CRP2 should not be limited to or restricted by this, and can be changed as needed.

[0167] Figure 13 is Figure 12 an enlarged plan view of the region DD' of Figure 13 In the following, in Figure 12 the same reference numerals denote the same elements in

[0168] Reference Figure 13 , the first protruding pattern CRP1 can protrude from the first drain region D-A1 towards the active region A-A. The first protruding pattern CRP1 can include a first-first protruding pattern CRP1-1, a first-second protruding pattern CRP1-2, a first-third protruding pattern CRP1-3, a first-fourth protruding pattern CRP1-4, a first-fifth protruding pattern CRP1-5, and a first-sixth protruding pattern CRP1-6 that protrude radially around the center point. The first hole HO-1 can be arranged between the first-fifth protruding pattern CRP1-5 and the first-sixth protruding pattern CRP1-6. The second hole HO-2 can be arranged between the first-fourth protruding pattern CRP1-4 and the first-fifth protruding pattern CRP1-5. The third hole HO-3 can be arranged between the first-third protruding pattern CRP1-3 and the first-fourth protruding pattern CRP1-4. The fourth hole HO-4 can be arranged between the first-second protruding pattern CRP1-2 and the first-third protruding pattern CRP1-3.

[0169] Each of the first-first protruding pattern CRP1-1, the first-second protruding pattern CRP1-2, the first-third protruding pattern CRP1-3, the first-fourth protruding pattern CRP1-4, the first-fifth protruding pattern CRP1-5, and the first-sixth protruding pattern CRP1-6 can be arranged adjacent to at least one of the first hole HO-1, the second hole HO-2, the third hole HO-3, and the fourth hole HO-4.

[0170] Since the first protruding pattern CRP1 includes various protruding portions, various current paths can be formed when current flows from the active region A-A to the first drain region D-A1.

[0171] The current flowing through the surrounding current path SCP can flow from the active region A-A into the first drain region D-A1 while avoiding the hole HO. The current flowing through the additional current path CSP can include a first additional current path CSP1, a second additional current path CSP2, a third additional current path CSP3, a fourth additional current path CSP4, and a fifth additional current path CSP5. The current flowing through the additional current path CSP can pass through the first protruding pattern CRP1 and can flow into the first drain region D-A1.

[0172] The first additional current path CSP1 can travel toward the first drain region D-A1 in a direction opposite to the first direction DR1 along the first-first protruding pattern CRP1-1 after passing through the first-second protruding pattern CRP1-2. The second additional current path CSP2 can travel in a direction opposite to the first direction DR1 along the first-first protruding pattern CRP1-1 after passing through the first-third protruding pattern CRP1-3. The third additional current path CSP3 can travel in a direction opposite to the first direction DR1 along the first-fourth protruding pattern CRP1-4 and the first-first protruding pattern CRP1-1. The fourth additional current path CSP4 can travel in a direction opposite to the first direction DR1 along the first-first protruding pattern CRP1-1 after passing through the first-fifth protruding pattern CRP1-5. The fifth additional current path CSP5 can travel in a direction opposite to the first direction DR1 along the first-first protruding pattern CRP1-1 after passing through the first-sixth protruding pattern CRP1-6.

[0173] As described above, since the first protruding pattern CRP1 includes the first-first protruding pattern CRP1-1, the first-second protruding pattern CRP1-2, the first-third protruding pattern CRP1-3, the first-fourth protruding pattern CRP1-4, the first-fifth protruding pattern CRP1-5, and the first-sixth protruding pattern CRP1-6, the widths of the additional current paths CSP1, CSP2, CSP3, CSP4, and CSP5 can be increased, and the resistance can be reduced.

[0174] Figures 14 to 23 is a cross-sectional view showing a method of manufacturing a display device DD according to an embodiment of the present disclosure. In Figures 14 to 23 wherein, the same reference numerals denote Figures 1 to 13 the same elements in

[0175] Refer to Figure 14, a preliminary display device P-DD can be prepared. The preliminary display device P-DD includes a base substrate BS, a first conductive pattern CPT1 disposed on the base substrate BS, and a second conductive pattern CPT2 spaced apart from the first conductive pattern CPT1 when viewed in a plane. Each of the first conductive pattern CPT1 and the second conductive pattern CPT2 may include a first pattern layer PT1 and a second pattern layer PT2 stacked in a thickness direction.

[0176] Reference Figure 15 , a buffer layer BFL can be formed to cover the first conductive pattern CPT1 and the second conductive pattern CPT2. A preliminary semiconductor pattern P-SP including a source region S-A, an active region A-A, and a drain region D-A can be formed on the buffer layer BFL.

[0177] Reference Figure 16 , a gate insulating pattern GI can be formed on the preliminary semiconductor pattern P-SP. A first contact hole CH1 can be formed through the gate insulating pattern GI to expose the upper surface of the first conductive pattern CPT1. A second contact hole CH2 can be formed through the gate insulating pattern GI to expose the upper surface of the second conductive pattern CPT2. A first opening OP-TR can be formed through the gate insulating pattern GI to expose a first portion of the preliminary semiconductor pattern P-SP. The gate insulating pattern GI may include a first gate insulating pattern GI1, a second gate insulating pattern GI2, and a third gate insulating pattern GI3 spaced apart from each other. The first gate insulating pattern GI1 may cover the second drain region D-A2. The second gate insulating pattern GI2 may cover the first-second drain region D-A1-2, the active region A-A, and the first-second source region S-A1-2. The third gate insulating pattern GI3 may cover the second source region S-A2.

[0178] When the first opening OP-TR is formed, doping can be performed on the first portion of the preliminary semiconductor pattern P-SP exposed through the first opening OP-TR. In this case, doping can be performed on the exposed first-first drain region D-A1-1 and the first-first source region S-A1-1.

[0179] Reference Figure 17 , conductive layers ML1, ML2, and ML3 can be formed on the gate insulating pattern GI. The conductive layers ML1, ML2, and ML3 may include a first conductive layer ML1, a second conductive layer ML2, and a third conductive layer ML3. The conductive layers ML1, ML2, and ML3 may cover the preliminary semiconductor pattern P-SP. The conductive layers ML1, ML2, and ML3 may be filled in the first contact hole CH1, the second contact hole CH2, and the first opening OP-TR.

[0180] Reference Figure 18 and Figure 19, a photoresist layer PR may be formed on the conductive layers ML1, ML2, and ML3, and a photolithography opening PR-OP may be defined through the photoresist layer PR. The photoresist layer PR may be configured to etch portions of the conductive layers ML1, ML2, and ML3 corresponding to the photolithography opening PR-OP.

[0181] Reference Figure 20 , a second opening OP-CH1 may be formed through the conductive layers ML1, ML2, and ML3 to correspond to the photolithography opening PR-OP. Portions of a first part of the preliminary semiconductor pattern P-SP may be exposed through the second opening OP-CH1. That is, portions of each of the first-first drain region D-A1-1 and the first-first source region S-A1-1 may be exposed. The conductive layers ML1, ML2, and ML3 may be divided into a gate electrode GE, a first connection electrode CNE1, and a second connection electrode CNE2 through the second opening OP-CH1. The gate electrode GE may correspond to the active region A-A.

[0182] In this case, the protruding patterns CRP1 and CRP2 (reference Figure 5 ) may be formed together with the gate electrode GE, the first connection electrode CNE1, and the second connection electrode CNE2. The protruding patterns CRP1 and CRP2 (reference Figure 5 ) may correspond to portions of the connection electrodes CNE1 and CNE2 and may protrude toward the active region A-A. That is, the first connection electrode CNE1, the second connection electrode CNE2, the gate electrode GE, and the protruding patterns CRP1 and CRP2 (reference Figure 5 ) may be formed by etching the conductive layers ML1, ML2, and ML3. The protruding patterns CRP1 and CRP2 (reference Figure 5 ) have been described previously, and thus, their details will be omitted.

[0183] Reference Figure 21 , portions of the second gate insulating pattern GI2 corresponding to the second opening OP-CH1 may be etched. In this case, the first-second drain region D-A1-2 and the first-second source region S-A1-2 covered by the second gate insulating pattern GI2 may be doped.

[0184] In addition, holes HO may be formed through the preliminary semiconductor pattern P-SP, and the holes HO may be disposed adjacent to one of the source region S-A and the drain region D-A. The holes HO may be provided in plurality, and each of the holes HO may overlap with the first drain region D-A1 or the first source region S-A1. The holes HO may penetrate the semiconductor pattern SP. Portions of the upper surface of the buffer layer BFL may be exposed through the holes HO.

[0185] Reference Figure 22 , the photoresist layer PR used as a mask may be removed.

[0186] Reference Figure 23 , an insulating layer INS1 and INS2, a display element layer DP-OL, and a packaging layer TFE can be formed on a preliminary display device P-DD of Figure 22 to manufacture a display panel DP.

[0187] Although embodiments of the present disclosure have been described, it is to be understood that the present disclosure should not be limited to these embodiments, but rather various changes and modifications can be made by those of ordinary skill in the art within the spirit and scope of the present disclosure as claimed in the claims. Therefore, the disclosed subject matter should not be limited to any single embodiment described herein, and the scope of the inventive concept should be determined in accordance with the appended claims.

Claims

1. A display device, comprising: a base substrate; a transistor disposed on the base substrate and including a semiconductor pattern and a gate electrode, the semiconductor pattern including a source region, an active region, and a drain region; a gate insulating pattern disposed on the semiconductor pattern; and a connection electrode disposed on the gate insulating pattern and electrically connected to the semiconductor pattern, wherein a first hole extends through the transistor and is adjacent to one of the source region and the drain region, the connection electrode is disposed on the same layer as the gate electrode, and the connection electrode includes a protruding pattern that protrudes toward the active region when viewed in a plane.

2. The display device according to claim 1, wherein, The first holes are provided in plurality, and the protruding pattern is provided between the plurality of first holes.

3. The display device according to claim 1, wherein, The protruding pattern includes a first protruding pattern that extends from one of the source region and the drain region toward the active region in a direction parallel to a first direction.

4. The display device according to claim 3, wherein, The protruding pattern further includes a second protruding pattern that extends from the first protruding pattern in a direction parallel to a second direction intersecting the first direction.

5. The display device according to claim 1, wherein, The connection electrode is electrically connected to the source region or the drain region.

6. The display device according to claim 1, wherein, The protruding pattern is electrically connected to the active region.

7. The display device according to claim 1, wherein, The protruding pattern is directly disposed on the source region or the drain region.

8. The display device according to claim 1, wherein, The first hole does not overlap with the protruding pattern.

9. The display device according to claim 1, wherein, The protruding patterns are provided in plurality, and the plurality of protruding patterns protrude radially around a center point.

10. The display device according to claim 1, wherein, The connection electrodes are provided in plurality, and the plurality of connection electrodes include: a first connection electrode connected to the drain region; and a second connection electrode connected to the source region.

11. The display device according to claim 10 further includes a first conductive pattern and a second conductive pattern, the first conductive pattern and the second conductive pattern being disposed between the base substrate and the transistor and spaced apart from each other when viewed in the plane, wherein, The first conductive pattern is electrically connected to the drain region via the first connection electrode, and the second conductive pattern is electrically connected to the source region via the second connection electrode.

12. The display device according to claim 1, wherein, Each of the source region and the drain region includes: a first portion having a first conductivity; and a second portion having a second conductivity lower than the first conductivity.

13. The display device according to claim 12, wherein, The protruding pattern protrudes from the first portion.

14. The display device according to claim 12, wherein, The active region, the first portion, and the protruding pattern are electrically connected to each other.

15. The display device according to claim 1 further includes a light-emitting element, the light-emitting element being disposed on the connection electrode and including a first electrode, a light-emitting layer, and a second electrode, the first electrode being connected to the connection electrode, wherein, The connection electrode electrically connects the first electrode to the transistor.

16. A display device, comprising: a base substrate; a transistor disposed on the base substrate and including a semiconductor pattern and a gate electrode, the semiconductor pattern including a source region, an active region, and a drain region; a gate insulating pattern disposed on the semiconductor pattern; and a connection electrode disposed on the gate insulating pattern and electrically connected to the semiconductor pattern, wherein a first hole extends through the transistor and is adjacent to one of the source region and the drain region, the connection electrode is disposed on the same layer as the gate electrode, the first holes are provided in plurality, and the connection electrode includes a protruding pattern provided between the plurality of first holes.

17. A method of manufacturing a display device, comprising: Prepare a preliminary display device, the preliminary display device including a base substrate, a preliminary semiconductor pattern, and a gate insulating pattern, the preliminary semiconductor pattern being disposed on the base substrate and including a source region, an active region, and a drain region, the gate insulating pattern being disposed on the preliminary semiconductor pattern; Form a first opening through the gate insulating pattern to expose a first portion of the preliminary semiconductor pattern; Form a conductive layer on the gate insulating pattern; Form a second opening through the conductive layer to expose a portion of the first portion of the preliminary semiconductor pattern and form a gate electrode and a connection electrode from the conductive layer; And Form a first hole through the preliminary semiconductor pattern adjacent to one of the source region and the drain region to form a semiconductor pattern from the preliminary semiconductor pattern, wherein the connection electrode includes a protruding pattern that protrudes toward the active region when viewed in a plane.

18. The method according to claim 17, further comprising: After forming the first opening, dope the first portion of the preliminary semiconductor pattern exposed through the first opening.

19. The method according to claim 17, wherein, Forming the gate electrode and the connection electrode includes: Form a photoresist layer on the conductive layer, a photolithography opening being defined through the photoresist layer; and Etch the conductive layer.

20. The method according to claim 17, wherein The connection electrode is disposed on the gate insulating pattern and electrically connected to the semiconductor pattern, and the connection electrode is disposed on the same layer as the gate electrode.

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