Display device and method of manufacturing same

Abstract

A display device includes a substrate including a first region, a second region surrounding at least a portion of the first region, and a third region between the first region and the second region. The light emitting diodes are arranged in the second region. The first spacer is disposed in the third region. The first spacer includes an organic pattern layer having a groove. The metal pattern layer is disposed on the organic pattern layer and includes a tip extending toward a center of the groove. In a cross section, a top surface of the organic pattern layer includes a first point having a maximum vertical distance from a top surface of the substrate. An imaginary line passing through a first point of the organic pattern layer and an edge of a terminal of the metal pattern layer is inclined in a direction toward a top surface of the substrate.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2024 - 0014317, filed with the Korean Intellectual Property Office on January 30, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] One or more embodiments relate to a display device and a method of manufacturing the display device. Background art

[0004] Recently, display devices have been applied to various electronic devices and used for various purposes. Due to the reduction in the thickness and weight of display devices, the use of display devices has been increasing.

[0005] As the size of the display area in a display device has increased, various functions incorporated in or connected to the display device have increased. Research has been conducted to arrange various components in some parts of the display area of the display device to increase various functions while increasing the size of the display area. Summary of the invention

[0006] One or more embodiments include a display device having an area for arranging various types of components and having increased reliability, and a method of manufacturing the display device. However, this is merely an example, and the scope of the embodiments of the present disclosure need not be limited thereto.

[0007] Additional aspects will be set forth in part in the following description, and in part will be obvious from the description, or may be learned by practice of the presented embodiments of the present disclosure.

[0008] According to an embodiment of the present disclosure, a display device includes: a substrate including a first area, a second area surrounding at least a part of the first area, and a third area between the first area and the second area. Light - emitting diodes are arranged in the second area and include a sub - pixel electrode, a counter electrode, and an intermediate layer between the sub - pixel electrode and the counter electrode. A first spacer is disposed in the third area. The first spacer includes an organic pattern layer having a groove. A metal pattern layer is disposed on the organic pattern layer and includes an end extending toward the center of the groove. In a cross - section, a top surface of the organic pattern layer includes a first point having a maximum vertical distance from a top surface of the substrate. An imaginary line passing through the first point of the organic pattern layer and an edge of the end of the metal pattern layer is inclined in a direction toward the top surface of the substrate.

[0009] In an embodiment, the organic pattern layer may include a first portion overlapping the groove and a second portion outside the first portion. The second portion does not overlap the groove. A top surface of the second portion may include a bevel.

[0010] In one embodiment, the metal pattern layer may at least partially cover the top surface and the outer surface of the organic pattern layer.

[0011] In one embodiment, at least a portion of the end of the metal pattern layer may be inclined in a direction toward the top surface of the substrate.

[0012] In one embodiment, at least a portion of the end of the metal pattern layer may extend parallel to the top surface of the substrate.

[0013] In one embodiment, at least a portion of the end of the metal pattern layer may be inclined in a direction away from the top surface of the substrate.

[0014] In one embodiment, the display device may further include an inorganic insulating layer disposed on the substrate. The organic pattern layer is directly disposed on the inorganic insulating layer. The second spacer is spaced apart from the first spacer in the third region. The third region may include an inorganic contact region in the space between the first spacer and the second spacer. The metal pattern layer directly contacts the top surface of the inorganic insulating layer in the inorganic contact region.

[0015] In one embodiment, the display device may include a cover layer including a first cover portion covering the top surface and the side surface of the metal pattern layer and a second cover portion disposed in the groove.

[0016] In one embodiment, the cover layer may include the same material as that of the sub-pixel electrode.

[0017] In one embodiment, the metal pattern layer may include a first sub-layer, a second sub-layer, and a third sub-layer sequentially stacked. The third sub-layer may extend from the point where the side surface of the second sub-layer intersects the bottom surface of the third sub-layer toward the center of the groove.

[0018] In one embodiment, the intermediate layer may include at least one organic material layer, and the at least one organic material layer and the counter electrode may be blocked from each other by the first spacer in the third region.

[0019] According to one embodiment, a method of manufacturing a display device includes: preparing a substrate including a first region, a second region surrounding at least a portion of the first region, and a third region between the first region and the second region. Forming an organic pattern layer in the third region. Forming a metal pattern layer on the organic pattern layer. Forming a first spacer including a groove and an end by removing a portion of the organic pattern layer. In the second region, forming a light-emitting diode including a sub-pixel electrode, a counter electrode, and an intermediate layer between the sub-pixel electrode and the counter electrode. In a cross-section, the top surface of the organic pattern layer includes a first point having a maximum vertical distance from the top surface of the substrate. The metal pattern layer includes an end extending toward the center of the groove. An imaginary line passing through the first point of the organic pattern layer and the edge of the end of the metal pattern layer is inclined in a direction toward the top surface of the substrate.

[0020] In one embodiment, forming the organic pattern layer may include forming a preliminary organic pattern layer on a substrate, disposing a mask on the preliminary organic pattern layer, and exposing and developing the preliminary organic pattern layer by using the mask.

[0021] In one embodiment, forming the organic pattern layer may be performed by using a phase shift mask.

[0022] In one embodiment, forming the organic pattern layer may be performed by using a halftone mask or a slit.

[0023] In one embodiment, the organic pattern layer may include a central portion and an edge portion, and a vertical distance from the top surface of the substrate to the top surface of the central portion may be less than a vertical distance from the top surface of the substrate to the top surface of the edge portion.

[0024] In one embodiment, forming the metal pattern layer may include forming a preliminary metal pattern layer and forming a metal pattern layer including an opening by patterning the preliminary metal pattern layer, and the opening in the metal pattern layer may expose at least a part of the central portion of the organic pattern layer.

[0025] In one embodiment, removing a part of the organic pattern layer may include ashing the organic pattern layer by using the metal pattern layer as a mask.

[0026] In one embodiment, the method may further include forming a cover layer on the metal pattern layer, the cover layer including a material same as that of the sub-pixel electrode.

[0027] In one embodiment, the method may further include forming an opening region overlapping with the first region in the substrate.

[0028] According to one embodiment, an electronic device includes a display device.

[0029] In one embodiment, the electronic device may be at least one of a television, a notebook computer, a monitor, a billboard chart, an Internet of Things (IoT) device, a mobile phone, a smart phone, a tablet personal computer, a mobile communication terminal, an electronic notepad, an e-book, a portable multimedia player, a navigation device, an ultra-mobile personal computer, a smart watch, a watch phone, and a head-mounted display. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects, features, and advantages of certain non-limiting embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0031] Figure 1 A perspective view schematically illustrating an electronic device according to an embodiment of the present disclosure;

[0032] Figure 2 To briefly illustrate a cross-sectional view of an electronic device taken along line I-I' shown in Figure 1 ;

[0033] Figure 3 To schematically illustrate a top view of a display device according to an embodiment of the present disclosure;

[0034] Figure 4 And Figure 5 To be equivalent circuit diagrams, each briefly illustrating any one sub-pixel included in a display device according to an embodiment of the present disclosure;

[0035] Figure 6 To be a top view of a part of a display device according to an embodiment of the present disclosure;

[0036] Figure 7 To illustrate a cross-sectional view of a part of a display device taken along line III-III' shown in Figure 6 ;

[0037] Figure 8 To be a cross-sectional view of a part of a display device according to an embodiment of the present disclosure;

[0038] Figure 9A And Figure 9B To be cross-sectional views of some parts of a display device according to an embodiment of the present disclosure;

[0039] Figure 10A 、 Figure 10B And Figure 11 To be cross-sectional views of some parts of a display device according to an embodiment of the present disclosure;

[0040] Figures 12A to 12G To briefly illustrate a cross-sectional view of a method for manufacturing a display device according to an embodiment of the present disclosure;

[0041] Figures 13A to 13D To briefly illustrate a cross-sectional view of a method for manufacturing a display device according to an embodiment of the present disclosure;

[0042] Figures 14A to 14C To briefly illustrate a cross-sectional view of a method for manufacturing a display device according to an embodiment of the present disclosure;

[0043] Figure 15 To be a cross-sectional view of a part of a display device according to an embodiment of the present disclosure;

[0044] Figure 16 To be a cross-sectional view of a part of a display device according to an embodiment of the present disclosure;

[0045] Figures 17A to 17EA cross-sectional view for briefly illustrating a method of manufacturing a display device according to an embodiment of the present disclosure; and

[0046] Figures 18A to 18C A cross-sectional view for briefly illustrating a method of manufacturing a display device according to an embodiment of the present disclosure. Detailed Description

[0047] Now, embodiments will be described in detail with reference to examples, which are illustrated in the accompanying drawings, wherein the same reference numerals refer to the same elements throughout. In this regard, the embodiments of the present disclosure may have different forms and should not be construed as limited to the descriptions set forth herein. Therefore, the following non-limiting embodiments are described only by referring to the drawings to explain aspects of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Throughout the present disclosure, the expression "at least one of a, b, and c" indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0048] As used herein, the terms "first" and "second" are used only to distinguish one element from other elements and are not used in a limiting sense.

[0049] As used herein, unless the context clearly dictates otherwise, the singular forms are also intended to include the plural forms.

[0050] It will be further understood that terms such as "comprise / comprising / include / including" and "have / having" when used herein indicate the presence of the recited features and / or elements, but do not preclude the presence or addition of one or more other features and / or elements.

[0051] In the following embodiments, when a part such as a film, region, or component is on or above another part, the part may be directly on the other part, or other films, regions, or components may be located therebetween.

[0052] In the drawings, for convenience, the dimensions of the elements may be enlarged or reduced. For example, since the dimensions such as thickness of each element may be arbitrarily illustrated in the drawings for ease of description, the embodiments of the present disclosure are not necessarily limited to those illustrated.

[0053] When some embodiments can be implemented differently, a specific process sequence may be performed in a sequence different from the description. For example, two processes described successively may be performed substantially simultaneously, or may be performed in an order opposite to the described order.

[0054] In this specification, "A and / or B" indicates A, B, or both A and B. "At least one of A and B" indicates A, B, or both A and B.

[0055] In this specification, when referring to a film, region, and component being connected to another film, region, and component, the film, region, and component may be directly connected to the other film, region, and component, or may be indirectly connected through another film, region, and component therebetween. For example, when referring to a film, region, and component being electrically connected to another film, region, and component, the film, region, and component may be directly electrically connected to the other film, region, and component, or may be indirectly electrically connected to the other film, region, and component through other films, regions, and components therebetween.

[0056] The x-direction, y-direction, and z-direction are not necessarily limited to the directions corresponding to the three axes on a rectangular coordinate system, and may be interpreted in a broader sense including the same. For example, the x-direction, y-direction, and z-direction may be orthogonal to each other, but may also refer to different directions that cross each other but are not orthogonal to each other.

[0057] Figure 1 A perspective view schematically illustrating an electronic device 1 according to an embodiment.

[0058] Reference Figure 1 , the electronic device 1 may include a display device, which is a device configured to display video and / or still images. In one embodiment, the display device may be used for the display screens of various products such as televisions, notebook computers, monitors, billboard charts, or Internet of Things (IoT) devices, as well as for the display screens of mobile electronic devices such as mobile phones, smart phones, tablet personal computers (tablet PCs), mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, or ultra-mobile personal computers (UMPCs). Additionally, the display device according to an embodiment may be used as the display screen of wearable devices such as smart watches, watch phones, and head-mounted displays (HMDs). Additionally, the display device according to an embodiment may be used as the dashboard of a vehicle, a central information display (CID) arranged on the center console or dashboard of a vehicle, an interior mirror display replacing the side mirror of a vehicle, an entertainment device for the rear seats of a vehicle, and a display arranged on the rear surface of the front panel. For ease of explanation, Figure 1 the electronic device 1 according to an embodiment is illustrated as a smart phone. However, the embodiments of the present disclosure are not necessarily limited thereto.

[0059] In one embodiment, in a plan view (e.g., in a plane defined by the x-direction and y-direction), the electronic device 1 may have a rectangular form. For example, as Figure 1As shown, the electronic device 1 may have the form of a rectangular plane, having a short axis in the x direction and a long axis in the y direction. The corners where the short axis in the x direction intersects the long axis in the y direction may be rounded to have a certain curvature or may be formed into a square shape. However, the planar shape of the electronic device 1 need not be limited to a rectangle and may be formed into other polygons, an oval shape, or an amorphous shape.

[0060] The electronic device 1 may include an opening area OA and a display area DA that surrounds at least a portion of the opening area OA (e.g., in the x direction and / or the y direction). The electronic device 1 may include an intermediate area MA between the opening area OA and the display area DA and a peripheral area PA that surrounds the outside of the display area DA (e.g., in the x direction and / or the y direction). In one embodiment, the intermediate area MA may have a closed-loop shape in a plan view that completely surrounds the opening area OA (e.g., in the x direction and / or the y direction).

[0061] The opening area OA may be inside the display area DA. In one embodiment, as Figure 1 illustrated, the opening area OA may be in the middle of the upper side (e.g., in the y direction) of the display area DA (e.g., in the x direction). Alternatively, the opening area OA may be arranged in various ways, such as on the upper left side of the display area DA or on the upper right side of the display area DA. Although Figure 1 illustrated with the opening area OA arranged in an odd number (e.g., only one opening area OA is arranged in the electronic device 1), the embodiments of the present disclosure need not be limited thereto, and in some embodiments, the electronic device 1 may include a plurality of opening areas OA.

[0062] In one embodiment, the opening area OA may include a first area, the display area DA may include a second area, and the intermediate area MA may include a third area.

[0063] Figure 2 For a brief illustration of a cross-sectional view of the electronic device 1 taken along the Figure 1 line I-I’ shown.

[0064] Referring to Figure 2 , the electronic device 1 may include a display device 10 and a component 70 arranged in the opening area OA of the display device 10. In one embodiment, the display device 10 and the component 70 may be accommodated in a housing HS.

[0065] In one embodiment, the display device 10 may include an image generation layer 20, an input sensing layer 40, an optical function layer 50, and a cover window 60 (e.g., arranged in the z direction).

[0066] The image generation layer 20 may include display elements configured to emit light to display an image. In one embodiment, the display elements may include light-emitting diodes, such as organic light-emitting diodes including an organic emission layer. In some embodiments, the light-emitting diodes may include inorganic light-emitting diodes containing inorganic materials. The inorganic light-emitting diodes may include PN junction diodes containing inorganic semiconductor-like materials. When a voltage is applied in the forward direction to the PN junction diode, holes and electrons are injected, and light of a specific color may be emitted by converting the energy generated by the recombination of holes and electrons into light energy. The above-mentioned inorganic light-emitting diodes may have a width of several micrometers to several hundred micrometers or several nanometers to several hundred nanometers. In some embodiments, the image generation layer 20 may include quantum dot light-emitting diodes. For example, the emission layer of the image generation layer 20 may include organic materials, may include inorganic materials, may include quantum dots, may include organic materials and quantum dots, or may include inorganic materials and quantum dots.

[0067] The input sensing layer 40 may include coordinate information according to an external input such as a touch event. The input sensing layer 40 may include touch electrodes (or referred to as sensing electrodes) and traces connected to the touch electrodes. The input sensing layer 40 may be disposed on the image generation layer 20. The input sensing layer 40 may be configured to sense an external input by a mutual capacitance method and / or a self-capacitance method.

[0068] The input sensing layer 40 may be directly disposed on the image generation layer 20, or may be separately formed and then bonded to the image generation layer 20 through an adhesive layer such as an optically clear adhesive OCA. For example, in one embodiment, the input sensing layer 40 may be continuously formed after the process of forming the image generation layer 20, and in this embodiment, the adhesive layer (e.g., in the z direction) may not be disposed between the input sensing layer 40 and the image generation layer 20. Although Figure 2 illustrating the input sensing layer 40 (e.g., in the z direction) between the image generation layer 20 and the optical function layer 50, in some embodiments, the input sensing layer 40 may be disposed on the optical function layer 50, and the optical function layer 50 may (e.g., in the z direction) be disposed between the image generation layer 20 and the input sensing layer 40.

[0069] The optical function layer 50 may include an antireflection layer. The antireflection layer may be configured to reduce the reflectance of light (e.g., external light) incident on the display device 10 from the outside (e.g., the external environment) through the cover window 60. In one embodiment, the antireflection layer may include a retarder and a polarizer. However, the embodiments of the present disclosure are not necessarily limited thereto. In some embodiments, the antireflection layer may include a black matrix and a color filter. The color filter may be arranged in consideration of the color of light emitted from each of the light-emitting diodes in the image generation layer 20.

[0070] To increase the transmittance of the opening area OA, the display device 10 may include an opening 10OP that penetrates some of the layers included in the display device 10. The opening 10OP may include, for example, in the z direction, a first opening 20OP, a second opening 40OP, and a third opening 50OP that respectively penetrate the image generation layer 20, the input sensing layer 40, and the optical function layer 50. The first opening 20OP in the image generation layer 20, the second opening 40OP in the input sensing layer 40, and the third opening 50OP in the optical function layer 50 may overlap each other to form the opening 10OP of the display device 10.

[0071] The cover window 60 may be disposed on the optical function layer 50. In one embodiment, the cover window 60 may be bonded to the optical function layer 50 through an adhesive layer such as an optically clear adhesive OCA disposed (for example, in the z direction) between the cover window 60 and the optical function layer 50. The cover window 60 may cover the first opening 20OP in the image generation layer 20, the second opening 40OP in the input sensing layer 40, and the third opening 50OP in the optical function layer 50.

[0072] The cover window 60 may include glass or plastic. In one embodiment, the glass may include ultra-thin glass. The plastic may include polyethersulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate, etc.

[0073] The opening area OA may include a type of component area (for example, a sensor area, a camera area, or a speaker area, etc.) in which components 70 for adding various functions to the electronic device 1 are arranged.

[0074] The components 70 may include electronic components. For example, in one embodiment, the components 70 may include electronic components that use light or sound. For example, the electronic components may include sensors such as infrared sensors configured to use light, cameras configured to receive light and capture images, sensors configured to measure distances or identify fingerprints by outputting and sensing light or sound, small lamps configured to output light, or speakers configured to output sound, etc. The electronic components configured to use light may use light in various wavelength bands, such as visible light, infrared light, or ultraviolet light, etc. The opening area OA corresponds to an area through which light and / or sound output from the components 70 to the outside or traveling from the outside (for example, the external environment) toward the electronic components can be transmitted.

[0075] Figure 3 FIG. is a schematic top view of a display device 10 according to an embodiment.

[0076] Reference Figure 3, the display device 10 may include a plurality of sub-pixels PX arranged in a display area DA, and may be configured to display an image using light emitted from each of the plurality of sub-pixels PX. In one embodiment, each of the plurality of sub-pixels PX may be configured to emit red, green, or blue light using a light-emitting diode. However, embodiments of the present disclosure are not necessarily limited thereto, and the color of the light emitted by the plurality of sub-pixels PX may vary. The light-emitting diodes of each of the plurality of sub-pixels PX may be electrically connected to a scan line SL and a data line DL.

[0077] In one embodiment, a scan driver 2100 configured to provide a scan signal to each of the sub-pixels PX, a data driver 2200 configured to provide a data signal to each of the sub-pixels PX, a first main power supply wiring configured to provide a first power supply voltage (e.g., a driving voltage), and a second main power supply wiring configured to provide a second power supply voltage (e.g., a common voltage) may be arranged in a peripheral area PA. In one embodiment, the scan driver 2100 may be respectively arranged on both sides of the display area DA, and the display area DA (e.g., in the x direction) is located between the scan drivers 2100. In this embodiment, the sub-pixels PX arranged on the left side of the opening area OA may be connected to the scan driver 2100 arranged on the left side of the display area DA, and the sub-pixels PX arranged on the right side of the opening area OA may be connected to the scan driver 2100 arranged on the right side of the display area DA.

[0078] An intermediate area MA may surround the opening area OA. The intermediate area MA indicates an area in which display elements such as light-emitting diodes configured to emit light are not arranged. Signal lines configured to provide signals to the sub-pixels PX provided near the opening area OA may pass through the intermediate area MA. For example, the data line DL and / or the scan line SL may pass through the display area DA, and some of the data lines DL and / or the scan line SL may bypass in the intermediate area MA along the edge of the opening 10OP of the display device 10 formed in the opening area OA. In one embodiment, Figure 3 Illustratively, the data line DL passes through the display area DA in the y direction, and some of the data lines DL bypass in the intermediate area MA to partially surround the opening area OA. In one embodiment, the scan line SL may pass through the display area DA in the x direction, and may be spaced apart from each other with the opening area OA between the scan lines SL.

[0079] Although Figure 3 illustrates that the data driver 2200 is arranged adjacent to one side of the substrate 100 (e.g., the lower side in the y direction), embodiments of the present disclosure are not necessarily limited thereto. For example, in one embodiment, the data driver 2200 may be provided on a printed circuit board electrically connected to a pad arranged on one side of the display device 10. The printed circuit board may be flexible, and a part of the printed circuit board may be bent to be under the back surface of the substrate 100.

[0080] Figure 4 and Figure 5 is an equivalent circuit diagram of any one sub-pixel PX included in the display device 10 according to an embodiment.

[0081] Referring to Figure 4 , the sub-pixel PX may include a sub-pixel circuit PC and an organic light-emitting diode OLED, such as a display element electrically connected to the sub-pixel circuit PC.

[0082] For example, in one embodiment, the sub-pixel circuit PC may include a first thin-film transistor T1, a second thin-film transistor T2, a third thin-film transistor T3, a fourth thin-film transistor T4, a fifth thin-film transistor T5, a sixth thin-film transistor T6, a seventh thin-film transistor T7, and a capacitor Cst. However, embodiments of the present disclosure are not necessarily limited thereto, and the number of thin-film transistors in the sub-pixel circuit PC may vary.

[0083] In one embodiment, the first thin-film transistor T1 may include a driving transistor, the second thin-film transistor T2 may include a switching transistor, the third thin-film transistor T3 may include a compensating transistor, the fourth thin-film transistor T4 may include a first initialization transistor, the fifth thin-film transistor T5 may include an operation control transistor, the sixth thin-film transistor T6 may include an emission control transistor, and the seventh thin-film transistor T7 may include a second initialization transistor.

[0084] The organic light-emitting diode OLED may include a sub-pixel electrode and a counter electrode. The sub-pixel electrode of the organic light-emitting diode OLED may be connected to the first thin-film transistor T1 through the sixth thin-film transistor T6, and may receive a driving current Ioled, and the counter electrode may receive a common voltage ELVSS. The organic light-emitting diode OLED may be configured to generate light having a brightness corresponding to the driving current Ioled.

[0085] In one embodiment, all of the first thin-film transistor T1 to the seventh thin-film transistor T7 may include PMOS transistors. In one embodiment, the first thin-film transistor T1 to the seventh thin-film transistor T7 may include amorphous silicon or polysilicon.

[0086] The signal lines may include a first scan line SL1, a previous scan line SLp, a next scan line SLn, an emission control line EL, and a data line DL. However, embodiments of the present disclosure are not necessarily limited thereto. Additionally, the first scan line SL1 may be configured to transmit a first scan signal Sn. The previous scan line SLp may be configured to transmit a previous scan signal Sn-1 to the fourth thin film transistor T4. The next scan line SLn may be configured to transmit a next scan signal Sn+1 to the seventh thin film transistor T7. The emission control line EL may be configured to transmit an emission control signal EM to the fifth thin film transistor T5 and the sixth thin film transistor T6. The data line DL may be configured to convey a data signal DATA.

[0087] The driving voltage line PL may be configured to transmit a driving voltage ELVDD to the first thin film transistor T1, and the initialization voltage line VIL may be configured to transmit an initialization voltage VINT for initializing the first thin film transistor T1 and the organic light emitting diode OLED to the sub-pixel PX. For example, in one embodiment, the first initialization voltage line VIL1 may be configured to transmit the initialization voltage VINT to the fourth thin film transistor T4, and the second initialization voltage line VIL2 may be configured to transmit the initialization voltage VINT to the seventh thin film transistor T7.

[0088] The gate electrode of the first thin film transistor T1 may be connected to the capacitor Cst. Either the source region or the drain region of the first thin film transistor T1 may be connected to the driving voltage line PL via the fifth thin film transistor T5 through the first node N1, and the other of the source region and the drain region of the first thin film transistor T1 may be electrically connected to the sub-pixel electrode of the organic light emitting diode OLED via the sixth thin film transistor T6. The first thin film transistor T1 may be configured to receive the data signal DATA in response to the switching operation of the second thin film transistor T2 and provide a driving current Ioled to the organic light emitting diode OLED.

[0089] The gate electrode of the second thin film transistor T2 may be connected to the first scan line SL1 configured to transmit the first scan signal Sn. One of the source region and the drain region of the second thin film transistor T2 may be connected to the data line DL, and the other of the source region and the drain region of the second thin film transistor T2 may be connected to the first thin film transistor T1 through the first node N1 and connected to the driving voltage line PL via the fifth thin film transistor T5. In one embodiment, the second thin film transistor T2 may be turned on in response to the first scan signal Sn transmitted through the first scan line SL1 and perform a switching operation to transmit the data signal DATA transmitted from the data line DL to the first thin film transistor T1 through the first node N1.

[0090] The gate electrode of the third thin film transistor T3 can be connected to the first scan line SL1. One of the source region and the drain region of the third thin film transistor T3 can be connected to the sub-pixel electrode of the organic light emitting diode OLED via the sixth thin film transistor T6. The other of the source region and the drain region of the third thin film transistor T3 can be connected to the capacitor Cst and the gate electrode of the first thin film transistor T1. In one embodiment, the third thin film transistor T3 can be turned on in response to the first scan signal Sn transmitted through the first scan line SL1, and diode-connect the first thin film transistor T1.

[0091] The gate electrode of the fourth thin film transistor T4 can be connected to the previous scan line SLp. One of the source region and the drain region of the fourth thin film transistor T4 can be connected to the first initialization voltage line VIL1. The other of the source region and the drain region of the fourth thin film transistor T4 can be connected to the first capacitor electrode of the capacitor Cst and the gate electrode of the first thin film transistor T1. In one embodiment, the fourth thin film transistor T4 can be turned on in response to the previous scan signal Sn-1 transmitted through the previous scan line SLp, and perform an initialization operation to initialize the voltage of the gate electrode of the first thin film transistor T1 by transmitting the initialization voltage VINT to the gate electrode of the first thin film transistor T1.

[0092] The gate electrode of the fifth thin film transistor T5 can be connected to the emission control line EL. One of the source region and the drain region of the fifth thin film transistor T5 can be connected to the driving voltage line PL, and the other of the source region and the drain region of the fifth thin film transistor T5 can be connected to the first thin film transistor T1 and the second thin film transistor T2 through the first node N1.

[0093] The gate electrode of the sixth thin film transistor T6 can be connected to the emission control line EL. One of the source region and the drain region of the sixth thin film transistor T6 can be connected to the first thin film transistor T1 and the third thin film transistor T3, and the other of the source region and the drain region of the sixth thin film transistor T6 can be electrically connected to the sub-pixel electrode of the organic light emitting diode OLED.

[0094] In one embodiment, the fifth thin film transistor T5 and the sixth thin film transistor T6 can be turned on simultaneously in response to the emission control signal EM transmitted through the emission control line EL, so that the driving voltage ELVDD is transmitted to the organic light emitting diode OLED, and the driving current Ioled flows through the organic light emitting diode OLED.

[0095] The gate electrode of the seventh thin film transistor T7 may be connected to the next scan line SLn. One of the source and drain regions of the seventh thin film transistor T7 may be connected to the sub-pixel electrode of the organic light emitting diode OLED, and the other of the source and drain regions of the seventh thin film transistor T7 may be connected to the second initialization voltage line VIL2 and receive the initialization voltage VINT. In one embodiment, the seventh thin film transistor T7 may be turned on in response to the next scan signal Sn+1 transmitted through the next scan line SLn, and initialize the sub-pixel electrode of the organic light emitting diode OLED. In one embodiment, the next scan line SLn may be the same as the first scan line SL1. In this embodiment, the scan line may be configured to transmit the same electrical signal at regular time intervals, and thus may be used as both the first scan line SL1 and the next scan line SLn. In some embodiments, the seventh thin film transistor T7 may be omitted.

[0096] The capacitor Cst may be configured to hold the voltage applied to the gate electrode of the first thin film transistor T1 by connecting to the driving voltage line PL and the gate electrode of the first thin film transistor T1 and storing and maintaining a voltage corresponding to the difference between the voltages at both ends of the capacitor Cst.

[0097] Details of the operation of the sub-pixel circuit PC according to an embodiment and the organic light emitting diode OLED as a display element are as follows.

[0098] During initialization, when the previous scan signal Sn-1 is provided through the previous scan line SLp, the fourth thin film transistor T4 is turned on corresponding to the previous scan signal Sn-1, and the first thin film transistor T1 may be initialized due to the initialization voltage VINT provided from the first initialization voltage line VIL1.

[0099] In one embodiment, during data programming, when the first scan signal Sn is provided through the first scan line SL1, the second thin film transistor T2 and the third thin film transistor T3 may be turned on corresponding to the first scan signal Sn. In this embodiment, the first thin film transistor T1 may be diode-connected through the turned-on third thin film transistor T3 and biased in the positive direction. By doing so, the compensation voltage DATA+Vth (where Vth is negative), which is the data signal DATA provided from the data line DL minus the threshold voltage Vth of the first thin film transistor T1, may be applied to the gate electrode of the first thin film transistor T1. The driving voltage ELVDD and the compensation voltage DATA+Vth may be applied to both ends of the capacitor Cst, and a load corresponding to the difference between the voltages at both ends of the capacitor Cst may be stored in the capacitor Cst.

[0100] In one embodiment, during emission, the fifth thin film transistor T5 and the sixth thin film transistor T6 may be simultaneously turned on in response to an emission control signal EM provided through an emission control line EL. A drive current Ioled corresponding to a voltage difference between a voltage of a gate electrode of the first thin film transistor T1 and a drive voltage ELVDD is generated, and the drive current Ioled may be provided to the organic light emitting diode OLED through the sixth thin film transistor T6.

[0101] Reference Figure 5 , in one embodiment, a sub-pixel circuit PC of the sub-pixel PX may include first to seventh thin film transistors T1 to T7, a capacitor Cst, and a second capacitor Cbt.

[0102] In one embodiment, some of the first to seventh thin film transistors T1 to T7 may include n-channel MOSFET (NMOS) transistors, while other transistors of the first to seventh thin film transistors T1 to T7 may include p-channel MOSFET (PMOS) transistors. For example, as Figure 5 shown, among the first to seventh thin film transistors T1 to T7, the third thin film transistor T3 and the fourth thin film transistor T4 may include NMOS transistors, and the first thin film transistor T1, the second thin film transistor T2, the fifth thin film transistor T5, the sixth thin film transistor T6, and the seventh thin film transistor T7 may include PMOS transistors. Alternatively, among the first to seventh thin film transistors T1 to T7, the third thin film transistor T3, the fourth thin film transistor T4, and the seventh thin film transistor T7 may include NMOS transistors, and the first thin film transistor T1, the second thin film transistor T2, the fifth thin film transistor T5, and the sixth thin film transistor T6 may include PMOS transistors. Alternatively, all of the first to seventh thin film transistors T1 to T7 may include NMOS transistors.

[0103] The signal lines may include a first scan line SL1 configured to transmit a first scan signal Sn', a second scan line SL2 configured to transmit a second scan signal Sn", a previous scan line SLp configured to transmit a previous scan signal Sn-1 to the fourth thin film transistor T4, an emission control line EL configured to transmit the emission control signal EM to the fifth thin film transistor T5 and the sixth thin film transistor T6, a next scan line SLn configured to transmit a next scan signal Sn+1 to the seventh thin film transistor T7, and a data line DL configured to transmit a data signal DATA.

[0104] The first thin film transistor T1 can be connected to the driving voltage line PL via the fifth thin film transistor T5 and can be electrically connected to the organic light emitting diode OLED via the sixth thin film transistor T6. In one embodiment, the first thin film transistor T1 can be configured to receive a data signal DATA in response to the switching operation of the second thin film transistor T2 and supply a driving current Ioled to the organic light emitting diode OLED.

[0105] The second thin film transistor T2 can be connected to the first scan line SL1 and the data line DL and can be connected to the driving voltage line PL via the fifth thin film transistor T5. In one embodiment, the second thin film transistor T2 can be turned on in response to a first scan signal Sn' transmitted through the first scan line SL1 and perform a switching operation to transmit the data signal DATA transmitted from the data line DL to the first node N1.

[0106] The third thin film transistor T3 can be connected to the second scan line SL2 and can be connected to the organic light emitting diode OLED via the sixth thin film transistor T6. In one embodiment, the third thin film transistor T3 can be configured to be turned on by a second scan signal Sn'' transmitted from the second scan line SL2 and diode-connect the first thin film transistor T1 to compensate for the threshold voltage of the first thin film transistor T1.

[0107] The fourth thin film transistor T4 can be connected to the previous scan line SLp and the first initialization voltage line VIL1. In one embodiment, the fourth thin film transistor T4 can be turned on in response to a previous scan signal Sn-1 transmitted through the previous scan line SLp and can initialize the voltage of the gate electrode of the first thin film transistor T1 by transmitting an initialization voltage VINT transmitted from the first initialization voltage line VIL1 to the gate electrode of the first thin film transistor T1.

[0108] In one embodiment, the fifth thin film transistor T5 and the sixth thin film transistor T6 can be connected to the emission control line EL, can be turned on simultaneously in response to an emission control signal EM transmitted through the emission control line EL, and can form a current path such that the driving current Ioled can flow from the driving voltage line PL in the direction toward the organic light emitting diode OLED.

[0109] The seventh thin film transistor T7 can be connected to the next scan line SLn and the second initialization voltage line VIL2. In one embodiment, the seventh thin film transistor T7 can be turned on in response to a next scan signal Sn+1 transmitted through the next scan line SLn and can transmit the initialization voltage VINT from the second initialization voltage line VIL2 to the organic light emitting diode OLED to initialize the organic light emitting diode OLED. However, embodiments of the present disclosure are not necessarily limited thereto. For example, in some embodiments, the seventh thin film transistor T7 can be omitted.

[0110] The capacitor Cst includes a first capacitor electrode CE1 and a second capacitor electrode CE2. The first capacitor electrode CE1 may be connected to the gate electrode of the first thin film transistor T1, and the second capacitor electrode CE2 may be connected to the driving voltage line PL. In one embodiment, the capacitor Cst may be configured to maintain the voltage applied to the gate electrode of the first thin film transistor T1 by storing and maintaining a voltage corresponding to the difference between the voltage of the driving voltage line PL and the voltage at both ends of the gate electrode of the first thin film transistor T1.

[0111] The second capacitor Cbt may include a third capacitor electrode CE3 and a fourth capacitor electrode CE4. The third capacitor electrode CE3 may be connected to the first scan line SL1 and the gate electrode of the second thin film transistor T2. The fourth capacitor electrode CE4 may be connected to the gate electrode of the first thin film transistor T1 and the first capacitor electrode CE1 of the capacitor Cst. In one embodiment, when the first scan signal Sn' of the first scan line SL1 is a voltage for turning off the second thin film transistor T2, the second capacitor Cbt may be a boosting capacitor for increasing the voltage of the second node N2 and clearly represent a black gray scale.

[0112] In one embodiment, at least one of the first thin film transistor T1 to the seventh thin film transistor T7 may include a semiconductor layer containing an oxide, and the other thin film transistors may include a semiconductor layer containing amorphous silicon or polycrystalline silicon.

[0113] For example, in one embodiment, the first thin film transistor T1, as a driving transistor that has a direct impact on the brightness of the display device 10, is arranged to include a semiconductor layer containing polycrystalline silicon with high reliability, and by doing so, a display device with high resolution can be achieved.

[0114] Since the oxide semiconductor has a high carrier mobility and a low leakage current, even when the oxide semiconductor is driven for a long time, the voltage drop of the oxide semiconductor may not be obvious. For example, the oxide semiconductor can be driven at a low frequency because even when the oxide semiconductor is driven at a low frequency, the color change in the image due to the voltage drop is not obvious.

[0115] The oxide semiconductor has the advantage of a small leakage current. Therefore, by using the oxide semiconductor for any one of the third thin film transistor T3 and the fourth thin film transistor T4 connected to the gate electrode of the first thin film transistor T1, the power consumption can be reduced while preventing the leakage current that may flow into the gate electrode of the first thin film transistor T1.

[0116] The sub-pixel circuit PC need not be limited to the reference Figure 4 and Figure 5The number and circuit design of the described thin film transistors and capacitors, and the number and circuit design can be modified in various ways.

[0117] Figure 6 FIG. 4 is a top view of a part of a display device 10 according to an embodiment.

[0118] Figure 6 Illustrate the opening area OA, the middle area MA, and the display area DA of the display device 10. Sub-pixels PX can be arranged in the display area DA. The sub-pixels PX can be arranged in the display area DA to surround the opening area OA and the middle area MA (e.g., in the x direction and / or the y direction). The sub-pixel PX can include the smallest area through which light is emitted, and light can be emitted through a display element such as an organic light-emitting diode OLED. The position of the sub-pixel PX can correspond to the position of the organic light-emitting diode OLED. The description that the sub-pixels PX are arranged in the display area DA can indicate that the organic light-emitting diodes OLED are arranged in the display area DA.

[0119] In a plan view, the sub-pixels PX and / or the organic light-emitting diodes OLED adjacent to the opening area OA can be arranged to be spaced apart from each other around the opening area OA. For example, in one embodiment, in a plan view, the sub-pixels PX and / or the organic light-emitting diodes OLED can be arranged to be vertically spaced apart from each other around the opening area OA (e.g., in the y direction), or can be arranged to be horizontally spaced apart from each other around the opening area OA (e.g., in the x direction).

[0120] In one embodiment, the spacers SP can be arranged to be spaced apart from each other in the middle area MA. For example, the spacers SP can be arranged to be spaced apart from each other between the display area DA and the opening area OA or between the display area DA and the opening 10OP. In one embodiment, each of the spacers SP can have a closed-loop shape in a plan view (e.g., when viewed from a direction perpendicular to the top surface of the substrate 100, such as the z direction).

[0121] Figure 7 FIG. 20 is a cross-sectional view of a part of the display device 10 taken along the line III-III' shown in FIG. 18 to illustrate an embodiment. Figure 6 FIG. 20 is a cross-sectional view of a part of the display device 10 taken along the line III-III' shown in FIG. 18 to illustrate an embodiment. Figure 8 FIG. 22 is a cross-sectional view of a part of the display device 10 according to an embodiment, which illustrates the part V shown in FIG. 22. Figure 7 FIG. 22 is a cross-sectional view of a part of the display device 10 according to an embodiment, which illustrates the part V shown in FIG. 22.

[0122] Referring to Figure 7 the display area DA in Figure 7 FIG. 31 illustrates the image generation layer 20 of the display device 10. In one embodiment, the image generation layer 20 can include a substrate 100, a circuit diode layer provided on the substrate 100 and including a sub-pixel circuit PC and an organic light-emitting diode OLED, and a packaging layer 300.

[0123] The circuit diode layer may include a sub-pixel circuit PC and a plurality of insulating layers (e.g., in the z-direction) disposed on or under the components of the sub-pixel circuit PC. The insulating layers may include an inorganic insulating layer and an organic insulating layer. In one embodiment, the inorganic insulating layer IIL may include, for example, a first buffer layer 101a, a second buffer layer 101b, a first gate insulating layer 103, a first interlayer insulating layer 105, a second interlayer insulating layer 107, a second gate insulating layer 109, and a third interlayer insulating layer 110 (e.g., arranged in the z-direction). In one embodiment, the organic insulating layer may include, for example, a first planarization layer 111 and a second planarization layer 113. However, embodiments of the present disclosure are not necessarily limited thereto.

[0124] The substrate 100 may include glass or a polymer resin. In one embodiment, the substrate 100 may have a structure in which a base layer including a polymer resin and an isolation layer including an inorganic insulator (such as silicon oxide or silicon nitride) (e.g., in the z-direction) are alternately stacked. In one embodiment, the polymer resin may include polyether sulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, triacetyl cellulose, or cellulose acetate propionate, etc.

[0125] The sub-pixel circuit PC may be formed on the substrate 100, and a light-emitting diode such as an organic light-emitting diode OLED may be disposed on the sub-pixel circuit PC.

[0126] Before forming the sub-pixel circuit PC, a first buffer layer 101a and a second buffer layer 101b for preventing impurities from penetrating into the sub-pixel circuit PC may be formed on the substrate 100. In one embodiment, the first buffer layer 101a and the second buffer layer 101b may include an inorganic insulator such as silicon nitride, silicon oxynitride, or silicon oxide, and may include a single-layer or multi-layer structure including the above inorganic insulator.

[0127] The back metal layer BML may be disposed between the first buffer layer 101a and the second buffer layer 101b. The back metal layer BML may prevent external light from reaching the sub-pixel circuit PC. In one embodiment, the back metal layer BML may include, for example, a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), etc., and may include a single-layer or multi-layer structure including the above materials.

[0128] The sub-pixel circuit PC may include a plurality of transistors and capacitors, as referred to above Figure 5 In this regard, Figure 7 the first thin film transistor T1, the third thin film transistor T3, and the capacitor Cst are illustrated.

[0129] The first thin film transistor T1 may include a semiconductor layer A1 (hereinafter, referred to as the first semiconductor layer) on the second buffer layer 101b (e.g., directly disposed thereon in the z direction) and a gate electrode GE1 (hereinafter, referred to as the first gate electrode) overlapping the channel region of the first semiconductor layer A1 (e.g., in the z direction). In one embodiment, the first semiconductor layer A1 may include a silicon-based semiconductor material such as polysilicon. The first semiconductor layer A1 may include a channel region and impurity regions disposed on both sides of the channel region. One of the impurity regions may correspond to a source region, and the other may correspond to a drain region.

[0130] The first gate insulating layer 103 may be disposed (e.g., in the z direction) between the first semiconductor layer A1 and the first gate electrode GE1. In one embodiment, the first gate insulating layer 103 may include an inorganic insulator such as silicon oxide, silicon nitride, or silicon oxynitride, and may include a single-layer or multi-layer structure including the above inorganic insulator.

[0131] In one embodiment, the first gate electrode GE1 may include a conductive material including Mo, Al, Cu, or TI, etc., and may include a single-layer or multi-layer structure including the above materials.

[0132] In one embodiment, the capacitor Cst may include (e.g., in the z direction) a first capacitor electrode CE1 and a second capacitor electrode CE2 overlapping each other. The second capacitor electrode CE2 may be disposed above the first capacitor electrode CE1. In one embodiment, the first capacitor electrode CE1 of the capacitor Cst may include the first gate electrode GE1. For example, the first gate electrode GE1 may include the first capacitor electrode CE1 of the capacitor Cst. For example, the first gate electrode GE1 and the first capacitor electrode CE1 of the capacitor Cst may be integrally formed.

[0133] The first interlayer insulating layer 105 may be disposed (e.g., in the z direction) between the first capacitor electrode CE1 and the second capacitor electrode CE2 of the capacitor Cst. In one embodiment, the first interlayer insulating layer 105 may include an inorganic insulator such as silicon oxide, silicon nitride, or silicon oxynitride, etc., and may include a single-layer or multi-layer structure including the above inorganic insulator.

[0134] In one embodiment, the second capacitor electrode CE2 of the capacitor Cst may include a low-resistance conductive material such as Mo, Al, Cu, and / or Ti, and may include a single-layer or multi-layer structure including the above materials.

[0135] The second interlayer insulating layer 107 may be disposed on the capacitor Cst. For example, the second interlayer insulating layer 107 may be directly disposed on the second capacitor electrode CE2 of the capacitor Cst. In one embodiment, the second interlayer insulating layer 107 may include an inorganic insulator, such as silicon oxide, silicon nitride, or silicon oxynitride, etc., and may include a single-layer or multi-layer structure including the above inorganic insulator.

[0136] The semiconductor layer A3 of the third thin film transistor T3 (hereinafter referred to as the third semiconductor layer) may be disposed on the second interlayer insulating layer 107 (e.g., directly disposed thereon in the z direction). In one embodiment, the third semiconductor layer A3 may include an oxide-based semiconductor material. For example, the third semiconductor layer A3 may include a zinc oxide-based material, such as zinc oxide, indium zinc oxide, or gallium indium zinc oxide, etc. In some embodiments, the third semiconductor layer A3 may include an indium gallium zinc oxide semiconductor (IGZO), an indium tin zinc oxide semiconductor (ITZO), or an indium gallium tin zinc oxide semiconductor (IGTZO) semiconductor, which includes metals such as indium (In), gallium (Ga), or tin (Sn) in addition to zinc oxide.

[0137] The third semiconductor layer A3 may include a channel region and impurity regions disposed on both sides of the channel region. Any one of the impurity regions may correspond to the source region, and the other may correspond to the drain region.

[0138] The third thin film transistor T3 may include (e.g., in the z direction) a gate electrode GE3 (hereinafter referred to as the third gate electrode) overlapping with the channel region of the third semiconductor layer A3. In one embodiment, the third gate electrode GE3 may have a double-gate structure, including (e.g., in the z direction) a lower gate electrode G3A disposed under the third semiconductor layer A3 and (e.g., in the z direction) an upper gate electrode G3B disposed on the third semiconductor layer A3.

[0139] In one embodiment, the lower gate electrode G3A and the second capacitor electrode CE2 of the capacitor Cst may be disposed on the same layer (e.g., the first interlayer insulating layer 105) (e.g., directly disposed thereon). In one embodiment, the lower gate electrode G3A may include the same material as the material of the second capacitor electrode CE2 of the capacitor Cst.

[0140] The upper gate electrode G3B may be disposed on the third semiconductor layer A3, with the second gate insulating layer 109 (e.g., in the z direction) therebetween. In one embodiment, the second gate insulating layer 109 may include an inorganic insulator, such as silicon oxide, silicon nitride, or silicon oxynitride, and may include a single-layer or multi-layer structure including the above inorganic insulator.

[0141] The third interlayer insulating layer 110 may be disposed on the upper gate electrode G3B (e.g., directly thereon). In one embodiment, the third interlayer insulating layer 110 may include an inorganic insulator such as silicon oxide, silicon nitride, or silicon oxynitride, and may include a single-layer or multi-layer structure including the above inorganic insulator.

[0142] Although Figure 7 the first thin film transistor T1 and the third thin film transistor T3 among the exemplified plurality of thin film transistors, and the first semiconductor layer A1 and the third semiconductor layer A3 are disposed on different layers from each other, the embodiments of the present disclosure are not necessarily limited thereto.

[0143] In one embodiment, reference has been made to Figure 5 the second thin film transistor T2, the fifth thin film transistor T5, the sixth thin film transistor T6, and the seventh thin film transistor T7 described (see Figure 5 ) may have the same structure as the first thin film transistor T1 described with reference to Figure 7 . For example, the second thin film transistor T2, the fifth thin film transistor T5, the sixth thin film transistor T6, and the seventh thin film transistor T7 (see Figure 5 ) may include a semiconductor layer disposed on the same layer as the first semiconductor layer A1 of the first thin film transistor T1 and a gate electrode disposed on the same layer as the first gate electrode GE1 of the first thin film transistor T1.

[0144] In one embodiment, the fourth thin film transistor T4 described with reference to Figure 5 may have the same structure as the third thin film transistor T3 described with reference to Figure . For example, the fourth thin film transistor T4 may include a semiconductor layer disposed on the same layer as the third semiconductor layer A3 of the third thin film transistor T3 and a gate electrode formed on the same layer as the third gate electrode GE3 of the third thin film transistor T3. In one embodiment, the semiconductor layer of the fourth thin film transistor T4 and the third semiconductor layer A3 of the third thin film transistor T3 may be integrally connected to each other.

[0145] The first thin film transistor T1 and the third thin film transistor T3 can be electrically connected to each other through the first connection electrode CM. In one embodiment, the first connection electrode CM can be disposed on the third interlayer insulating layer 110 (e.g., directly thereon). One side of the first connection electrode CM can directly contact the first gate electrode GE1 of the first thin film transistor T1, and the other side of the first connection electrode CM can directly contact the third semiconductor layer A3 of the third thin film transistor T3. For example, one side of the first connection electrode CM can pass through a contact hole penetrating the third interlayer insulating layer 110, the second gate insulating layer 109, the second interlayer insulating layer 107, and the first interlayer insulating layer 105 to directly contact the first gate electrode GE1. The other side of the first connection electrode CM can pass through a contact hole penetrating the third interlayer insulating layer 110 and the second gate insulating layer 109 to directly contact the third semiconductor layer A3.

[0146] In one embodiment, the first connection electrode CM can include Al, Cu, and / or Ti, and can include a single layer or multiple layers containing the above materials. For example, the first connection electrode CM can have a three-layer structure including Ti / Al / Ti.

[0147] The first planarization layer 111 can be disposed on the first connection electrode CM (e.g., directly thereon).

[0148] The data line DL and the second connection electrode CM' can be disposed on the first planarization layer 111 (e.g., directly thereon in the z direction) and covered by the second planarization layer 113. The second connection electrode CM' can be electrically connected to the first connection electrode CM through a contact hole penetrating the first planarization layer 111.

[0149] In one embodiment, each of the data line DL and the second connection electrode CM' can include Al, Cu, and / or Ti, and can include a single layer or multiple layers containing the above materials. For example, each of the data line DL and the second connection electrode CM' can have a three-layer structure including Ti / Al / Ti.

[0150] Although ​ illustrated that the data line DL is disposed on the first planarization layer 111 (e.g., directly thereon in the z direction) and is located on the same layer as the second connection electrode CM', embodiments of the present disclosure are not necessarily limited thereto. For example, in one embodiment, the data line DL and the first connection electrode CM can be disposed on the same layer as each other.

[0151] Light-emitting diodes, such as organic light-emitting diodes (OLEDs), may be disposed on the second planarization layer 113 (e.g., directly thereon in the z direction). The organic light-emitting diode (OLED) may be electrically connected to the second connection electrode CM' through a contact hole extending through the second planarization layer 113. The organic light-emitting diode (OLED) may be electrically connected to the sub-pixel circuit PC through the first connection electrode CM and the second connection electrode CM'.

[0152] In one embodiment, the sub-pixel electrode 210 of the organic light-emitting diode (OLED) may include a reflective film, and the reflective film includes silver (Ag), magnesium (Mg), Al, platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. However, the embodiments of the present disclosure are not necessarily limited thereto. For example, in one embodiment, the sub-pixel electrode 210 may further include (e.g., in the z direction) a conductive oxide layer above and / or below the above-mentioned reflective film. In one embodiment, the conductive oxide layer may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and / or aluminum zinc oxide (AZO). In one embodiment, the sub-pixel electrode 210 may include a three-layer structure including ITO / Ag / ITO.

[0153] The bank layer 115 may be disposed on the sub-pixel electrode 210 (e.g., directly thereon). The bank layer 115 may include an opening overlapping with the sub-pixel electrode 210 and cover the edge of the sub-pixel electrode 210. In one embodiment, the bank layer 115 may include an organic insulator.

[0154] The intermediate layer 220 of the organic light-emitting diode (OLED) includes an emission layer 222. The intermediate layer 220 may include a functional layer 220f. The functional layer 220f may include a first functional layer 221 disposed below the emission layer 222 and / or a second functional layer 223 disposed above the emission layer 222. In one embodiment, the emission layer 222 may include a high-molecular-weight or low-molecular-weight organic material that emits light of certain colors. The second functional layer 223 may include an electron transport layer (ETL) and / or an electron injection layer (EIL). The first functional layer 221 and the second functional layer 223 may include organic materials.

[0155] The counter electrode 230 of the organic light-emitting diode (OLED) may include a conductive material having a small work function. For example, in one embodiment, the counter electrode 230 may include a (semi) transparent layer containing Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, or an alloy thereof. Alternatively, the counter electrode 230 may further include a layer containing ITO, IZO, ZnO, or In2O3, etc. on the (semi) transparent layer containing the above materials.

[0156] The emission layer 222 may be formed in the display area DA to overlap with the sub-pixel electrode 210 (e.g., in the z direction) through the opening in the bank layer 115. Conversely, in one embodiment, the first functional layer 221, the second functional layer 223, and the counter electrode 230 may extend into the intermediate area MA as well as the display area DA.

[0157] The organic light-emitting diode OLED may be covered by the encapsulation layer 300. In one embodiment, the encapsulation layer 300 may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. In ​ One embodiment shown, the encapsulation layer 300 includes a first inorganic encapsulation layer 310, a second inorganic encapsulation layer 330, and an organic encapsulation layer 320 disposed therebetween (e.g., in the z direction). However, embodiments of the present disclosure are not necessarily limited thereto, and the encapsulation layer 300 may include at least one organic encapsulation layer and at least one inorganic encapsulation layer having various different arrangements.

[0158] In one embodiment, the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may each include one or more inorganic materials such as alumina, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may each include a single layer or multiple layers containing the above materials. In one embodiment, the organic encapsulation layer 320 may include a polymer-based material. The polymer-based material may include acrylic resin, epoxy resin, polyimide, or polyethylene, etc. In one embodiment, the organic encapsulation layer 320 may include acrylate.

[0159] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may have different thicknesses from each other (e.g., the length in the z direction). In one embodiment, the thickness of the first inorganic encapsulation layer 310 may be greater than the thickness of the second inorganic encapsulation layer 330. Alternatively, the thickness of the second inorganic encapsulation layer 330 may be greater than the thickness of the first inorganic encapsulation layer 310, or the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may have the same thickness as each other.

[0160] Referring to ​ the intermediate area MA shown, the partition wall PW and the spacer SP may be arranged to be spaced apart from each other between the display area DA and the opening area OA. In one embodiment, the encapsulation layer 300 may extend into the intermediate area MA and cover the partition wall PW and the spacer SP.

[0161] In one embodiment, the partition wall PW may include a first partition wall PW1 and a second partition wall PW2. The first partition wall PW1 may be disposed between the display area DA and the opening area OA, and the second partition wall PW2 may be disposed between the first partition wall PW1 and the opening area OA. In a plan view, the first partition wall PW1 and the second partition wall PW2 may be disposed along the outer periphery of the opening area OA. Although ​ it is illustrated that two partition walls PW are provided in the middle area MA, embodiments of the present disclosure are not necessarily limited thereto. In some embodiments, one, three, or more than four partition walls PW may be provided in the middle area MA.

[0162] In one embodiment, the first partition wall PW1 and the second partition wall PW2 may be provided on the top surface of the inorganic insulating layer IIL. For example, the first partition wall PW1 and the second partition wall PW2 may be provided on the top surface of the third interlayer insulating layer 110 (e.g., directly provided thereon in the z direction).

[0163] In one embodiment, the first partition wall PW1 may include a part 111P1 of the first planarization layer 111, a part 113P1 of the second planarization layer 113, and a part 115P1 of the dam layer 115. The second partition wall PW2 may include a part 111P2 of the first planarization layer 111, a part 113P2 of the second planarization layer 113, and a part 115P2 of the dam layer 115. However, embodiments of the present disclosure are not necessarily limited thereto, and in some embodiments, the first partition wall PW1 and the second partition wall PW2 may further include parts of other layers, or some of the above layers may be omitted.

[0164] The spacer SP may be provided on the top surface of the inorganic insulating layer IIL. For example, on the top surface of the third interlayer insulating layer 110, the spacers SP may be arranged to be spaced apart from each other in a direction parallel to the top surface of the substrate 100. In one embodiment, the adjacent spacers SP may be arranged at a certain interval IV. The interval IV between the adjacent spacers SP may indicate a region in which the organic pattern layer 1110 included in each spacer SP is not arranged.

[0165] ​ The embodiment shown includes five spacers SP arranged in the middle area MA. For example, two spacers SP may be arranged between the display area DA and the first partition wall PW1, two spacers SP may be arranged between the first partition wall PW1 and the second partition wall PW2, and one spacer SP may be arranged between the second partition wall PW2 and the opening area OA. However, embodiments of the present disclosure are not limited thereto. For example, in some embodiments, one to four, or more than six spacers SP may be arranged in the middle area MA.

[0166] Reference ​ and​ , the spacer SP may have a stacked structure including an organic pattern layer 1110 and at least one metal layer. For example, in one embodiment, the spacer SP may have a stacked structure including an organic pattern layer 1110 and a metal pattern layer ML. The metal pattern layer ML may be arranged to overlap the organic pattern layer 1110. For example, the metal pattern layer ML may cover the organic pattern layer 1110. The spacer SP may include a groove G. The spacer SP may include at least one end TP. For example, in one embodiment, the spacer SP may include (e.g., in a cross-sectional view) two end TPs on both sides (e.g., lateral sides) of the groove G. The end TP may overlap the groove G (e.g., in the z direction).

[0167] The organic pattern layer 1110 may be disposed on the inorganic insulating layer IIL. For example, the organic pattern layer 1110 may be disposed on the third interlayer insulating layer 110 (e.g., directly thereon in the z direction). In one embodiment, the organic pattern layer 1110 may be disposed on the same layer as the first planarization layer 111 and may include the same material as the material of the first planarization layer 111. In one embodiment, the organic pattern layer 1110 and the first planarization layer 111 may be formed in the same process.

[0168] The groove G may be provided in the organic pattern layer 1110. The groove G may have a shape defined by removing a part of the organic pattern layer 1110 in the thickness direction. Although ​ and ​ illustrate that the groove G is defined by the inner surface 1110is of the organic pattern layer 1110, but the embodiments of the present disclosure are not necessarily limited thereto. For example, in some embodiments, a lower metal layer overlapping the organic pattern layer 1110 may be disposed (e.g., in the z direction) between the organic pattern layer 1110 and the inorganic insulating layer IIL. The groove G may expose at least a part of the top surface of the lower metal layer. The groove G may be defined by the inner surface 1110is of the organic pattern layer 1110 and the top surface of the lower metal layer.

[0169] The organic pattern layer 1110 may include (e.g., in the z direction) a first part 1110a overlapping the groove G and a second part 1110b extending outside the first part 1110a. In one embodiment, the second part 1110b of the organic pattern layer 1110 may not overlap the groove G (e.g., in the z direction). The second part 1110b may include an edge part (e.g., a lateral edge part) of the organic pattern layer 1110. In one embodiment, the top surface 1110t corresponding to the second part 1110b of the organic pattern layer 1110 may include a bevel. In one embodiment, the top surface 1110t of the organic pattern layer 1110 is inclined in the direction toward the top surface 100t of the substrate 100. Although ​ and ​The top surface 1110t corresponding to the second portion 1110b of the organic pattern layer 1110 is illustrated as having an angled slope, but the embodiments of the present disclosure are not necessarily limited thereto. For example, in some embodiments, the top surface 1110t corresponding to the second portion 1110b of the organic pattern layer 1110 may include slopes having different angles. In one embodiment, the angle of the slope may decrease from the edge of the organic pattern layer 1110 toward the center of the organic pattern layer 1110. For example, the top surface 1110t corresponding to the second portion 1110b of the organic pattern layer 1110 may have a shape that is concave in a direction toward the top surface 100t of the substrate 100. In this specification, the angle of the slope refers to the angle between the slope and the top surface 100t of the substrate 100. In one embodiment, in a cross-section, the top surface 1110t of the organic pattern layer 1110 may include a first point P1 having a maximum vertical distance (e.g., in the z-direction) from the top surface 110t of the substrate 100 compared to all other surfaces of the organic pattern layer 1110. For example, the top surface 1110t corresponding to the second portion 1110b of the organic pattern layer 1110 may include the first point P1, which is the portion of the organic pattern layer 1110 having the maximum vertical distance from the top surface 100t of the substrate 100.

[0170] In one embodiment, the metal pattern layer ML may include the same material as that of the data line DL and / or the second link electrode CM'. In one embodiment, the metal pattern layer ML and the data line DL and / or the second link electrode CM' may be formed in the same process. In one embodiment, as will be described later ​ 、 ​ and ​ As illustrated in FIG, the metal pattern layer ML may have a multilayer structure including a first sublayer ML1, a second sublayer ML2, and a third sublayer ML3. In one embodiment, the first sublayer ML1 and the third sublayer ML3 may include the same material, and the first sublayer ML1 and the second sublayer ML2 may include different materials. For example, in one embodiment, the first sublayer ML1 and the third sublayer ML3 may include Ti, and the second sublayer ML2 may include Al.

[0171] The metal pattern layer ML may be disposed on the top surface 1110t of the organic pattern layer 1110 (e.g., directly thereon). The metal pattern layer ML may at least partially cover the top surface 1110t and the outer surface 1110es (e.g., the external surface) of the organic pattern layer 1110. The metal pattern layer ML may extend to regions where the organic pattern layer 1110 is not disposed. In one embodiment, the metal pattern layer ML may directly contact the top surface of the inorganic insulating layer IIL at a level below the organic pattern layer 1110 in regions where the organic pattern layer 1110 is not disposed, such as the interval IV between adjacent spacers SP. The metal pattern layer ML and the inorganic insulating layer IIL (e.g., the third interlayer insulating layer 110) that are in direct contact with each other may form an inorganic contact region ICR. In one embodiment, the interval IV between adjacent spacers SP may include the inorganic contact region ICR. By including the inorganic contact region ICR, the intermediate region MA may prevent moisture, etc. from traveling through the organic pattern layer 1110 toward the display region DA.

[0172] The metal pattern layer ML may include a terminal TP. In one embodiment, the terminal TP of the metal pattern layer ML may include a portion extending toward the center of the groove G. The terminal TP may include a portion extending from a second point P2 where the inner surface 1110is of the organic pattern layer 1110 intersects the bottom surface MLb of the metal pattern layer ML toward the center of the groove G. The terminal TP may include a portion that is a component of the metal pattern layer ML and does not directly contact the organic pattern layer 1110.

[0173] Reference ​ and ​ , a virtual line (e.g., an imaginary line) passing through the first point P1 of the organic pattern layer 1110 and the edge TPe of the terminal TP of the metal pattern layer ML may be inclined in the direction toward the top surface 100t of the substrate 100 (e.g., the -z direction). In one embodiment, the angle θ1 formed by the virtual line passing through the first point P1 of the organic pattern layer 1110 and the edge TPe of the terminal TP of the metal pattern layer ML and the top surface 100t of the substrate 100 may be greater than 0° but less than 90°. The vertical height of the first point P1 may be greater than the vertical height of the edge TPe of the terminal TP of the metal pattern layer ML. With respect to the virtual line, the edge TPe of the terminal TP may refer to the point of the terminal TP closest to the center of the groove G.

[0174] In one embodiment, the end TP of the metal pattern layer ML may not extend parallel to the top surface 100t of the substrate 100. For example, the entire lower surface of the end TP of the metal pattern layer ML may be inclined in a direction (e.g., -z direction) toward the top surface 100t of the substrate 100. The end TP of the metal pattern layer ML may be inclined in a direction (e.g., -z direction) toward the top surface 100t of the substrate 100 along the inclined surface of the top surface 1110t of the organic pattern layer 1110 on which the metal pattern layer ML is disposed.

[0175] The first dummy stack DS1, including a first covering portion CV1 such as a covering layer CVL described later, a functional layer 220f, and a counter electrode 230, which are disposed on the metal pattern layer ML, may have the same inclined surface structure as that of the inclined surface structure of the metal pattern layer ML.

[0176] As a comparative example, when a virtual line passing through a first point of the organic pattern layer and the edge of the end of the metal pattern layer is inclined in a direction (e.g., z direction) away from the top surface of the substrate or parallel to the top surface of the substrate, an organic material layer (such as a functional layer) formed on the end may be deposited on the bottom surface of the end (e.g., the bottom surface of the metal pattern layer), and may not be blocked or separated by the end. In this comparative embodiment, moisture or the like introduced into the opening of the display device may move toward the display area DA through the functional layer.

[0177] However, according to one embodiment, a virtual line passing through the first point P1 of the organic pattern layer 1110 and the edge TPe of the end TP of the metal pattern layer ML may be inclined in a direction (e.g., -z direction) toward the top surface 100t of the substrate 100. Therefore, the functional layer 220f formed on the end TP may not be deposited on the bottom surface of the end TP (e.g., the bottom surface MLb of the metal pattern layer ML), and may be blocked and separated by the end TP. Therefore, a moisture penetration path may be prevented from being formed through the functional layer 220f. Therefore, the reliability of the display device 10 may be increased.

[0178] In one embodiment, the spacer SP may have a stacked structure including the organic pattern layer 1110, the metal pattern layer ML, and the covering layer CVL. In one embodiment, a part of the covering layer CVL may be blocked at the side surface MLs of the metal pattern layer ML. The covering layer CVL may include a first covering portion CV1 (e.g., and directly disposed thereon) covering the top surface MLt and the side surface MLs of the metal pattern layer ML and a second covering portion CV2 disposed in the groove G. The first covering portion CV1 and the second covering portion CV2 may be spaced apart from each other and may not be in direct contact (e.g., isolated from each other).

[0179] The second covering portion CV2 may directly contact at least a part of the inner surface 1110is of the organic pattern layer 1110 that defines the groove G. The second covering portion CV2 may expose at least a part of the organic pattern layer 1110. In one embodiment, the second covering portion CV2 may expose a region of the inner surface 1110is of the organic pattern layer 1110 that defines the groove G and that is adjacent to the metal pattern layer ML.

[0180] Similarly, the functional layer 220f and the counter electrode 230, which will be described later, may also have a shape that is partially blocked at the side surface MLs of the metal pattern layer ML. In this embodiment, it is possible to more effectively prevent impurities such as moisture from being introduced toward the display area DA through the functional layer 220f.

[0181] In one embodiment, the covering layer CVL may include a metal material. The covering layer CVL may include, for example, the same material as that of the sub-pixel electrode 210. In one embodiment, the covering layer CVL and the sub-pixel electrode 210 may be formed in the same process. In one embodiment, the covering layer CVL may have a three-layer structure including ITO / Ag / ITO.

[0182] In the intermediate layer 220 of the display area DA, the functional layer 220f and the counter electrode 230 may extend to the intermediate area MA. The functional layer 220f may include an organic material and thus may be a travel path for moisture. When external moisture is introduced through the opening 10OP of the display device 10 and reaches the organic light-emitting diode OLED, the organic light-emitting diode OLED may be damaged. However, as ​ and ​ shown, in the intermediate area MA, the functional layer 220f and the counter electrode 230 may be discontinuously arranged due to the spacer SP.

[0183] When depositing the functional layer 220f (such as the first functional layer 221 and / or the second functional layer 223), the materials included in the first functional layer 221 and / or the second functional layer 223 may be deposited discontinuously by the groove G of the spacer SP. As ​ and ​ shown, the functional layer 220f may include a first portion disposed on the top surface of the spacer SP and a second portion in the groove G of the spacer SP, and the first portion and the second portion may be isolated and separated from each other. Therefore, the spacer SP may prevent moisture and the like introduced through the opening 10OP from traveling toward the display area DA through the functional layer 220f including an organic material.

[0184] Similar to the functional layer 220f, the counter electrode 230 of the organic light-emitting diode OLED may also include portions that are discontinuously arranged in the intermediate region MA. For example, a first portion of the counter electrode 230 disposed on the top surface of the spacer SP and a second portion of the counter electrode 230 in the groove G may be blocked and separated from each other.

[0185] For example, a stack including the functional layer 220f and the counter electrode 230 disposed on the top surface of the spacer SP (hereinafter referred to as the first dummy stack DS1) may be separated from a stack including the functional layer 220f and the counter electrode 230 in the groove G (hereinafter referred to as the second dummy stack DS2). In one embodiment, the first dummy stack DS1 may be disposed on a first covering portion CV1 of the covering layer CVL (e.g., directly thereon). The second dummy stack DS2 may be disposed on a second covering portion CV2 of the covering layer CVL (e.g., directly thereon).

[0186] The functional layer 220f and the counter electrode 230 separated by the spacer SP may be covered by an inorganic encapsulation layer. For example, as ​ shown, the first inorganic encapsulation layer 310 may cover the functional layer 220f and the counter electrode 230 separated by the groove G of the spacer SP. The first inorganic encapsulation layer 310 has relatively excellent step coverage and may thus be continuous in the intermediate region MA.

[0187] The organic encapsulation layer 320 may cover at least a portion of the intermediate region MA. The organic encapsulation layer 320 may cover some of the spacers SP. In one embodiment, the organic encapsulation layer 320 may cover, for example, the spacers SP disposed between the display region DA and the first partition wall PW1 and the spacers SP between the first partition wall PW1 and the second partition wall PW2. The second inorganic encapsulation layer 330 may generally cover the intermediate region MA on the organic encapsulation layer 320.

[0188] When forming the organic encapsulation layer 320, the flow of the monomer may be controlled by the partition walls PW and / or the spacers SP. In one embodiment, the organic encapsulation layer 320 in the intermediate region MA may be discontinuous due to the partition walls PW. For example, one portion of the organic encapsulation layer 320 may cover the region from the display region DA to the first partition wall PW1, and another portion of the organic encapsulation layer 320 may cover the region between the first partition wall PW1 and the second partition wall PW2. At the first partition wall PW1 and the second partition wall PW2 where the organic encapsulation layer 320 terminates, a portion of the second inorganic encapsulation layer 330 may directly contact a portion of the first inorganic encapsulation layer 310.

[0189] Referring to the opening area OA, the display device 10 may include an opening 10OP. In one embodiment, the opening 10OP of the display device 10 may include an opening of an element included in the display device 10. For example, the opening 10OP of the display device 10 may include an opening 100OP of the substrate 100, an opening 310OP of the first inorganic encapsulation layer 310, and an opening 330OP of the second inorganic encapsulation layer 330, etc.

[0190] In one embodiment, the openings of the elements included in the display device 10 may be formed simultaneously. Accordingly, the inner surface 100IS of the substrate 100 that defines the opening 100OP of the substrate 100 and the inner surfaces 310IS and 330IS of the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 that respectively define the opening 310OP of the first inorganic encapsulation layer 310 and the opening 330OP of the second inorganic encapsulation layer 330 may be on the same vertical line with each other.

[0191] ​ and ​ is a cross-sectional view of a part of the display device 10 according to an embodiment of the present disclosure. ​ and ​ Illustrates an embodiment that modifies the embodiment shown in ​ and ​ and ​ The embodiment in ​ is different from the embodiment in

[0192] In cross-section, the top surface 1110t of the organic pattern layer 1110 may include a first point P1 that has the maximum vertical distance from the top surface 100t of the substrate 100. A virtual line passing through the first point P1 of the organic pattern layer 1110 and the edge TPe of the end TP of the metal pattern layer ML may be inclined in the direction (e.g., -z direction) toward the top surface 100t of the substrate 100. In one embodiment, the angle θ1 formed by the virtual line passing through the first point P1 of the organic pattern layer 1ll0 and the edge TPe of the end TP of the metal pattern layer ML and the top surface 100t of the substrate 100 may be greater than 0° and less than 90°.

[0193] Referring to ​ at least a part of the end TP of the metal pattern layer ML may extend parallel to the top surface 100t of the substrate 100 and may not be inclined. In one embodiment, as shown in ​As illustrated, the entire end TP of the metal pattern layer ML may extend substantially parallel to the top surface 100t of the substrate 100. However, embodiments of the present disclosure are not necessarily limited thereto. For example, in one embodiment, only a part of the end TP of the metal pattern layer ML may be inclined in the direction (e.g., -z direction) toward the top surface 100t of the substrate 100. For example, in the end TP of the metal pattern layer ML, the portion adjacent to the second point P2 may be inclined in the direction (e.g., -z direction) toward the top surface 100t of the substrate 100, and the remaining portion of the end TP may extend parallel to the top surface 100t of the substrate 100. In one embodiment, the end TP of the metal pattern layer ML may have an inclined surface having an angle decreasing from the portion adjacent to the second point P2 toward the edge TPe. The edge TPe of the end TP of the metal pattern layer ML may extend parallel to the top surface 100t of the substrate 100. In this specification, the angle of the inclined surface of the end TP indicates the angle formed by the end TP and the top surface 100t of the substrate 100.

[0194] Reference ​ , at least a part of the end TP of the metal pattern layer ML may be inclined in the direction (e.g., z direction) away from the top surface 100t of the substrate 100. In one embodiment, as ​ illustrated, the edge TPe of the end TP of the metal pattern layer ML may be inclined in the direction (e.g., z direction) away from the top surface 100t of the substrate 100. In one embodiment, at least a part of the end TP of the metal pattern layer ML may extend parallel to the top surface 100t of the substrate 100. For example, in the end TP of the metal pattern layer ML, the portion adjacent to the second point P2 may extend parallel to the top surface 100t of the substrate 100. The angle of the inclined surface of the end TP of the metal pattern layer ML may increase from the portion adjacent to the second point P2 toward the edge TPe. However, embodiments of the present disclosure are not necessarily limited thereto. For example, in one embodiment, the end TP of the metal pattern layer ML may be inclined in the direction (e.g., -z direction) toward the top surface 100t of the substrate 100, and the portion adjacent to the second point P2 may be inclined in the direction (e.g., z direction) away from the top surface 100t of the substrate 100.

[0195] ​ , ​ and ​ are cross-sectional views each illustrating a part of the display device 10 according to an embodiment of the present disclosure. ​ , ​ and ​ illustrate ​ , ​ and ​Embodiments modified from the embodiments shown. Hereinafter, the differences will be mainly described, and for simplicity of description, repeated descriptions of similar or identical elements may be omitted.

[0196] The metal pattern layer ML may include a terminal TP. Refer to ​ The structure of the terminal TP of the metal pattern layer ML described can be applied to ​ . For example, in one embodiment, ​ and ​ The terminal TP of the metal pattern layer ML illustrated in may have the same inclined surface structure as the inclined surface of the terminal TP of the metal pattern layer ML illustrated in ​ . ​ The terminal TP of the metal pattern layer ML illustrated in may extend parallel to the top surface 100t of the substrate 100, having the same structure as the terminal TP of the metal pattern layer ML illustrated in ​ .

[0197] Refer to ​ , the metal pattern layer ML may be provided as a plurality of sub-layers. For example, in one embodiment, the metal pattern layer ML may have a multi-layer structure including a first sub-layer ML1, a second sub-layer ML2, and a third sub-layer ML3 (e.g., continuously stacked). Regarding a virtual line passing through the first point P1 of the organic pattern layer 1110 (see ​ ) and the edge TPe of the terminal TP of the metal pattern layer ML (see ​ ), the edge TPe of the terminal TP may refer to the point of the first sub-layer ML1 of the terminal TP closest to the center of the groove G.

[0198] A cover layer CVL may be disposed on the metal pattern layer ML (e.g., directly thereon). The cover layer CVL may include a first cover portion CV1 and a second cover portion CV2 that are spaced apart from each other and isolated from each other. In an embodiment where the metal pattern layer ML is provided as a plurality of sub-layers, the first cover portion CV1 may cover the side surfaces of each of the plurality of sub-layers. Refer to ​ , ​ and ​ , the metal pattern layer ML includes the first sub-layer ML1 to the third sub-layer ML3, and thus, the side surface MLs of the metal pattern layer ML may indicate the side surface ML1s of the first sub-layer ML1, the side surface ML2s of the second sub-layer ML2, and the side surface ML3s of the third sub-layer ML3. The first cover portion CV1 may extend from the top surface MLt of the metal pattern layer ML to the side surface ML3s of the third sub-layer ML3, the side surface ML2s of the second sub-layer ML2, and the side surface ML1s of the first sub-layer ML1. Refer to ​ and ​, in one embodiment, the first sub-layer ML1 and the third sub-layer ML3 may extend further towards the center of the groove G than the second sub-layer ML2. For example, the third sub-layer ML3 may extend towards the center of the groove G from the point where the side surface ML2s of the second sub-layer ML2 intersects the bottom surface of the third sub-layer ML3. However, the embodiments of the present disclosure are not necessarily limited thereto. For example, as ​ illustrated, in one embodiment, the first sub-layer ML1 and the third sub-layer ML3 may not extend further towards the center of the groove G than the second sub-layer ML2. For example, the first sub-layer ML1 and the third sub-layer ML3 may not protrude relative to the second sub-layer ML2. In this embodiment, the side surface ML1s of the first sub-layer ML1 and the side surface ML3s of the third sub-layer ML3 may be on substantially the same line as the side surface ML2s of the second sub-layer ML2.

[0199] In one embodiment, the first covering portion CV1 may be partially blocked on the side surface MLs of the metal pattern layer ML. In one embodiment, as ​ illustrated, since the third sub-layer ML3 extends further towards the center of the groove G than the second sub-layer ML2, the first covering portion CV1 may not be deposited on the bottom surface of the third sub-layer ML3. However, the embodiments of the present disclosure are not necessarily limited thereto. For example, in some embodiments, as ​ illustrated, the first covering portion CV1 may be deposited on the bottom surface of the third sub-layer ML3 (e.g., directly disposed thereon). In this embodiment, the first covering portion CV1 may not be deposited on a part of the side surface ML2s of the second sub-layer ML2 (e.g., directly disposed thereon).

[0200] The functional layer 220f and the counter electrode 230 may be sequentially disposed on the covering layer CVL. Additionally, the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may be sequentially disposed on the counter electrode 230. In some embodiments, as ​ illustrated, a cavity CT where the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 are not arranged may be formed on the lower portion of the end TP of the metal pattern layer ML.

[0201] However, according to one embodiment, a virtual line passing through the first point P1 of the organic pattern layer 1110 (see ​ ) and the edge TPe of the end TP of the metal pattern layer ML (see ​ ) may be inclined in the direction towards the top surface 100t of the substrate 100 (e.g., -z direction). Therefore, the functional layer 220f formed on the end TP may be completely blocked and separated by the end TP without being deposited on the bottom surface of the end TP (e.g., the bottom surface MLb of the metal pattern layer ML). Thus, even when the cavity CT is formed in the lower portion of the end TP, the risk of moisture penetration such as water can be reduced.

[0202] ​ A cross-sectional view schematically illustrating a method of manufacturing a spacer SP included in a display device 10 according to an embodiment of the present disclosure. ​ and ​ The spacer SP illustrated in ​ may be formed through the process illustrated in

[0203] Referring to ​ and ​ , an inorganic insulating layer IIL may be formed on a substrate 100 (e.g., directly thereon). A preliminary organic pattern layer 1110' may be formed on the inorganic insulating layer IIL (e.g., directly thereon).

[0204] In one embodiment, the preliminary organic pattern layer 1110' may include the same material as that of the first planarization layer 111 in the display area DA. In one embodiment, the preliminary organic pattern layer 1110' may include, for example, a positive photoresist. Although an example in which the preliminary organic pattern layer 1110' includes a positive photoresist is described with reference to ​ and ​ , in some embodiments, the preliminary organic pattern layer 1110' may also include a negative photoresist.

[0205] A first mask MS1 may be placed on the preliminary organic pattern layer 1110' (e.g., directly disposed thereon). In one embodiment, the first mask MS1 may include a phase shift mask (PSM). The first mask MS1 may include a first portion AR1 and a second portion AR2. A phase shift pattern RP may be disposed under the first portion AR1 and may not be disposed under the second portion AR2. The phase shift pattern RP may be configured to change the wavelength of transmitted light. Accordingly, the phase shift pattern RP of the first mask MS1 may be configured to change the wavelength of light transmitted through the first portion AR1.

[0206] In one embodiment, the first mask MS1 may include a rim-type phase shift mask (Rim PSM). The phase shift pattern RP may include a rim-type pattern.

[0207] The preliminary organic pattern layer 1110' may be exposed through the first mask MS1 with different exposure amounts according to each portion. The first portion AR1 and the second portion AR2 of the first mask MS1 may include transmissive portions. The transmittance of a portion where the first portion AR1 of the first mask MS1 and the phase shift pattern RP overlap each other may be less than the transmittance of the second portion AR2.

[0208] In one embodiment, the preliminary organic pattern layer 1110' may then be patterned through a developing process to form an organic pattern layer 1110. The organic pattern layer 1110 and the first planarization layer 111 in the display area DA may be formed simultaneously in the same process.

[0209] The organic pattern layer 1110 may correspond to a portion exposed by overlapping portions of the first partial AR1 and the phase shift pattern RP with each other. A portion of the preliminary organic pattern layer 1110' exposed by the second partial AR2 of the first mask MS1 may be removed in the developing process.

[0210] Depending on the characteristics of the phase shift pattern RP, the organic pattern layer 1110 formed by the first mask MS1 may include a central portion 1110P1 and an edge portion 1110P2, as ​ shown. The average thickness (e.g., the length in the z direction) of the central portion 1110P1 of the organic pattern layer 1110 may be less than the average thickness (e.g., the length in the z direction) of the edge portion 1110P2 of the organic pattern layer 1110. For example, the vertical distance h1 (e.g., the length in the z direction) from the top surface 100t of the substrate 100 to the top surface 1110t1 of the central portion 1110P1 of the organic pattern layer 1110 may be less than the vertical distance h2 (e.g., the length in the z direction) from the top surface 100t of the substrate 100 to the top surface 1110t2 of the edge portion 1110P2 of the organic pattern layer 1110. In one embodiment, the vertical distance h2 from the top surface 100t of the substrate 100 to the top surface 1100t2 of the edge portion 1110P2 of the organic pattern layer 1110 may decrease as the distance to the central portion 1110P1 of the organic pattern layer 1110 decreases.

[0211] The top surface 1110t2 of the edge portion 1110P2 of the organic pattern layer 1110 may include a first point P1 having the maximum vertical distance from the top surface 100t of the substrate 100.

[0212] In a cross section, the top surface 1110t2 of the edge portion 1110P2 of the organic pattern layer 1110 may be inclined in a direction (e.g., the -z direction) toward the top surface 100t of the substrate 100. Although ​The top surface 1110t2 of the edge portion 1110P2 of the exemplary organic pattern layer 1110 has a bevel with a constant angle, but embodiments of the present disclosure are not necessarily limited thereto. For example, in one embodiment, the top surface 1110t2 of the edge portion 1110P2 of the organic pattern layer 1110 may include bevels having different angles respectively. The angle of the bevel may decrease toward the central portion 1110P1 of the organic pattern layer 1110. For example, the top surface 1110t2 of the edge portion 1110P2 of the organic pattern layer 1110 may have a shape that is recessed toward the top surface 100t of the substrate 100. In one embodiment, the end portion 1110e of the edge portion 1110P2 of the organic pattern layer 1110 corresponding to the first point P1 may be inclined in a direction away from the top surface 100t of the substrate 100 (e.g., the z direction or the upward direction).

[0213] Reference ​ and ​ , a preliminary metal pattern layer ML' may be formed on the organic pattern layer 1110 (e.g., directly formed thereon). The preliminary metal pattern layer ML' may be directly formed on the top surface 1110t of the organic pattern layer 1110. A photoresist pattern PR may be formed on the preliminary metal pattern layer ML' (e.g., directly formed thereon). In one embodiment, the photoresist pattern PR may be formed on a mask through an exposure and development process.

[0214] Reference ​ , a metal pattern layer ML may be formed by patterning the preliminary metal pattern layer ML'. In one embodiment, the metal pattern layer ML and the data lines DL and / or the second connection electrodes CM' in the display area DA may be formed simultaneously in the same process. The etching process for patterning the preliminary metal pattern layer ML' may be performed by, for example, dry etching, wet etching, or a combination thereof.

[0215] The metal pattern layer ML may include an opening OP to expose at least a part of the central portion 1110P1 of the organic pattern layer 1110. The opening OP may expose at least a part of the top surface 1110t1 of the central portion 1110P1 of the organic pattern layer 1110.

[0216] The end portion of the metal pattern layer ML may be disposed on the top surface 1110t2 of the edge portion 1110P2 of the organic pattern layer 1110. For example, the end portion of the metal pattern layer ML may be inclined in a direction toward the top surface 100t of the substrate 100 (e.g., the -z direction).

[0217] Reference ​, a groove G can be formed by removing a part of the organic pattern layer 1110 using the metal pattern layer ML as a mask. In one embodiment, the etching process for removing a part of the organic pattern layer 1110 can be performed, for example, as a dry etching process (e.g., ashing process). For example, in the etching process, at least a central part 1110P1 and an edge part 1110P2 of the organic pattern layer 1110 can be removed. In the etching process, a terminal TP provided at an end part of the metal pattern layer ML can be formed. A virtual line passing through a first point P1 of the organic pattern layer 1110 and the edge TPe of the terminal TP of the metal pattern layer ML can be inclined in a direction (e.g., -z direction) toward the top surface 100t of the substrate 100. In one embodiment, the terminal TP of the metal pattern layer ML can be inclined in a direction (e.g., -z direction) toward the top surface 100t of the substrate 100.

[0218] Reference ​ , a cover layer CVL can be formed on the metal pattern layer ML (e.g., directly formed thereon). The cover layer CVL can form a first cover part CV1 covering the top surface and side surfaces of the metal pattern layer ML and a second cover part CV2 in the groove G. In one embodiment, the cover layer CVL and the sub-pixel electrodes 210 in the display area DA can be formed simultaneously in the same process.

[0219] In one embodiment, the organic pattern layer 1110, the metal pattern layer ML, and the cover layer CVL included in the spacers SP arranged in the intermediate area MA and the structures in the display area DA can be formed in the same process, and thus, the process of manufacturing the display device 10 can be simplified.

[0220] ​ A cross-sectional view briefly illustrating a manufacturing method of a spacer SP included in a display device according to an embodiment, which illustrates an embodiment modified from the ​ embodiment. ​ The spacer SP illustrated in ​ can be formed by the process illustrated in

[0221] ​ The process illustrated in ​ can be applied to this embodiment. In one embodiment, in the process of patterning the organic pattern layer 1110 using the first mask MS1 illustrated in ​ , the organic pattern layer 1110 illustrated in

[0222] Reference ​, according to the characteristics of the phase shift pattern RP, the organic pattern layer 1110 formed through the first mask MS1 may include a central portion 1110P1 and an edge portion 1110P2. Different from the embodiment in ​ , in the embodiment in ​ , the central portion 1110P1 of the organic pattern layer 1110 may include a first central portion 1110P1-1 adjacent to the edge portion 1110P2 and a second central portion 1110P1-2 inside the first central portion 1110P1-1. In one embodiment, the average thickness (e.g., the length in the z direction) of the second central portion 1110P1-2 of the organic pattern layer 1110 may be greater than the average thickness (e.g., the length in the z direction) of the first central portion 1110P1-1 of the organic pattern layer 1110. Additionally, the average thickness of the second central portion 1110P1-2 of the organic pattern layer 1110 may be less than the average thickness of the edge portion 1110P2 of the organic pattern layer 1110. ​ The embodiment shown in ​ and the embodiment shown in ​ may be formed through the first mask MS1 including the phase shift pattern RP (see ​ ), and the embodiment shown in ​ may be formed in a shape with a part of the central portion 1110P1 protruding during the curing process after patterning.

[0223] For example, the vertical distance h2' from the top surface 100t of the substrate 100 to the top surface 1110t1-2 of the second central portion 1110P1-2 of the organic pattern layer 1110 may be greater than or equal to the vertical distance h1' from the top surface 100t of the substrate 100 to the top surface 1110t1-1 of the first central portion 1110P1-1 of the organic pattern layer 1110. In one embodiment, the vertical distance h2' from the top surface 100t of the substrate 100 to the top surface 1110t1-2 of the second central portion 1110P1-2 may decrease towards the first central portion 1110P1-1 of the organic pattern layer 1110. Additionally, the vertical distance h1' from the top surface 100t of the substrate 100 to the top surface 1110t1-1 of the first central portion 1110P1-1 of the organic pattern layer 1110 may be less than or equal to the vertical distance h3' from the top surface 100t of the substrate 100 to the top surface 1110t2 of the edge portion 1110P2 of the organic pattern layer 1110. In one embodiment, the vertical distance h3' from the top surface 100t of the substrate 100 to the top surface 1110t2 of the edge portion 1110P2 of the organic pattern layer 1110 may decrease towards the first central portion 1110P1 of the organic pattern layer 1110.

[0224] The top surface 1110t2 of the edge portion 1110P2 of the organic pattern layer 1110 may include a first point P1, which is the portion of the organic pattern layer 1110 having the maximum vertical distance from the top surface 100t of the substrate 100.

[0225] In a cross-section, the top surface 1110t2 of the edge portion 1110P2 of the organic pattern layer 1110 may be inclined in a direction (e.g., -z direction) toward the top surface 100t of the substrate 100. Although ​ the top surface 1110t2 of the edge portion 1110P2 of the organic pattern layer 1110 is illustrated as including a descending slope with a constant angle, in some embodiments, the top surface 1110t2 of the edge portion 1110P2 of the organic pattern layer 1110 may include inclined surfaces having different angles respectively. For example, in some embodiments, the top surface 1110t2 of the edge portion 1110P2 of the organic pattern layer 1110 may have a shape inclined in a direction away from the top surface 100t of the substrate 100. In one embodiment, the end portion 1110e of the edge portion 1110P2 of the organic pattern layer 1110 corresponding to the first point P1 may have a shape inclined in a direction away from the top surface 100t of the substrate 100 (e.g., z direction).

[0226] At least a portion of the top surface 1110t1-1 of the first central portion 1110P1-1 of the organic pattern layer 1110 may extend parallel to the top surface 100t of the substrate 100. For example, as ​ illustrated, the top surface 1110t1-1 of the first central portion 1110P1-1 of the organic pattern layer 1110 may extend substantially parallel to the top surface 100t of the substrate 100.

[0227] In one embodiment, the top surface 1110t1-2 of the second central portion 1110P1-2 of the organic pattern layer 1110 may be inclined in a direction away from the top surface 100t of the substrate 100 (e.g., the z direction). The top surface 1110t1-2 of the second central portion 1110P1-2 of the organic pattern layer 1110 may include inclined surfaces having different angles respectively. For example, the portion of the second central portion 1110P1-2 of the organic pattern layer 1110 adjacent to the first central portion 1110P1-1 and the top surface 1110t1-2 of the second central portion 1110P1-2 of the organic pattern layer 1110 corresponding to the central portion 1110m may be substantially parallel to the top surface 100t of the substrate 100. In one embodiment, the angle of the inclined surface may increase away from the first central portion 1110P1-1 near the first central portion 1110P1-1 of the organic pattern layer 1110, and then may decrease toward the central portion 1110m near the central portion 1110m. The central portion 1110m of the second central portion 1110P-2 of the organic pattern layer 1110 may have a shape protruding in a direction away from the top surface 100t of the substrate 100 (e.g., the z direction).

[0228] Reference ​ and ​ , a preliminary metal pattern layer ML' may be formed on the organic pattern layer 1110 (e.g., directly formed thereon). A photoresist pattern PR may be formed on the preliminary metal pattern layer ML' (e.g., directly formed thereon). In one embodiment, the metal pattern layer ML may then be formed by patterning the preliminary metal pattern layer ML' using the photoresist pattern PR.

[0229] The form of the metal pattern layer ML may vary according to the form of the photoresist pattern PR. In one embodiment, as ​ illustrated in, the photoresist pattern PR may overlap with the first central portion 1110P1-1 of the organic pattern layer 1110 (e.g., in the z direction), and may not overlap with the second central portion 1110P1-2 (e.g., in the z direction). Reference ​ , in this embodiment, the patterned metal pattern layer ML may include an opening OP exposing the second central portion 1110P1-2 of the organic pattern layer 1110. The opening OP may expose the top surface 1110t1-2 of the second central portion 1110P1-2 of the organic pattern layer 1110.

[0230] In one embodiment, the end portion of the metal pattern layer ML may be disposed on the top surface 1110t1-1 of the first central portion 1110P1-1 of the organic pattern layer 1110. The end portion of the metal pattern layer ML may extend parallel to the top surface 100t of the substrate 100.

[0231] Reference ​ and ​ , a groove G can be formed by removing a part of the organic pattern layer 1110 using the metal pattern layer ML as a mask. In one embodiment, the second central portion 1110P1-2 and the first central portion 1110P1-1 of the organic pattern layer 1110 can be at least partially removed. An end TP provided at the end portion of the metal pattern layer ML can be formed. A virtual line passing through the first point P1 of the organic pattern layer 1110 and the edge TPe of the end TP of the metal pattern layer ML can be inclined in the direction (e.g., -z direction) toward the top surface 100t of the substrate 100. In one embodiment, at least a part of the end TP of the metal pattern layer ML can extend parallel to the top surface 100t of the substrate 100.

[0232] ​ A cross-sectional view briefly illustrating a method of manufacturing a spacer SP included in a display device 10 according to an embodiment. ​ Illustrative of ​ An embodiment in which the embodiment illustrated in ​ The spacer SP illustrated in ​ can be formed by the process illustrated in

[0233] As with ​ the embodiment shown in ​ in the process of patterning the organic pattern layer 1110 using the first mask MS1 illustrated in ​ the organic pattern layer 1110 having the form shown in

[0234] Reference ​ , a preliminary metal pattern layer ML' can be formed on the organic pattern layer 1110 (e.g., directly formed thereon). A photoresist pattern PR can be formed on the preliminary metal pattern layer ML'. In one embodiment, the metal pattern layer ML can then be formed by patterning the preliminary metal pattern layer ML' using the photoresist pattern PR.

[0235] The form of the metal pattern layer ML can vary according to the form of the photoresist pattern PR. Different from ​ the embodiment shown in ​ in the embodiment shown in ​, in this embodiment, the metal pattern layer ML may partially overlap with the first central portion 1110P1-1 and the second central portion 1110P1-2 of the organic pattern layer 1110, and may include an opening OP that exposes a part of the second central portion 1110P1-2. The opening OP may expose a part of the top surface 1110t1-2 of the second central portion 1110P1-2 of the organic pattern layer 1110.

[0236] In one embodiment, an end portion of the metal pattern layer ML may be disposed on the top surface 1110t1-2 of the second central portion 1110P1-2 of the organic pattern layer 1110. Accordingly, the end portion of the metal pattern layer ML may be inclined in a direction away from the top surface 100t of the substrate 100 (e.g., the z direction).

[0237] Reference ​ and ​ , a groove G may be formed by removing a part of the organic pattern layer 1110 by using the metal pattern layer ML as a mask. In one embodiment, at least a part of the second central portion 1110P1-2 and the first central portion 1110P1-1 of the organic pattern layer 1110 may be removed. An end tip TP provided at the end portion of the metal pattern layer ML may be formed. A virtual line passing through the first point P1 of the organic pattern layer 1110 and the edge TPe of the end tip TP of the metal pattern layer ML may be inclined in a direction toward the top surface 100t of the substrate 100 (e.g., the -z direction). In one embodiment, at least a part of the end tip TP of the metal pattern layer ML may be inclined in a direction away from the top surface 100t of the substrate 100 (e.g., the z direction).

[0238] ​ is a cross-sectional view of a part of a display device according to an embodiment; ​ Illustrates an embodiment modifying the embodiment shown in ​ , and ​ Illustrates an embodiment modifying the embodiment shown in ​ . Hereinafter, differences will be mainly described, and for simplicity of description, repeated descriptions of the same or similar elements may be omitted.

[0239] Reference ​ and ​ , the spacer SP may have a stacked structure including the organic pattern layer 1110 and the metal pattern layer ML. In one embodiment, the spacer SP may include the groove G and two end tips TP disposed on both sides (e.g., lateral sides) of the groove G (in cross-section). The end tips TP may overlap with the groove G (e.g., in the z direction).

[0240] The organic pattern layer 1110 may include (e.g., in the z-direction) a first portion 1110a that overlaps with the groove G and a second portion 1110b that extends to the outside of the first portion 1110a and does not overlap with the groove G (e.g., in the z-direction). The second portion 1110b may include an edge portion of the organic pattern layer 1110.

[0241] In one embodiment, as ​ illustrated, the top surface 1110t corresponding to the second portion 1110b of the organic pattern layer 1110 may not include a bevel. The top surface 1110t corresponding to the second portion 1110b of the organic pattern layer 1110 may extend substantially parallel to the top surface 100t of the substrate 100. However, embodiments of the present disclosure are not necessarily limited thereto. In some embodiments, as ​ illustrated, the top surface corresponding to at least a part of the second portion 1110b of the organic pattern layer 1110, such as a part of the second portion 1110b adjacent to the first portion 1110a, may include a bevel. In one embodiment, the bevel may be a downward slope in the direction towards the top surface 100t of the substrate 100 (e.g., the -z direction).

[0242] In cross-section, the top surface 1110t of the organic pattern layer 1110 may include a first point P1 that has the maximum vertical distance from the top surface 100t of the substrate 100. For example, the top surface 1110t corresponding to the second portion 1110b of the organic pattern layer 1110 may include a first point P1 that has the maximum vertical distance from the top surface 100t of the substrate 100.

[0243] The metal pattern layer ML may be disposed on the top surface 1110t of the organic pattern layer 1110 (e.g., directly thereon). The metal pattern layer ML may include a terminal TP. The terminal TP may include a portion that extends from a second point P2 where the inner surface 1110is of the organic pattern layer 1110 intersects the bottom surface MLb of the metal pattern layer ML towards the center of the groove G. In one embodiment, as ​ illustrated, the terminal TP of the metal pattern layer ML may not extend parallel to the top surface 100t of the substrate 100. In one embodiment, the terminal TP of the metal pattern layer ML may be inclined in the direction towards the top surface 100t of the substrate 100 (e.g., the -z direction). However, embodiments of the present disclosure are not necessarily limited thereto. For example, in some embodiments, as ​As illustrated, at least a part of the end TP of the metal pattern layer ML may extend parallel to the top surface 100t of the substrate 100. For example, the edge TPe of the end TP of the metal pattern layer ML may extend parallel to the top surface 100t of the substrate 100. In the end TP of the metal pattern layer ML, the remaining part except for the part including the edge TPe may be inclined in the direction towards the top surface 100t of the substrate 100 (e.g., -z direction).

[0244] A virtual line passing through the first point P1 of the organic pattern layer 1110 and the edge TPe of the end TP of the metal pattern layer ML may extend in the direction towards the top surface 100t of the substrate 100 (e.g., -z direction). In one embodiment, the angle θ1 formed by the virtual line passing through the first point P1 of the organic pattern layer 1110 and the edge TPe of the end TP of the metal pattern layer ML and the top surface 100t of the substrate 100 may be greater than 0° but less than 90°.

[0245] In one embodiment, among the layers provided on the metal pattern layer ML, such as the first covering portion CV1 including the covering layer CVL, the functional layer 220f, and the first dummy stack DS1 of the counter electrode 230, the portion provided on the end TP of the metal pattern layer ML may have the same inclined surface structure as the inclined surface structure of the end TP.

[0246] ​ A cross-sectional view for briefly illustrating a method of manufacturing the spacer SP of the display device 10 according to an embodiment. ​ The spacer SP illustrated in ​ may be formed by the process shown in ​ Illustrate ​ An embodiment in which the embodiment shown in

[0247] is modified. Hereinafter, the differences will be mainly described, and for simplicity of description, the repeated description of the same or similar elements may be omitted. ​ and ​ Referring to

[0248] The preliminary organic pattern layer 1110' can be exposed according to each part with different exposure amounts through a second mask MS2. In one embodiment, in the second mask MS2, the first part AR1' may include a semi-transmissive part, the second part AR2' may include a transmissive part, and the third part AR3' may include a light-shielding unit. The transmittance of the first part AR1' of the second mask MS2 may be less than the transmittance of the second part AR2' and greater than the transmittance of the third part AR3'.

[0249] In one embodiment, the preliminary organic pattern layer 1110' may then be patterned through a developing process to form the organic pattern layer 1110.

[0250] The central part 1110P1' of the organic pattern layer 1110 may include the part exposed through the first part AR1' of the second mask MS2. The edge part 1110P2' of the organic pattern layer 1110 may include the part exposed through the third part AR3' of the second mask MS2. The part exposed through the second part AR2' of the second mask MS2 may be removed from the preliminary organic pattern layer 1110' in the developing process. The bevel part 1110P3' may be between the central part 1110P1' and the edge part 1110P2' of the organic pattern layer 1110.

[0251] The top surface 1110t2' of the edge part 1110P2' of the organic pattern layer 1110 may include a first point P1 having the maximum vertical distance from the top surface 100t of the substrate 100. The thickness (e.g., the length in the z direction) of the central part 1110P1' of the organic pattern layer 1110 may be less than the thickness (e.g., the length in the z direction) of the edge part 1110P2' of the organic pattern layer 1110. For example, the vertical distance h1'' from the top surface 100t of the substrate 100 to the top surface 1110t1' of the central part 1110P1' of the organic pattern layer 1110 may be less than the vertical distance h2'' from the top surface 100t of the substrate 100 to the top surface 1110t2' of the edge part 1110P2' of the organic pattern layer 1110.

[0252] In cross-section, the top surface 1110t3' of the bevel part 1110P3' of the organic pattern layer 1110 may be inclined in the direction (e.g., the -z direction) toward the top surface 100t of the substrate 100.

[0253] Reference ​ and ​, a preliminary metal pattern layer ML' may be formed on the organic pattern layer 1110 (e.g., directly thereon). A photoresist pattern PR' may be formed on the preliminary metal pattern layer ML' (e.g., directly thereon). The metal pattern layer ML may be formed by patterning the preliminary metal pattern layer ML'. The photoresist pattern PR' may overlap (e.g., in the z direction) with the edge portion 1110P2' and the bevel portion 1110P3' of the organic pattern layer 1110, and may not overlap (e.g., in the z direction) with the central portion 1110P1' of the organic pattern layer 1110. The metal pattern layer ML may include an opening OP exposing the central portion 1110P1' of the organic pattern layer 1110. The opening OP may expose the top surface 1110t1' of the central portion 1110P1' of the organic pattern layer 1110. The end portion of the metal pattern layer ML may be disposed on the top surface 1110t3' of the bevel portion 1110P3' of the organic pattern layer 1110. The end portion of the metal pattern layer ML may be inclined in the direction (e.g., -z direction) toward the top surface 100t of the substrate 100.

[0254] Reference ​ , a groove G may be formed by removing a part of the organic pattern layer 1110 using the organic pattern layer 1110 as a mask. For example, at least a part of the central portion 1110P1' and the bevel portion 1110P3' of the organic pattern layer 1110 may be removed. An end tip TP provided at the end portion of the metal pattern layer ML may be formed. A virtual line passing through the first point P1 of the organic pattern layer 1110 and the edge TPe of the end tip TP of the metal pattern layer ML may be inclined in the direction (e.g., -z direction) toward the top surface 100t of the substrate 100. In one embodiment, the end tip TP of the metal pattern layer ML may be inclined in the direction (e.g., -z direction) toward the top surface 100t of the substrate 100.

[0255] ​ A cross-sectional view briefly illustrating a method of manufacturing a spacer SP of a display device according to an embodiment. ​ The spacer SP shown in ​ may be formed by the process shown in ​ Illustrating an example of ​ an embodiment modifying the embodiment shown in

[0256] Similar to ​ the embodiment shown in ​ in the process of patterning the organic pattern layer 1110 using the second mask MS2 shown in ​ an organic pattern layer 1110 having the form shown in

[0257] Reference ​ , a preliminary metal pattern layer ML' may be formed on the organic pattern layer 1110 (e.g., directly thereon). A photoresist pattern PR' may be formed on the preliminary metal pattern layer ML' (e.g., directly thereon). In one embodiment, the metal pattern layer ML may then be formed by patterning the preliminary metal pattern layer ML' using the photoresist pattern PR'.

[0258] The form of the metal pattern layer ML may vary according to the form of the photoresist pattern PR'. Different from the embodiment shown in ​ , in the embodiment shown in ​ , the photoresist pattern PR' may overlap (e.g., in the z direction) with a part of the edge portion 1110P2', the bevel portion 1110P3', and the central portion 1110P1' of the organic pattern layer 1110, and may not overlap (e.g., in the z direction) with another part of the central portion 1110P1' of the organic pattern layer 1110. Reference ​ , in this embodiment, the metal pattern layer ML may overlap (e.g., in the z direction) with the edge portion 1110P2', the bevel portion 1110P3', and a part of the central portion 1110P1', and may include an opening OP exposing a part of the central portion 1110P1' of the organic pattern layer 1110. The opening OP may expose a part of the top surface 1110t1' of the central portion 1110P1' of the organic pattern layer 1110.

[0259] In one embodiment, the end portion of the metal pattern layer ML may be disposed on the top surface 1110t1' of the central portion 1110P1' of the organic pattern layer 1110. Thus, the end portion of the metal pattern layer ML may extend parallel to the top surface 100t of the substrate 100.

[0260] [[ID=IS]]Reference ​ and ​ , a groove G may be formed by removing a part of the organic pattern layer 1110 using the metal pattern layer ML as a mask. In one embodiment, the central portion 1110P1' and the bevel portion 1110P3' of the organic pattern layer 1110 may be at least partially removed. An end tip TP provided at the end portion of the metal pattern layer ML may be formed. A virtual line passing through the first point P1 of the organic pattern layer 1110 and the edge TPe of the end tip TP of the metal pattern layer ML may be inclined in the direction (e.g., -z direction) toward the top surface 100t of the substrate 100. In one embodiment, at least a part of the end tip TP of the metal pattern layer ML may extend parallel to the top surface 100t of the substrate 100.

[0261] According to the above-described embodiments, a display device can be realized that has areas for arranging various components in a display area and whose reliability is increased. However, the scope of the embodiments of the present disclosure need not be limited thereto.

[0262] It should be understood that the embodiments described herein should be considered only in a descriptive sense and not for purposes of limitation. The description of features or aspects in each embodiment should generally be considered applicable to other similar features or aspects in the embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those of ordinary skill in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the present disclosure.

Claims

1. A display device, comprising: a substrate including a first region, a second region surrounding at least a part of the first region, and a third region between the first region and the second region; a light-emitting diode disposed in the second region and including a sub-pixel electrode, a counter electrode, and an intermediate layer between the sub-pixel electrode and the counter electrode; and a first spacer disposed in the third region, wherein the first spacer includes: an organic pattern layer disposed on the substrate and having a groove; and a metal pattern layer disposed on a top surface of the organic pattern layer and including an end extending toward a center of the groove, wherein, in a cross-section, a top surface of the organic pattern layer includes a first point having a maximum vertical distance from a top surface of the substrate, and an imaginary line passing through the first point of the organic pattern layer and an edge of the end of the metal pattern layer is inclined in a direction toward the top surface of the substrate.

2. The display device according to claim 1, wherein: the organic pattern layer includes a first part overlapping with the groove and a second part outside the first part, and the second part does not overlap with the groove; and a top surface of the second part includes an inclined surface.

3. The display device according to claim 1, wherein the metal pattern layer at least partially covers the top surface and an outer surface of the organic pattern layer.

4. The display device according to claim 1, wherein at least a part of the end of the metal pattern layer is inclined in the direction toward the top surface of the substrate.

5. The display device according to claim 1, wherein at least a part of the end of the metal pattern layer extends parallel to the top surface of the substrate.

6. The display device according to claim 1, wherein at least a part of the end of the metal pattern layer is inclined in a direction away from the top surface of the substrate.

7. The display device according to claim 1, further comprising: an inorganic insulating layer disposed on the substrate, and the organic pattern layer is directly disposed on the inorganic insulating layer; a second spacer spaced apart from the first spacer in the third region; and the third region includes an inorganic contact region in a space between the first spacer and the second spacer, wherein the metal pattern layer directly contacts a top surface of the inorganic insulating layer in the inorganic contact region.

8. The display device according to claim 1, further comprising a cover layer, the cover layer including: a first cover part covering a top surface and a side surface of the metal pattern layer; and a second cover part disposed in the groove.

9. The display device according to claim 8, wherein the cover layer includes a material same as a material of the sub-pixel electrode.

10. The display device according to claim 1, wherein the metal pattern layer includes: a first sub-layer, a second sub-layer, and a third sub-layer stacked in sequence, wherein the third sub-layer extends from a point where a side surface of the second sub-layer intersects a bottom surface of the third sub-layer toward the center of the groove.

11. The display device according to claim 1, wherein: the intermediate layer includes at least one organic material layer; and the at least one organic material layer and the counter electrode are isolated from each other by the first spacer in the third region.

12. A method of manufacturing a display device, the method comprising: preparing a substrate including a first region, a second region surrounding at least a part of the first region, and a third region between the first region and the second region; forming an organic pattern layer in the third region; forming a metal pattern layer on the organic pattern layer; forming a first spacer including a groove and an end by removing a part of the organic pattern layer; and forming a light-emitting diode in the second region, the light-emitting diode including a sub-pixel electrode, a counter electrode, and an intermediate layer between the sub-pixel electrode and the counter electrode, wherein, in a cross section, a top surface of the organic pattern layer includes a first point having a maximum vertical distance from a top surface of the substrate, and the metal pattern layer includes the end extending toward a center of the groove, and an imaginary line passing through an edge of the first point of the organic pattern layer and the end of the metal pattern layer is inclined in a direction toward the top surface of the substrate.

13. The method according to claim 12, wherein the forming of the organic pattern layer includes: forming a preliminary organic pattern layer on the substrate; providing a mask on the preliminary organic pattern layer; and exposing and developing the preliminary organic pattern layer by using the mask.

14. The method according to claim 12, wherein the forming of the organic pattern layer is performed using a phase-shift mask.

15. The method according to claim 12, wherein the forming of the organic pattern layer is performed using a halftone mask or a slit.

16. The method according to claim 12, wherein: the organic pattern layer includes a central portion and an edge portion; and a vertical distance from the top surface of the substrate to a top surface of the central portion is smaller than a vertical distance from the top surface of the substrate to a top surface of the edge portion.

17. The method according to claim 16, wherein the forming of the metal pattern layer includes: forming a preliminary metal pattern layer; and forming a metal pattern layer including an opening by patterning the preliminary metal pattern layer, wherein the opening in the metal pattern layer exposes at least a part of the central portion of the organic pattern layer.

18. The method according to claim 12, wherein the removing of the part of the organic pattern layer includes ashing the organic pattern layer by using the metal pattern layer as a mask.

19. The method according to claim 12, further comprising forming a covering layer on the metal pattern layer, the covering layer including a material same as a material of the sub-pixel electrode.

20. The method according to claim 12, further comprising forming an opening region overlapping with the first region in the substrate.

21. An electronic device including the display device according to claim 1.

22. The electronic device according to claim 21, wherein the electronic device is at least one of a television set, a notebook computer, a monitor, a billboard chart, an Internet of Things device, a mobile phone, a smart phone, a tablet personal computer, a mobile communication terminal, an electronic notepad, an e-book, a portable multimedia player, a navigation device, an ultra-mobile personal computer, a smart watch, a watch phone, and a head-mounted display.

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