Display device

Abstract

A display device includes a first pixel and a second pixel, the first pixel and the second pixel being spaced apart from each other. Each of the first pixel and the second pixel includes: a plurality of emission regions in which a plurality of light emitting elements are disposed; a light blocking layer including a plurality of holes overlapping the plurality of emission regions, and disposed between adjacent emission regions of the plurality of emission regions; and a plurality of color filters disposed in the plurality of holes of the light blocking layer and overlapping the plurality of emission regions. The plurality of emission regions includes a first emission region, a second emission region, and a third emission region spaced apart from each other. A light-emitting element disposed in the first emission region among the plurality of light-emitting elements of the first pixel is positioned at a lower horizontal height than a light-emitting element disposed in the first emission region among the plurality of light-emitting elements of the second pixel.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0014565, filed with the Korean Intellectual Property Office on January 31, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a display device. Background Art

[0004] With the evolution of an information-oriented society, various demands for display devices have been increasing continuously. The display device may be a liquid crystal display device, a field emission display device, a light-emitting display device, or the like. The light-emitting display device may include an organic light-emitting display device including an organic light-emitting diode as a light-emitting element, an inorganic light-emitting display device including an inorganic light-emitting diode as a light-emitting element, or the like.

[0005] Due to the light diffusion characteristics, an image in the display device can be observed not only from the front but also from the side. In order to protect the privacy of a user using the display device, it is necessary to prevent the image in the display device from being seen by others other than the user. Therefore, a wide range of research on viewing angle control is being conducted. Summary of the Invention

[0006] Aspects of the present disclosure provide a display device capable of controlling the viewing angle of high-resolution pixels.

[0007] Aspects of the present disclosure also provide a display device having improved process efficiency.

[0008] It should be noted that the features of the present disclosure are not limited to the features mentioned above; and other features of the present disclosure will be apparent to those skilled in the art from the following description.

[0009] According to an aspect of the present disclosure, a display device is provided. The display device includes a first pixel and a second pixel, and the first pixel and the second pixel are spaced apart from each other. Each of the first pixel and the second pixel includes: a plurality of emission regions, a plurality of light-emitting elements disposed in the plurality of emission regions; a light-blocking layer including a plurality of holes overlapping the plurality of emission regions, and the light-blocking layer is disposed between adjacent emission regions among the plurality of emission regions; and a plurality of color filters disposed in the plurality of holes of the light-blocking layer and overlapping the plurality of emission regions. The plurality of emission regions include a first emission region, a second emission region, and a third emission region spaced apart from each other. The light-emitting element disposed in the first emission region among the plurality of light-emitting elements of the first pixel is positioned at a lower level height than the light-emitting element disposed in the first emission region among the plurality of light-emitting elements of the second pixel.

[0010] In an embodiment, the distance between the light-emitting element disposed in the first emission region of the first pixel and the light-blocking layer is greater than the distance between the light-emitting element disposed in the first emission region of the second pixel and the light-blocking layer.

[0011] In an embodiment, in the first pixel and the second pixel respectively, the plurality of holes of the light-blocking layer include a first hole, a second hole, and a third hole overlapping the first emission region, the second emission region, and the third emission region respectively. The width of the first hole of the first pixel is smaller than the width of the first hole of the second pixel.

[0012] In an embodiment, each of the first pixel and the second pixel may further include: a thin-film transistor layer configured to drive the plurality of light-emitting elements; a first protective film disposed on the thin-film transistor layer; and a pixel defining layer disposed on the first protective film and including openings overlapping corresponding emission regions among the plurality of emission regions. The first protective film further includes a first connection opening connected to the opening of the pixel defining layer in the first pixel.

[0013] In an embodiment, in the first pixel and the second pixel respectively, each of the plurality of light-emitting elements includes an emission layer. The emission layer is disposed in the first connection opening in the first pixel.

[0014] In an embodiment, each of the plurality of light-emitting elements in the second pixel is disposed on the first protective film.

[0015] In an embodiment, the emission layer in the second pixel is disposed in the opening of the pixel defining layer.

[0016] In an embodiment, in each of the first pixel and the second pixel, each of the plurality of light-emitting elements includes a first electrode, an emission layer disposed on the first electrode, and a second electrode disposed on the emission layer. The second electrode covers an inner surface of the first connection opening in the first pixel.

[0017] In an embodiment, each of the first pixel and the second pixel may further include: a thin film encapsulation layer disposed on the second electrode. At least a part of the thin film encapsulation layer is disposed in the first connection opening in the first pixel.

[0018] In an embodiment, each of the first pixel and the second pixel may further include: a second protective film disposed between the first protective film and the thin film transistor layer. In the first pixel and the second pixel respectively, the second protective film includes a second connection opening connected to the opening through the first connection opening. In the first pixel and the second pixel respectively, each of the plurality of light-emitting elements includes an emission layer, and the emission layer is disposed in the second connection opening in the first pixel.

[0019] In an embodiment, each of the first pixel and the second pixel may further include: a thin film transistor layer configured to drive the plurality of light-emitting elements; a first protective film disposed on the thin film transistor layer; and a pixel defining layer disposed on the first protective film and including an opening overlapping a corresponding emission region among the plurality of emission regions. The first protective film includes a valley connected to the opening of the pixel defining layer in the first pixel.

[0020] In an embodiment, in each of the first pixel and the second pixel, each of the plurality of light-emitting elements includes an emission layer, and the emission layer is disposed in the valley in the first pixel.

[0021] In an embodiment, in each of the first pixel and the second pixel, the plurality of color filters include a first color filter overlapping the first emission region, a second color filter overlapping the second emission region, and a third color filter overlapping the third emission region.

[0022] According to an aspect of the present disclosure, a display device is provided. The display device includes: a plurality of emission regions in which a plurality of light-emitting elements are disposed; a light-blocking layer including a plurality of holes overlapping with the plurality of emission regions, and the light-blocking layer is disposed between adjacent emission regions among the plurality of emission regions; and a plurality of color filters disposed in the plurality of holes of the light-blocking layer and overlapping with the plurality of emission regions. The plurality of emission regions include a first emission region and a second emission region spaced apart from each other. The first emission region and the second emission region emit light of the same color. The light-emitting elements disposed in the first emission region among the plurality of light-emitting elements are positioned lower than the light-emitting elements disposed in the second emission region among the plurality of light-emitting elements.

[0023] In an embodiment, the distance between the light-emitting element disposed in the first emission region and the light-blocking layer is greater than the distance between the light-emitting element disposed in the second emission region and the light-blocking layer.

[0024] In an embodiment, the plurality of holes in the light-blocking layer include a first hole overlapping with the first emission region and a second hole overlapping with the second emission region. The width of the first hole is smaller than the width of the second hole.

[0025] In an embodiment, the display device may further include: a thin-film transistor layer configured to drive the plurality of light-emitting elements; a first protective film disposed on the thin-film transistor layer; and a pixel defining layer disposed on the first protective film and including openings overlapping with corresponding emission regions among the plurality of emission regions. The first protective film includes a first connection opening that overlaps with the first emission region and is connected to the opening of the pixel defining layer.

[0026] In an embodiment, each of the plurality of light-emitting elements includes an emission layer, and the emission layer overlapping with the first emission region is disposed in the first connection opening.

[0027] In an embodiment, the light-emitting element disposed in the second emission region is disposed on the first protective film.

[0028] In an embodiment, the emission layer overlapping with the second emission region is disposed in the opening of the pixel defining layer.

[0029] In an embodiment, each of the plurality of light-emitting elements includes a first electrode, an emission layer disposed on the first electrode, and a second electrode disposed on the emission layer. At least a part of the second electrode overlapping with the first emission region covers the inner surface of the first connection opening.

[0030] In an embodiment, the display device may further include: a thin film encapsulation layer disposed on the second electrode, wherein at least a portion of the thin film encapsulation layer overlapping the first emission region is disposed in the first connection opening.

[0031] In an embodiment, the display device may further include a second protective film disposed between the first protective film and the thin film transistor layer. The second protective film includes a second connection opening connected to the opening through the first connection opening. Each of the plurality of light-emitting elements includes an emission layer, and the emission layer overlapping the first emission region is disposed in the second connection opening.

[0032] In an embodiment, the display device may further include: a thin film transistor layer configured to drive the plurality of light-emitting elements; a first protective film disposed on the thin film transistor layer; and a pixel defining layer disposed on the first protective film and including an opening overlapping with a corresponding emission region among the plurality of emission regions. The first protective film includes a valley, the valley overlapping with the first emission region and connected to the opening of the pixel defining layer.

[0033] In an embodiment, each of the plurality of light emitting elements includes an emission layer, and the emission layer overlapping the first emission region is disposed in the valley.

[0034] In an embodiment, the plurality of color filters include a first color filter overlapping the first emission area and a second color filter overlapping the second emission area, wherein the first color filter and the second color filter transmit light of the same color.

[0035] According to an embodiment of the present disclosure, the viewing angle of high-resolution pixels can be controlled.

[0036] According to the embodiments of the present disclosure, the process efficiency of a display device can be improved.

[0037] It should be noted that the effects of the present disclosure are not limited to the above-described effects, and other effects of the present disclosure will be apparent to those skilled in the art from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The above and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the attached drawings.

[0039] Figure 1 is a perspective view of an electronic device according to an exemplary embodiment of the present disclosure.

[0040] Figure 2 is a perspective view showing a foldable electronic device according to an embodiment of the present disclosure when it is folded.

[0041] Figure 3 is a perspective view showing Figure 2 a foldable electronic device when it is unfolded.

[0042] Figure 4 is a perspective view showing a display device included in an electronic device according to an embodiment of the present disclosure.

[0043] Figure 5 is Figure 4 a cross-sectional view of the display device as seen from the side.

[0044] Figure 6 is a plan view showing a display layer of a display device according to an embodiment of the present disclosure.

[0045] Figure 7 is a plan view showing a touch sensing layer of a display device according to an embodiment of the present disclosure.

[0046] Figure 8 is a plan view showing the arrangement of emission regions and touch electrodes in a display region of a display device according to an embodiment.

[0047] Figure 9 is a plan view showing the arrangement of color filters in a display region of a display device according to an embodiment.

[0048] Figure 10 is a plan view showing the arrangement of normal pixels and privacy pixels in a display region of a display device according to an embodiment.

[0049] Figure 11 is a cross-sectional view taken along Figure 10 line X1-X1' in

[0050] Figure 12 is a cross-sectional view taken along Figure 10 line X2-X2' of

[0051] Figure 13 is a cross-sectional view taken along Figure 10 lines X3-X3' and X4-X4' in

[0052] Figure 14 is a cross-sectional view showing an emission region in a privacy pixel of a display device according to an embodiment.

[0053] Figure 15 is a cross-sectional view showing an emission region of a privacy pixel of a display device according to an embodiment.

[0054] Figure 16 is a cross-sectional view showing a privacy pixel in a display device according to an embodiment of the present disclosure.

[0055] Figure 17 is a plan view showing an arrangement of color filters in a display area of a display device according to an embodiment.

[0056] Figure 18 is a plan view showing an arrangement of color filters in a display area of a display device according to an embodiment. DETAILED DESCRIPTION

[0057] The inventive concept will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the inventive concept are shown. However, the inventive concept may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art.

[0058] It will also be understood that when a layer is referred to as being “on” another layer or substrate, the layer may be directly on the other layer or substrate, or an intervening layer may also be present. Throughout the specification, like reference numerals refer to like components.

[0059] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0060] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0061] Figure 1 is a perspective view of an electronic device 1 according to an exemplary embodiment of the present disclosure.

[0062] Referring to Figure 1 , the electronic device 1 displays moving images or still images. The electronic device 1 may refer to any electronic device that provides a display screen. For example, the electronic device 1 may include a television, a laptop computer, a monitor, an electronic billboard, an Internet of Things device, a mobile phone, a smartphone, a tablet personal computer (PC), an electronic watch, a smart watch, a watch phone, a head-mounted display device, a mobile communication terminal, an electronic notebook, an e-book, a portable multimedia player (PMP), a navigation device, a game console, and a digital camera, a camcorder, etc.

[0063] The electronic device 1 may include a display device 10 for providing a display screen (see Figure 4 ). Examples of the display device may include an inorganic light-emitting display device, an organic light-emitting display device, a quantum dot light-emitting display device, a plasma display device, a field emission display device, etc. In the following description, an organic light-emitting display device is taken as an example of the display device, but the present disclosure is not limited thereto. Any other display device may be adopted as long as the technical idea of the present disclosure can be equally applied.

[0064] The shape of the electronic device 1 can be modified in various ways. For example, in a plan view, the electronic device 1 can have a shape such as a rectangle with a longer horizontal side, a rectangle with a longer vertical side, a square, a quadrilateral with rounded corners (vertices), other polygons, a circle, etc. In a plan view, the shape of the display area DA of the electronic device 1 can also be similar to the overall shape of the electronic device 1. In Figure 1 In the example shown in, in a plan view, the electronic device 1 has a rectangular shape with a longer side in the second direction DR2.

[0065] The electronic device 1 can include a display area DA and a non-display area NDA. In the display area DA, an image can be displayed. In the non-display area NDA, no image is displayed. The display area DA can be referred to as an active area, and the non-display area NDA can also be referred to as a non-active area. The display area DA can generally occupy the center of the electronic device 1.

[0066] The display area DA can include a first display area DA1, a second display area DA2, and a third display area DA3. In the second display area DA2 and the third display area DA3, components for adding various features to the electronic device 1 can be provided. In other words, the second display area DA2 and the third display area DA3 can be referred to as component areas.

[0067] Figure 2 FIG. is a perspective view of the foldable electronic device 1 according to an embodiment of the present disclosure when it is folded. Figure 3 FIG. shows Figure 2 a perspective view of the foldable electronic device 1 when it is unfolded.

[0068] Referring to Figure 2 and Figure 3 , according to an embodiment, the electronic device 1 can be a foldable display device. The foldable electronic device 1 can be folded along a folding axis FL. The display area DA can be located on the outer side and / or the inner side of the foldable electronic device 1. According to Figure 2 and Figure 3 an embodiment of, the display area DA is provided on each of the outer side and the inner side of the foldable electronic device 1.

[0069] The display area DA can be provided on the outer side of the electronic device 1. The outer surface of the electronic device 1 when it is folded can include the display area DA, and the inner surface of the electronic device 1 when it is unfolded can include the display area DA. Figure 3The display area DA of the foldable electronic device 1 may include a first display area DA1 that occupies most of the display area DA, and a second display area DA2 and a third display area DA3 that occupy smaller areas than the first display area DA1. The first display area DA1 may include a first display portion DA1L and a second display portion DA1R that are respectively positioned on both sides of the folding axis FL. The second display area DA2 and the third display area DA3 may be disposed in the area where the second display portion DA1R is positioned, but the present disclosure is not limited thereto. According to an embodiment, the second display area DA2 and the third display area DA3 may be positioned in the area where the first display portion DA1L is positioned, or one of the second display area DA2 and the third display area DA3 may be positioned in the area where the first display portion DA1L is positioned, and the other display area may be positioned in the area where the second display portion DA1R is positioned.

[0070] As in the example shown in Figures 1 to 3 each of the second display area DA2 and the third display area DA3 may have an area smaller than the area of the first display area DA1. The second display area DA2 and the third display area DA3 may have different sizes or areas, but the present disclosure is not limited thereto. In the following description, the second display area DA2 has a smaller area than the third display area DA3 in the drawings. Each of the second display area DA2 and the third display area DA3 may be surrounded by the first display area DA1. However, it will be understood that the present disclosure is not limited thereto.

[0071] Figure 4 is a perspective view of a display device 10 included in an electronic device 1 (see Figure 1 ) according to an embodiment of the present disclosure.

[0072] Referring to Figure 4 , an electronic device 1 according to an exemplary embodiment of the present disclosure may include a display device 10. The display device 10 may provide a display screen for displaying an image in the electronic device 1. The display device 10 may have a shape similar to the shape of the electronic device 1 when viewed from the top. For example, the display device 10 may have a shape similar to a rectangle having a shorter side in a first direction DR1 and a longer side in a second direction DR2. The corner where the shorter side in the first direction DR1 intersects the longer side in the second direction DR2 may be rounded with a predetermined curvature. However, it should be understood that the present disclosure is not limited thereto. The corner may be formed at a right angle. The shape of the display device 10 when viewed from the top is not limited to a quadrilateral shape, but may be formed in a shape similar to other polygonal shapes, circular shapes, or elliptical shapes.

[0073] The display device 10 may include a display panel 100, a display driver 200, a circuit board 300, and a touch driver 400.

[0074] The display panel 100 may include a main area MA and a sub-area SBA.

[0075] The main area MA may include a display area DA and a non-display area NDA. The display area DA includes pixels for displaying an image, and the non-display area NDA is positioned around the display area DA. The display area DA may include a first display area DA1, a second display area DA2, and a third display area DA3. The display area DA may output light from a plurality of emission areas or a plurality of opening areas. For example, the display panel 100 may include a pixel circuit including a switching element, a pixel defining layer defining the emission area or the opening area, and a self-emitting element.

[0076] For example, the self-emitting element may include, but is not limited to, at least one of the following: an organic light-emitting diode including an organic emission layer, a quantum dot light-emitting diode (quantum dot LED) including a quantum dot emission layer, an inorganic light-emitting diode (inorganic LED) including an inorganic semiconductor, and a micro light-emitting diode (micro LED).

[0077] The non-display area NDA may be positioned on the outer side of the display area DA. The non-display area NDA may be defined as an edge of the main area MA of the display panel 100. The non-display area NDA may include a gate driver (not shown) for applying a gate signal to a gate line and fan-out lines (not shown) connecting the display driver 200 to the display area DA.

[0078] The sub-area SBA may extend from one side of the main area MA. The sub-area SBA may include a flexible material that can be bent, folded, or curled. For example, when the sub-area SBA is bent, the sub-area SBA may overlap the main area MA in the thickness direction (third direction DR3). The sub-area SBA may include pads connected to the display driver 200 and the circuit board 300. According to another exemplary embodiment, the sub-area SBA may be removed, and the display driver 200 and the pads may be provided in the non-display area NDA.

[0079] The display driver 200 can output signals and voltages for driving the display panel 100. The display driver 200 can supply data voltages to data lines. The display driver 200 can apply a power voltage to a voltage line and can supply a gate control signal to a gate driver. The display driver 200 can be implemented as an integrated circuit (IC) and can be attached to the display panel 100 by a chip on glass (COG) technique, a chip on plastic (COP) technique, or an ultrasonic bonding technique. For example, the display driver 200 can be disposed in the auxiliary area SBA and can overlap with the main area MA in the thickness direction when the auxiliary area SBA is bent. As another example, the display driver 200 can be mounted on a circuit board 300.

[0080] The circuit board 300 can be attached to the pad area of the display panel 100 using an anisotropic conductive film (ACF). The leads of the circuit board 300 can be electrically connected to the pads of the display panel 100. The circuit board 300 can be a flexible printed circuit board (FPCB), a printed circuit board (PCB), or a flexible film such as a chip on film (COF).

[0081] The touch driver 400 can be mounted on the circuit board 300. The touch driver 400 can be connected to the touch sensing unit of the display panel 100. The touch driver 400 can supply touch driving signals to a plurality of touch electrodes of the touch sensing unit and can sense changes in capacitance between the plurality of touch electrodes. For example, the touch driving signal can be a pulse signal having a predetermined frequency. The touch driver 400 can determine whether an input exists and can find the coordinates of the input based on the amount of change in capacitance between the touch electrodes. The touch driver 400 can be implemented as an integrated circuit (IC).

[0082] Figure 5 is Figure 4 a cross-sectional view of the display device as seen from the side.

[0083] Referring to Figure 5 , the display panel 100 can include a display layer DU, a touch sensing layer TSU, and a color filter layer CFL. The display layer DU can include a substrate SUB, a thin film transistor layer TFTL, an emission material layer EML, and a packaging layer TFEL.

[0084] The substrate SUB can be a base substrate or a base member. The substrate SUB can be a flexible substrate that can be bent, folded, or curled. For example, the substrate SUB can include, but is not limited to, a polymer resin such as polyimide (PI). According to another exemplary embodiment, the substrate SUB can include a glass material or a metal material.

[0085] The thin film transistor layer TFTL may be disposed on the substrate SUB. The thin film transistor layer TFTL may include a plurality of thin film transistors forming pixel circuits of pixels. The thin film transistor layer TFTL may include gate lines, data lines, voltage lines, gate control lines, fan-out lines for connecting the display driver 200 to the data lines, leads for connecting the display driver 200 to pads, and the like. Each of the thin film transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, when the gate driver is formed on one side of the non-display area NDA of the display panel 100, the gate driver may include thin film transistors.

[0086] The thin film transistor layer TFTL may be disposed in the display area DA, the non-display area NDA, and the auxiliary area SBA. The thin film transistors, gate lines, data lines, and voltage lines in each of the pixels in the thin film transistor layer TFTL may be disposed in the display area DA. The gate control lines and fan-out lines in the thin film transistor layer TFTL may be disposed in the non-display area NDA. The leads of the thin film transistor layer TFTL may be disposed in the auxiliary area SBA.

[0087] The emission material layer EML may be disposed on the thin film transistor layer TFTL. The emission material layer EML may include a plurality of light-emitting elements and a pixel defining layer for defining pixels, and each of the plurality of light-emitting elements includes a first electrode, a second electrode, and an emission layer for emitting light. The plurality of light-emitting elements in the emission material layer EML may be disposed in the display area DA.

[0088] According to an exemplary embodiment of the present disclosure, the emission layer may be an organic emission layer including an organic material. The emission layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. When the first electrode receives a voltage through the thin film transistors in the thin film transistor layer TFTL and the second electrode receives a cathode voltage, holes and electrons may move to the organic light-emitting layer through the hole transport layer and the electron transport layer, respectively, so that they recombine in the organic light-emitting layer to emit light.

[0089] According to an embodiment, the light-emitting elements may include a plurality of quantum dot light-emitting diodes each including a quantum dot emission layer, a plurality of inorganic light-emitting diodes each including an inorganic semiconductor, or a plurality of micro light-emitting diodes.

[0090] The encapsulation layer TFEL may cover the upper surface and side surfaces of the emission material layer EML and may protect the emission material layer EML. The encapsulation layer TFEL may include at least one inorganic layer and at least one organic layer for encapsulating the emission material layer EML.

[0091] The touch sensing layer TSU may be disposed on the encapsulation layer TFEL. The touch sensing layer TSU may include a plurality of touch electrodes for sensing a user's touch by capacitance sensing, and touch lines connecting the plurality of touch electrodes to the touch driver 400. For example, the touch sensing layer TSU may sense a user's touch by mutual capacitance sensing or self-capacitance sensing.

[0092] For another example, the touch sensing layer TSU may be disposed on a separate substrate that is disposed on the display layer DU. In this case, the substrate supporting the touch sensing layer TSU may be a base member for encapsulating the display layer DU.

[0093] The plurality of touch electrodes of the touch sensing layer TSU may be disposed in a touch sensor area that overlaps with the display area DA. The touch lines of the touch sensing layer TSU may be disposed in a touch peripheral area that overlaps with the non-display area NDA.

[0094] The color filter layer CFL may be disposed on the touch sensing layer TSU. The color filter layer CFL may include a plurality of color filters respectively corresponding to a plurality of emission areas. Each of the color filters may selectively transmit light of a specific wavelength and block or absorb light of other wavelengths. The color filter layer CFL may absorb some light introduced from the outside of the display device 10 to reduce the reflection of external light. Therefore, the color filter layer CFL may prevent color distortion caused by the reflection of external light.

[0095] Since the color filter layer CFL is directly disposed on the touch sensing layer TSU, the display device 10 may not require a separate substrate for the color filter layer CFL. Therefore, the thickness of the display device 10 may be relatively small.

[0096] In some embodiments, the display device 10 may further include an optical device 500 and a window member 600.

[0097] The optical device 500 may be disposed in the second display area DA2 or the third display area DA3. The optical device 500 may output or receive light in the infrared light range, ultraviolet light range, and visible light range. For example, the optical device 500 may be an optical sensor that senses light incident on the display device 10, such as a proximity sensor, an illuminance sensor, a camera sensor, and an image sensor.

[0098] The window member 600 may be disposed on the display panel 100. The window member 600 may cover the display panel 100. The window member 600 may completely cover the display area DA and the non-display area NDA of the display device 10. In a plan view, the shape of the window member 600 may be the same as the shape of the display panel 100. The window member 600 may protect the display panel 100 from external impacts and provide an input surface to the user.

[0099] The window member 600 may be transparent so that the light generated in the display panel 100 can be transmitted. The window member 600 may include a glass or plastic material. In some embodiments where the window member 600 includes glass, the window member 600 may include chemically strengthened glass by ion substitution. According to embodiments where the window member 600 includes plastic, the window member 600 may include a polyimide film.

[0100] According to some embodiments, the color filter layer CFL is bonded to the display panel 100 such that the window member 600 can be directly mounted on the display panel 100. For example, an optical member such as a polarizing film may not be provided on the window member 600 and the display panel 100. Therefore, the thickness of the display device 10 can be reduced. If the display device 10 is a foldable device, the folding stress can be reduced.

[0101] Figure 6 is a plan view showing a display layer DU of a display device 10 (see Figure 5 ) according to an embodiment of the present disclosure.

[0102] Referring to Figure 6 and also referring to Figure 5 , the display layer DU may include a display area DA and a non-display area NDA.

[0103] The display area DA may be provided at the center of the display device 10. In the display area DA, a plurality of pixels PX, a plurality of gate lines GL, a plurality of data lines DL, and a plurality of voltage lines VL may be provided. Each of the plurality of pixels PX may be defined as the smallest unit for outputting light.

[0104] The plurality of gate lines GL may supply gate signals received from the gate driver 210 to the plurality of pixels PX. The plurality of gate lines GL may extend in a first direction DR1 and may be spaced apart from each other in a second direction DR2 intersecting the first direction DR1.

[0105] The plurality of data lines DL may supply data voltages received from the display driver 200 to the plurality of pixels PX. The plurality of data lines DL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1.

[0106] The plurality of voltage lines VL may apply power voltages received from the display driver 200 to the plurality of pixels PX. The power voltage may be at least one of a driving voltage, an initialization voltage, a reference voltage, and a low-level voltage. The plurality of voltage lines VL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1.

[0107] The non-display area NDA can surround the display area DA. In the non-display area NDA, a gate driver 210, fan-out lines FOL, and gate control lines GCL can be provided. The gate driver 210 can generate a plurality of gate signals based on a gate control signal and can sequentially supply the plurality of gate signals to a plurality of gate lines GL in a predetermined order.

[0108] The fan-out lines FOL can extend from the display driver 200 to the display area DA. The fan-out lines FOL can supply data voltages received from the display driver 200 to a plurality of data lines DL.

[0109] The gate control lines GCL can extend from the display driver 200 to the gate driver 210. The gate control lines GCL can supply the gate control signals received from the display driver 200 to the gate driver 210.

[0110] The auxiliary area SBA can include a display driver 200, a pad area PA, and a first touch pad area TPA1 and a second touch pad area TPA2.

[0111] The display driver 200 can output signals and voltages for driving the display panel 100 to the fan-out lines FOL. The display driver 200 can supply data voltages to the data lines DL through the fan-out lines FOL. The data voltages can be applied to a plurality of pixels PX so that the brightness of the plurality of pixels PX can be controlled. The display driver 200 can supply the gate control signals to the gate driver 210 through the gate control lines GCL.

[0112] The pad area PA, the first touch pad area TPA1, and the second touch pad area TPA2 can be provided at the edge of the auxiliary area SBA. The pad area PA, the first touch pad area TPA1, and the second touch pad area TPA2 can be electrically connected to the circuit board 300 using materials such as anisotropic conductive films and self-assembled anisotropic conductive pastes (SAP).

[0113] The pad area PA can include a plurality of display pads DP. The plurality of display pads DP can be connected to a graphics system through the circuit board 300. The plurality of display pads DP can be connected to the circuit board 300 to receive digital video data and can supply the digital video data to the display driver 200.

[0114] Figure 7 is a plan view of a touch sensing layer TSU of a display device 10 (see Figure 5 ) according to an embodiment of the present disclosure.

[0115] Refer to Figure 7 and also refer to Figure 5, the touch sensing layer TSU may include a touch sensor area TSA for sensing a user's touch and a touch peripheral area TOA disposed around the touch sensor area TSA. The touch sensor area TSA may be disposed in the display area DA of the display device 10, and the touch peripheral area TOA may be disposed in the non-display area NDA of the display device 10.

[0116] The touch sensor area TSA may include a plurality of touch electrodes SEN and a plurality of dummy electrodes DME. The plurality of touch electrodes SEN may form mutual capacitance or self-capacitance to sense the touch of an object or a person. The plurality of touch electrodes SEN may include a plurality of driving electrodes TE and a plurality of sensing electrodes RE.

[0117] The driving electrodes TE may be arranged in a first direction DR1 and a second direction DR2. The driving electrodes TE may be spaced apart from each other in the first direction DR1 and the second direction DR2. The driving electrodes TE adjacent to each other in the second direction DR2 may be electrically connected through a bridging electrode BE.

[0118] The plurality of driving electrodes TE may be connected to a first touch pad TP1 through driving lines TDL. The driving lines TDL may include a lower driving line TDLa and an upper driving line TDLb. For example, the driving electrodes TE disposed on the lower side of the touch sensor area TSA may be connected to the first touch pad TP1 through the lower driving line TDLa, and the driving electrodes TE disposed on the upper side of the touch sensor area TSA may be connected to the first touch pad TP1 through the upper driving line TDLb. The lower driving line TDLa may extend to the first touch pad TP1 via the lower side of the touch peripheral area TOA. The upper driving line TDLb may extend to the first touch pad TP1 via the upper side, left side, and lower side of the touch peripheral area TOA. The first touch pad TP1 may be connected to the touch driver 400 through a circuit board 300.

[0119] The bridging electrode BE may be bent at least once. Although the bridging electrode BE may have a shape of an angle bracket "<" or ">", the shape of the bridging electrode BE when viewed from the top is not limited thereto. The driving electrodes TE adjacent to each other in the second direction DR2 may be connected through a plurality of bridging electrodes BE. Even if one of the plurality of bridging electrodes BE is disconnected, the driving electrodes TE may be stably connected through the remaining bridging electrodes BE. The adjacent driving electrodes TE may be connected through two bridging electrodes BE, but the number of the bridging electrodes BE is not limited thereto.

[0120] The bridging electrode BE can be disposed on a different layer from the plurality of driving electrodes TE and the plurality of sensing electrodes RE. The sensing electrodes RE adjacent to each other in the first direction DR1 can be electrically connected through a connecting member disposed in the same layer as the plurality of driving electrodes TE or the plurality of sensing electrodes RE. The driving electrodes TE adjacent to each other in the second direction DR2 can be electrically connected through the bridging electrode BE disposed in a different layer from the plurality of driving electrodes TE or the plurality of sensing electrodes RE. Thus, even if the bridging electrode BE overlaps with the plurality of sensing electrodes RE in the third direction DR3, the plurality of driving electrodes TE and the plurality of sensing electrodes RE can be insulated from each other. A mutual capacitance can be formed between the driving electrode TE and the sensing electrode RE.

[0121] The sensing electrodes RE can extend in the first direction DR1 and can be spaced apart from each other in the second direction DR2. The sensing electrodes RE can be arranged in the first direction DR1 and the second direction DR2, and the sensing electrodes RE adjacent to each other in the first direction DR1 can be electrically connected through a connecting member.

[0122] The plurality of sensing electrodes RE can be connected to the second touch pad TP2 through the sensing lines RL. For example, the sensing electrode RE disposed on the right side of the touch sensor area TSA can be connected to the second touch pad TP2 through the sensing line RL. The sensing line RL can extend along the right side and the lower side of the touch peripheral area TOA to the second touch pad TP2. The second touch pad TP2 can be connected to the touch driver 400 through the circuit board 300.

[0123] Each of the plurality of dummy electrodes DME can be surrounded by the driving electrode TE or the sensing electrode RE. Each of the plurality of dummy electrodes DME can be spaced apart from and insulated from the driving electrode TE or the sensing electrode RE. Thus, the dummy electrode DME can be electrically floating.

[0124] The pad area PA, the first touch pad area TPA1, and the second touch pad area TPA2 can be disposed at the edge of the auxiliary area SBA. The pad area PA, the first touch pad area TPA1, and the second touch pad area TPA2 can be electrically connected to the circuit board 300 using materials with low resistance and high reliability (such as anisotropic conductive film and self-assembled anisotropic conductive paste (SAP)).

[0125] The first touch pad area TPA1 can be disposed on one side of the pad area PA and can include a plurality of first touch pads TP1. The plurality of first touch pads TP1 can be electrically connected to the touch driver 400 disposed on the circuit board 300. The plurality of first touch pads TP1 can supply touch driving signals to the plurality of driving electrodes TE through a plurality of driving lines TDL.

[0126] The second touch pad area TPA2 may be disposed on the opposite side of the pad area PA and may include a plurality of second touch pads TP2. The plurality of second touch pads TP2 may be electrically connected to a touch driver 400 disposed on the circuit board 300. The touch driver 400 may receive a touch sensing signal through a plurality of sensing lines RL connected to the plurality of second touch pads TP2, and may sense a change in capacitance between the driving electrode TE and the sensing electrode RE.

[0127] According to an embodiment, the touch driver 400 may supply a touch driving signal to each of the plurality of driving electrodes TE and the plurality of sensing electrodes RE, and may receive a touch sensing signal from each of the plurality of driving electrodes TE and the plurality of sensing electrodes RE. The touch driver 400 may sense a change in the amount of charge in each of the plurality of driving electrodes TE and the plurality of sensing electrodes RE based on the touch sensing signal.

[0128] Figure 8 is a plan view showing the arrangement of the emission areas EA1, EA2, and EA3 and the touch electrodes TL in the display area DA of the display device 10 according to an embodiment. Figure 9 is a plan view showing the arrangement of the color filters CF1, CF2, and CF3 in the display area DA of the display device 10 according to an embodiment.

[0129] Referring to Figure 8 and Figure 9 and further referring to Figure 1 、 Figure 5 and Figure 11 the display device 10 may include a plurality of emission areas EA1, EA2, and EA3 disposed in the display area DA.

[0130] The emission areas EA1, EA2, and EA3 may include a first emission area EA1, a second emission area EA2, and a third emission area EA3 that emit light of different colors. The first emission area EA1, the second emission area EA2, and the third emission area EA3 may emit red light, green light, and blue light, respectively. The colors of the light emitted from the emission areas EA1, EA2, and EA3 may vary according to the type of the light emitting element ED (see Figure 11 ) provided in the emission material layer EML, which will be described later. According to an embodiment of the present disclosure, the first emission area EA1 may emit first light of red color, the second emission area EA2 may emit second light of green color, and the third emission area EA3 may emit third light of blue color. However, it should be understood that the embodiments of the present disclosure are not limited thereto.

[0131] The emission areas EA1, EA2, and EA3 may be arranged in a matrix (e.g., diamond Matrix arrangement. For example, the first emission area EA1 and the third emission area EA3 are spaced apart from each other in the first direction DR1, and can be alternately arranged in the first direction DR1 and the second direction DR2. Regarding the arrangement of the emission areas EA1, EA2, and EA3, the first emission area EA1 and the third emission area EA3 can be alternately arranged in the first row R1 and the third row R3 in the first direction DR1. In the first column C1 and the third column C3, the first emission area EA1 and the third emission area EA3 can be alternately arranged in the second direction DR2.

[0132] The second emission area EA2 can be spaced apart from another adjacent second emission area EA2 in the first direction DR1 and the second direction DR2, and can be spaced apart from the adjacent first emission area EA1 and third emission area EA3 in the fourth direction DR4 or the fifth direction DR5. A plurality of second emission areas EA2 can be repeatedly arranged in the first direction DR1 and the second direction DR2, and the second emission area EA2 and the first emission area EA1 or the second emission area EA2 and the third emission area EA3 can be alternately arranged in the fourth direction DR4 or the fifth direction DR5. Regarding the arrangement of the emission areas EA1, EA2, and EA3, the second emission area EA2 can be repeatedly arranged in the second row R2 and the fourth row R4 in the first direction DR1, and the second emission area EA2 can be repeatedly arranged in the second column C2 and the fourth column C4 in the second direction DR2.

[0133] The first emission area EA1, the second emission area EA2, and the third emission area EA3 can be defined by a plurality of openings OPE1, OPE2, and OPE3 formed in a pixel defining layer PDL (see Figure 11 ) of the emission material layer EML, which will be described later. For example, the first emission area EA1 can be defined by the first opening OPE1 of the pixel defining layer PDL, the second emission area EA2 can be defined by the second opening OPE2 of the pixel defining layer PDL, and the third emission area EA3 can be defined by the third opening OPE3 of the pixel defining layer PDL.

[0134] According to an embodiment of the present disclosure, the first emission area EA1, the second emission area EA2, and the third emission area EA3 can have different areas or sizes. In Figure 8In the example shown, the third emission region EA3 may be larger than the first emission region EA1 and the second emission region EA2, and the first emission region EA1 may be larger than the second emission region EA2. The sizes of the emission regions EA1, EA2, and EA3 may vary according to the sizes of the openings OPE1, OPE2, and OPE3 formed in the pixel defining layer PDL. The intensities of the light emitted from the emission regions EA1, EA2, and EA3 may vary according to the sizes of the emission regions EA1, EA2, and EA3. The color of the image displayed in the display device 10 or the electronic device 1 may be controlled by adjusting the sizes of the emission regions EA1, EA2, and EA3. Although in Figure 8 the example shown the third emission region EA3 is the largest, the present disclosure is not limited thereto. The sizes of the emission regions EA1, EA2, and EA3 may be adjusted as desired according to the color of the image required by the display device 10 and the electronic device 1. In addition, the sizes of the emission regions EA1, EA2, and EA3 may be related to the light efficiency, the lifetime of the light-emitting element ED, etc., and may have a trade-off relationship with the reflection of external light. The sizes of the emission regions EA1, EA2, and EA3 may be adjusted by considering the above factors.

[0135] In a display device 10 having an arrangement of emission regions EA1, EA2, and EA3 as shown in Figure 8 one first emission region EA1, two second emission regions EA2, and one third emission region EA3 adjacent to each other may form a single pixel group. The single pixel group may represent white by including emission regions EA1, EA2, and EA3 that emit light of different colors. However, it should be understood that the present disclosure is not limited thereto. The combination of the emission regions EA1, EA2, and EA3 forming the single pixel group may be modified according to the arrangement of the emission regions EA1, EA2, and EA3 and the colors of the light emitted from the emission regions EA1, EA2, and EA3.

[0136] [[ID=~10]]The display device 10 may include a plurality of color filters CF1, CF2, and CF3 disposed on the emission regions EA1, EA2, and EA3. The color filters CF1, CF2, and CF3 may correspond to the emission regions EA1, EA2, and EA3, respectively. For example, the color filters CF1, CF2, and CF3 may be disposed on the light blocking layer BM, and the light blocking layer BM includes a plurality of holes OPT1_N, OPT1_P, OPT2_N, OPT2_P, OPT3_N, and OPT3_P that overlap with the emission regions EA1, EA2, and EA3 or the openings OPE1, OPE2, and OPE3, respectively.

[0137] The light blocking layer BM (see Figure 11) The holes OPT1_N, OPT1_P, OPT2_N, OPT2_P, OPT3_N, and OPT3_P can be formed to overlap with the openings OPE1, OPE2, and OPE3, and can form a light output region where the light emitted from the emission regions EA1, EA2, and EA3 exits. The light blocking layer BM (see Figure 11 ) The widths and dimensions (or areas) of the holes OPT1_N, OPT1_P, OPT2_N, OPT2_P, OPT3_N, and OPT3_P can be larger than the widths and dimensions (or areas) of the emission regions EA1, EA2, and EA3.

[0138] The color filters CF1, CF2, and CF3 can have an area larger than the areas of the holes OPT1_N, OPT1_P, OPT2_N, OPT2_P, OPT3_N, and OPT3_P of the light blocking layer BM and the openings OPE1, OPE2, and OPE3. The color filters CF1, CF2, and CF3 can completely cover the light output region formed through the holes OPT1_N, OPT1_P, OPT2_N, OPT2_P, OPT3_N, and OPT3_P.

[0139] The color filters CF1, CF2, and CF3 include a first color filter CF1, a second color filter CF2, and a third color filter CF3 corresponding to different emission regions EA1, EA2, and EA3, respectively. The color filters CF1, CF2, and CF3 can include colorants (such as dyes and pigments) that absorb light in other wavelength ranges than in a specific wavelength range and can be arranged corresponding to the light emitted from the emission regions EA1, EA2, and EA3. For example, the first color filter CF1 can be a red color filter arranged to overlap with the first emission region EA1 and transmit only the first red light. The second color filter CF2 can be a green color filter arranged to overlap with the second emission region EA2 and transmit only the second green light. The third color filter CF3 can be a blue color filter arranged to overlap with the third emission region EA3 and transmit only the third blue light.

[0140] Similar to the arrangement of the emission regions EA1, EA2, and EA3, the color filters CF1, CF2, and CF3 can be arranged in a matrix (e.g., diamond matrix). For example, the first color filter CF1 and the third color filter CF3 can be alternately arranged in a first direction DR1 and a second direction DR2. The color filters CF1, CF2, and CF3 can be arranged as follows: the first color filter CF1 and the third color filter CF3 can be alternately arranged in the first direction DR1 in the first row R1 and the third row R3; in the first column C1 and the third column C3, the first color filter CF1 and the third color filter CF3 can be alternately arranged in the second direction DR2.

[0141] The second color filter CF2 may be alternately arranged with another adjacent second color filter CF2 in a first direction DR1 and a second direction DR2, and may be alternately arranged with an adjacent first color filter CF1 and a third color filter CF3 in a fourth direction DR4 or a fifth direction DR5. A plurality of second color filters CF2 may be repeatedly arranged in the first direction DR1 and the second direction DR2, and the second color filter CF2 and the first color filter CF1 or the second color filter CF2 and the third color filter CF3 may be alternately arranged in the fourth direction DR4 or the fifth direction DR5. Regarding the arrangement of the color filters CF1, CF2, and CF3, the second color filter CF2 may be repeatedly arranged in the first direction DR1 in the second row R2 and the fourth row R4, and the second color filter CF2 may be repeatedly arranged in the second direction DR2 in the second column C2 and the fourth column C4.

[0142] According to an embodiment of the present disclosure, the color filters CF1, CF2, and CF3 may partially overlap each other. Although in the example shown in Figure 9 the adjacent color filters among the color filters CF1, CF2, and CF3 are in contact with each other, as will be described later in Figure 11 etc., the adjacent color filters among the color filters CF1, CF2, and CF3 may partially overlap each other at the boundary where they are in contact with each other. Figure 9 The arrangement of the color filters CF1, CF2, and CF3 when viewed from the top is shown. It will be understood that the edges of the underlying color filters CF1, CF2, and CF3 are hidden by the overlying color filters CF1, CF2, and CF3. Different color filters CF1, CF2, and CF3 may overlap each other on a light-blocking layer BM (see Figure 11 ) that will be described later and does not overlap with the emission regions EA1, EA2, and EA3.

[0143] In the display device 10, since the color filters CF1, CF2, and CF3 overlap each other, the intensity of the reflected light caused by external light can be reduced. In addition, the color of the reflected light due to external light can be controlled by adjusting the arrangement, shape, and area of the color filters CF1, CF2, and CF3 when viewed from the top. Therefore, since no separate optical film is provided on the display panel 100, the thickness of the display device 10 can be reduced. In addition, in the case where the display device 10 is a foldable device, the folding stress can be reduced.

[0144] The touch electrode TL may be disposed between the emission regions EA1, EA2, and EA3. The touch electrode TL may extend in a fourth direction DR4 and a fifth direction DR5, and may not overlap with and may be spaced apart from the emission regions EA1, EA2, and EA3. The touch electrode TL may overlap with a pixel defining layer PDL including openings OPE1, OPE2, and OPE3 (see Figure 11 ) and a light blocking layer BM including a plurality of holes OPT1_N, OPT1_P, OPT2_N, OPT2_P, OPT3_N, and OPT3_P (see Figure 11 ). Although the touch electrode TL is briefly shown in Figure 8 , the touch electrode TL may be a driving electrode TE or a sensing electrode RE of Figure 7 .

[0145] Figure 10 is a plan view showing an arrangement of a normal pixel NMP and a privacy pixel PVP in a display area DA of a display device 10 according to an embodiment (see Figure 8 ). Figure 11 is a cross-sectional view taken along line X1-X1' in Figure 10 . Figure 12 is a cross-sectional view taken along line X2-X2' of Figure 10 .

[0146] Combined with Figure 8 and Figure 9 Referring to Figures 10 to 12 , the display device 10 may include a normal mode and a privacy mode. The normal mode may be a driving mode in which the viewing angle is not controlled, and the privacy mode may be a driving mode in which the viewing angle is controlled. For example, in the normal mode, on a side with a viewing angle of 45 degrees with respect to the front of the display surface, the brightness ratio may be 20% or greater, while in the privacy mode, on a side with a viewing angle of 45 degrees with respect to the front of the display surface, the brightness ratio may be 10% or less. The numerical values of the viewing angle and the brightness ratio are merely illustrative and are not limited to the above values.

[0147] The display area DA may include a normal pixel NMP and a privacy pixel PVP. The normal pixel NMP and the privacy pixel PVP may be distinguished from each other based on whether they emit light in the privacy mode. For example, in the normal mode, both the normal pixel NMP and the privacy pixel PVP may emit light, while in the privacy mode, the normal pixel NMP may not emit light and only the privacy pixel PVP may emit light. As another example, in the normal mode, only the normal pixel NMP may emit light and the privacy pixel PVP may not emit light.

[0148] The normal pixels NMP and the privacy pixels PVP can be alternately arranged in a fourth direction DR4 and a fifth direction DR5. For example, the normal pixels NMP can be arranged in a first direction DR1 in a first pixel row PR1 and a third pixel row PR3, and the privacy pixels PVP can be arranged in a first direction DR1 in a second pixel row PR2. The privacy pixels PVP can be arranged in a second direction DR2 in a first pixel column PC1 and a third pixel column PC3, and the normal pixels NMP can be arranged in a second direction DR2 in a second pixel column PC2.

[0149] Each of the normal pixels NMP and the privacy pixels PVP can include emission regions EA1, EA2, and EA3. As described above, one first emission region EA1, two second emission regions EA2, and one third emission region EA3 can form a single pixel group. The single pixel group can be a normal pixel NMP or a privacy pixel PVP. Specifically, each of the normal pixels NMP and the privacy pixels PVP can include one first emission region EA1, two second emission regions EA2, and one third emission region EA3. However, it should be understood that the present disclosure is not limited thereto. The combination of the emission regions EA1, EA2, and EA3 forming the normal pixels NMP and the privacy pixels PVP can be modified according to the arrangement of the emission regions EA1, EA2, and EA3 and the color of the light emitted from the emission regions EA1, EA2, and EA3.

[0150] Hereinafter, reference will be made to Figure 11 describe the cross-sectional structure of the normal pixel NMP.

[0151] As Figure 11 shown in, the display panel 100 of the display device 10 can include a display layer DU, a touch sensing layer TSU, and a color filter layer CFL. The display layer DU can include a substrate SUB, a thin film transistor layer TFTL, an emission material layer EML, and a packaging layer TFEL. The display panel 100 can include a light blocking layer BM disposed on the touch sensing layer TSU, and color filters CF1, CF2, and CF3 of the color filter layer CFL can be disposed above the light blocking layer BM.

[0152] The substrate SUB can be a base substrate or a base member. The substrate SUB can be a flexible substrate that can be bent, folded, or curled. For example, the substrate SUB can include, but is not limited to, a polymer resin such as polyimide (PI). Again, for example, the substrate SUB can include a glass material or a metal material.

[0153] The thin film transistor layer TFTL may include a first buffer layer BF1, a bottom metal layer BML, a second buffer layer BF2, a thin film transistor TFT, a gate insulator GI, a first interlayer dielectric layer ILD1, a capacitor electrode CPE, a second interlayer dielectric layer ILD2, a first connection electrode CNE1, a first passivation layer PAS1, a second connection electrode CNE2, and a second passivation layer PAS2.

[0154] The first buffer layer BF1 may be disposed on a substrate SUB. The first buffer layer BF1 may include an inorganic film capable of preventing the penetration of air or moisture. For example, the first buffer layer BF1 may include a plurality of inorganic films stacked alternately with each other.

[0155] The bottom metal layer BML may be disposed on the first buffer layer BF1. For example, the bottom metal layer BML may be composed of a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and their alloys.

[0156] The second buffer layer BF2 may cover the first buffer layer BF1 and the bottom metal layer BML. The second buffer layer BF2 may include an inorganic film capable of preventing the penetration of air or moisture. For example, the second buffer layer BF2 may include a plurality of inorganic films stacked alternately with each other.

[0157] The thin film transistor TFT may be disposed on the second buffer layer BF2 and may form a pixel circuit for each of a plurality of pixels. For example, the thin film transistor TFT may be a driving transistor or a switching transistor of the pixel circuit. The thin film transistor TFT may include a semiconductor layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0158] The semiconductor layer ACT may be disposed on the second buffer layer BF2. The semiconductor layer ACT may overlap the bottom metal layer BML and the gate electrode GE in the thickness direction, and may be insulated from the gate electrode GE through the gate insulator GI. A part of the material of the semiconductor layer ACT may be made conductive to form the source electrode SE and the drain electrode DE.

[0159] The gate electrode GE may be disposed on the gate insulator GI. The gate electrode GE may overlap the semiconductor layer ACT and the gate insulator GI may be interposed between the gate electrode GE and the semiconductor layer ACT.

[0160] The gate insulator GI may be disposed on the semiconductor layer ACT. For example, the gate insulator GI may cover the semiconductor layer ACT and the second buffer layer BF2, and may insulate the semiconductor layer ACT from the gate electrode GE. The gate insulator GI may include a contact hole through which the first connection electrode CNE1 passes.

[0161] The first interlayer dielectric layer ILD1 may cover the gate electrode GE and the gate insulator GI. The first interlayer dielectric layer ILD1 may include contact holes through which the first connection electrode CNE1 passes. The contact holes of the first interlayer dielectric layer ILD1 may be connected to the contact holes of the gate insulator GI and the contact holes of the second interlayer dielectric layer ILD2.

[0162] The capacitor electrode CPE may be disposed on the first interlayer dielectric layer ILD1. The capacitor electrode CPE may overlap the gate electrode GE in the thickness direction. The capacitor electrode CPE and the gate electrode GE may form a capacitance.

[0163] The second interlayer dielectric layer ILD2 may cover the capacitor electrode CPE and the first interlayer dielectric layer ILD1. The second interlayer dielectric layer ILD2 may include contact holes through which the first connection electrode CNE1 passes. The contact holes of the second interlayer dielectric layer ILD2 may be connected to the contact holes of the first interlayer dielectric layer ILD1 and the contact holes of the gate insulator GI.

[0164] The first connection electrode CNE1 may be disposed on the second interlayer dielectric layer ILD2. The first connection electrode CNE1 may electrically connect the drain electrode DE of the thin film transistor TFT to the second connection electrode CNE2. The first connection electrode CNE1 may be inserted into the contact holes formed in the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, and the gate insulator GI to contact the drain electrode DE of the thin film transistor TFT.

[0165] The first passivation layer PAS1 may cover the first connection electrode CNE1 and the second interlayer dielectric layer ILD2. The first passivation layer PAS1 may protect the thin film transistor TFT. The first passivation layer PAS1 may include contact holes through which the second connection electrode CNE2 passes.

[0166] The second connection electrode CNE2 may be disposed on the first passivation layer PAS1. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 to the pixel electrode AE of the light emitting element ED. The second connection electrode CNE2 may be inserted into the contact holes formed in the first passivation layer PAS1 to contact the first connection electrode CNE1.

[0167] The second passivation layer PAS2 may cover the second connection electrode CNE2 and the first passivation layer PAS1. The second passivation layer PAS2 may include contact holes through which the pixel electrode AE of the light emitting diode ED passes.

[0168] The emission material layer EML may be disposed on the thin film transistor layer TFTL. The emission material layer EML may include a light emitting element ED and a pixel defining layer PDL. The light emitting element ED (sometimes referred to as a light emitting diode ED) may include a pixel electrode AE, an emission layer EL, and a common electrode CE.

[0169] The pixel electrode AE may be disposed on the second passivation layer PAS2. The pixel electrode AE may be disposed to overlap with one of the openings OPE1, OPE2, and OPE3 of the pixel defining layer PDL. The pixel electrode AE may be electrically connected to the drain electrode DE of the thin film transistor TFT through a first connection electrode CNE1 and a second connection electrode CNE2.

[0170] The emission layer EL may be disposed on the pixel electrode AE. The emission layer EL may be disposed in the openings OPE1, OPE2, and OPE3 of the pixel defining layer PDL. For example, the emission layer EL may be, but is not limited to, an organic emission layer made of an organic material. If the emission layer EL is an organic emission layer, when the thin film transistor TFT applies a predetermined voltage to the pixel electrode AE of the light emitting diode ED and the common electrode CE of the light emitting diode ED receives a common voltage or a cathode voltage, holes and electrons may move to the emission layer EL through a hole transport layer and an electron transport layer, respectively, and the holes and electrons recombine in the emission layer EL to emit light.

[0171] The common electrode CE may be disposed on the emission layer EL. For example, the common electrode CE may be implemented as an electrode shared by all pixels, rather than being disposed as a separate electrode for each of the pixels. The common electrode CE may be disposed on the emission layer EL in the first emission region EA1, the second emission region EA2, and the third emission region EA3, and may be disposed on the pixel defining layer PDL in other regions outside the first emission region EA1, the second emission region EA2, and the third emission region EA3.

[0172] The common electrode CE may receive a common voltage or a low level voltage. When the pixel electrode AE receives a voltage equal to the data voltage and the common electrode CE receives a low level voltage, a potential difference is formed between the pixel electrode AE and the common electrode CE, so that the emission layer EL can emit light.

[0173] The pixel defining layer PDL may include a plurality of openings OPE1, OPE2, and OPE3, and may be disposed on the second passivation layer PAS2 and a part of the pixel electrode AE. The pixel defining layer PDL may include a first opening OPE1, a second opening OPE2, and a third opening OPE3, and each of the openings OPE1, OPE2, and OPE3 extends to a part of the pixel electrode AE. As described above, the openings OPE1, OPE2, and OPE3 of the pixel defining layer PDL may respectively define a first emission region EA1, a second emission region EA2, and a third emission region EA3, and the first emission region EA1, the second emission region EA2, and the third emission region EA3 may have different areas or sizes. The pixel defining layer PDL may separate and insulate the pixel electrode AE of one light emitting diode among the plurality of light emitting diodes ED from the pixel electrode AE of another light emitting diode among the plurality of light emitting diodes ED. The pixel defining layer PDL may include a light absorbing material to prevent light reflection. For example, the pixel defining layer PDL may include a polyimide (PI)-based binder and a pigment in which red, green, and blue are mixed. In an embodiment, the pixel defining layer PDL may include a cardo-based binder resin and a mixture of a lactam black pigment and a blue pigment. In an embodiment, the pixel defining layer PDL may include carbon black.

[0174] The encapsulation layer TFEL may be disposed on the common electrode CE to cover the light emitting element ED. The encapsulation layer TFEL may include at least one inorganic layer to prevent oxygen or moisture from penetrating into the emission material layer EML. The encapsulation layer TFEL may include at least one organic layer to protect the emission material layer EML from foreign substances such as dust.

[0175] According to an embodiment of the present disclosure, the encapsulation layer TFEL may include a first encapsulation layer TFE1, a second encapsulation layer TFE2, and a third encapsulation layer TFE3. The first encapsulation layer TFE1 and the third encapsulation layer TFE3 may be inorganic encapsulation layers, and the second encapsulation layer TFE2 disposed between the first encapsulation layer TFE1 and the third encapsulation layer TFE3 may be an organic encapsulation layer.

[0176] Each of the first encapsulation layer TFE1 and the third encapsulation layer TFE3 may include one or more inorganic insulating materials. The inorganic insulating materials may include alumina, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0177] The second encapsulation layer TFE2 may include a polymeric material. The polymeric material may include acrylic resins, epoxy resins, polyimides, polyethylene, etc. For example, the second encapsulation layer TFE2 may include an acrylic resin (e.g., polymethyl methacrylate, polyacrylic acid, etc.). The second encapsulation layer TFE2 may be formed by curing monomers or by applying a polymer.

[0178] The touch sensing layer TSU may be disposed on the encapsulation layer TFEL. The touch sensing layer TSU may include a first touch insulation layer SIL1, a second touch insulation layer SIL2, a touch electrode TL, and a third touch insulation layer SIL3.

[0179] The first touch insulation layer SIL1 may be disposed on the encapsulation layer TFEL. The first touch insulation layer SIL1 may have insulation properties and optical characteristics. The first touch insulation layer SIL1 may include at least one inorganic film. Optionally, the first touch insulation layer SIL1 may be removed.

[0180] The second touch insulation layer SIL2 may cover the first touch insulation layer SIL1. Although not shown in the drawings, touch electrodes of another layer may be further disposed on the first touch insulation layer SIL1, and the second touch insulation layer SIL2 may cover such touch electrodes. The second touch insulation layer SIL2 may have insulation properties and optical characteristics. For example, the second touch insulation layer SIL2 may be an inorganic layer including at least one selected from the group consisting of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0181] Some of the touch electrodes TL may be disposed on the second touch insulation layer SIL2. The touch electrodes TL may not overlap with the first emission region EA1, the second emission region EA2, and the third emission region EA3. Each of the touch electrodes TL may be composed of a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or indium tin oxide (ITO), or may be composed of a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, and a stacked structure of an APC alloy and ITO (ITO / APC / ITO).

[0182] The third touch insulation layer SIL3 may cover the touch electrodes TL and the second touch insulation layer SIL2. The third touch insulation layer SIL3 may have insulation properties and optical characteristics. The third touch insulation layer SIL3 may be made of one of the materials listed above as the material of the second touch insulation layer SIL2.

[0183] The light blocking layer BM may be disposed on the third touch insulating layer SIL3 of the touch sensing layer TSU. The light blocking layer BM may be disposed to cover the conductive lines of the touch electrodes TL and may include a plurality of holes OPT1_N, OPT2_N, and OPT3_N respectively disposed in the emission regions EA1, EA2, and EA3. For example, the first hole OPT1_N may overlap with the first emission region EA1 or the first opening OPE1, the second hole OPT2_N may overlap with the second emission region EA2 or the second opening OPE2, and the third hole OPT3_N may overlap with the third emission region EA3 or the third opening OPE3. The area or size of the holes OPT1_N, OPT2_N, and OPT3_N may be greater than the area or size of the openings OPE1, OPE2, and OPE3 of the pixel defining layer PDL. Since the holes OPT1_N, OPT2_N, and OPT3_N of the light blocking layer BM are larger than the openings OPE1, OPE2, and OPE3 of the pixel defining layer PDL, a user can see the light output from the emission regions EA1, EA2, and EA3 not only from the front but also from the side of the display device 10.

[0184] The light blocking layer BM may include a light absorbing material. For example, the light blocking layer BM may include an inorganic black pigment or an organic black pigment. The inorganic black pigment may be, but is not limited to, carbon black, and the organic black pigment may include at least one of, but is not limited to, lactam black, perylene black, and aniline black. The light blocking layer BM may prevent visible light from penetrating and mixing colors between the first emission region EA1, the second emission region EA2, and the third emission region EA3 to improve the color gamut of the display device 10.

[0185] The color filters CF1, CF2, and CF3 of the color filter layer CFL may be disposed on the light blocking layer BM. Different color filters CF1, CF2, and CF3 may be disposed to overlap with different emission regions EA1, EA2, and EA3 or openings OPE1, OPE2, and OPE3 and the holes OPT1_N, OPT2_N, and OPT3_N of the light blocking layer BM respectively. For example, the first color filter CF1 may overlap with the first emission region EA1, the second color filter CF2 may overlap with the second emission region EA2, and the third color filter CF3 may overlap with the third emission region EA3. The first color filter CF1 may be disposed in the first hole OPT1_N of the light blocking layer BM, the second color filter CF2 may be disposed in the second hole OPT2_N of the light blocking layer BM, and the third color filter CF3 may be disposed in the third hole OPT3_N of the light blocking layer BM. The color filters CF1, CF2, and CF3 may have a larger area than the holes OPT1_N, OPT2_N, and OPT3_N of the light blocking layer BM when viewed from the top, and some of the color filters CF1, CF2, and CF3 may be directly disposed on the light blocking layer BM.

[0186] The color filters CF1, CF2, and CF3 of the display device 10 may be arranged to overlap with other adjacent color filters CF1, CF2, and CF3 on the light blocking layer BM. The color filters CF1, CF2, and CF3 provided on the light blocking layer BM may be arranged such that two adjacent color filters among the color filters CF1, CF2, and CF3 completely cover the light blocking layer BM. Two adjacent color filters among the color filters CF1, CF2, and CF3 may be arranged to partially overlap each other on the light blocking layer BM. Since these color filters CF1, CF2, and CF3 overlap each other, the reflection of external light caused by the light blocking layer BM can be further reduced.

[0187] The planarization layer OC may be provided on the color filters CF1, CF2, and CF3 to provide a flat upper end portion of the color filters CF1, CF2, and CF3. The planarization layer OC may be a colorless light-transmitting layer that does not have a color in the visible light range. For example, the planarization layer OC may include a colorless light-transmitting organic material such as an acrylic resin.

[0188] Hereinafter, Figure 12 the cross-sectional structure of the privacy pixel PVP will be described. In the following description, configurations that are the same as the cross-sectional structure of the conventional pixel NMP described above Figure 11 will not be described or will be briefly described. The description will focus on the differences.

[0189] In the privacy pixel PVP, the second passivation layer PAS2 may include a plurality of connection openings OPP1, OPP2, and OPP3 that overlap the plurality of openings OPE1, OPE2, and OPE3 or the emission regions EA1, EA2, and EA3 of the pixel definition layer PDL. For example, the first connection opening OPP1 may overlap the first emission region EA1 or the first opening OPE1, the second connection opening OPP2 may overlap the second emission region EA2 or the second opening OPE2, and the third connection opening OPP3 may overlap the third emission region EA3 or the third opening OPE3.

[0190] In the privacy pixel PVP, the second passivation layer PAS2 may be included in the emission material layer EML. The connection openings OPP1, OPP2, and OPP3 of the second passivation layer PAS2 may be respectively connected to the plurality of openings OPE1, OPE2, and OPE3 of the pixel definition layer PDL to form a single opening. For example, the first connection opening OPP1 may be connected to the first opening OPE1 to form a single opening, the second connection opening OPP2 may be connected to the second opening OPE2 to form a single opening, and the third connection opening OPP3 may be connected to the third opening OPE3 to form a single opening.

[0191] The openings formed by connecting the connection openings OPP1, OPP2, and OPP3 of the second passivation layer PAS2 to the plurality of openings OPE1, OPE2, and OPE3 of the pixel definition layer PDL can extend to respective portions of the pixel electrode AE and expose the respective portions of the pixel electrode AE.

[0192] In the privacy pixel PVP, the emission material layer EML can be disposed on the first passivation layer PAS1. The pixel electrode AE can be disposed on the first passivation layer PAS1. The pixel electrode AE can overlap with one of the openings OPE1, OPE2, and OPE3 of the pixel definition layer PDL, and can overlap with one of the connection openings OPP1, OPP2, and OPP3 of the second passivation layer PAS2.

[0193] According to an embodiment of the present disclosure, the second connection electrode CNE2 can be removed in the privacy pixel PVP. The pixel electrode AE can be electrically connected to the drain electrode DE of the thin film transistor TFT through the first connection electrode CNE1.

[0194] The emission layer EL can be disposed in each of the openings formed by connecting the connection openings OPP1, OPP2, and OPP3 of the second passivation layer PAS2 to the openings OPE1, OPE2, and OPE3 of the pixel definition layer PDL. Although the upper surface of the emission layer EL is lower than the upper surface of the second passivation layer PAS2 in the drawings, the present disclosure is not limited thereto. For example, the upper surface of the emission layer EL can be higher than the upper surface of the second passivation layer PAS2, and the upper surface of the emission layer EL can be positioned in each of the openings OPE1, OPE2, and OPE3 of the pixel definition layer PDL.

[0195] The common electrode CE can cover the inner surfaces of the openings OPE1, OPE2, and OPE3 of the pixel definition layer PDL and the inner surfaces of the connection openings OPP1, OPP2, and OPP3 of the second passivation layer PAS2. For example, at least a portion of the common electrode CE that overlaps with the first emission region EA1 can cover the inner surface of the first connection opening OPP1.

[0196] At least a portion of the first encapsulation layer TFE1 and at least a portion of the second encapsulation layer TFE2 can be disposed in the openings formed by connecting the connection openings OPP1, OPP2, and OPP3 of the second passivation layer PAS2 to the openings OPE1, OPE2, and OPE3 of the pixel definition layer PDL.

[0197] In the privacy pixel PVP, the light blocking layer BM may include a plurality of holes OPT1_P, OPT2_P, and OPT3_P that respectively overlap with the emission regions EA1, EA2, and EA3. For example, the fourth hole OPT1_P may overlap with the first emission region EA1 or the first opening OPE1, the fifth hole OPT2_P may overlap with the second emission region EA2 or the second opening OPE2, and the sixth hole OPT3_P may overlap with the third emission region EA3 or the third opening OPE3. The area or size of the holes OPT1_P, OPT2_P, and OPT3_P may be larger than the area or size of the openings OPE1, OPE2, and OPE3 of the pixel defining layer PDL. Since the holes OPT1_P, OPT2_P, and OPT3_P of the light blocking layer BM are larger than the openings OPE1, OPE2, and OPE3 of the pixel defining layer PDL, a user can see the light output from the emission regions EA1, EA2, and EA3 not only from the front of the display device 10 but also from the side of the display device 10.

[0198] According to some embodiments, the widths of the holes OPT1_P, OPT2_P, and OPT3_P of the light blocking layer BM in the privacy pixel PVP may be smaller than the widths of the holes OPT1_N, OPT2_N, and OPT3_N of the light blocking layer BM in the conventional pixel NMP. For example, the width W4 of the fourth hole OPT1_P may be smaller than the width W1 of the first hole OPT1_N, the width W5 of the fifth hole OPT2_P may be smaller than the width W2 of the second hole OPT2_N, and the width W6 of the sixth hole OPT3_P may be smaller than the width W3 of the third hole OPT3_N.

[0199] In the display device 10 according to the present embodiment, since the widths of the holes OPT1_P, OPT2_P, and OPT3_P of the light blocking layer BM in the privacy pixel PVP are smaller than the widths of the holes OPT1_N, OPT2_N, and OPT3_N of the light blocking layer BM in the conventional pixel NMP, the brightness of the light emitted at a certain angle or higher angle on the side can be reduced, and thus the viewing angle of the display device 10 can be reduced.

[0200] Incidentally, in the display device 10 according to the present embodiment, by adjusting the distance between the light blocking layer BM and the emission layer EL (e.g., the distance in the third direction DR3), the viewing angle of the display device 10 can be further reduced. Therefore, even in a high-resolution display device 10, the viewing angle can be adjusted regardless of the widths of the holes OPT1_P, OPT2_P, and OPT3_P in the light blocking layer BM. This will be described below with reference to Figure 13 This will be described.

[0201] Figure 13 is along Figure 10Cross-sectional views taken along lines X3-X3' and X4-X4' in

[0202] Combined with Figures 10 to 12 Refer to Figure 13 , since the display device 10 (refer to Figure 8 ) includes a first connection opening OPP1 of the second passivation layer PAS2, the emission layer EL in the privacy pixel PVP can be positioned lower than the emission layer EL in the normal pixel NMP. For example, the emission layer EL in the privacy pixel PVP can be positioned lower than the emission layer EL in the normal pixel NMP by a first height H1.

[0203] The distance between the emission layer EL and the light blocking layer BM in the privacy pixel PVP can be greater than the distance between the emission layer EL and the light blocking layer BM in the normal pixel NMP. The maximum viewing angle of the light emitted from the emission layer EL of the normal pixel NMP can be a first angle θ1. The maximum viewing angle of the light emitted from the emission layer EL of the privacy pixel PVP can be a second angle θ2. The second angle θ2 can be less than the first angle θ1.

[0204] In the display device 10 according to the present embodiment, the light emitting element ED in the privacy pixel PVP is positioned lower than the light emitting element ED in the normal pixel NMP, so that a driving mode with different viewing angles can be achieved using one light blocking layer BM. Therefore, no separate louver or additional second light blocking layer is required on the light blocking layer BM to control the viewing angle, and thus the process efficiency can be improved and the thickness of the display device 10 can be reduced.

[0205] Hereinafter, a display device according to other exemplary embodiments of the present disclosure will be described. In the following description, the same or similar elements will be denoted by the same or similar reference numerals, and redundant descriptions will be omitted or briefly described.

[0206] Refer to Figures 14 to 18 , Figure 14 is a cross-sectional view showing an emission region EA1 in the privacy pixel PVP of the display device 10 according to an embodiment. Although Figure 14 shows the first emission region EA1 as an example, it will be understood that the same technical concept can be applied to the second emission region EA2 and the third emission region EA3.

[0207] Figure 14 The display device 10 according to the present embodiment of Figure 12 etc. is different from the display device 10 according to the embodiment in that the first passivation layer PAS1 includes a fourth connection opening OPQ1.

[0208] More specifically, in the privacy pixel PVP, the first passivation layer PAS1 may include a fourth connection opening OPQ1 that overlaps with the first opening OPE1 of the pixel definition layer PDL and the first connection opening OPP1 of the second passivation layer PAS2.

[0209] In the privacy pixel PVP, the first passivation layer PAS1 may be included in the emission material layer EML. The fourth connection opening OPQ1 of the first passivation layer PAS1 may be connected to the first opening OPE1 of the pixel definition layer PDL and the first connection opening OPP1 of the second passivation layer PAS2 to form a single opening.

[0210] The opening formed by connecting the fourth connection opening OPQ1 of the first passivation layer PAS1 with the first connection opening OPP1 of the second passivation layer PAS2 and the first opening OPE1 of the pixel definition layer PDL may extend to a part of the pixel electrode AE and expose the said part of the pixel electrode AE.

[0211] In the privacy pixel PVP, the emission material layer EML may be disposed on the second interlayer dielectric layer ILD2. The pixel electrode AE may be disposed on the second interlayer dielectric layer ILD2. The pixel electrode AE may overlap with the first opening OPE1 of the pixel definition layer PDL, may overlap with the first connection opening OPP1 of the second passivation layer PAS2, and may overlap with the fourth connection opening OPQ1 of the first passivation layer PAS1.

[0212] According to an embodiment of the present disclosure, the first connection electrode CNE1 may be removed in the privacy pixel PVP. The pixel electrode AE may be directly electrically connected to the drain electrode DE of the thin film transistor TFT.

[0213] The emission layer EL may be disposed in the opening formed by connecting the fourth connection opening OPQ1 of the first passivation layer PAS1 with the first connection opening OPP1 of the second passivation layer PAS2 and the first opening OPE1 of the pixel definition layer PDL. Although the upper surface of the emission layer EL is lower than the upper surface of the first passivation layer PAS1 in the drawings, the present disclosure is not limited thereto. For example, the upper surface of the emission layer EL may be higher than the upper surface of the first passivation layer PAS1, and the upper surface of the emission layer EL may be positioned in the first connection opening OPP1 of the second passivation layer PAS2 or may be positioned in the first opening OPE1 of the pixel definition layer PDL.

[0214] The common electrode CE may cover the inner surface of the first opening OPE1 of the pixel definition layer PDL, the inner surface of the first connection opening OPP1 of the second passivation layer PAS2, and the inner surface of the fourth connection opening OPQ1 of the first passivation layer PAS1.

[0215] At least a part of the first encapsulation layer TFE1 and at least a part of the second encapsulation layer TFE2 may be disposed in an opening formed by connecting a fourth connection opening OPQ1 of the first passivation layer PAS1, a first connection opening OPP1 of the second passivation layer PAS2, and a first opening OPE1 of the pixel definition layer PDL.

[0216] In the display device 10 according to the present embodiment, the difference between the distance from the emission layer EL to the light blocking layer BM in the privacy pixel PVP and the distance from the emission layer EL to the light blocking layer BM in the normal pixel NMP may be greater than the difference between the distance from the emission layer EL to the light blocking layer BM in the privacy pixel PVP and the distance from the emission layer EL to the light blocking layer BM in the normal pixel NMP in the display device 10 described above with reference to Figure 13 etc. In the display device 10 according to the present embodiment, the maximum viewing angle of the light emitted from the emission layer EL in the privacy pixel PVP may be a third angle θ3. The third angle θ3 may be smaller than the second angle θ2 (see Figure 13 ). Accordingly, the viewing angle of the display device 10 may be further reduced.

[0217] Figure 15 is a cross-sectional view showing an emission region EA1 of a privacy pixel PVP of a display device 10 according to an embodiment. Although Figure 15 the first emission region EA1 is shown as an example, it will be understood that the same technical idea may be applied to the second emission region EA2 and the third emission region EA3.

[0218] Figure 15 The display device 10 according to an embodiment of Figure 12 etc. is different from the display device 10 according to an embodiment of

[0219] in that the second passivation layer PAS2 includes a peak CRS and a valley VAL.

[0220] More specifically, in the privacy pixel PVP, the second passivation layer PAS2 may include a valley VAL overlapping with the first opening OPE1 of the pixel definition layer PDL and a peak CRS disposed on one side of the valley VAL. The thickness TH1 of the valley VAL may be smaller than the thickness TH2 of the peak CRS. The upper surface of the valley VAL may be lower than the upper surface of the peak CRS.

[0221] In the privacy pixel PVP, the second passivation layer PAS2 may be included in the emission material layer EML. The valley VAL of the second passivation layer PAS2 may be connected to the first opening OPE1 of the pixel definition layer PDL to form a recessed portion.

[0222] The recessed portion formed by connecting the valley VAL of the second passivation layer PAS2 to the first opening OPE1 of the pixel definition layer PDL may extend to a part of the pixel electrode AE and expose the said part of the pixel electrode AE.

[0223] In the privacy pixel PVP, the emission material layer EML may be disposed on the first passivation layer PAS1. The pixel electrode AE may be disposed on the valley VAL of the second passivation layer PAS2. The pixel electrode AE may overlap with the first opening OPE1 of the pixel definition layer PDL and may overlap with the valley VAL of the second passivation layer PAS2. According to an embodiment of the present disclosure, the pixel electrode AE of the privacy pixel PVP may be electrically connected to the drain electrode DE of the thin film transistor TFT through the first connection electrode CNE1 and the second connection electrode CNE2.

[0224] The emission layer EL may be disposed in the recessed portion formed by connecting the valley VAL of the second passivation layer PAS2 to the first opening OPE1 of the pixel definition layer PDL. Although the upper surface of the emission layer EL is higher than the upper surface of the peak CRS of the second passivation layer PAS2 in the drawings, the present disclosure is not limited thereto. For example, the upper surface of the emission layer EL may be positioned lower than the upper surface of the peak CRS of the second passivation layer PAS2.

[0225] The common electrode CE may cover the inner surface of the first opening OPE1 of the pixel definition layer PDL. Although not shown in the drawings, in some embodiments, the common electrode CE may cover the side surface of the second passivation layer PAS2 positioned between the peak CRS and the valley VAL.

[0226] At least a part of the first encapsulation layer TFE1 and at least a part of the second encapsulation layer TFE2 may be disposed in the recessed portion formed by connecting the valley VAL of the second passivation layer PAS2 to the first opening OPE1 of the pixel definition layer PDL.

[0227] The display device 10 according to the present embodiment may adjust the distance between the emission layer EL and the light blocking layer BM by adjusting the thicknesses of the peak CRS and the valley VAL of the second passivation layer PAS2 using a halftone mask. Therefore, the viewing angle of the display device 10 may be adjusted as desired.

[0228] In some embodiments, although not shown in the drawings, the second passivation layer PAS2 may include a first connection opening OPP1 (see Figure 14), and the first passivation layer PAS1 may include a valley VAL. In this case, the first opening OPE1 of the pixel defining layer PDL, the first connection opening OPP1 of the second passivation layer PAS2 (see Figure 14 ) and the valley VAL of the first passivation layer PAS1 may form a single recessed portion.

[0229] Figure 16 is a cross-sectional view showing a privacy pixel PVP in the display device 10 according to an embodiment of the present disclosure.

[0230] Figure 16 The display device 10 according to an embodiment of Figure 12 etc. is different from the display device 10 according to an embodiment in that the emission layer EL has different horizontal levels in different emission regions EA1, EA2, and EA3.

[0231] More specifically, the emission layer EL of the first emission region EA1 according to the present embodiment may be positioned at the same horizontal level as the emission layer EL of the privacy pixel PVP described above with reference to Figure 12 and Figure 13 etc. The emission layer EL of the second emission region EA2 according to the present embodiment may be positioned at the same horizontal level as the emission layer EL described above with reference to Figure 14 described. The emission layer EL of the third emission region EA3 according to the present embodiment may be positioned at the same horizontal level as the emission layer EL described above with reference to Figure 15 described.

[0232] The second passivation layer PAS2 of the first emission region EA1 may include a first connection opening OPP1. The second passivation layer PAS2 of the second emission region EA2 may include a second connection opening OPP2, and the first passivation layer PAS1 of the second emission region EA2 may include a fifth connection opening OPQ2. The second passivation layer PAS2 of the third emission region EA3 may include a valley VAL and a peak CRS.

[0233] Although in the drawings, the emission layer EL of the first emission region EA1 is positioned at the same horizontal level as the emission layer EL of the privacy pixel PVP of the embodiments of Figure 12 and Figure 13 , the emission layer EL of the second emission region EA2 is positioned at the same horizontal level as the emission layer EL of the embodiments of Figure 14 , and the emission layer EL of the third emission region EA3 is positioned at the same horizontal level as the emission layer EL of the embodiments of Figure 15 , but the present disclosure is not limited thereto. As an example, the emission layer EL in all the emission regions EA1, EA2, and EA3 may be the same as that of the embodiments of Figure 12 and Figure 13 embodiments,Figure 14 and embodiments of Figure 15 in one of the embodiments, the emission layer EL is positioned at the same horizontal height. As another example, the emission layer EL of the first emission region EA1 may be Figure 14 positioned at the same horizontal height as the emission layer EL of the embodiment of Figure 15 the emission layer EL of the second emission region EA2 may be positioned at the same horizontal height as the emission layer EL of the embodiment of Figure 12 and Figure 13 the emission layer EL of the privacy pixel PVP of the embodiment of

[0234] According to this embodiment, the viewing angle can be adjusted by precisely adjusting the horizontal height of the emission layer EL in each of the emission regions EA1, EA2, and EA3, and the color position on color coordinates such as CIE 1931 can be adjusted independently.

[0235] Figure 17 is a plan view showing the arrangement of the color filters CF1, CF2, and CF3 in the display area DA of the display device 10 according to an embodiment.

[0236] Figure 17 The display device 10 according to an embodiment of Figure 9 etc. is different from the display device 10 described above in that the color filters CF1, CF2, and CF3 have the same area.

[0237] More specifically, in the display device 10 according to this embodiment, the areas of the color filters CF1, CF2, and CF3 may all be equal. Although not shown in the drawings, adjacent color filters among the color filters CF1, CF2, and CF3 may partially overlap each other on the light blocking layer BM. In addition, the areas of the color filters CF1, CF2, and CF3 may be designed according to the colors required by the display device 10 or the electronic device 1 so as to obtain the desired values of the intensity and color of the reflected light from the outside.

[0238] In the display device 10 according to this embodiment, the first color filter CF1, the second color filter CF2, and the third color filter CF3 may have the same area, and the sides extending in the fourth direction DR4 and the fifth direction DR5 may have the same shape. Therefore, the first color filter CF1, the second color filter CF2, and the third color filter CF3 may have the same shape and area regardless of their positions.

[0239] Figure 18 is a plan view showing the arrangement of the color filters CF1, CF2, and CF3 in the display area DA of the display device 10 according to an embodiment.

[0240] Figure 18 The display device 10 according to an embodiment is different from the display device 10 described above with reference to Figure 9 etc. in that the color filters CF1, CF2, and CF3 have different shapes when viewed from the top.

[0241] More specifically, in the display device 10 according to the present embodiment, the second color filter CF2 and the third color filter CF3 have a circular shape when viewed from the top, and the first color filter CF1 can be entirely disposed on the light blocking layer BM and the first emission region EA1.

[0242] For example, the first color filter CF1 may include holes overlapping with the second emission region EA2 and the third emission region EA3, the second color filter CF2 may be disposed to overlap with the second emission region EA2, and the third color filter CF3 may be disposed to overlap with the third emission region EA3.

[0243] Similar to Figure 17 the embodiment of, the areas of the color filters CF1, CF2, and CF3 can be designed according to the colors required by the display device 10 or the electronic device 1 so as to obtain an expected value for the intensity and color of the reflected light from the outside.

[0244] At the end of the detailed description, those skilled in the art will appreciate that many changes and modifications can be made to the embodiments without substantially departing from the principles of the present disclosure. Therefore, the disclosed embodiments are used only in a general and descriptive sense and not for the purpose of limitation.

Claims

1. A display device, wherein, The display device includes: a first pixel and a second pixel, the first pixel and the second pixel being spaced apart from each other, wherein each of the first pixel and the second pixel includes: a plurality of emission regions, a plurality of light-emitting elements being disposed in the plurality of emission regions; a light-blocking layer including a plurality of holes overlapping with the plurality of emission regions, and the light-blocking layer being disposed between adjacent emission regions among the plurality of emission regions; and a plurality of color filters disposed in the plurality of holes of the light-blocking layer and overlapping with the plurality of emission regions, wherein the plurality of emission regions include a first emission region, a second emission region, and a third emission region spaced apart from each other, and wherein the light-emitting elements of the plurality of light-emitting elements of the first pixel disposed in the first emission region are positioned at a lower level height than the light-emitting elements of the plurality of light-emitting elements of the second pixel disposed in the first emission region.

2. The display device according to claim 1, wherein, The distance between the light-emitting element of the first pixel disposed in the first emission region and the light-blocking layer is greater than the distance between the light-emitting element of the second pixel disposed in the first emission region and the light-blocking layer.

3. The display device according to claim 2, wherein, In the first pixel and the second pixel respectively, the plurality of holes of the light-blocking layer include a first hole, a second hole, and a third hole overlapping with the first emission region, the second emission region, and the third emission region respectively, and wherein the width of the first hole of the first pixel is smaller than the width of the first hole of the second pixel.

4. The display device according to claim 1, wherein Each of the first pixel and the second pixel further includes: a thin-film transistor layer configured to drive the plurality of light-emitting elements; a first protective film disposed on the thin-film transistor layer; and a pixel defining layer disposed on the first protective film and including openings overlapping with corresponding ones of the plurality of emission regions, and wherein the first protective film further includes a first connection opening connected to the opening of the pixel defining layer in the first pixel.

5. The display device according to claim 4, wherein, In the first pixel and the second pixel respectively, each of the plurality of light-emitting elements includes an emission layer, and wherein the emission layer is disposed in the first connection opening in the first pixel.

6. The display device according to claim 5, wherein, Each of the plurality of light-emitting elements in the second pixel is disposed on the first protective film.

7. The display device according to claim 6, wherein, The emission layer in the second pixel is disposed in the opening of the pixel defining layer.

8. The display device according to claim 4, wherein, In the first pixel and the second pixel respectively, each of the plurality of light-emitting elements includes a first electrode, an emission layer disposed on the first electrode, and a second electrode disposed on the emission layer, and wherein the second electrode covers an inner surface of the first connection opening in the first pixel.

9. The display device according to claim 8, wherein, Each of the first pixel and the second pixel further includes: a thin-film encapsulation layer disposed on the second electrode, wherein at least a part of the thin-film encapsulation layer is disposed in the first connection opening in the first pixel.

10. The display device according to claim 4, wherein, Each of the first pixel and the second pixel further includes: A second protective film is disposed between the first protective film and the thin film transistor layer. Wherein, in the first pixel and the second pixel respectively, the second protective film includes second connection openings that are connected to the openings through the first connection openings. Wherein, in the first pixel and the second pixel respectively, each of the plurality of light-emitting elements includes an emission layer, and wherein, in the first pixel, the emission layer is disposed in the second connection openings.

11. The display device according to claim 1, wherein, Each of the first pixel and the second pixel further includes: A thin film transistor layer configured to drive the plurality of light-emitting elements; A first protective film disposed on the thin film transistor layer; and A pixel defining layer disposed on the first protective film and including openings overlapping corresponding ones of the plurality of emission regions. Wherein, in the first pixel, the first protective film includes valleys connected to the openings of the pixel defining layer.

12. The display device according to claim 11, wherein, Wherein, in the first pixel and the second pixel respectively, each of the plurality of light-emitting elements includes an emission layer, and wherein, in the first pixel, the emission layer is disposed in the valleys.

13. The display device according to claim 1, wherein, Wherein, in the first pixel and the second pixel respectively, the plurality of color filters include a first color filter overlapping the first emission region, a second color filter overlapping the second emission region, and a third color filter overlapping the third emission region.

14. A display device, wherein, The display device includes: A plurality of emission regions in which a plurality of light-emitting elements are disposed; A light-blocking layer including a plurality of holes overlapping the plurality of emission regions, and the light-blocking layer is disposed between adjacent ones of the plurality of emission regions; and A plurality of color filters disposed in the plurality of holes of the light-blocking layer and overlapping the plurality of emission regions. Wherein, the plurality of emission regions include a first emission region and a second emission region spaced apart from each other. Wherein, the first emission region and the second emission region emit light of the same color, and wherein, the light-emitting elements disposed in the first emission region among the plurality of light-emitting elements are positioned lower than the light-emitting elements disposed in the second emission region among the plurality of light-emitting elements.

15. The display device according to claim 14, wherein, The distance between the light-emitting elements disposed in the first emission region and the light-blocking layer is greater than the distance between the light-emitting elements disposed in the second emission region and the light-blocking layer.

16. The display device according to claim 15, wherein, The plurality of holes in the light-blocking layer include a first hole overlapping the first emission region and a second hole overlapping the second emission region, and wherein, the width of the first hole is smaller than the width of the second hole.

17. The display device according to claim 14, wherein, The display device further includes: A thin film transistor layer configured to drive the plurality of light-emitting elements; A first protective film disposed on the thin film transistor layer; and A pixel defining layer disposed on the first protective film and including openings overlapping corresponding ones of the plurality of emission regions. Wherein, the first protective film includes a first connection opening that overlaps the first emission region and is connected to the opening of the pixel defining layer.

18. The display device according to claim 17, wherein, Each of the plurality of light-emitting elements includes an emission layer, and wherein, the emission layer overlapping with the first emission region is disposed in the first connection opening.

19. The display device according to claim 18, wherein, The light-emitting element disposed in the second emission region is disposed on the first protective film.

20. The display device according to claim 19, wherein, The emission layer overlapping with the second emission region is disposed in the opening of the pixel defining layer.

21. The display device according to claim 17, wherein, Each of the plurality of light-emitting elements includes a first electrode, an emission layer disposed on the first electrode, and a second electrode disposed on the emission layer, and wherein, at least a part of the second electrode overlapping with the first emission region covers an inner surface of the first connection opening.

22. The display device according to claim 21, wherein, The display device further includes: a thin film encapsulation layer disposed on the second electrode, wherein, at least a part of the thin film encapsulation layer overlapping with the first emission region is disposed in the first connection opening.

23. The display device according to claim 17, wherein The display device further includes: a second protective film disposed between the first protective film and the thin film transistor layer, wherein, the second protective film includes a second connection opening connected to the opening through the first connection opening, wherein, each of the plurality of light-emitting elements includes an emission layer, and wherein, the emission layer overlapping with the first emission region is disposed in the second connection opening.

24. The display device according to claim 14, wherein, The display device further includes: a thin film transistor layer configured to drive the plurality of light-emitting elements; a first protective film disposed on the thin film transistor layer; and a pixel defining layer disposed on the first protective film and including an opening overlapping with a corresponding emission region of the plurality of emission regions, and wherein, the first protective film includes a valley overlapping with the first emission region and the valley is connected to the opening of the pixel defining layer.

25. The display device according to claim 24, wherein, Each of the plurality of light-emitting elements includes an emission layer, and wherein, the emission layer overlapping with the first emission region is disposed in the valley.

26. The display device according to claim 14, wherein, The plurality of color filters include a first color filter overlapping with the first emission region and a second color filter overlapping with the second emission region, and wherein, the first color filter and the second color filter transmit light of the same color.

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