Module, device and method for carrying out linear power amplification by using class AB power amplifier and non-instantaneous computer readable storage medium

Abstract

The linear power amplifier module has: a splitter for splitting an input signal into a plurality of split signals; a plurality of circuit branches connected to the splitter, each circuit branch for receiving one of the plurality of shunt signals; and an output terminal connected to the plurality of circuit branches for combining outputs of the plurality of circuit branches and outputting an output signal. Each circuit branch is configured to receive one of the plurality of shunt signals, each circuit branch comprising a class AB PA operable at a bias voltage, the one or more circuit branches each comprising a respective control circuit connected to an input of its class AB PA.

Description

Technical Field

[0001] The present disclosure generally relates to modules, devices, methods, and non-transitory computer-readable storage media for linear power amplification, and more particularly to modules, devices, methods, and non-transitory computer-readable storage media for linear power amplification using class-AB power amplifiers. Background Art

[0002] Wireless communication systems such as millimeter-wave (mmWave) fifth-generation (5G) systems, sixth-generation (6G) systems, etc. typically employ phased arrays with high-order quadrature amplitude modulation (QAM) to overcome high path losses in free space and provide high data throughput and low latency. Such systems typically require amplitude adjustment and / or power attenuation of signals for beamforming. However, low power levels and variable power levels may reduce operating efficiency and make system design inefficient under fixed maximum power requirements.

[0003] Complex QAM signals typically have a high peak-to-average power ratio (PAPR), which may cause power amplifiers (PAs) to operate at a higher power back-off (PBO) relative to the peak power to maintain linearity, thus greatly reducing the efficiency of traditional class-A, class-AB, and class-B PAs at low output powers. Summary of the Invention

[0004] According to one aspect of the present disclosure, there is provided a linear power amplification module, including: a splitter for splitting an input signal into a plurality of split signals; a plurality of circuit branches connected to the splitter, each circuit branch for receiving one of the plurality of split signals; an output terminal connected to the plurality of circuit branches for combining the outputs of the plurality of circuit branches and outputting an output signal; each circuit branch for receiving one of the plurality of split signals; each circuit branch includes a class-AB power amplifier (PA) operable at a bias voltage; the one or more circuit branches each include a corresponding control circuit connected to the input terminal of its class-AB PA.

[0005] In some embodiments, each circuit branch includes a corresponding control circuit connected to the input terminal of its corresponding class-AB PA.

[0006] In some embodiments, one or more control circuits of the one or more circuit branches are used to adjust the input power of the class-AB PA.

[0007] In some embodiments, one or more control circuits of the one or more circuit branches are used to adjust the input power of the class-AB PA by adjusting the power distribution percentage of the input power of the class-AB PA according to the following formula:

[0008] ,

[0009] where P1 is the power proportional to the power of the input signal, i = 1, 2, …, N is the index of the class-AB PA, N is the total number of the class-AB PAs, Pin i is the input power of the i-th class-AB PA, x i is the power distribution percentage of the input power of the i-th class-AB PA, 1 ≥ x i ≥ 0, .

[0010] In some embodiments, one or more control circuits of the one or more circuit branches are used to adjust the bias voltage of at least one class-AB PA.

[0011] In some embodiments, one or more control circuits of the one or more circuit branches are used to adjust the bias voltage of the at least one class-AB PA by adjusting the bias current of the at least one class-AB PA.

[0012] In some embodiments, one or more control circuits of the one or more circuit branches are used to apply phase adjustment between the input signals of the class-AB PAs in the circuit branch.

[0013] In some embodiments, at least one control circuit of the one or more control circuits of the one or more circuit branches includes at least one of an attenuator and one or more regulating amplifiers.

[0014] In some embodiments, one or more control circuits of the one or more circuit branches are used to adjust the input power of the class-AB PA by adjusting at least one of the attenuation of the attenuator and the bias voltage of each of the one or more regulating amplifiers.

[0015] In some embodiments, one or more control circuits of the one or more circuit branches are used to adjust the phase shift between the input signals of the class-AB PAs in the circuit branch by adjusting the bias voltage of at least one of the one or more regulating amplifiers.

[0016] In some embodiments, the linear power amplification module includes two circuit branches, and each circuit branch includes a corresponding control circuit connected to the input end of its corresponding class-AB PA.

[0017] In some embodiments, the one or more control circuits of the one or more circuit branches are used to adjust the input power of the class-AB PA according to the following formula by a parameter r:

[0018] ,

[0019] ,

[0020] where P1 is the power proportional to the power of the input signal, and are the input powers of the two class-AB PAs respectively, and 1 ≥ r ≥ 0.

[0021] In some embodiments, 1 ≥ r ≥ 0.5.

[0022] In some embodiments, the two control circuits of the two circuit branches are used to adjust the bias voltages of the two class-AB PAs, or are used to adjust the bias voltage of the peaking PA in the two class-AB PAs while keeping the bias voltage of the main PA in the two class-AB PAs constant.

[0023] In some embodiments, at least one of the plurality of circuit branches includes an impedance inverter coupled to the output end of the class-AB PA.

[0024] In some embodiments, the plurality of circuit branches are connected to the output end through a matching network.

[0025] According to one aspect of the present disclosure, a method for determining a phase adjustment value used in the above linear power amplification module is provided, including: while fixing the power ratio and the bias voltage of the class-AB PA, introducing a series of phase shift values into the plurality of circuit branches; for each phase shift value in the series of phase shift values, inputting signals of different powers to the linear power amplification module, and determining a set of intermodulation distortion (IMD) values and a set of power-added-efficiency (PAE) values for the phase shift value, so as to obtain a plurality of sets of IMD values and a plurality of sets of PAE values; identifying one or more phase shift values for which the corresponding IMD value within the target power output or power input range is greater than the IMD threshold; for each of the plurality of power output or power input values within the target power output or power input range, selecting the phase shift value having the maximum PAE value from the identified one or more phase shift values as the phase adjustment value for the power output or power input value.

[0026] According to one aspect of the present disclosure, a method for determining a plurality of power ratio values of the class-AB PA used in the above linear power amplification module is provided, including: introducing a series of power ratio values of the class-AB PA; for each power ratio value in the series of power ratio values, inputting signals of different powers to the linear power amplification module, and determining a set of IMD values and a set of PAE values for the phase shift value, so as to obtain a plurality of sets of IMD values and a plurality of sets of PAE values; identifying one or more power ratio values for which the corresponding IMD value within the target power output or power input range is greater than the IMD threshold; for each of the plurality of power output or power input values within the target power output or power input range, selecting the power ratio value having the maximum PAE value from the identified one or more power ratio values as the power ratio value determined for the power output or power input value.

[0027] According to one aspect of the present disclosure, there is provided a method for determining one or more values of one or more parameters used in the linear power amplification module described above, including: introducing a plurality of parameter value sets of the one or more parameters into the linear power amplification module; for each parameter value set, inputting signals of different powers into the linear power amplification module, and determining an IMD value set and a PAE value set for the parameter value set, so as to obtain a plurality of IMD value sets and a plurality of PAE value sets; identifying one or more parameter value sets in which the corresponding IMD value within the target power output or power input range is greater than the IMD threshold; for each of the plurality of power output or power input values within the target power output or power input range, selecting the parameter value set with the maximum PAE value from the identified one or more parameter value sets as the power ratio value determined for the power output or power input value.

[0028] In some embodiments, the one or more parameters include at least one of phase adjustment between circuit branches and power ratio of class AB PA.

[0029] According to one aspect of the present disclosure, there is provided a non-transitory computer-readable storage medium having computer-executable instructions stored thereon, which when executed by a computer, cause the computer to execute the above method.

[0030] The linear power amplification module disclosed herein provides various advantages, such as:

[0031] Both the main PA and the peaking PA operate in their linear class AB regions, so there is no need to match the peaking and compression responses in the final response;

[0032] The adaptive biasing of the main PA and the peaking PA improves both the efficiency and linearity of the linear power amplification module. Therefore, the main PA can maintain an ideal load at the required output power to ensure linearity and efficiency performance without dynamic load changes;

[0033] By using a simple LUT method to digitally control the attenuator, gain amplifier, and driver amplifier to reconfigure the input power distribution ratio and phase shift, the system complexity is reduced due to the use of simple LUT digital control for analog linearization instead of using complex DSP and / or DPD and changing the drain bias as in the prior art;

[0034] The linear power amplification module disclosed herein does not depend on frequency and does not require complex high-speed DSP, DAC, and DPD;

[0035] The linear power amplification module disclosed in this document can be used in embodiments that employ phase array tapering to vary the relative output power with improved efficiency while maintaining the required linearity. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] To more fully understand the present disclosure, reference is made to the following description and drawings, in which:

[0037] Figure 1 is a graph of the input / output relationship of a linear power amplifier (PA);

[0038] FIG. 2 is a schematic structural diagram of a conventional average power tracking Doherty power amplifier (DPA);

[0039] FIG. 3 is a circuit diagram of a conventional average power tracking DPA;

[0040] FIG. 4 is a graph of the behavior of the average power tracking DPA shown in FIG. 2;

[0041] FIG. 5 is a graph of the simulation results of the average power tracking DPA shown in FIG. 2 during reduced power operation;

[0042] FIG. 6 is a schematic diagram of a dual-input DPA transmitter architecture;

[0043] FIG. 7 is a graph of the simulated power-added-efficiency (PAE) of the dual-input DPA shown in FIG. 6 with and without adaptive phase alignment;

[0044] Figure 8 is a schematic diagram of a simulated linear power amplification module provided by some embodiments of the present disclosure;

[0045] Figure 9 is provided by some embodiments of the present disclosure Figure 8 a schematic diagram of the details of the linear power amplification module shown;

[0046] Figure 10 is Figure 9 a graph of the relationship between the intermodulation distortion (IMD) and PAE of the linear power amplification module shown in

[0047] Figure 11 is Figure 9Graph showing the relationship between the amplitude-to-phase (AM-PM) distortion of the linear power amplification module shown in and the output power under different input signal phase shifts but with a fixed input power distribution ratio;

[0048] Figure 12 is Figure 9 Graph showing the relationship between the output power and the sample simulation results of IMD and PAE of the linear power amplification module shown in under different input power distribution ratios with a fixed phase shift. Detailed implementation

[0049] A. Linear power amplifier

[0050] Traditional linear-mode power amplifiers (PAs) typically include class-A, class-B, and class-AB PAs defined by different conduction angles. Specifically, class-A PAs have a conduction angle of 360°, class-B PAs have a conduction angle of 180°, and class-AB PAs have a conduction angle between 180° and 360°.

[0051] Linear-mode PAs typically have a limited linear range. Figure 1 Shows the input / output power relationship of a linear-mode PA. As shown, the input / output power relationship is typically linear between the origin and point B of P1dB (thus defining the input linear range from zero (0) to P B ), where the P1dB point is the point where the output power is one (1) decibel (dB) less than the linearly amplified power value. When the input power is greater than P B , the output will be significantly distorted (i.e., no longer a linear amplification of the input power) and will eventually saturate to the maximum output power.

[0052] Signals with a high peak-to-average power ratio (PAPR), such as quadrature amplitude modulation (QAM) signals, typically have a maximum power that is much greater than their average power. Therefore, when using a PA to amplify a signal with a high PAPR, the operating point A of the PA (corresponding to the average power of the signal) must be "backed off" sufficiently from the saturation point S. In other words, the average power P A of the signal input to the PA must be sufficiently less than P B (the upper limit of the PA linear range) to ensure that the entire signal can be linearly amplified without significant distortion. P B and P AThe difference therebetween represents power back-off (PBO). A high PBO may greatly reduce the efficiency of a conventional linear-mode PA at low output power, resulting in a low-PBO efficiency issue.

[0053] A Doherty power amplifier (DPA) provides a solution to the low-PBO efficiency issue. As shown in Figure 2, a conventional DPA 20 includes a splitter or hybrid coupler 24 to divide an input signal 22 into two signals 26 and 28 with a 90° phase shift therebetween. Signal 26 passes through a main PA 30 (also denoted as the “carrier PA”), which is a class-A or class-AB PA operating on the entire input signal 26. Signal 28 passes through a peak PA 32 (also denoted as the “peaking PA”), which is a class-C PA operating only on the peak-power portion of the input signal 28 (i.e., the peak PA 32 turns off on the main portion of the input signal 28 and turns on only when the power of the input signal 28 is greater than a threshold). By carefully selecting the parameters of PAs 30 and 32, the peak PA 32 can turn on and operate when the main PA 30 starts to saturate. The outputs 34 and 36 of PAs 30 and 32 are combined by a combiner 38 (with a reverse 90° phase shift) to use the output 36 of the peak PA 32 to compensate for the peak distortion / saturation of the output 34 of the main PA 30. Then, the combined output signal 40 is a substantially linear amplified version of the input signal 22.

[0054] The conventional DPA 20 faces a potential linearity issue in the final response (i.e., the output signal 40). First, at low input power levels, only the main PA 30 turns on and operates at a peak or near-peak power-added-efficiency (PAE) at PBO. Second, at high input power levels, the peak PA 32 starts to turn on and relies on active load modulation to change the load impedance presented at the main PA 30. Any additional unnecessary non-linearity caused by this load modulation will directly affect the final response.

[0055] Figure 3 is a circuit diagram of an average-power tracking DPA 20 described in reference [1], where the carrier PA 30 is a class-A or class-AB PA, and the peaking PA 32 is a class-C PA. By changing the drain bias voltage V DS and the gate bias voltages V GS,C and V GS,P , the average-power tracking DPA 20 provides a further extended efficiency range (greater than 6 dB at PBO).

[0056] FIG. 4 is a graph of the behavior of the average power tracking DPA 20 shown in FIG. 3. When the peak output power is reduced from P1 to P2, the average power tracking DPA 20 needs to reduce the drain bias voltage V DS and the gate bias voltage V GS,C and V GS,P to achieve high efficiency at the low peak power P2. Sample simulation results of the average power tracking DPA 20 are shown in FIG. 5. As will be understood by those skilled in the art, in the average power tracking DPA 20 shown in FIG. 3, changing the drain bias voltage requires digital fine-tuning of an internal or external power supply regulator, which may further increase system complexity and power consumption, and its power efficiency improvement may be reduced.

[0057] FIG. 6 is a schematic diagram of the DPA 20 proposed in reference [2] and described in reference [3], where the carrier PA 30 is a class A or AB class PA, and the peaking PA 32 is a class C PA. The DPA 20 shown in FIG. 6 improves the PAE through adaptive phase alignment. As shown, the dual input signal Y d (including in-phase and quadrature (I / Q) components and an upconverter 58) is processed by a digital signal processing (DSP) unit 52 and digital-to-analog convertors (DACs) 54 (also through lowpass filters (LPFs) 56) to adaptively align the carrier and peaking paths at all power levels when the peaking PA 32 is turned on, thereby optimizing the overall efficiency of the DPA 20. FIG. 7 is a graph of the PAE improvement.

[0058] However, the dual input using DSP technology only takes care of the phase alignment of the main PA 30 and the peaking PA 32 to prevent efficiency degradation.

[0059] Digital predistortion (DPD) can potentially solve the linearity problem of the DPA. For example, the DPA shown in FIGS. 3 and 6 can use advanced DPD algorithms to improve its linearity performance. However, due to the low output power levels in millimeter-wave (mmWave) applications and their system complexity (due to high signal bandwidth and a large number of PAs that need to be linearized), DPD may not be preferred.

[0060] In a wireless communication system, especially in systems such as mmWave, 5G, beyond-the-fifth-generation (B5G), 6G phased arrays, etc., which adopt complex modulation methods to achieve high throughput, high-efficiency and high-linearity PAs are always required, where the system requires the PA to operate at a high PAPR and perform PBO from the peak power.

[0061] In the following, a cost-effective analog linear PA is disclosed, which can be applied to wireless communication systems such as 5G and 6G systems, improving the efficiency and linearity of the PA at PBO. The linear PA disclosed here can be considered an improved DPA, used to provide a cost-effective solution to optimize the power efficiency and linearity in the PBO region, thereby meeting the system requirements of phased arrays with high-order QAM. The PBO efficiency and linearity of the DPA are optimized simultaneously in the analog domain without using DPD linearization, thus effectively reducing the overall system complexity.

[0062] Now turning to Figure 8 , which shows an analog linear power amplification module provided by some embodiments of the present disclosure, generally identified by the reference numeral 100. In various embodiments, the linear power amplification module 100 can be used in any suitable wireless communication system, such as RF, millimeter wave, 5G, beyond the fifth generation (B5G), 6G transceivers, which have complex modulation methods for high throughput and require high-efficiency and high-linearity PAs to operate at a high PAPR and perform PBO at the peak power. The linear power amplification module 100 allows for improved efficiency within the operating output power range and maintains reasonable linearity.

[0063] As shown, the linear power amplification module 100 has an improved DPA structure and includes a splitter or hybrid coupler 104 for splitting the input signal 202 into a first split signal 204 and a second split signal 206. In these embodiments, the first signal 204 and the second signal 206 have substantially equal amplitudes and have a phase shift therebetween, such as a 90° phase shift.

[0064] The first signal 204 passes through the first branch or path 104A, passes through the first control circuit 106A, and is then amplified by the main PA 108, which is a class-AB PA in these embodiments. The amplified first signal 212 passes through an impedance inverter 112, such as a quarter-wave (λ / 4, where λ is the wavelength of the first signal 204) transmission line, which modulates the load impedance presented at the output of the main PA 108 and applies a -90° phase shift to the amplified first signal 212 to cancel the phase shift introduced by the splitter 104. The amplified and phase-corrected first signal 214 is then output from the impedance inverter 112. In the simplest embodiments, the control circuit 106A may include only a gain stage and not include level adjustment or bias control. The control circuit 106A may also include phase adjustment.

[0065] The second signal 206 passes through the second branch or path 104B, passes through the second control circuit 106B, and is then amplified by the peaking PA 110, which is a class-AB PA in these embodiments. The amplified second signal 216 is combined with the amplified and phase-corrected first signal 214 (which are in phase) to form a combined signal 218, which is a linear amplification of the input signal 202. Those skilled in the art will recognize that when the signal 216 is combined with the signal 212, the impedance presented by the main amplifier 108 can be changed in a relationship opposite to the relative levels of the signals 216 and 212. In these embodiments, the combined signal 218 is output through a matching network 114. As those skilled in the art will understand, the matching network 114 is used to convert the load impedance to the desired impedance at the output connection of the peaking and main PAs 108 and 110 to optimize overall efficiency and linearity. Those skilled in the art will also understand that other DPA topologies can be improved in a similar manner, such as using series or parallel coupled transformers or other means of splitting the signal 202 into signals 204 / 206 and combining the signals 212 / 216 into the signal 218.

[0066] In these embodiments, if the output characteristics are repeatable and depend on the desired / expected target output power, the control circuits 106A and / or 106B use an adaptive control method, such as a calibration-based control method or a look-up table (LUT)-based control method (described in more detail later), to adaptively control the input power Pin of the main PA 108 and the peaking PA 110 and their operating points main and Pin peaking 。

[0067] For example, in some embodiments, a non-constant envelope signal such as a QAM signal (i.e., a signal whose envelope (i.e., its peak value) is non-constant) is used as the input signal 202, and the output signal 220 is a linearly amplified version of the input QAM signal. In these embodiments, the input and output powers of the linear power amplification module 100 and the Pin of the main PA 108 and the peaking PA 110 main and Pin peaking refer to the corresponding powers of the non-constant envelope signal input to the linear power amplification module 100.

[0068] The control circuits 106A and / or 106B can use an adaptive control method to adjust the Pin of the main PA 108 and the peaking PA 110 and their operating points based on the target output power (or equivalently, the input power, e.g., the power of each input QAM signal). main and Pin peaking , so as to achieve linear amplification of the input signal 202 with improved PAE, where the amplification linearity can be measured by the intermodulation distortion (IMD) of the output signal 220. For example, the output signal 220 can be expressed as:

[0069] (1)

[0070] where is the output signal 220, is the input signal 202, is the amplification factor, is the distortion introduced by the non-linearity of the linear power amplification module 100. Then, the IMD can be defined as:

[0071] (2)

[0072] where and are and powers, in units of dB or decibel-milliwatts (dBm).

[0073] For example, in some embodiments, the control circuits 106A and / or 106B can use an adaptive control method to adjust the power distribution ratio r (1 ≥ r ≥ 0), which is used to adjust the Pin main and Pin peaking , so as to change the load impedance on the main PA 108, as follows:

[0074] (3)

[0075] (4)

[0076] Among them, P1 is the power proportional to the input power corresponding to the target output power (i.e., the target power of the output signal 220) (i.e., the power of the input QAM signal that is the input signal 220). In these embodiments, 1 ≥ power distribution ratio r ≥ 0.5.

[0077] As the Pin of the main PA 108 and the peaking PA 110 main and Pin peaking are adjusted, the adaptive control method can also correspondingly adjust the bias voltage Vbias of the main PA 108 main and the bias voltage Vbias of the peaking PA 110 peak to ensure that they operate within their class-AB linear region. In some embodiments, the bias voltages Vbias main and Vbias peak of the main PA 108 and the peaking PA 110 can be adjusted, for example, by adjusting their bias currents through the following formula:

[0078] (5)

[0079] (6)

[0080] Among them, Iref main is the reference bias current of the main PA 108 (i.e., the bias current of the main PA 108 to be adjusted), Iref peaking is the reference bias current of the peaking PA 110, I main is the input current of the main PA 108, I sub is a predefined current value, and m is the current mirror ratio. In these embodiments, I main and I sub are constant currents depending on the required or desired target output power range (equivalent to the input power range) of the linear power amplification module 100, and the current mirror ratio m has the same value as the power distribution ratio r (i.e., m = r).

[0081] Based on formulas (5) and (6), the adaptive control method can use various ways to adjust or control the bias voltages Vbias main and Vbias peak . For example, in one embodiment, the adaptive control method can set the reference bias current Iref of the main PA 108 main (and thereby determine the bias voltage Vbias main ) and thereby set the bias voltage Vbias mainSet to a constant level (except for possible variations for typical process and temperature compensation, which are outside the scope of this disclosure and are omitted), and adjust or control the reference bias current Iref of the peaking PA 110 peaking to set Vbias peak . In another embodiment, the adaptive control method can adjust or control the reference bias current Iref main and Iref peaking both to set Vbias main and Vbias peak .

[0082] Figure 9 is a schematic diagram of the details of the linear power amplification module 100 provided by some embodiments of this disclosure. As shown, the first control circuit 106A includes a high-resolution attenuator (Att-a) 122A, such as a digital control attenuator for receiving the first signal 204, a gain amplifier (gain stage 1a) 124A connected to the attenuator 122A, and a driver amplifier (gain stage 2a) 126A that connects the gain amplifier 124A to the main PA 108

[0083] Similarly, the second control circuit 106B includes a high-resolution attenuator (Att-b) 122B, such as a digital control attenuator for receiving the second signal 206, a gain amplifier (gain stage 1b) 124B connected to the attenuator 122B, and a driver amplifier (gain stage 2b) 126B that connects the gain amplifier 124B to the peaking PA 110. In these embodiments, the corresponding components 122A and 122B, 124A and 124B, and 126A and 126B of the main path 106A and the peaking path 106B are substantially the same. For ease of description, the gain amplifiers 124A and 124B and the driver amplifiers 126A and 126B can be collectively referred to as "adjusting amplifiers".

[0084] In these embodiments, the adaptive control method adaptively controls the attenuation of the attenuators 122A and 122B, and the bias voltages Vbias of the gain amplifier 124A 1a , Vbias of the gain amplifier 124B 1b , Vbias of the driver amplifier 126A 2a , and Vbias of the driver amplifier 124B 2b to adjust the power distribution ratio r as described above. The adaptive control method also controls the reference bias currents Iref main and Iref peaking to set Vbias main and Vbias peak so as to operate the main PA 108 and the peaking PA 110 within their linear ranges

[0085] In some embodiments, the phase shift introduced by impedance inverter 112 may not exactly match (i.e., fully compensate for) the phase shift introduced by splitter 102. In these embodiments, the adaptive control method may also adaptively control control circuits 106A and / or 106B to adjust the phase shift between input signals 208 and 210 of main amplifier 108 and peaking amplifier 110 to align the amplified first signal 214 and second signal 216 in phase.

[0086] For example, in Figure 9 the example shown, attenuators 122A and 122B generally have a relatively constant phase shift within their attenuation ranges. To achieve the desired input power distribution ratio with an appropriate phase shift within the range between Pin main and Pin peaking , each of attenuators 122A and 122B can be set to a desired attenuation setting (determined by a calibration procedure, described in more detail below), and the bias voltages of gain amplifiers 124A and 124B and drive amplifiers 126A and 126B can also be set to appropriate values (determined by a calibration procedure, described in more detail below) to satisfy the relationships in equations (3) and (4). Then, while setting the constant power relative level between Pin main and Pin peaking (e.g., by setting the power distribution ratio r), the phase shift between the two branches 104A and 104B can be fine-tuned, and the power distribution ratio to optimize the efficiency and linearity of linear power amplification module 100. For phase array tapering, the output power of each path of the drive element or group of elements may not be constant. The relative output power of each path can be set by the same mechanism as described above without adjusting the power supply voltage while optimizing the efficiency and linearity of power amplification module 100.

[0087] In some embodiments, a calibration procedure can be used to determine the control parameters used by the adaptive control method.

[0088] The calibration procedure first determines the phase adjustment for compensating the possibly mismatched phase shifts introduced by splitter 102 and impedance inverter 112. Referring to Figure 10 , the power distribution ratio r (i.e., the power ratio of the input powers of main PA 108 and peaking PA 110) and the bias voltages Vbias main and Vbias peak of main amplifier 108 and peaking amplifier 110 are set to fixed values, and control circuits 106A and / or 106B are tuned to introduce a series of phase adjustment values between input signals 208 and 210 of main amplifier 108 and peaking amplifier 110 (e.g., at Figure 10in the example shown, from 0° to 85°) (thus introducing a phase adjustment value between the amplified signals 212 and 216). For each phase adjustment value, signals 102 of different powers are input into the linear power amplification module 100. The IMD and PAE are calculated based on the output signal 220. Then, a plurality of IMD curves 302 are obtained (each IMD curve has a plurality of IMD values, each IMD value corresponding to a target output power or a target input power) and a plurality of PAE curves 304 (each PAE curve has a plurality of PAE values, each PAE value corresponding to a target output power or a target input power), each IMD curve and each PAE curve corresponding to a specific phase adjustment value, and each IMD curve corresponding to a PAE curve. It can be seen that the IMD curve 302 generally decreases as the output power Pout increases, and the PAE curve 304 generally increases as Pout increases.

[0089] When the IMD is greater than the IMD threshold, the linearity requirement of the linear power amplification module 100 is satisfied, where the value of the IMD threshold depends on the application or usage scenario. Figure 10 in the example shown, when the IMD is greater than the IMD threshold of 35 dB (represented by the dashed line 306), the linearity requirement of the linear power amplification module 100 is satisfied. In the desired or required target Pout range, for example, between 4.5 dBm and 12 dBm, some phase adjustment values are eliminated because their IMD values are less than the IMD threshold. The PAE curves of the remaining phase adjustment values are used to select the phase adjustment value with the maximum PAE value among the remaining PAE curves for each Pout value within the target Pout range. For example, when Pout = 7 dBm, the phase adjustment value of –35° results in an IMD greater than 35 dB and the maximum PAE value, increasing the IMD from 26 dB to 35 dB and the PAE from 6.6% to 10.4% (at the same output power level, the power is reduced by approximately 36.5%).

[0090] Figure 11 is a diagram showing the simulation results with a fixed Pin peaking and Pin main power distribution ratio r and the bias points for the main PA 108 and the peaking PA 110, but with different phase alignments (phase shifts) between the input signals of the main PA 108 and the peaking PA 110. It can be seen that while improving the IMD, the amplitude-to-phase (AM-PM) distortion is optimized.

[0091] After determining the phase adjustment value, the calibration procedure then determines the value of the power distribution ratio r (i.e., the power ratio of the input powers of the main PA 108 and the peaking PA 110) for different output powers Pout (or different input powers). As Figure 12 shown, the control circuits 106A and / or 106B introduce the determined phase adjustment value and are tuned to set a series of values of the power distribution ratio r. For each power distribution ratio r, signals 102 of different powers are input into the linear power amplification module 100. The IMD and PAE are calculated based on the output signal 220. Then, a plurality of IMD curves 302 and a plurality of PAE curves 304 are obtained, each IMD curve and each PAE curve corresponding to a specific phase adjustment value, and each IMD curve corresponding to a PAE curve. It can be seen that the IMD curves 302 generally decrease as the output power Pout increases, and the PAE curves 304 generally increase as Pout increases.

[0092] When the IMD is greater than the IMD threshold, the linearity requirement of the linear power amplification module 100 is satisfied, where the value of the IMD threshold depends on the application or usage scenario. In Figure 11 the example shown, when the IMD is greater than the IMD threshold of 35 dB (represented by the dashed line 306), the linearity requirement of the linear power amplification module 100 is satisfied. In the target Pout range, for example, between 4.5 dBm and 12 dBm, some r values are eliminated because their IMD values are less than the IMD threshold. For each Pout value within the target Pout range, the PAE curves of the remaining r values are used to select the r value with the maximum PAE value among the remaining PAE curves, thereby generating the aggregated PAE curve 308. For example, for Pout = 4.75 dBm, r = 0.9 results in an IMD greater than 35 dBm and the maximum PAE value, thereby increasing the PAE from 7.1% to 11.7% (the PAE increases by approximately 4.7% when the peak operating power is reduced by 6 dB, and the power is reduced by approximately 40% at the same output power level).

[0093] The aggregated PAE curve 308 can be used in an adaptive control method to adaptively adjust the power distribution ratio during the operation of the linear power amplification module 100. For example, in some embodiments, a LUT can be obtained from the aggregated PAE curve 308, which has a lookup column for different Pout values (or corresponding input power values) and a column for the corresponding r values. The adaptive control method can use the LUT to select an appropriate r value based on the desired output power (or based on the input power).

[0094] Those skilled in the art will understand that in these embodiments, the adaptive control method uses bias to adjust the IMD and PAE curves. Therefore, the PBO of each curve is basically the same. However, P1dB is offset to maintain linearity (IMD) and efficiency (PAE).

[0095] In the above embodiments, the calibration procedure determines the phase adjustment value and the value of the power distribution ratio r (i.e., the power ratio between the input powers of the main PA 108 and the peaking PA 110) respectively.

[0096] When determining the phase adjustment value, the calibration procedure introduces a series of phase adjustment values between circuit branches 104A and 104B while fixing the power ratio and the bias voltage of the main PA 108 and the peaking PA 110. For each of the series of phase adjustment values, the calibration procedure inputs signals of different powers into the linear power amplification module 100 and determines a set of IMD values and a set of PAE values for the phase adjustment value, so as to obtain multiple sets of IMD values (where each IMD value corresponds to the target output power or the target input power of the linear power amplification module 100, and each set of IMD values can be intuitively represented by an IMD curve as shown in Figure 10 and multiple sets of PAE values (where each PAE value corresponds to the target output power or the target input power of the linear power amplification module 100, and each set of PAE values can be intuitively represented by a PAE curve as shown in Figure 10 ).

[0097] The calibration procedure identifies one or more phase adjustment values whose corresponding IMD values within the target power output or power input range are greater than the IMD threshold. Then, for each of the multiple power output or power input values within the target power output or power input range, the calibration procedure selects the phase adjustment value with the maximum PAE value from the identified one or more phase adjustment values corresponding to the power output or power input value as the phase adjustment value for the power output or power input value.

[0098] Similarly, when determining the value of the power distribution ratio r (i.e., the power ratio value), the calibration procedure introduces a series of power ratio values for the main PA 108 and the peaking PA 110. For each of the series of power ratio values, the calibration procedure inputs signals of different powers into the linear power amplification module 100 and determines a set of IMD values and a set of PAE values for the power ratio value, so as to obtain multiple sets of IMD values (where each IMD value corresponds to the target output power or the target input power of the linear power amplification module 100, and each set of IMD values can be intuitively represented by an IMD curve as shown in Figure 12The IMD curves shown (visually represent) and multiple sets of PAE values (where each PAE value corresponds to the target output power or target input power of the linear power amplification module 100, and each set of PAE values can be visually represented by a PAE curve as shown in Figure 10 .

[0099] The calibration procedure identifies one or more power ratio values whose corresponding IMD values within the target power output or power input range are greater than the IMD threshold. Then, for each of the multiple power output or power input values within the target power output or power input range, the calibration procedure selects the power ratio value with the maximum PAE value from the one or more power ratio values identified as corresponding to the power output or power input value as the power ratio value determined for that power output or power input value.

[0100] In some embodiments, the calibration procedure can determine the phase adjustment value and the power ratio value together.

[0101] In these embodiments, the calibration procedure introduces multiple combinations of the phase adjustment value and the power ratio value to the linear power amplification module 100. For each combination of the phase adjustment value and the power ratio value, the calibration procedure inputs signals of different powers to the linear power amplification module 100 and determines a set of IMD values and a set of PAE values for the power ratio value, thereby obtaining multiple sets of IMD values (where each IMD value corresponds to the target output power or target input power of the linear power amplification module 100, and each set of IMD values can be visually represented by an IMD curve as shown in Figure 12 ) and multiple sets of PAE values (where each PAE value corresponds to the target output power or target input power of the linear power amplification module 100, and each set of PAE values can be visually represented by a PAE curve as shown in Figure 10 .

[0102] The calibration procedure identifies one or more combinations of the phase adjustment value and the power ratio value whose corresponding IMD values within the target power output or power input range are greater than the IMD threshold. Then, for each of the multiple power output or power input values within the target power output or power input range, the calibration procedure selects the combination of the phase adjustment value and the power ratio value with the maximum PAE value from the one or more combinations of the phase adjustment value and the power ratio value identified as corresponding to the power output or power input value as the combination of the phase adjustment value and the power ratio value determined for that power output or power input value.

[0103] In some embodiments, the calibration procedure does not determine the phase adjustment value (therefore, assuming that the phase shifts introduced by the splitter 102 and the impedance inverter 112 are matched, and any phase shift mismatch may introduce IMD).

[0104] In the above embodiments, the splitter 104 performs 90° signal splitting. In some other embodiments, other suitable elements or circuits may be used for 90° signal splitting. Additionally, in various embodiments, the attenuators 122A and 122B can be any suitable attenuators, such as analog-controlled attenuators, digital variable gain amplifiers (VGAs), analog VGAs, and / or the like, to operate the main PA 108 and the peaking PA 110 in their class-AB regions, but the P1dB operating point changes.

[0105] As will be understood by those skilled in the art, the phase shift introduced by the splitter 102 is used to compensate for the phase shift caused by the impedance converter 112. In some embodiments, the impedance converter 112 causes a phase shift θ (not necessarily 90° and can be 0°) between the first split signal 204 and the second split signal 206, and the splitter 102 can introduce a reverse phase shift –θ. In some embodiments, the splitter 102 can introduce a reverse phase shift –θ. Conversely, a separate phase shifter can be included in the first control circuit 106A and / or the second control circuit 106B to compensate for the phase shift caused by the impedance converter 112.

[0106] In some embodiments, the first control circuit 106A and / or the second control circuit 106B may not include any attenuators.

[0107] In some embodiments, the first control circuit 106A may include a plurality of gain amplifiers 124A, and the first control circuit 106A may include a plurality of gain amplifiers 124B, depending on the overall gain requirements of the linear power amplification module 100. Each of the gain amplifiers 124A and 124B may include dedicated digital control of its bias voltage to simultaneously facilitate optimization of power efficiency and linearity.

[0108] In some embodiments, the gain amplifier 124A and the drive amplifier 126A can be combined into a single amplifier. Similarly, the gain amplifier 124B and the drive amplifier 126B can be combined into a single amplifier.

[0109] In some embodiments, the linear power amplification module 100 may not include any gain and / or drive amplifiers 124A, 124B, 126A, and / or 126B, and the adjustment of the power distribution ratio is performed by the attenuators 122A and 122B. However, the efficiency of the linear power amplification module 100 in these embodiments may be reduced.

[0110] In some embodiments using phased array tapering, the output power of each phased array channel may not be constant. In these embodiments, the linear power amplification module 100 may employ variable relative output power. That is, by controlling the bias voltages of amplifiers 124A, 124B, 126A, 126B, 108, and 110, the output power can be adjusted without adjusting the input power of the linear power amplification module 100, thereby not adjusting the power supply voltage of each channel of the phased array.

[0111] In the above embodiments, the adaptive control method adjusts the bias voltage Vbias of the main PA 108 main . In some other embodiments, the adaptive control method may not adjust the bias voltage Vbias of the main PA 108 main .

[0112] In the above embodiments, the splitter 102 splits the input signal into a first signal and a second signal having substantially equal power. In some embodiments, the first signal and the second signal may have different powers.

[0113] In some of the above embodiments, the adaptive control method is used to adjust the power distribution ratio r according to formulas (3) and (4). Those skilled in the art can understand that adjusting the power distribution ratio r is equivalent to adjusting the input powers Pin main and Pin peaking of the power distribution percentages, that is:

[0114] (7)

[0115] (8)

[0116] wherein, x main and x peaking are respectively the power distribution percentages of the input powers Pin main and Pin peaking , 1 > x main > 0, 1 > x peaking > 0, x main + x peaking = 1. In some embodiments, 1 > power distribution ratio x main ≥ 0.5.

[0117] In the above embodiments, the linear power amplification module 100 includes two branches 104A and 104B. In some embodiments, the linear power amplification module 100 may include more than two branches. One or more splitters may be used to provide split signals to the branches. In addition, an adaptive control method is used to adjust the power distribution percentage of the input power of the PAs of more than two branches according to the following formula:

[0118] (9)

[0119] where i = 1, 2,..., N is the index of the PA (N is the total number of PAs), Pin i is the input power of the ith PA, and x i is the power distribution percentage of the input power of the ith PA, 1 ≥ x i ≥ 0, .

[0120] Although in the above embodiments, each branch includes a control circuit, in some embodiments, some branches may not include a control circuit.

[0121] In some embodiments, the linear power amplification module 100 may not include any matching network 114.

[0122] The linear power amplification module 100 disclosed herein provides various advantages, such as:

[0123] Both the main PA 108 and the peaking PA 110 operate in their linear class AB regions, so there is no need for matching of peaking and compression responses in the final response;

[0124] The adaptive biasing of the main PA 108 and the peaking PA 110 improves both the efficiency and linearity of the linear power amplification module 100. Therefore, the main PA 108 can maintain an ideal load at the required output power to ensure linearity and efficiency performance without dynamic load changes;

[0125] By using a simple LUT method to digitally control the attenuators 122A and 122B, the gain amplifiers 124A and 124B, and the driver amplifiers 126A and 126B to reconfigure the input power distribution ratio and phase shift, the system complexity is reduced due to the use of simple LUT digital control for analog linearization instead of using complex DSP and / or DPD and changing the drain bias as in the prior art;

[0126] The linear power amplification module 100 disclosed herein is not frequency-dependent and does not require complex high-speed DSP, DAC, and DPD;

[0127] The linear power amplification module 100 disclosed in this document can be used in embodiments using phase array tapering to vary the relative output power with improved efficiency while maintaining the required linearity.

[0128] B. Abbreviations and Keywords

[0129] Digital Predistortion: DPD

[0130] Digital Signal Processing: DSP

[0131] Doherty Power Amplifier: DPA

[0132] Intermodulation Distortion: IMD

[0133] "In-phase" and "Quadrature": I / Q

[0134] Look-Up Table: LUT

[0135] Millimeter Wave: mmWave

[0136] Peak-to-Average Power Ratio: PAPR

[0137] Power Added Efficiency: PAE

[0138] Power Amplifier: PA

[0139] Power Back-Off: PBO

[0140] Quadrature Amplitude Modulation: QAM

[0141] Variable Gain Amplifier: VGA

[0142] C. References:

[0143] [1] Y. Park, J. Lee, S. Kim, D. Minn and B. Kim, “Analysis of AveragePower Tracking Doherty Power Amplifier,” in IEEE Microwave and WirelessComponents Letters, 20 vol. 25, no. 7, pp. 481-483, July 2015, doi: 10.1109 / LMWC.2015.2429071.

[0144] [2] R. Darraji, “A Dual-Input Digitally Driven Doherty Amplifier Architecture for Performance Enhancement of Doherty Transmitters,” in IEEE Transactions on Microwave Theory and Techniques, 2011.

[0145] [3] R. Pengelly, “Doherty’s Legacy: A History of the Doherty Power Amplifier from 1936 to the Present Day,” in IEEE Microwave Magazine, 2016.

[0146] Although the embodiments have been described above with reference to the accompanying drawings, those skilled in the art will understand that changes and modifications can be made without departing from the scope defined by the appended claims.

Claims

1. A linear power amplification module, comprising: A splitter for splitting an input signal into a plurality of split signals; A plurality of circuit branches connected to the splitter, each of the plurality of circuit branches for receiving one of the plurality of split signals; An output terminal connected to the plurality of circuit branches for combining the outputs of the plurality of circuit branches and outputting an output signal; Wherein each of the plurality of circuit branches includes a class AB power amplifier (PA) operable at a bias voltage; Wherein one or more of the plurality of circuit branches each include a respective control circuit connected to the input of its class AB PA.

2. The linear power amplification module according to claim 1, wherein Each of the plurality of circuit branches includes a respective control circuit connected to the input of its respective class AB PA.

3. The linear power amplification module according to claim 1 or 2, wherein The one or more control circuits of the one or more circuit branches are configured to adjust the input power of the class AB PA.

4. The linear power amplification module according to claim 3, wherein, The one or more control circuits of the one or more circuit branches are configured to adjust the input power of the class AB PA by adjusting the power distribution percentage of the input power of the class AB PA according to the following formula: ， Among them, P1 is the power proportional to the power of the input signal, i = 1, 2, …, N is the index of the class-AB PA, N is the total number of the class-AB PAs, and Pin i is the input power of the i-th class-AB PA, and x i is the power distribution percentage of the input power of the i-th class-AB PA, where 1 ≥ x i ≥ 0, .

5. The linear power amplification module according to any one of claims 1 to 4, wherein, The one or more control circuits of the one or more circuit branches are configured to adjust the bias voltage of at least one class AB PA.

6. The linear power amplification module according to claim 5, wherein The one or more control circuits of the one or more circuit branches are configured to adjust the bias voltage of the at least one class AB PA by adjusting the bias current of the at least one class AB PA.

7. The linear power amplification module according to any one of claims 1 to 6, wherein, The one or more control circuits of the one or more circuit branches are configured to apply a phase adjustment between the input signals of the class AB PAs of the circuit branch.

8. The linear power amplification module according to any one of claims 1 to 7, wherein, At least one of the one or more control circuits of the one or more circuit branches includes at least one of an attenuator and one or more regulating amplifiers.

9. The linear power amplification module according to claim 8, which depends on claim 3, wherein, The one or more control circuits of the one or more circuit branches are configured to adjust the input power of the class AB PA by adjusting at least one of the attenuation of the attenuator and the bias voltage of each of the one or more regulating amplifiers.

10. The linear power amplification module according to claim 8, which depends on claim 7, wherein, The one or more control circuits of the one or more circuit branches are configured to adjust the phase shift between the input signals of the class AB PA of the circuit branch by adjusting the bias voltage of at least one of the one or more regulating amplifiers.

11. The linear power amplification module according to any one of claims 1 to 10, wherein The linear power amplification module includes two circuit branches, each circuit branch including a respective control circuit connected to the input of its respective class AB PA.

12. The linear power amplification module according to claim 11, which depends on claim 3, wherein, The one or more control circuits of the one or more circuit branches are configured to adjust the input power of the class AB PA by a parameter r according to the following formula: ， ， wherein, P1 is the power proportional to the power of the input signal, and are the input powers of two class-AB PAs respectively, and 1 ≥ r ≥ 0.

13. The linear power amplification module according to claim 12, wherein, 1 ≥ r ≥ 0.5。 14. The linear power amplification module according to any one of claims 11 to 13, which depends on claim 5, wherein, The two control circuits of the two circuit branches are configured to adjust the bias voltages of the two class AB PAs, or to adjust the bias voltage of the peaking PA of the two class AB PAs while keeping the bias voltage of the main PA of the two class AB PAs constant.

15. The power amplification module according to any one of claims 1 to 14, wherein, At least one of the plurality of circuit branches includes an impedance inverter coupled to the output of the class AB PA.

16. The linear power amplification module according to any one of claims 1 to 15, wherein, The multiple circuit branches are connected to the output terminal through a matching network.

17. A method for determining one or more values of one or more parameters used in a linear power amplification module, the linear power amplification module being the linear power amplification module according to any one of claims 1 to 16, comprising: Introducing a plurality of parameter value sets of the one or more parameters into the linear power amplification module; For each parameter value set, inputting signals of different powers into the linear power amplification module, and determining an IMD value set and a PAE value set for the parameter value set, thereby obtaining a plurality of IMD value sets and a plurality of PAE value sets; Identifying one or more parameter value sets for which the corresponding IMD value within the target power output or power input range is greater than the IMD threshold; For each of the plurality of power output or power input values within the target power output or power input range, selecting the parameter value set having the maximum PAE value from the identified one or more parameter value sets as the power ratio value determined for the power output or power input value.

18. The method according to claim 17, wherein, The one or more parameters include at least one of phase adjustment between the circuit branches and power ratio of class AB PA.

19. A non-transitory computer-readable storage medium having computer-executable instructions stored thereon, which when executed by a computer cause the computer to perform the method according to claim 17 or 18.

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