Transmission / reception device for serial bus system substance station and method for receiving differential signal in serial bus system
By using a transmitting and receiving device with the first and second comparators in the CAN FD bus system, and combining the shielding block to handle high-frequency interference, the reliability and cost problems of bus signal recognition under the CAN XL standard are solved, and efficient bus communication is achieved.
Patent Information
- Application Number
- CN202380085678.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2022-12-13
- Filing Date
- 2023-10-25
- Publication Date
- 2025-08-01
AI Technical Summary
The existing CAN FD bus system is difficult to reliably identify the level changes of the bus signal during the high data rate communication stage, resulting in the newly accessed user stations that may interfere with existing communications, and the existing receiving devices are costly and have large bandwidth requirements.
Using a transmitting and receiving device with first and second comparators, bus signals are identified at different communication stages through different reception thresholds, and high-frequency interference is handled using masking blocks to ensure efficient communication under the CAN XL standard.
It realizes efficient and reliable bus signal recognition under the CAN XL standard, avoids interference with existing communications by new access user stations, and reduces the cost and bandwidth requirements of the receiving device.
Smart Images
Figure CN120419136A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a transmitting and receiving device for a user station in a serial bus system and a method for receiving differential signals in a serial bus system, which can be used in a transmitting / receiving device (transceiver). Background Art
[0002] Serial bus systems are used for message or data transmission in technical devices. A serial bus system can, for example, enable communication between sensors and controllers in vehicles or technical production devices, etc.
[0003] In a CAN bus system, messages are transmitted by means of the CAN and / or CAN FD protocols, as described in the standard ISO-11898-1:2015 as the CAN protocol specification with CAN FD. In CAN FD, during transmission on the bus, a slow operating mode in the first communication phase (arbitration phase) and a fast operating mode in the second communication phase (data phase) are switched back and forth. In a CAN FD bus system, a data transmission rate greater than 1 megabit per second (1 Mbps) can be achieved in the second communication phase. CAN FD is first used by most manufacturers in vehicles at an arbitration bit rate of 500 kbit / s and a data bit rate of 2 Mbit / s.
[0004] In order to be able to achieve a greater data rate in the second communication phase, there are successor bus systems for CAN FD, such as CAN-SIC and CAN XL. In CAN-SIC according to the standard CiA601-4, a data rate of approximately 5 to 8 Mbit / s can be achieved in the second communication phase. In CAN XL, a data rate > 10 Mbit / s in the second communication phase is required. For CAN XL, the CiA610-3 standard is currently specified by the CAN in Automation (CiA) organization.
[0005] In all the above-mentioned CAN-based bus systems, for the transmitted signal TxD, the bus signal CAN_H is driven onto the bus separately and ideally the bus signal CAN_L is also driven onto the bus simultaneously. In this case, at least in the first communication phase, one bus state is actively driven in the bus signals CAN_H, CAN_L. The other bus state is not driven and occurs based on the terminal resistance of the bus line or bus core wire for the bus.
[0006] For sending and receiving bus signals, in a CAN bus system, transmission / reception devices, also known as CAN transceivers or CAN FD transceivers, etc., are generally used for each communication participant. In CAN XL, the transmission / reception device must be able to send the bus signals CAN_H, CAN_L to the bus in a second communication phase using a different physical layer than in the first communication phase and receive the bus signal using a different reception threshold than in the first communication phase. The physical layer corresponds to the bit transmission layer or layer 1 of the known OSI model (Open Systems Interconnection Modell). Currently, the physical layer of the CAN-XL transmission / reception device is specified in the standard CiA610-3.
[0007] Thereby, data can be sent to the bus in the second communication phase at a significantly higher data rate than in the first communication phase. In addition, the bus levels of the bus signals CAN_H, CAN_L for the first communication phase can be different from the bus levels in the second communication phase. Here, for a low error rate, it is important that user stations in newly accessed communication on the bus recognize in which communication phase communication is currently taking place on the bus.
[0008] Therefore, for all operating phases of communication on the bus, it is necessary to ensure that the receiving user stations of the bus system can correctly recognize and evaluate the levels of the bus signals CAN_H, CAN_L. Summary of the Invention
[0009] Therefore, an object of the present invention is to provide a transmission / reception device for a user station of a serial bus system and a method for receiving differential signals in a serial bus system, which solve the problems mentioned above. In particular, even if the transmission / reception device is not the sender of the message currently being transmitted on the bus and the physical layer is switched between two communication phases during communication on the bus, the transmission / reception device and the method should be able to achieve reliable and uncomplicated recognition of the bus signal.
[0010] This object is achieved by a transmitting and receiving device for a user station of a serial bus system having the features of claim 1. In the bus system, differential signals on the bus of the bus system are generated using a first physical layer in a first communication phase of the communication on the bus and using a second physical layer in a second communication phase of the communication on the bus. The transmitting and receiving device has: a first comparator for evaluating the differential signal received from the bus using a first reception threshold in the first communication phase and for evaluating the differential signal received from the bus using a third reception threshold in the second communication phase, wherein the first comparator is designed to output an output signal in order to output a digital reception signal to the communication control device of the user station; a second comparator for evaluating the differential signal received from the bus using a second reception threshold for a reception signal driver in the first communication phase; and a shielding block for generating a shielded comparator signal, which is a temporarily shielded output signal of the second comparator; and for generating an output signal for the reception signal driver from the shielded comparator signal and the output signal of the first comparator.
[0011] The described transmitting and receiving device is designed such that reliable and uncomplicated recognition of bus signals is achieved during operation of the bus system. This especially also applies to a communication in which the transmitting and receiving device is not the transmitter of the message currently being transmitted on the bus and a physical layer conversion takes place between two communication phases for communication at the bus. The transmitting and receiving device can reliably distinguish the respective bus states of the individual communication phases and thus the individual communication phases when communicating at the bus.
[0012] Here, the described transmitting and receiving device can implement a specification of the communication that meets the requirements according to CAN XL, which is especially established in the standard CiA610-3. However, for this purpose, even when receiving a signal with a bit time of approximately 50 ns from the bus (which corresponds to a transmission rate of approximately 20 Mbit / s at the bus), the transmitting and receiving device requires a relatively cost - low reception comparator as the second reception comparator. The reason for this is that the comparator does not require the very high bandwidth required for receiving signals with a bit time of approximately 50 ns or shorter.
[0013] Furthermore, the described transmitting and receiving device is designed such that the signal level of the bus signal can be converted into a digital reception signal by synchronously evaluating two reception thresholds. Here, the two reception thresholds used in the individual communication phases can be different for each communication phase.
[0014] Thereby, the transmitting and receiving device ensures that its higher-level user stations, such as newly connected or attempting to connect after an error and integrated into the communication at the bus, do not interfere with the communication at the bus. That is to say, the user station can reliably identify whether there is no data traffic on the bus by means of the transmitting and receiving device. Since the transmitting and receiving device reliably assigns the current bus state, a user station newly connected to the bus communication will only send the data itself onto the bus when the bus is idle. Therefore, the access of, for example, an initially started user station or a user station attempting to be integrated into the communication at the bus after an error occurs in the bus communication will not cause interference with the communication at the bus.
[0015] Thereby, the transmitting and receiving device can implement the following function, that is, using different reception thresholds for the arbitration phase and the data phase. Thereby, not only is the communication in the bus system achieved at a higher bit rate, but also the transmissible bit rate is not reduced due to errors in the communication.
[0016] Further advantageous design options of the transmitting and receiving device are described in the dependent claims.
[0017] The shielding block can have a timing element and a logic circuit. The timing element is connected to the output of the second comparator and is designed to output a shielded comparator signal. The logic circuit is designed to generate a signal for output to the receive signal driver from the output signal of the first comparator and the shielded comparator signal.
[0018] Optionally, the logic circuit is an AND gate to form a logical "AND" connection of the output signal of the first comparator and the shielded comparator signal in a serial manner.
[0019] Feasibly, the transmitting / receiving device further has a driver for driving a digital receive signal to the communication control device of the user station of the bus system and a receive signal logic circuit. The receive signal logic circuit is used to transmit the output signal of the first comparator line having the first comparator and the output signal of the second comparator line having the second comparator to the driver when communicating in the first communication phase; and is used to transmit only the output signal of the first comparator line to the driver when communicating in the second communication phase.
[0020] Feasibly, the transmitting / receiving device further has: a first voltage divider connected to the bus, and the first voltage divider outputs the differential signal received from the bus to the first comparator; and a second voltage divider connected to the bus, and the second voltage divider outputs the differential signal received from the bus to the second comparator.
[0021] The first voltage divider and the second voltage divider can each have a circuit composed of resistors, and the first comparator and the second comparator are connected to the resistors, wherein the first comparator and the second comparator synchronously evaluate differential signals.
[0022] The first voltage divider can have a switch which is arranged to set a first reception threshold for the first voltage divider in a first switching position and a third reception threshold for the first voltage divider in a second switching position, and wherein the second voltage divider is designed to set a second reception threshold.
[0023] The switch unit can be arranged to connect or disconnect a ground resistor.
[0024] Optionally, the switch unit is an NMOS transistor.
[0025] In a particular design, the transmit / receive device is designed to output the output signal of the second comparator to the receive signal driver when the switch has set the first reception threshold in the first voltage divider in its first switching position, and wherein the transmit / receive device can furthermore be designed not to output the output signal of the second comparator to the receive signal driver when the switch has set the third reception threshold in the first voltage divider in its second switching position.
[0026] It can be envisaged that the transmit / receive device furthermore has an operating mode setting unit which is used to control the switch in order to switch the first voltage divider between the first reception threshold and the third reception threshold depending on whether a first communication phase or a second communication phase is taking place on the bus.
[0027] Feasibly, the transmit / receive device furthermore has a transmit module for transmitting signals onto the bus of the bus system.
[0028] The transmit / receive device described above can be part of a user station for a serial bus system. The user station can furthermore have a communication control device which is used to control communication in the bus system and to generate a digital transmit signal for the transmit module.
[0029] Optionally, the user station is designed for communication in a bus system in which at least temporarily exclusive, conflict-free access of the user station to the bus of the bus system is ensured.
[0030] The above-mentioned object is furthermore achieved by a method for receiving differential signals in a serial bus system having the features of claim 15. In the bus system, differential signals on the bus of the bus system are generated using a first physical layer in a first communication phase of the communication on the bus and using a second physical layer in a second communication phase of the communication on the bus. The method has the following steps: receiving the differential signal from the bus using a transceiver; evaluating the differential signal received from the bus using a first comparator with a first reception threshold in the first communication phase; evaluating the differential signal received from the bus using the first comparator with a third reception threshold in the second communication phase, wherein the first comparator for outputting an output signal in the first and second communication phases outputs a digital reception signal to the communication control device of the user station; and evaluating the differential signal received from the bus using a second comparator with a second reception threshold for a reception signal driver in the first communication phase; and generating a shielded comparator signal using a shielding block, the shielded comparator signal being a temporarily shielded output signal of the second comparator; and generating an output signal for the reception signal driver from the shielded comparator signal and the output signal of the first comparator using the shielding block. [[ID= 1]] [[ID= 2]]
[0031] [[ID= 3]]The method offers the same advantages as those mentioned above with respect to the transceiver. [[ID= 4]] [[ID= 5]]
[0032] [[ID= 6]]Further possible implementations of the invention also include combinations of features or embodiments not explicitly mentioned that are described above or below with respect to the embodiments. Here, the person skilled in the art will also add the various aspects as improvement or supplementary solutions to the corresponding basic forms of the invention. [[ID= 7]] [[ID= 8]]Description of the Drawings [[ID= 9]] [[ID= 10]]
[0033] [[ID= 11]]The invention will now be described in more detail with reference to the drawings and in accordance with the embodiments. Among them: [[ID= 12]] [[ID= 13]]
[0034] [[ID= 14]] Figure 1 [[ID= 15]]A simplified block diagram of a bus system according to a first embodiment is shown, [[ID= 16]] [[ID= 17]]
[0035] [[ID= 18]] Figure 2 [[ID= 19]]A schematic structural diagram for illustrating a message that can be sent by a user station of the bus system according to the first embodiment is shown, [[ID= 20]] [[ID= 21]]
[0036] [[ID= 22]] Figure 3 [[ID= 23]]Shows for [[ID= 24]] Figure 1 [[ID= 25]]an example of the ideal time profile of the bus signals CAN_H, CAN_L in the bus system, [[ID= 26]] [[ID= 27]]
[0037] [[ID= 28]] Figure 4 [[ID= 29]]Shows based on [[ID= 30]] Figure 4 [[ID= 31]]the time profile of the differential voltage VDIFF formed by the bus signals on the bus of the bus system, [[ID= 32]] [[ID= 33]]
[0038] Figure 5 Shows a simplified block diagram of a transmitting and receiving device having a receiving module for a bus system user station according to a first embodiment,
[0039] Figure 6 Shows a circuit diagram of a receiving module according to a first embodiment,
[0040] Figure 7 Shows the time profile of the differential voltage VDIFF formed on the bus of a bus system based on Figure 5 of the transmitting and receiving device,
[0041] Figure 8 Shows the time profile of the received signal formed by the received signal from the bus of Figure 6 the receiving module when the timing element of the receiving module is not activated, Figure 7 by the receiving module,
[0042] Figure 9 Shows the time profile of the received signal formed by the received signal from the bus of Figure 6 the receiving module when the timing element of the receiving module is activated, Figure 7 by the receiving module,
[0043] Figure 10 Shows an example of the time profile of a digital transmission signal that is to be converted into bus signals CAN_H and CAN_L for the bus of a bus system according to a second embodiment during an arbitration phase (SIC operating mode) for Figure 1 the bus system,
[0044] Figure 11 Shows the time profile of the bus signals CAN_H and CAN_L during the transition from a recessive bus state to a dominant bus state and back to the recessive bus state, which bus signals are transmitted onto the bus based on Figure 10 the transmission signal during an arbitration phase (SIC operating mode),
[0045] Figure 12 Shows an example of the time profile of a digital transmission signal that is to be converted into bus signals CAN_H and CAN_L for the bus of a bus system according to a second embodiment during a data phase, and Figure 1 the bus system, and
[0046] Figure 13 Shows the time profile of the bus signals CAN_H and CAN_L transmitted onto the bus based on Figure 12 the transmission signal during the data phase.
[0047] Unless otherwise specified, identical or functionally identical elements in the figures are provided with the same reference numerals. Detailed Description
[0048] Figure 1 The bus system 1 is shown, and the bus system can be, for example, a CAN bus system, a CAN-FD bus system, etc. at least partially. The bus system 1 can be used in vehicles, especially motor vehicles, aircraft, etc. or in hospitals, etc.
[0049] In Figure 1 , the bus system 1 has a plurality of user stations 10, 20, 30, and these user stations are respectively connected to a bus 40 or a bus line having a first bus core wire 41 and a second bus core wire 42. The bus core wires 41, 42 can also be referred to as CAN_H and CAN_L for signals on the bus 40. Messages 45, 46, 47 can be transmitted in the form of signals between the respective user stations 10, 20, 30 through the bus 40. The user stations 10, 20, 30 can be, for example, controllers or display devices of a motor vehicle.
[0050] As Figure 1 shown, the user stations 10, 30 respectively have a communication control device 11 and a transmitting / receiving device 12. The transmitting / receiving device 12 has a transmitting module 121 and a receiving module 122.
[0051] The user station 20 has a communication control device 21 and a transmitting / receiving device 22. The transmitting / receiving device 22 has a transmitting module 221 and a receiving module 222.
[0052] The transmitting / receiving devices 12 of the user stations 10, 30 and the transmitting / receiving device 22 of the user station 20 are respectively directly connected to the bus 40, even though this is not shown in Figure 1 .
[0053] The communication control devices 11, 21 are respectively used to control the communication of the corresponding user stations 10, 20, 30 with at least one other user station of the user stations 10, 20, 30 connected to the bus 40 through the bus 40.
[0054] The communication control device 11 creates and reads first messages 45, 47, and the first messages are, for example, modified CAN messages 45, 47. In this case, the modified CAN messages 45, 47 are established, for example, on the basis of the CAN XL format. The transmitting / receiving device 12 is used to receive messages 45, 47 from the bus 40 and send the message to the bus. The transmitting module 121 receives the digital transmission signal TxD created by the communication control device 11 for one of the messages 45, 47 and converts it into a signal on the bus 40. The receiving module 121 receives the signal corresponding to the messages 45 to 47 transmitted on the bus 40 and thereby generates a digital reception signal RxD. The receiving module 122 sends the reception signal RxD to the communication control device 11.
[0055] The communication control device 21 can be implemented like a conventional CAN controller according to ISO 11898-1:2015, that is, like a CAN FD-compatible classic CAN controller or a CAN FD controller. The communication control device 21 creates and reads a second message 46, such as a CAN FD message 46. The transmitting / receiving device 22 is used to receive the message 46 from the bus 40 and send the message to the bus. The transmitting module 221 receives the digital transmission signal TxD created by the communication control device 21 and converts it into a signal for the message 46 on the bus 40. The receiving module 221 receives the signal corresponding to the messages 45 to 47 transmitted on the bus 40 and thereby generates a digital reception signal RxD. In addition, the transmitting / receiving device 22 can be implemented like a conventional CAN transceiver.
[0056] To transmit the messages 45, 47 using CAN SIC or CAN XL, the proven features responsible for the robustness and user-friendliness of CAN and CAN FD are adopted, in particular the frame structure with identifiers and arbitration according to the known CSMA / CR method. The CSMA / CR method results in the so-called recessive state that must exist on the bus 40, which can be overwritten by other user stations 10, 20, 30 on the bus 40 with a dominant level or dominant state.
[0057] Using two user stations 10, 30, it is possible to establish and then transmit a message 45 and receive such a message 45 using different CAN formats, in particular CAN FD format or CAN SIC format or CAN XL format, which is described in detail below.
[0058] Figure For the message 45, a frame 450 is shown, which is especially a CAN XL frame. The communication control device 11 provides the frame for the transmitting / receiving device 12 to send to the bus 40. In this case, the communication control device 11 creates the frame 450 in a CANFD-compatible manner in this embodiment. As an alternative, the frame 450 is CAN SIC-compatible.
[0059] According to , the frame 450 for CAN communication on the bus 40 is divided into different communication phases 451, 452, namely an arbitration phase 451 (first communication phase) and a data phase 452 (second communication phase). The frame 450 has an arbitration field 453, a control field 454 (in which the conversion from the arbitration phase 451 to the data phase 452 takes place), a data field 455, a checksum field 456, and a frame end field 457 after the start-of-frame bit SOF.
[0060] In arbitration phase 451, bit by bit in arbitration field 453, for example by means of an identifier (ID) having bit IDs 28 to 18, it is agreed between user stations 10, 20, 30 which user station 10, 20, 30 wants to send messages 45, 46 with the highest priority and thus obtains exclusive access to bus 40 of bus system 1 for transmission in the subsequent data phase 452. The physical layer used in arbitration phase 451 is like that in CAN and CAN-FD. The physical layer corresponds to the bit transmission layer or layer 1 of the known OSI model (Open System Interconnection model).
[0061] The focus during phase 451 is on using the known CSMA / CR method, which allows user stations 10, 20, 30 to access bus 40 simultaneously without corrupting higher-priority messages 45, 46. This enables additional bus-user stations 10, 20, 30 to be added to bus system 1 relatively easily, which is highly advantageous.
[0062] The CSMA / CR method results in a so-called recessive state that must exist on bus 40 and can be overwritten by other user stations 10, 20, 30 on bus 40 with a dominant level or dominant state. In the recessive state, there is a high-impedance situation at each user station 10, 20, 30, which in combination with the parasitics of the bus circuit leads to a longer time constant. This currently limits the maximum bit rate of today's CAN-FD physical layer to approximately 2 megabits per second in practical vehicle applications.
[0063] In data phase 452, in addition to a part of transmission control field 454, the valid data from data field 455 of CAN-XL frame 450 or message 45 and checksum field 456 are also transmitted. In checksum field 456, the checksum of the data of data phase 452 (including padding bits) can be included, and the padding bits are inserted as inverted bits by the transmitter of message 45 after a corresponding predetermined number of identical bits, especially 10 identical bits. At the end of data phase 452, it switches back to arbitration phase 451 again.
[0064] In the end field in frame end phase 457, at least one acknowledgment bit can be included. In addition, there can be a sequence of 11 identical bits, which indicates the end of CAN XL frame 450. With at least one acknowledgment bit, the receiver can be notified whether an error has been found in the received CAN XL frame 450 or message 45.
[0065] Only when user station 10 has won arbitration as the transmitter and user station 10 thus has exclusive access to bus 40 of bus system 1 for transmission as the transmitter does the transmitter of message 45 start to send the bits of data phase 452 onto bus 40.
[0066] Thus, in the arbitration phase 451, which is the first communication phase, the user stations 10, 30 partially, especially up to and including the FDF-bit, use the format known from CAN / CAN-FD according to ISO 11898-1:2015. However, compared to CAN or CAN FD, in the data phase 452, which is the second communication phase, an increased net data transfer rate can be achieved, especially increased to more than 10 megabits per second. In addition, an increase in the size of the useful data per frame can be achieved, especially increased to about 2 kilobytes or any other value.
[0067] On the left side, it is shown that the user stations 10, 20, 30 in the arbitration phase 451 use the first physical layer 451_P to send the signals CAN_H, CAN_L regarding the time t to the bus 40 respectively, and this signal has the first bit duration t_bt1. The signals CAN_H, CAN_L are serial signals and alternately have at least one dominant state 401 (in this dominant state, VCAN_H = 3.5V and VCAN_L = 1.5V are applicable) or at least one recessive state 402 (in this recessive state, VCAN_H = VCAN_L = 2.5 is applicable). If TxD = 0 or L (low level) is applicable, the dominant state 401 is driven in the phase 451 in the case of NRZ encoding of the transmitted signal TxD. If TxD = 1 or H (high level) is applicable, the recessive state 402 is generated or appears in the phase 451 in the case of NRZ encoding of the transmitted signal TxD. After the arbitration in the arbitration phase 451, one of the user stations 10, 20, 30 is determined as the winner.
[0068] If the user stations 10, 20, 30 recognize the signal in the control field 454 for transitioning from the first communication phase 451 to the second communication phase 452, the corresponding transmit / receive device 12 converts its physical layer 451_P from the first operating mode (SLOW), which can also be implemented in the SIC operating mode, to the physical layer 452_P of the data phase 452 at the end of the arbitration phase 451, as shown on the right side in. For this purpose, the operating mode of the data phase 452 is switched on in the following manner.
[0069] Assume that user station 10 wins the arbitration. Then, the transmitting / receiving device 12 of user station 10 converts its physical layer 451_P from the first operating mode (SLOW) to the physical layer 452_P for the second operating mode (FAST_TX) at the end of the arbitration phase 451, because user station 10 is the transmitter of message 45 in the data phase 452. The transmitting module 121 then successively and thus serially generates states L0 or L1 for signals CAN_H, CAN_L on the bus 40 in the data phase 452 or in the second operating mode (FAST_TX) according to the transmission signal TxD. In the case of pulse width modulation (PWM encoding) of the transmission signal TxD, state L0 (VCAN_H = 3.0V, VCAN_L = 2.0V) is driven for the first PWM symbol in the transmission signal TxD. In the case of pulse width modulation (PWM encoding) of the transmission signal TxD, state L1 (VCAN_H = 2.0V and VCAN_L = 3.0V) is driven for the second PWM symbol different from the first PWM symbol in the transmission signal TxD.
[0070] The frequencies of signals CAN_H, CAN_L can be increased in the data phase 452, as shown on the right side in the example. For this, in the example, the bit time or bit duration t_bt2 in the data phase 452 is shorter or less than the bit time or bit duration t_bt1 in the arbitration phase 451. Therefore, in the example, the net data transfer rate in the data phase 452 increases compared to the arbitration phase 451.
[0071] In contrast, the transmitting / receiving device 12 of user station 30 converts its physical layer 451_P from the first operating mode (SLOW) to the physical layer 452_P for the third operating mode (FAST_RX) at the end of the arbitration phase 451, because user station 30 is only the receiver of frame 450 in the data phase 452, that is, not the transmitter. After the data phase 452 ends, all the transmitting / receiving devices 12 of user stations 10, 30 convert their operating modes to the first operating mode (SLOW). Therefore, all the transmitting / receiving devices 12 also convert their physical layers.
[0072] According to , in the arbitration phase 451, ideally, a differential signal VDIFF = CAN_H – CAN_L is formed on the bus 40, where the value of this differential signal is VDIFF = 2V for the dominant state 401 and the value of this differential signal is VDIFF = 0V for the recessive state 402. This is in shown on the left side in the figure. In contrast, in the data phase 452, a differential signal VDIFF = CAN_H – CAN_L with states L0 and L1 is formed on the bus 40, as shown on the right side in the figure. State L0 has a value of VDIFF = 1V. State L1 has a value of VDIFF = -1V.
[0073] The receiving module 122 can distinguish between the states 401 and 402 by using two of the receiving thresholds T1, T2, and T3 within the ranges TH_T1, TH_T2, and TH_T3, respectively. For this purpose, the receiving module 122 scans at the time point t_A or the signal. To evaluate the scan result, the receiving module 122 uses, for example, a receiving threshold T1 of 0.7V and a receiving threshold T2 of -0.35V in the arbitration phase 451. In contrast, the receiving module 122 only uses the signal evaluated with the receiving threshold T3 in the data phase 452. When switching between the first to third operating modes (SLOW, FAST_TX, FAST_RX) described above the receiving module 122 correspondingly switches the receiving thresholds T2 and T3, which will be described below.
[0074] The receiving threshold T2 is used to identify whether the bus 40 is idle when the user station 12 newly accesses the communication on the bus 40 and attempts to integrate into the communication on the bus 40. The receiving threshold T2 is abbreviated as OOB (= Out-of-Boundary = outside the limit value) in the CAN standard. For a CAN-XL bus without traffic, the condition is that no dominant state 401 appears, which usually has a differential voltage VDIFF = 2V. Therefore, it is not allowed to exceed the receiving threshold T1 of, for example, 0.7V. In addition, it is not allowed to have a level according to state L1, which usually has a differential voltage VDIFF = -1V with a differential voltage VDIFF = 2V. Therefore, it is not allowed to be lower than the receiving threshold T2 of, for example, -0.35V.
[0075] When the user station 12 newly accesses the communication on the bus 40, each of the user stations 10 and 30 converts the operating mode of the transmitting / receiving device 12 to the operating mode of the arbitration phase 451.
[0076] On the one hand, when the user station 10 is initially started and is to be integrated into the communication at the bus 40, access to the user station 10 is required. On the other hand, when the user station 10 attempts to be integrated into the communication at the bus 40 after an error has occurred in the bus communication, access to the user station 10 is required. Only when the bus is recognized as idle is the user station 10 allowed to send the data itself, in particular the messages 45, 47, onto the bus 40 in the situations mentioned. For this purpose, it is checked whether there is no dominant level at the bus 40, that is, whether the received threshold T1 is not exceeded. In addition, it is checked whether neither the L0 level nor the L1 level exists at the bus 40. In this case, depending on the transceiver - transmission level, the threshold T1 can be exceeded both by the level of state 401(dom) and by the level of state L0. Therefore, the threshold T2 is used, which performs the detection regarding the state L0.
[0077] The following Table 1 shows the values that can be set for the respective received thresholds at the bus 40. Here, VDIFF_min for each of the ranges TH_T1, TH_T2, TH_T3 indicates the minimum allowable lower limit in volts for the respective received thresholds T1, T2, T3. VDIFF_typ indicates the value typically or usually set in volts for the respective received thresholds T1, T2, T3. VDIFF_max for each of the ranges TH_T1, TH_T2, TH_T3 indicates the maximum allowable upper limit in volts for the respective received thresholds T1, T2, T3.
[0078]
[0079] Table 1: Tolerance ranges for the received thresholds T1, T2, T3
[0080] shows the basic structure of the transmit / receive device 12 of the user station 10. The transmit module 121 is shown only in a very simplified manner. The transmit module 121 is directly connected to the bus 40 in order to be able to send the transmit signal TxD of the communication control device 11 onto the bus 40 in order to generate a signal in accordance with the
[0081] The receive module 122 has a driver 1221 for the digital receive signal RxD, a logic circuit 1222, and a receive circuit 15. The receive circuit 15 has a first receive comparator line 151, a second receive comparator line 152, a receive stage 153, and a shielding block 155. The receive comparators 151, 152 are receive comparator lines each having a low - voltage comparator. Refer to explain this in more detail.
[0082] In accordance with , the receiving circuit 15 is connected between the bus 40 and the logic circuit 1222. The driver 1221 is connected to the output of the logic circuit 1222. The driver 1221 drives or transmits the digital receive signal RxD to the communication control device 11.
[0083] In the receiving circuit 15, the receiving stage 153 is connected to the bus 40. During the operation of the bus system 1, the receiving stage 153 generates signals S_1, S_2 from the signals CAN_H, CAN_L and transmits them to the first receiving comparator line 151. The first receiving comparator line 151 generates a comparator output signal C_1 from the signals S_1, S_2.
[0084] In addition, during the operation of the bus system 1, the receiving stage 153 additionally generates signals S_3, S_4 from the signals CAN_H, CAN_L and transmits them to the second receiving comparator line 152. The second receiving comparator line 152 generates a comparator output signal C_2 from the signals S_3, S_4.
[0085] The logic circuit 1222 is designed to output the signal C_1 and the signal C_2 to the driver 1221 or only the signal C_2 to the driver 1221 according to the operating mode of the transmit / receive device 12. The operating mode of the transmit / receive device 12, especially its receiving module 122, is one of the first to third operating modes (SLOW, FAST_TX, FAST_RX), as described above. For this purpose, the logic circuit 1222 can have or be at least one AND gate. As an alternative, the logic circuit 1222 has other logic components to meet the functions of the receiving module 122 described below.
[0086] According to The receiving stage 153, the shielding block 155 and their connections to the logic circuit 1222 are described in more detail.
[0087] As shown, the receiving circuit 15 further has a bus biasing voltage source (Bus-Biasing) 154, which supplies the voltage of CAN_SUPPLY / 2 to the receiving stage 153. Usually, CAN_SUPPLY = 5V applies. In this case, the bus biasing voltage source 154 supplies a voltage of 2.5V to the receiving stage 153.
[0088] The first receiving comparator circuit 151 has a first input filter 1511, a first comparator 1512 that outputs a digital output signal CA1, and a first output filter 1513 that outputs a digital output signal C_1. The second receiving comparator circuit 152 has a second input filter 1521, a second comparator 1522 that outputs a digital output signal CA2, and a second output filter 1523 that outputs a digital output signal C_2. The filters 1511, 1523, 1521, 1523 respectively filter the interference of the signals input into the corresponding filters 1511, 1523, 1521, 1523. Each of the receiving comparators 1512, 1522 is a low-voltage comparator.
[0089] The shielding block 155 is connected between the receiving comparator circuits 151, 152. The shielding block 155 has a timing element 1551 that outputs a digital signal CM and a logic circuit 1552 that outputs a digital signal C1. The logic circuit 1552 can have or be at least one AND gate. As an alternative, the logic circuit 1552 has other logic components to meet the functions described below for the receiving module 122.
[0090] The receiving stage 153 has: a first voltage divider 1531 with a first switch Sw1, a second voltage divider 1532, an operating mode setting unit 1533, and an optional second switch Sw2. The first voltage divider and the second voltage divider 1531, 1532 are respectively supplied with the same voltage by a bus bias voltage source 154, especially 2.5V for the recessive state 402 ( ). The second switch Sw2 can optionally turn off the second voltage divider 1532.
[0091] The first voltage divider 1531 and the second voltage divider 1532 are respectively resistive voltage dividers or resistance dividers, and they respectively have a plurality of resistors forming a resistance network. The first voltage divider 1531 and the second voltage divider 1532 respectively have resistors connected to the ground part (CAN_GND) or the connector 44, even though this is not shown in detail in this.
[0092] The first voltage divider 1531 can for example set the reception threshold T1 of or the reception threshold T3 of The reception threshold T3. For this purpose, a switch Sw1 can be arranged to switch, for example, the path to the ground resistor (connector 44) into a conducting state in order to set the reception threshold T1. If the switch Sw1 then switches the path to the ground resistor (connector 44) into a non-conducting state, then the third reception threshold T3 is set.
[0093] The output of the second voltage divider 1532 is connected to the input of the second input filter 1521. The second voltage divider 1532 can, for example, set the reception threshold T2.
[0094] The resistors in the resistor networks of the voltage dividers 1531, 1532 are constructed symmetrically in terms of circuitry.
[0095] In order to comply with the requirements for the input resistances Rin for CANH and CANL, the voltage dividers 1531, 1532 each have two resistor paths, namely a resistor path for the connector CANH and a resistor path for the connector CANL. Here, Rin_CANH and Rin_CANL = 25 kOhm... 50 kOhm apply. Generally, an input resistance Rin of 37.5 kOhm is selected for the connector (Pin) CANH for the signal CAN_H and for the connector (Pin) CANL for the signal CAN_L.
[0096] The switch unit Sw1 can be a transistor, in particular an NMOS transistor. The abbreviation "NMOS" stands for n-channel - MOSFET, where the abbreviation "MOSFET" stands for metal-oxide-semiconductor field-effect transistor.
[0097] The voltage dividers 1531, 1532 form a dual divider structure. The voltage dividers 1531, 1532 divide the bus voltage generated by the signals CAN_H, CAN_L into values that can be processed by the comparator lines 151, 152.
[0098] Due to the dual divider structure of the reception stage 15, two different reception thresholds of the reception thresholds T1, T2, T3 can be checked independently of each other and thus also simultaneously or synchronously. In addition, it is also possible to switch between two reception thresholds of the reception thresholds T1, T2, T3 by means of the switch unit Sw1 controlled by the operating mode setting unit 1533. Thereby, the reception thresholds T1, T2 according to can be checked independently of each other and simultaneously, or the reception thresholds T1, T3 according to can be checked independently of each other and simultaneously. Thus, two of the three reception thresholds T1, T2, T3 can be switched to the third reception threshold as required.
[0099] Therefore, the operation mode setting unit 1533 sets the reception thresholds T1, T2, and T3 according to the currently required operation mode (SLOW, FAST_TX, FAST_RX) of the transmission / reception device 12. Here, in the example described above, it applies that:
[0100]
[0101] Table 2: Assignment relationship between comparator - output signal and reception threshold
[0102] Specifically, this means for the aforementioned example that when the transmission / reception device 12 itself is in the FAST - operation mode (FAST_TX, FAST_RX), that is, during the data phase 452, only a single reception threshold, namely the reception threshold T3, is checked. For this purpose, the first reception comparator line 151 is used and switched to the reception threshold T3 (usually VDIFF = 0V). In contrast, during the arbitration phase 451, two reception comparator lines 151, 152 are used.
[0103] The second comparator 1522 can be set, for example, to identify a signal at the bus 40 during the data phase 452, which signal has a typical bit time t_bt2 of 50 ns ( ). In this case, the states L0 / L1 in the data phase 452 are transmitted or sent at a transmission rate of 20 Mbit / s. This requires a very high bandwidth for the second comparator 1522.
[0104] If the transmission / reception device 12 is currently a receiving node, that is, other user stations 10, 20, 30 at the bus 40 send messages 45 onto the bus 40, then the following applies. When an L1 state with t_bt2 = 50 ns is recognized ( ), the second comparator 1522 must confirm at its output in the signal CA2 with a pulse of at least 15 ns, as detailed in the standard CiA610 - 3. Thereby, when transitioning from the low - impedance dominant state 401 to the relatively higher - impedance recessive state 402, an oscillation S1 appears in the differential voltage VDIFF at the bus 40, as shown.
[0105] If the shielding block 155 is not activated, the reception signal driver 1221 outputs the reception signal RxD as shown in . Based on the required high bandwidth of the second comparator 1522, the undershoot (oscillation S1) appears as a dominant glitch G1 at the output RXD in the reception signal RxD, as shown in as shown. The glitch G1 is a small interference visible in the received signal RxD at the output RXD. In the example of all undershoots (oscillations S1) of
[0106] are respectively mapped in the RxD signal and are thus visible to the communication control device 11. Depending on the topology and the oscillation duration, the unwanted glitch G1 in the received signal RxD can occur up to the scan point t_A (sampling point). Since the glitch G1 distorts the received signal RxD, this interferes with the communication in the bus system 1.
[0107] However, if the shielding block 155 is activated, the received signal driver 1221 outputs the received signal RxD as shown in In the generated received signal of all undershoots (oscillations S1) of are respectively shielded and are thus not mapped in the RxD signal of and are thus also not visible to the communication control device 11.
[0108] In the receiving module 122, the output signal CA2 of the second comparator 1522 is output to the shielding block 155, in particular to its timing element 1551.
[0109] According to the first possible solution, the timing element 155 causes that, when entering the recessive bus state that drops below the reception threshold T1 and is detected by the first comparator 1512, the output of the second comparator 1522 is always shielded within a predefined shielding time t_22 according to the standard. Thereby, the undershoots (oscillations S1) in the differential voltage VDIFF of are "ignored" by the second comparator 1522 and are not signaled at RxD, as shown in
[0110] After the predefined time t_22 has elapsed, the output of the second comparator 1522 is switched on again. Thereby, the second comparator line 152 is fast and can achieve the values required in the standard CiA610-3.
[0111] Due to the shielding block 155, the second comparator 1522 does not have a high bandwidth according to the standard in the first communication phase 451 or in the first operating mode (SLOW phase) in order to detect at least 15 ns at the output for a 50 ns wide bit at the bus 40. The differential undershoot (oscillation S1) in the differential voltage VDIFF mainly depends on the bus topology, such as the number of branches, star topology, etc.
[0112] As an alternative, for a pre-determined value of the shielding time t_22, it can be automatically set in the transmitting / receiving device 12.
[0113] According to the second feasible solution, the following situation applies. If the reception threshold T1 in the transmitting / receiving device 12 is exceeded by a message 45 sent by other user stations 10, 20, 30 of the bus system 1, there is a dominant or L0 bus state. Thus, it is recognized in the transmitting / receiving device 12 that communication has occurred at the bus 40. Therefore, the received signal RxD becomes an LW (low level) value, whereby the communication control device 11 recognizes that the bus 40 is occupied.
[0114] According to the third feasible solution, the following situation applies. If the reception threshold T1 is not exceeded, it may be that a low L0 state has been sent by other user stations 10, 20, 30 of the bus system 1 and this L0 state is not detected by the reception threshold T1; or the bus 40 is indeed recessive and thus idle. Therefore, after a pre-determined time t_22 has elapsed, a measurement is made using the second comparator 1522, that is, using a high bandwidth. Thus, the L1 state in the signal on the bus 40 can be reliably recognized by the second comparator 1522.
[0115] That is, even if the physical layer is switched between the communication phases 451, 452 in order to send the signals CAN_H, CAN_L onto the bus 40, the shielding block 155 can always ensure in the receiving node, with the aid of the timing element 1551 and the logic circuit 1552, that the individual communication phases 451, 452 on the bus 40 are correctly recognized.
[0116] This enables a high data transfer rate at the bus 40 and thus a very efficient operation of the bus system 1.
[0117] According to the second embodiment, the transmitting module 121 generates the signals CAN_H, CAN_L for two communication phases on the bus 40, as described according to as follows.
[0118] An example of a part of the digital transmission signal TxD is shown. The transmitting module 121 receives this part from the communication control device 11 in the arbitration phase 451 and thereby generates the signals CAN_H, CAN_L for the bus 40. In it, the transmission signal TxD changes from an LW (low = Low) state to an HI (high = High) state and then back to the LW (low = Low) state.
[0119] Ideally, the received signal RxD is the same as the transmitted signal TxD. In such an ideal case, there is no transmission delay / runtime, especially via the bus 40, and no reception errors that may occur.
[0120] As shown in detail, the transmission module 121 can generate for the transmitted signal TxD of the signals CAN_H, CAN_L for the bus lines 41, 42 in CAN SIC or CANXL operation mode. Different from that, in the signals, there is additionally the state 403(sic). The state 403(sic) can have different durations, as shown by the state 403_0(sic) when transitioning from the state 402(rec) to the state 401(dom), and shown by the state 403_1(sic) when transitioning from the state 401(dom) to the state 402(rec). The state 403_0(sic) is shorter in time than the state 403_1(sic). To generate the signals according to the transmission module 121 is switched to the SIC operation mode (SIC mode).
[0121] According to the standard CiA610-3 for CAN XL, it is not required that the short sic state 403_0 operation is completed, and the state depends on the implementation method. For CAN-SIC and for the SIC operation mode in the case of CAN-XL, the duration of the "long" state 403_1(sic) is specified as t_sic < 530 ns, starting from the rising edge at the transmitted signal TxD of
[0122] The transmission module 121 should adapt the impedance between the bus lines 41 (CANH) and 42 (CANL) as well as possible to the characteristic impedance Zw of the used bus line during the "long" state 403_1(sic). Here, Zw = 100 Ohm or 120 Ohm applies. This adaptation prevents reflections and thus allows operation at higher bit rates. For simplicity, hereinafter, the state 403(sic) or the sic state 403 is always referred to.
[0123] Shows an example for other parts of the digital transmitted signal TxD. The transmission module 121 receives this part from the communication control device 11 ( ) in the data phase 452 according to the second embodiment, and thus generates the signals CAN_H, CAN_L for the bus 40. In In this case, the transmission signal TxD changes from the HI (High) state to the LW (Low) state multiple times and then back to the HI (High) state, and so on.
[0124] As shown in detail in for the transmission signal TxD of, the transmission module 121 generates signals CAN_H and CAN_L for the bus core wires 41 and 42 in such a way that the state L0 forms for the LW (Low) state. In addition, the state L1 forms for the HI (High) state.
[0125] It is feasible that for the two bus states L0 and L1, the dominant and recessive bus states are not used at least temporarily, but instead the first bus state and the second bus state are used, both of which are driven. An example of such a bus system is the CAN XL bus system.
[0126] The receiving module 122 can also receive signals in accordance with and in two different communication phases, namely the SIC operating mode or the arbitration phase 451 and the data phase 452. For this purpose, the receiving module 122 switches the reception thresholds T1 and T3 for the respective operating modes, as described above for the previous embodiments.
[0127] Therefore, the operating mode setting unit 1533 sets the reception thresholds T1, T2, and T3 in accordance with the currently required operating mode (SIC, FAST_TX, FAST_RX) of the transmission / reception device 120.
[0128] In this way, the comparator lines 151 and 152 with the shielding block 155 can also be operated very advantageously.
[0129] The transmission / reception device 12, the transmission module 121, the receiving module 122, the user stations 10, 20, 30, the bus system 1, and all the previously described design solutions of the method implemented therein according to the first embodiment and the second embodiment and their modifications can be used individually or in all feasible combinations. In particular, the following modifications can be envisaged additionally.
[0130] The bus system 1 described above according to the first embodiment and the second embodiment is described based on a bus system according to the CAN protocol. However, as an alternative, the bus system 1 according to the first embodiment and / or the second embodiment can be other types of communication networks, in which the signals are transmitted as differential signals. Advantageous but not a mandatory prerequisite is that in the bus system 1, at least for a specific period of time, exclusive and conflict-free access of the user stations 10, 20, 30 to the bus 40 is ensured.
[0131] The bus system 1 according to the first embodiment and / or the second embodiment and their modifications is in particular a CAN bus system or a CAN-HS bus system or a CAN FD bus system or a CAN SIC bus system or a CAN XL bus system. However, the bus system 1 can be other communication networks, in which signals are transmitted as differential signals and serially via the bus 40.
[0132] Therefore, the functions of the previously described embodiments can be used, for example, in the transmitting / receiving devices 12, 22, which can operate in a CAN bus system or a CAN-HS bus system or a CAN FD bus system or a CAN SIC bus system or a CAN XL bus system.
[0133] The number and arrangement of the user stations 10, 20, 30 in the bus system 1 according to the first embodiment and the second embodiment and their modifications are arbitrary. In particular, only the user station 10 or only the user station 30 is present in the bus system 1 of the first embodiment or the second embodiment.
Claims
1. A transmitting / receiving device (12) for a user station (10; 30) of a serial bus system (1), wherein, Differential signals (CAN_H, CAN_L) on the bus (40) of the bus system (1) are generated using a first physical layer (451_P) in a first communication phase (451) of communication on the bus (40) and using a second physical layer (452_P) in a second communication phase (452) of communication on the bus (40), wherein the transmitting / receiving device (12) has: A first comparator (1512) for evaluating differential signals (CAN_H, CAN_L) received from the bus (40) using a first reception threshold (T1) in the first communication phase (451) and for evaluating differential signals (CAN_H, CAN_L) received from the bus (40) using a third reception threshold (T3) in the second communication phase (452), wherein the first comparator (1512) is designed to output an output signal (CA1) in order to output a digital reception signal (RxD) to the communication control device (11) of the user station (10; 30); A second comparator (1522) for evaluating differential signals (CAN_H, CAN_L) received from the bus (40) using a second reception threshold (T2) for a reception signal driver (1221) in the first communication phase (451); and A shielding block (155) for generating a shielded comparator signal (Cm), which is a temporarily shielded output signal (CA2) of the second comparator (1522); and for generating an output signal (C1) for the reception signal driver (1221) from the shielded comparator signal (Cm) and the output signal (CA1) of the first comparator (1512).
2. The transmitting / receiving device (12) according to claim 1, wherein, The shielding block (155) has: A timing element (1551) connected to the output of the second comparator (1522) and designed to output the shielded comparator signal (Cm); And A logic circuit (1552) designed to generate a signal (C1) for output to the reception signal driver (1221) from the output signal (CA1) of the first comparator (1512) and the shielded comparator signal (Cm).
3. The transmitting / receiving device (12) according to claim 2, wherein, The logic circuit (1552) is an AND gate in order to form a logical "AND" connection of the output signal (CA1) of the first comparator (1512) and the shielded comparator signal (Cm) in a serial manner.
4. The transmitting / receiving device (12) according to any one of the preceding claims, which furthermore has: A driver (1221) for driving a digital reception signal (RxD) to the communication control device (11) of the user station (10; 30) of the bus system (1); and A received signal logic circuit (1222) that, when communicating in the first communication phase (451), transmits the output signal (C_1) of a first comparator line (151) having the first comparator (1512) and the output signal (C_2) of a second comparator line (152) having the second comparator (1522) to the driver (1221); and that, when communicating in the second communication phase (451), transmits only the output signal (C_1) of the first comparator line (151) to the driver (1221).
5. The transmitting / receiving device (12) according to any one of the preceding claims, which furthermore has: A first voltage divider (1531) connected to the bus (40), which outputs the differential signal (CAN_H, CAN_L) received from the bus (40) to the first comparator (1512); A second voltage divider (1532) connected to the bus (40), which outputs the differential signal (CAN_H, CAN_L) received from the bus (40) to the second comparator (1522).
6. The transmitting / receiving device (12) according to claim 5, Among them, The first and second voltage dividers (1531, 1532) have a circuit consisting of resistors, and the first and second comparators (1512, 1522) are connected to the resistors, and wherein the first and second comparators (1512, 1522) simultaneously evaluate the differential signal (CAN_H, CAN_L).
7. The transmitting / receiving device (12) according to claim 5 or 6, Among them, The first voltage divider (1531) has a switch (Sw1) arranged to set the first reception threshold (T1) for the first voltage divider (1532) in a first switching position and the third reception threshold (T3) for the first voltage divider (1532) in a second switching position, and wherein the second voltage divider (1532) is designed to set the second reception threshold (T2).
8. The transmitting / receiving apparatus (12) according to claim 7, wherein, The switch (Sw1) is arranged to connect or disconnect a ground resistor.
9. The transmitting / receiving device (12) according to claim 7 or 8, wherein, The switch (Sw1) is an NMOS transistor.
10. The transmitting / receiving device (12) according to any one of claims 7 to 9, Among them, The transmitting / receiving device (12) is designed such that, when the switch (Sw1) has set the first reception threshold (T1) in the first voltage divider (1532) in its first switching position, the output signal (CA2) of the second comparator (1522) is output to the received signal driver (1221), and Wherein, the transmitting / receiving device (12) is designed such that when the switch (Sw1) has set the third reception threshold (T3) in the first voltage divider (1532) in its second switching position, the output signal (CA2) of the second comparator (1522) is not output to the reception signal driver (1221).
11. The transmitting / receiving device (12) according to any one of claims 7 to 10, which further has an operating mode setting unit (1533) for controlling the switch (Sw1) to cause the first voltage divider (1531) to switch between the first reception threshold and the third reception threshold (T1, T3) according to whether a first communication phase or a second communication phase (451, 452) is being carried out on the bus (40).
12. The transmitting / receiving device (12; 22; 120) according to any one of the preceding claims, which further has a transmitting module (121) for transmitting a signal onto the bus (40) of the bus system (1).
13. A user station (10; 20; 30) for a serial bus system (1), the user station having: The transmitting / receiving device (12; 22) according to any one of the preceding claims; and A communication control device (11; 21) for controlling communication in the bus system (1) and for generating a digital transmission signal (TxD) for the transmitting module (121).
14. The user station (10; 20; 30) according to claim 11, wherein, The user station (10; 20; 30) is designed for communication in the bus system (1), in which at least temporarily exclusive and conflict-free access of the user station (10, 20, 30) to the bus (40) of the bus system (1) is ensured.
15. A method for receiving differential signals in a serial bus system (1), wherein, Differential signals (CAN_H, CAN_L) on the bus (40) of the bus system (1) are generated using a first physical layer (451_P) in a first communication phase (451) of communication on the bus (40) and using a second physical layer (452_P) in a second communication phase (452) of communication on the bus (40), wherein the method has the following steps: Receiving the differential signals (CAN_H, CAN_L) from the bus (40) using the transmitting and receiving device (12); Evaluating the differential signals (CAN_H, CAN_L) received from the bus (40) using a first comparator (1512) with a first reception threshold (T1) in the first communication phase (451); In the second communication phase (452), a first comparator (1512) is used to evaluate differential signals (CAN_H, CAN_L) received from the bus (40) by using a third reception threshold (T3), wherein the first comparator (1512) for outputting an output signal (CA1) in the first communication phase and the second communication phase (451, 452) outputs a digital reception signal (RxD) to a communication control device (11) of the user station (10; 30); and In the first communication phase (451), a second comparator (1522) is used to evaluate differential signals (CAN_H, CAN_L) received from the bus (40) by using a second reception threshold (T2) for the reception signal driver (1221); and A shield block (155) is used to generate a shielded comparator signal (Cm), which is a temporarily shielded output signal (CA2) of the second comparator (1522); and The shield block (155) is used to generate an output signal (C1) for the reception signal driver (1221) from the shielded comparator signal (Cm) and an output signal (CA1) of the first comparator (1512).