Method and system for verifying accuracy of impedance model of power electronic equipment

Abstract

The invention discloses a method and system for verifying the accuracy of an impedance model of power electronic equipment, and belongs to the technical field of power systems. The method comprises the following steps: measuring a first impedance characteristic of a power electronic semi-physical device or actual equipment; measuring a second impedance characteristic of the power electronic semi-physical device or the actual equipment simulation model; and verifying the accuracy of the power electronic semi-physical device or the actual equipment simulation model by adopting a sliding error method according to the first impedance characteristic and the second impedance characteristic. The accuracy of the simulation model is verified by adopting a sliding error method, and the accuracy of the impedance characteristic of the new energy unit can be accurately verified.

Description

Technical Field

[0001] The present invention relates to the technical field of power systems, and more particularly, to a method and system for verifying the accuracy of impedance models of power electronic devices. Background Art

[0002] Significantly increasing the proportion of non-fossil energy power and promoting the transformation of the main energy source from fossil energy to non-fossil energy are the core indicators of China's energy transformation. Around this indicator, the power system will play an irreplaceable role. With the access of ultra-large-scale AC / DC power transmission and a large number of new energy power electronic devices to the system, China's power grid pattern and power source structure are undergoing major changes.

[0003] On the one hand, the rapid development of DC power transmission has become the primary factor for the increase in the proportion of power electronic equipment. Since 2010, China has successively put into operation 13 UHV DC projects of ±800 kV and above; as of October 2019, the in-service DC transmission lines of ±800 kV and above were 25,209 km. The grid connection of high-proportion new energy units such as wind power and photovoltaic through power electronic devices and the increase in the DC proportion have led to the gradual emergence of multi-time-scale dynamic stability problems in the sub-synchronous - super-synchronous - high-frequency band.

[0004] In recent years, dynamic stability problems participated in or caused by power electronic equipment have frequently occurred at home and abroad, mainly manifested as oscillation phenomena with a frequency range from sub-synchronous to high-frequency band, and the power electronic equipment involved covers different types of power generation equipment such as wind power and photovoltaic, and transmission equipment such as DC and FACTS.

[0005] Compared with traditional electromagnetic conversion equipment such as generators, power electronic equipment has significant differences in physical structure, control mode, dynamic response, interaction with other equipment, etc. After power electronic equipment is widely used in the power system, its fast and flexible control characteristics will profoundly affect the dynamic behavior of the power system. At present, due to the relatively high proportion of power electronic equipment connected to the power system only in local power grids, the sub-synchronous - super-synchronous - high-frequency band dynamic stability problems and system frequency drop problems brought by power electronic equipment still show localized and single characteristics. For example, in areas with a relatively high proportion of new energy, there are oscillation problems of multiple power plants, multiple units, and multiple modes; the DC blocking of multiple DC feeders in the receiving-end power grid leads to the problem of abnormal frequency drop of the system, and the impact on the overall stability of the power system is relatively limited. However, as the overall proportion of power electronic equipment continues to increase, such stability problems will gradually develop towards globalization and complexity. The broadband oscillation and frequency stability problems brought by a high proportion of power electronic equipment will gradually become the dominant problems determining the stability characteristics of the entire power system in the future. The premise of impedance analysis for new energy is to conduct impedance modeling of new energy. However, currently, there is only one sentence mentioned in the standard for the verification method of the accuracy of the impedance characteristics modeling of a single new energy unit, lacking both accuracy and universality. Summary of the Invention

[0006] In view of the above problems, the present invention proposes a method for verifying the accuracy of the impedance model of power electronic equipment, including:

[0007] Measuring the first impedance characteristic of a power electronic hardware-in-the-loop device or an actual device;

[0008] Measuring the second impedance characteristic of the simulation model of a power electronic hardware-in-the-loop device or an actual device;

[0009] Using the sliding error method, verifying the accuracy of the simulation model of the power electronic hardware-in-the-loop device or an actual device according to the first impedance characteristic and the second impedance characteristic.

[0010] Optionally, the power electronic hardware-in-the-loop device or an actual device includes: a wind power, photovoltaic, energy storage, or SVG hardware-in-the-loop device or an actual device.

[0011] Optionally, measuring the first impedance characteristic of a power electronic hardware-in-the-loop device or an actual device includes:

[0012] Injecting a harmonic power signal into the power electronic hardware-in-the-loop device or an actual device by using a preset method. After injecting the harmonic power signal, measuring the first impedance characteristic curve of the power electronic hardware-in-the-loop device or an actual device, and determining the first impedance characteristic according to the first impedance characteristic curve.

[0013] Optionally, the injected harmonic power supply signal is divided into: positive-sequence harmonic signal fp and negative-sequence harmonic signal fn. The disturbance voltage amplitude of the harmonic power supply signal is: 1% - 5% of the rated voltage amplitude of the power electronic hardware-in-the-loop device or the actual equipment. The frequency interval is as follows:

[0014] When the frequency is 1 - 10 Hz, the step size is 0.1 Hz, and each step lasts for no less than 10 s;

[0015] When the frequency is 10 - 100 Hz, the step size is 1 Hz, and each step lasts for no less than 5 s;

[0016] When the frequency is 100 - 2500 Hz, the step size is 10 Hz, and each step lasts for no less than 2 s.

[0017] Optionally, measuring the first impedance characteristic curve of the power electronic hardware-in-the-loop device or the actual equipment includes:

[0018] Using the fft algorithm to calculate the positive-sequence voltage, positive-sequence current, negative-sequence voltage and negative-sequence current of the power electronic hardware-in-the-loop device or the actual equipment at the corresponding frequency. According to the positive-sequence voltage, positive-sequence current, negative-sequence voltage and negative-sequence current, calculate the positive-sequence impedance and negative-sequence impedance, and draw the first impedance characteristic curve according to the positive-sequence impedance and negative-sequence impedance.

[0019] Optionally, the first impedance characteristic includes: when P = 0.1 - 0.9, the impedance characteristics under Q = maximum inductive reactive power and Q = maximum capacitive reactive power.

[0020] Optionally, measuring the second impedance characteristic of the power electronic hardware-in-the-loop device or the actual equipment simulation model includes:

[0021] Injecting a harmonic power supply signal into the power electronic hardware-in-the-loop device or the actual equipment simulation model by using a preset method, and keeping the system equivalent impedance and the parameters of the transformer substation consistent. After injecting the harmonic power supply signal, measure the second impedance characteristic curve of the simulation model, and determine the second impedance characteristic according to the second impedance characteristic curve.

[0022] Optionally, the injected harmonic power supply signal is divided into: positive-sequence harmonic signal fp and negative-sequence harmonic signal fn. The disturbance voltage amplitude of the harmonic power supply signal is: 1% - 5% of the rated voltage amplitude of the power electronic hardware-in-the-loop device or the actual equipment. The frequency interval is as follows:

[0023] When the frequency is 1 - 10 Hz, the step size is 0.1 Hz, and each step lasts for no less than 10 s;

[0024] When the frequency is 10 - 100 Hz, the step size is 1 Hz, and each step lasts for no less than 5 s;

[0025] When the frequency is 100 - 2500 Hz, the step size is 10 Hz, and each step lasts for no less than 2 s.

[0026] Optionally, measure the second impedance characteristic curve of the power electronic hardware-in-the-loop device or the actual device, including:

[0027] Use the fft algorithm to calculate the positive sequence voltage, positive sequence current, negative sequence voltage and negative sequence current of the simulation model at the corresponding frequency. According to the positive sequence voltage, positive sequence current, negative sequence voltage and negative sequence current, calculate the positive sequence impedance and negative sequence impedance, and draw the second impedance characteristic curve according to the positive sequence impedance and negative sequence impedance.

[0028] Optionally, the second impedance characteristic includes: when P = 0.1 - 0.9, the impedance characteristics under the conditions of Q = maximum inductive reactive power and Q = maximum capacitive reactive power.

[0029] Optionally, adopt the sliding error method to verify the accuracy of the simulation model of the power electronic hardware-in-the-loop device or the actual device according to the first impedance characteristic and the second impedance characteristic, including:

[0030] Adopt the sliding error method, set the number of sampling points in the sliding window. Based on the set number of sampling points in the sliding window, calculate the first sliding average value of the impedance amplitude and impedance phase of the power electronic hardware-in-the-loop device or the actual device according to the first impedance characteristic. Based on the set number of sampling points in the sliding window, calculate the second sliding average value of the impedance amplitude and impedance phase of the simulation model according to the second impedance characteristic. Based on the first sliding average value and the second sliding average value, calculate the sliding error, and verify the accuracy of the simulation model based on the sliding error.

[0031] Optionally, the sliding error includes: the sliding error of the positive / negative sequence impedance amplitude and the sliding error of the positive / negative sequence impedance phase;

[0032] If the sliding error of the positive sequence impedance amplitude and the sliding error of the negative sequence impedance amplitude are both less than 5 db, and the sliding error of the positive sequence impedance phase and the sliding error of the negative sequence impedance phase are both less than 5°, it is determined that the simulation model meets the error requirements, that is, the simulation model meets the accuracy requirements.

[0033] On the other hand, the present invention proposes a system for verifying the accuracy of the impedance model of a power electronic device, including:

[0034] The first measurement unit is used to measure the first impedance characteristic of the power electronic hardware-in-the-loop device or the actual device;

[0035] The second measurement unit measures the second impedance characteristic of the simulation model of the power electronic hardware-in-the-loop device or the actual device;

[0036] A verification unit, which is used to verify the accuracy of the power electronic hardware-in-the-loop device or the simulation model of the actual device by using the sliding error method according to the first impedance characteristic and the second impedance characteristic.

[0037] Optionally, the power electronic hardware-in-the-loop device or the actual device includes: a wind power, photovoltaic, energy storage or SVG hardware-in-the-loop device or the actual device.

[0038] Optionally, measuring the first impedance characteristic of the power electronic hardware-in-the-loop device or the actual device includes:

[0039] Injecting a harmonic power supply signal into the power electronic hardware-in-the-loop device or the actual device by using a preset method. After injecting the harmonic power supply signal, measuring the first impedance characteristic curve of the power electronic hardware-in-the-loop device or the actual device, and determining the first impedance characteristic according to the first impedance characteristic curve.

[0040] Optionally, the injected harmonic power supply signal is divided into: a positive-sequence harmonic signal fp and a negative-sequence harmonic signal fn. The disturbance voltage amplitude of the harmonic power supply signal is: 1% - 5% of the rated voltage amplitude of the power electronic hardware-in-the-loop device or the actual device. The frequency interval is as follows:

[0041] When the frequency is 1 - 10 Hz, the step size is 0.1 Hz, and each step lasts for no less than 10 s;

[0042] When the frequency is 10 - 100 Hz, the step size is 1 Hz, and each step lasts for no less than 5 s;

[0043] When the frequency is 100 - 2500 Hz, the step size is 10 Hz, and each step lasts for no less than 2 s.

[0044] Optionally, measuring the first impedance characteristic curve of the power electronic hardware-in-the-loop device or the actual device includes:

[0045] Using the FFT algorithm to calculate the positive-sequence voltage, positive-sequence current, negative-sequence voltage and negative-sequence current of the power electronic hardware-in-the-loop device or the actual device at the corresponding frequency. According to the positive-sequence voltage, positive-sequence current, negative-sequence voltage and negative-sequence current, calculating the positive-sequence impedance and negative-sequence impedance, and drawing the first impedance characteristic curve according to the positive-sequence impedance and negative-sequence impedance.

[0046] Optionally, the first impedance characteristic includes: the impedance characteristics when Q = the maximum inductive reactive power and Q = the maximum capacitive reactive power when P = 0.1 - 0.9.

[0047] Optionally, measuring the second impedance characteristic of the simulation model of the power electronic hardware-in-the-loop device or the actual device includes:

[0048] Inject a harmonic power supply signal into the power electronic hardware-in-the-loop device or the simulation model of the actual equipment by using a preset method, and keep the equivalent impedance of the system and the parameters of the distribution transformer consistent. After injecting the harmonic power supply signal, measure the second impedance characteristic curve of the simulation model, and determine the second impedance characteristic according to the second impedance characteristic curve.

[0049] Optionally, the injected harmonic power supply signal is divided into: positive-sequence harmonic signal fp and negative-sequence harmonic signal fn, and the disturbance voltage amplitude of the harmonic power supply signal is: 1% - 5% of the rated voltage amplitude of the power electronic hardware-in-the-loop device or the actual equipment, and the frequency interval is as follows:

[0050] When the frequency is 1 - 10 Hz, the step size is 0.1 Hz, and each step lasts for no less than 10 s;

[0051] When the frequency is 10 - 100 Hz, the step size is 1 Hz, and each step lasts for no less than 5 s;

[0052] When the frequency is 100 - 2500 Hz, the step size is 10 Hz, and each step lasts for no less than 2 s.

[0053] Optionally, measuring the second impedance characteristic curve of the power electronic hardware-in-the-loop device or the actual equipment includes:

[0054] Use the fft algorithm to calculate the positive-sequence voltage, positive-sequence current, negative-sequence voltage and negative-sequence current of the simulation model at the corresponding frequency. According to the positive-sequence voltage, positive-sequence current, negative-sequence voltage and negative-sequence current, calculate the positive-sequence impedance and negative-sequence impedance, and draw the second impedance characteristic curve according to the positive-sequence impedance and negative-sequence impedance.

[0055] Optionally, the second impedance characteristic includes: the impedance characteristics when P = 0.1 - 0.9 and Q = the maximum inductive reactive power and Q = the maximum capacitive reactive power.

[0056] Optionally, adopt the sliding error method to verify the accuracy of the simulation model of the power electronic hardware-in-the-loop device or the actual equipment according to the first impedance characteristic and the second impedance characteristic, including:

[0057] Adopt the sliding error method to set the number of sampling points in the sliding window. Based on the set number of sampling points in the sliding window, calculate the first sliding average value of the impedance amplitude and impedance phase of the power electronic hardware-in-the-loop device or the actual equipment according to the first impedance characteristic. Based on the set number of sampling points in the sliding window, calculate the second sliding average value of the impedance amplitude and impedance phase of the simulation model according to the second impedance characteristic. Based on the first sliding average value and the second sliding average value, calculate the sliding error, and verify the accuracy of the simulation model based on the sliding error.

[0058] Optionally, the sliding error includes: the sliding error of the positive / negative sequence impedance amplitude and the sliding error of the positive / negative sequence impedance phase;

[0059] If both the sliding error of the positive sequence impedance amplitude and the sliding error of the negative sequence impedance amplitude are less than 5 dB, and both the sliding error of the positive sequence impedance phase and the sliding error of the negative sequence impedance phase are less than 5°, it is determined that the simulation model meets the error requirements, that is, the simulation model meets the accuracy requirements.

[0060] On the other hand, the present invention also provides a computing device, including: one or more processors;

[0061] The processor is configured to execute one or more programs;

[0062] When the one or more programs are executed by the one or more processors, the method as described above is implemented.

[0063] On the other hand, the present invention also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed, the method as described above is implemented.

[0064] Compared with the prior art, the beneficial effects of the present invention are:

[0065] The present invention provides a method for verifying the accuracy of an impedance model of a power electronic device, including: measuring the first impedance characteristic of a power electronic hardware-in-the-loop device or an actual device; measuring the second impedance characteristic of a simulation model of the power electronic hardware-in-the-loop device or the actual device; using the sliding error method to verify the accuracy of the simulation model of the power electronic hardware-in-the-loop device or the actual device according to the first impedance characteristic and the second impedance characteristic. The present invention uses the sliding error method to verify the accuracy of the simulation model, and can accurately verify the accuracy of the impedance characteristic of a new energy unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] Figure 1 is a flowchart of the method of the present invention;

[0067] Figure 2 is a schematic diagram of injecting a harmonic power source when measuring the impedance of a wind turbine by using a series harmonic voltage source in the method of the present invention;

[0068] Figure 3 is a schematic diagram of injecting a harmonic power source when measuring the impedance of a wind turbine by using a parallel harmonic current source in the method of the present invention;

[0069] Figure 4 is a schematic diagram of setting the number of sampling points of a sliding window in the method of the present invention;

[0070] Figure 5 is a structural diagram of the system of the present invention. DETAILED DESCRIPTION

[0071] Reference is now made to the accompanying drawings to describe exemplary embodiments of the present invention. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided to disclose the present invention in detail and completely, and to fully convey the scope of the present invention to those skilled in the art. The terms in the exemplary embodiments shown in the drawings are not limitations on the present invention. In the drawings, the same units / components are denoted by the same reference numerals.

[0072] Unless otherwise specified, the terms used herein (including scientific and technical terms) have the ordinary meaning understood by those skilled in the art. In addition, it can be understood that the terms defined in the commonly used dictionary should be understood as having a consistent meaning with the context of their related fields, and should not be understood as idealized or overly formal meanings.

[0073] Embodiment 1:

[0074] The present invention proposes a method for verifying the accuracy of the impedance model of a power electronic device, as Figure 1 shown, including:

[0075] Step 1, measuring the first impedance characteristic of a power electronic hardware-in-the-loop device or an actual device;

[0076] Step 2, measuring the second impedance characteristic of the simulation model of the power electronic hardware-in-the-loop device or the actual device;

[0077] Step 3, using the sliding error method to verify the accuracy of the simulation model of the power electronic hardware-in-the-loop device or the actual device according to the first impedance characteristic and the second impedance characteristic.

[0078] Among them, the power electronic hardware-in-the-loop device or the actual device includes: a wind power, photovoltaic, energy storage or SVG hardware-in-the-loop device or an actual device.

[0079] Among them, measuring the first impedance characteristic of the power electronic hardware-in-the-loop device or the actual device includes:

[0080] Injecting a harmonic power supply signal into the power electronic hardware-in-the-loop device or the actual device by using a preset method. After injecting the harmonic power supply signal, measuring the first impedance characteristic curve of the power electronic hardware-in-the-loop device or the actual device, and determining the first impedance characteristic according to the first impedance characteristic curve.

[0081] Among them, the injected harmonic power supply signal is divided into: a positive sequence harmonic signal fp and a negative sequence harmonic signal fn. The disturbance voltage amplitude of the harmonic power supply signal is: 1% - 5% of the rated voltage amplitude of the power electronic hardware-in-the-loop device or the actual device. The frequency interval is as follows:

[0082] When the frequency is 1 - 10 Hz, the step size is 0.1 Hz, and each step lasts for no less than 10 s;

[0083] When the frequency is 10 - 100 Hz, the step size is 1 Hz, and each step lasts for no less than 5 s;

[0084] When the frequency is 100 - 2500 Hz, the step size is 10 Hz, and each step lasts for no less than 2 s.

[0085] Among them, measuring the first impedance characteristic curve of the power electronic hardware-in-the-loop device or the actual equipment includes:

[0086] Using the fft algorithm to calculate the positive-sequence voltage, positive-sequence current, negative-sequence voltage and negative-sequence current of the power electronic hardware-in-the-loop device or the actual equipment at the corresponding frequency, calculating the positive-sequence impedance and negative-sequence impedance according to the positive-sequence voltage, positive-sequence current, negative-sequence voltage and negative-sequence current, and drawing the first impedance characteristic curve according to the positive-sequence impedance and negative-sequence impedance.

[0087] Among them, the first impedance characteristic includes: when P = 0.1 - 0.9, the impedance characteristics under Q = maximum inductive reactive power and Q = maximum capacitive reactive power.

[0088] Among them, measuring the second impedance characteristic of the power electronic hardware-in-the-loop device or the actual equipment simulation model includes:

[0089] Injecting a harmonic power supply signal into the power electronic hardware-in-the-loop device or the actual equipment simulation model by using a preset method, and keeping the system equivalent impedance and the box transformer parameters consistent. After injecting the harmonic power supply signal, measuring the second impedance characteristic curve of the simulation model, and determining the second impedance characteristic according to the second impedance characteristic curve.

[0090] Among them, the injected harmonic power supply signal is divided into: positive-sequence harmonic signal fp and negative-sequence harmonic signal fn, and the disturbance voltage amplitude of the harmonic power supply signal is: 1% - 5% of the rated voltage amplitude of the power electronic hardware-in-the-loop device or the actual equipment, and the frequency interval is as follows:

[0091] When the frequency is 1 - 10 Hz, the step size is 0.1 Hz, and each step lasts for no less than 10 s;

[0092] When the frequency is 10 - 100 Hz, the step size is 1 Hz, and each step lasts for no less than 5 s;

[0093] When the frequency is 100 - 2500 Hz, the step size is 10 Hz, and each step lasts for no less than 2 s.

[0094] Among them, measuring the second impedance characteristic curve of the power electronic hardware-in-the-loop device or the actual equipment includes:

[0095] Using the FFT algorithm, calculate the positive-sequence voltage, positive-sequence current, negative-sequence voltage, and negative-sequence current of the simulation model at the corresponding frequencies. Based on the positive-sequence voltage, positive-sequence current, negative-sequence voltage, and negative-sequence current, calculate the positive-sequence impedance and negative-sequence impedance, and draw the second impedance characteristic curve based on the positive-sequence impedance and negative-sequence impedance.

[0096] Among them, the second impedance characteristic includes: when P = 0.1 - 0.9, the impedance characteristics under the conditions of Q = maximum inductive reactive power and Q = maximum capacitive reactive power.

[0097] Among them, the sliding error method is used to verify the accuracy of the power electronic semi-physical device or the actual equipment simulation model according to the first impedance characteristic and the second impedance characteristic, including:

[0098] Using the sliding error method, set the number of sampling points in the sliding window. Based on the set number of sampling points in the sliding window, according to the first impedance characteristic, calculate the first sliding average value of the impedance amplitude and impedance phase of the power electronic semi-physical device or the actual equipment. Based on the set number of sampling points in the sliding window, according to the second impedance characteristic, calculate the second sliding average value of the impedance amplitude and impedance phase of the simulation model. Based on the first sliding average value and the second sliding average value, calculate the sliding error, and based on the sliding error, verify the accuracy of the simulation model.

[0099] Among them, the sliding error includes: the sliding error of the positive / negative sequence impedance amplitude and the sliding error of the positive / negative sequence impedance phase;

[0100] If the sliding error of the positive-sequence impedance amplitude and the sliding error of the negative-sequence impedance amplitude are both less than 5 dB, and the sliding error of the positive-sequence impedance phase and the sliding error of the negative-sequence impedance phase are both less than 5°, then it is determined that the simulation model meets the error requirements, that is, the simulation model meets the accuracy requirements.

[0101] The following further illustrates the present invention with specific cases:

[0102] The specific steps are as follows:

[0103] Step 1. Measure the impedance characteristics of the power electronic semi-physical device (or actual equipment):

[0104] Taking a fan as an example, including but not limited to wind power, photovoltaic, energy storage, SVG, etc.:

[0105] (1) According to Figure 2 Or Figure 3 The method shown injects a harmonic power supply.

[0106] (2) Measure the impedance characteristic curve of a single wind turbine generator set. Set the active power of the wind turbine generator set as P = 1 pu and Q = 0 pu, measure the terminal voltage vabc and terminal current iabc of the wind turbine generator set, and measure the impedance curve at the current power point. The measurement method is as follows:

[0107] ① The injected harmonic signals are divided into positive-sequence harmonic signal fp and negative-sequence harmonic signal fn. The disturbance voltage amplitude is 1% - 5% of the rated voltage amplitude of the wind turbine generator set, and the frequency interval is:

[0108] a. 1 - 10 Hz, with a step size of 0.1 Hz; each step lasts for no less than 10 s;

[0109] b. 10 - 100 Hz, with a step size of 1 Hz; each step lasts for no less than 5 s;

[0110] c. 100 - 2500 Hz, with a step size of 10 Hz; each step lasts for no less than 2 s;

[0111] ② Use the fft algorithm to calculate the positive-sequence voltage vph(fp), positive-sequence current iph(fp), negative-sequence voltage vnh(fn), and negative-sequence current inh(fn) at the corresponding frequencies;

[0112] ③ Calculate the positive-sequence impedance Zwph = vph(fp) / iph(fp) at the corresponding frequency points; the negative-sequence impedance Zwnh = vnh(fn) / inh(fn);

[0113] For the cases of P = 0.9, 0.8, 0.7, 0.6, 0.5, 0.4, 0.3, 0.2, 0.1, Q = maximum inductive reactive power and Q = maximum capacitive reactive power, repeat step (2).

[0114] Step 2. Measure the impedance characteristics of the electronic device simulation model:

[0115] Taking the wind turbine as an example, including but not limited to wind power, photovoltaic, energy storage, svg, etc.:

[0116] (1) According to Figure 1 Or Figure 2 Inject harmonic power supply according to the method shown, and at the same time ensure that the equivalent impedance of the system and the parameters of the box transformer are consistent.

[0117] (2) Measure the impedance characteristic curve of a single wind turbine generator set. Set the active power of the wind turbine generator set as P = 1 pu and Q = 0 pu, measure the terminal voltage vabc and terminal current iabc of the wind turbine generator set, and measure the impedance curve at the current power point. The measurement method is as follows:

[0118] ① The injected harmonic signals are divided into positive-sequence harmonic signal fp and negative-sequence harmonic signal fn. The disturbance voltage amplitude is 1% - 5% of the rated voltage amplitude of the wind turbine generator set, and the frequency interval is:

[0119] a. 1 - 10 Hz, with a step size of 0.1 Hz; each step lasts for no less than 10 s;

[0120] b. 10 - 100 Hz, with a step size of 1 Hz; each step lasts for no less than 5 s;

[0121] c. 100 - 2500 Hz, with a step size of 10 Hz; each step lasts for no less than 2 s;

[0122] ② Use the fft algorithm to calculate the positive - sequence voltage vps(fp), positive - sequence current ips(fp), negative - sequence voltage vns(fn), and negative - sequence current ins(fn) at the corresponding frequencies;

[0123] ③ Calculate the positive - sequence impedance Zwps = vps(fp) / ips(fp); negative - sequence impedance Zwns = vns(fn) / ins(fn);

[0124] For P = 0.9, 0.8, 0.7, 0.6, 0.5, 0.4, 0.3, 0.2, 0.1, Q = maximum inductive reactive power and Q = maximum capacitive reactive power cases, repeat step (2).

[0125] Step 3. Impedance characteristic consistency verification:

[0126] (1) Set the number of sampling points N in the sliding window, as Figure 4 shown;

[0127] where M represents the M - th frequency point and S represents the total number of S frequency points.

[0128] (2) Calculate the sliding average value Z Aveposh， Z Avenegh ;

[0129] The positive - sequence impedance Zwph can be written as Zwph = Z A +Z ph , where Z A is the impedance amplitude and Z ph is the impedance phase:

[0130]

[0131] Similarly, calculate the sliding average value Z Avenegh ;

[0132] (3) Calculate the sliding average value Z phaveposh ,Z phavenegh ;

[0133] First, convert the phase:

[0134]

[0135] Next, calculate the hardware-in-the-loop phase sliding average value Z phaveposh , Z phavenegh ;

[0136]

[0137] Finally, convert the phase back to -180° to 180°;

[0138]

[0139] Similarly, calculate the hardware-in-the-loop negative sequence impedance phase sliding average value Z phavenegh ;

[0140] (4) Calculate the simulation model impedance amplitude sliding average value Z Aveposs， Z Avenegs ;

[0141] The positive sequence impedance Zwps can be written as Zwph = Z A + Z ph , where Z A is the impedance amplitude and Z ph is the impedance phase;

[0142]

[0143] Similarly, calculate the simulation model negative sequence impedance amplitude sliding average value ZAvenegs;

[0144] (5) Calculate the simulation model impedance phase sliding average value Z phaveposs , Z phavenegs ;

[0145] First, convert the phase:

[0146]

[0147] Next, calculate the simulation model phase sliding average value Z phaveposs , Z phavenegs :

[0148]

[0149] Finally, convert the phase back to -180° to 180°;

[0150]

[0151] Similarly, calculate the simulation model negative sequence impedance phase sliding average value Z phavenegs ;

[0152] (6) Calculate the sliding error of the impedance of the hardware-in-the-loop and simulation model:

[0153] First, calculate the sliding error Z of the positive-sequence impedance amplitude Aerrorpos and the sliding error Z of the positive-sequence impedance phase pherrorpos ;

[0154] Z Aerrorpos (M) = abs(Z Aaveposh (M) - Z Aaveposs (M))

[0155] Z pherrorpos (M) = abs(Z phaveposh (M) - Z phaveposs (M))

[0156] Similarly, calculate the sliding error Z of the negative-sequence impedance amplitude Aerrorneg and the sliding error Z of the negative-sequence impedance phase pherrorneg ;

[0157] (7) Check whether the error meets the requirements:

[0158] The sliding error Z of the positive-sequence impedance amplitude Aerrorpos and the sliding error Z of the negative-sequence impedance amplitude Aerrorneg both need to be less than 5 db, and the sliding error Z of the positive-sequence impedance phase pherrorpos and the sliding error Z of the negative-sequence impedance phase pherrorneg both need to be less than 5° to meet the error requirements.

[0159] Embodiment 2:

[0160] The present invention also proposes a system 200 for verifying the accuracy of the impedance model of a power electronic device, as Figure 5 shown, including:

[0161] The first measurement unit 201 is used to measure the first impedance characteristic of the power electronic hardware-in-the-loop device or the actual device;

[0162] The second measurement unit 202 measures the second impedance characteristic of the simulation model of the power electronic hardware-in-the-loop device or the actual device;

[0163] The verification unit 203 is used to verify the accuracy of the simulation model of the power electronic hardware-in-the-loop device or the actual device by using the sliding error method according to the first impedance characteristic and the second impedance characteristic.

[0164] Among them, the power electronic hardware-in-the-loop device or the actual device includes: a wind power, photovoltaic, energy storage, or SVG hardware-in-the-loop device or the actual device.

[0165] Among them, measuring the first impedance characteristic of the power electronic hardware-in-the-loop device or the actual device includes:

[0166] Inject a harmonic power supply signal into the power electronic hardware-in-the-loop device or the actual equipment by using a preset method. After injecting the harmonic power supply signal, measure the first impedance characteristic curve of the power electronic hardware-in-the-loop device or the actual equipment, and determine the first impedance characteristic according to the first impedance characteristic curve.

[0167] Among them, the injected harmonic power supply signal is divided into: positive sequence harmonic signal fp and negative sequence harmonic signal fn. The disturbance voltage amplitude of the harmonic power supply signal is: 1% - 5% of the rated voltage amplitude of the power electronic hardware-in-the-loop device or the actual equipment. The frequency interval is as follows:

[0168] When the frequency is 1 - 10 Hz, the step size is 0.1 Hz, and each step lasts for no less than 10 s;

[0169] When the frequency is 10 - 100 Hz, the step size is 1 Hz, and each step lasts for no less than 5 s;

[0170] When the frequency is 100 - 2500 Hz, the step size is 10 Hz, and each step lasts for no less than 2 s.

[0171] Among them, measuring the first impedance characteristic curve of the power electronic hardware-in-the-loop device or the actual equipment includes:

[0172] Use the fft algorithm to calculate the positive sequence voltage, positive sequence current, negative sequence voltage and negative sequence current of the power electronic hardware-in-the-loop device or the actual equipment at the corresponding frequency. Calculate the positive sequence impedance and negative sequence impedance according to the positive sequence voltage, positive sequence current, negative sequence voltage and negative sequence current, and draw the first impedance characteristic curve according to the positive sequence impedance and negative sequence impedance.

[0173] Among them, the first impedance characteristic includes: the impedance characteristics when P = 0.1 - 0.9 and Q = the maximum inductive reactive power and Q = the maximum capacitive reactive power.

[0174] Among them, measuring the second impedance characteristic of the power electronic hardware-in-the-loop device or the actual equipment simulation model includes:

[0175] Inject a harmonic power supply signal into the power electronic hardware-in-the-loop device or the actual equipment simulation model by using a preset method, and keep the system equivalent impedance and the transformer substation parameters consistent. After injecting the harmonic power supply signal, measure the second impedance characteristic curve of the simulation model, and determine the second impedance characteristic according to the second impedance characteristic curve.

[0176] Among them, the injected harmonic power supply signal is divided into: positive sequence harmonic signal fp and negative sequence harmonic signal fn. The disturbance voltage amplitude of the harmonic power supply signal is: 1% - 5% of the rated voltage amplitude of the power electronic hardware-in-the-loop device or the actual equipment. The frequency interval is as follows:

[0177] When the frequency is 1 - 10 Hz, the step size is 0.1 Hz, and each step lasts for no less than 10 s;

[0178] When the frequency is 10 - 100 Hz, the step size is 1 Hz, and each step lasts for no less than 5 s;

[0179] When the frequency is 100 - 2500 Hz, the step size is 10 Hz, and each step lasts for no less than 2 s.

[0180] Among them, measuring the second impedance characteristic curve of the power electronic hardware - in - the - loop device or the actual equipment includes:

[0181] Using the fft algorithm to calculate the positive - sequence voltage, positive - sequence current, negative - sequence voltage and negative - sequence current of the simulation model at the corresponding frequency, calculating the positive - sequence impedance and negative - sequence impedance according to the positive - sequence voltage, positive - sequence current, negative - sequence voltage and negative - sequence current, and drawing the second impedance characteristic curve according to the positive - sequence impedance and negative - sequence impedance.

[0182] Among them, the second impedance characteristic includes: when P = 0.1 - 0.9, the impedance characteristics under Q = maximum inductive reactive power and Q = maximum capacitive reactive power.

[0183] Among them, using the sliding error method to verify the accuracy of the simulation model of the power electronic hardware - in - the - loop device or the actual equipment according to the first impedance characteristic and the second impedance characteristic includes:

[0184] Using the sliding error method, setting the number of sampling points in the sliding window, based on the set number of sampling points in the sliding window, calculating the first sliding average of the impedance amplitude and impedance phase of the power electronic hardware - in - the - loop device or the actual equipment according to the first impedance characteristic, based on the set number of sampling points in the sliding window, calculating the second sliding average of the impedance amplitude and impedance phase of the simulation model according to the second impedance characteristic, calculating the sliding error based on the first sliding average and the second sliding average, and verifying the accuracy of the simulation model based on the sliding error.

[0185] Among them, the sliding error includes: the sliding error of the positive / negative - sequence impedance amplitude and the sliding error of the positive / negative - sequence impedance phase;

[0186] If both the sliding error of the positive - sequence impedance amplitude and the sliding error of the negative - sequence impedance amplitude are less than 5 db, and both the sliding error of the positive - sequence impedance phase and the sliding error of the negative - sequence impedance phase are less than 5°, it is determined that the simulation model meets the error requirements, that is, the simulation model meets the accuracy requirements.

[0187] The present invention uses the sliding error method to verify the accuracy of the simulation model, and can accurately verify the accuracy of the impedance characteristics of the new - energy unit.

[0188] Embodiment 3:

[0189] Based on the same inventive concept, the present invention further provides a computer device, which includes a processor and a memory. The memory is used to store a computer program, and the computer program includes program instructions. The processor is used to execute the program instructions stored in the computer storage medium. The processor may be a Central Processing Unit (CPU), or may also be other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. It is the computing core and control core of the terminal, and is suitable for implementing one or more instructions. Specifically, it is suitable for loading and executing one or more instructions in the computer storage medium to implement the corresponding method flow or corresponding function, so as to implement the steps of the method in the above embodiment.

[0190] Embodiment 4:

[0191] Based on the same inventive concept, the present invention further provides a storage medium, specifically a computer-readable storage medium (Memory). The computer-readable storage medium is a memory device in the computer device and is used to store programs and data. It can be understood that the computer-readable storage medium here can include both the built-in storage medium in the computer device and, of course, the extended storage medium supported by the computer device. The computer-readable storage medium provides a storage space, and this storage space stores the operating system of the terminal. And, one or more instructions suitable for being loaded and executed by the processor are also stored in this storage space. These instructions can be one or more computer programs (including program codes). It should be noted that the computer-readable storage medium here can be a high-speed RAM memory or a non-volatile memory, such as at least one disk memory. The one or more instructions stored in the computer-readable storage medium can be loaded and executed by the processor to implement the steps of the method in the above embodiment.

[0192] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, a system, or a computer program product. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memory, CD-ROM, optical memory, etc.) containing computer-usable program code. The solutions in the embodiments of the present invention can be implemented using various computer languages. For example, object-oriented programming languages such as Java and interpreted scripting languages such as JavaScript.

[0193] The present invention is described with reference to the flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each flow and / or block in the flowchart and / or block diagram, as well as the combination of flows and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing devices generate means for implementing the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0194] These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory generate a manufactured product including instruction means, and the instruction means implement the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0195] These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process. Thus, the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0196] Although the preferred embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications to these embodiments once they know the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present invention.

[0197] Obviously, those skilled in the art can make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these modifications and variations.

Claims

1. A method for verifying the accuracy of an impedance model of a power electronic device, characterized in that: include: Measure the first impedance characteristics of power electronic semi-physical devices or actual equipment; Measuring the second impedance characteristics of power electronic hardware-in-the-loop devices or simulation models of actual equipment; The sliding error method is used to verify the accuracy of the power electronic hardware-in-the-loop device or the actual equipment simulation model based on the first impedance characteristic and the second impedance characteristic.

2. The method according to claim 1, characterized in that The power electronics semi-physical device or actual equipment includes: wind power, photovoltaic, energy storage or SVG semi-physical device or actual equipment.

3. The method according to claim 1, characterized in that The measuring of the first impedance characteristic of the power electronic hardware-in-the-loop device or the actual equipment includes: A preset method is used to inject a harmonic power signal into the power electronic semi-physical device or actual equipment. After the harmonic power signal is injected, a first impedance characteristic curve of the power electronic semi-physical device or actual equipment is measured, and the first impedance characteristic is determined based on the first impedance characteristic curve.

4. The method according to claim 3, characterized in that The injected harmonic power signal is divided into a positive sequence harmonic signal fp and a negative sequence harmonic signal fn. The disturbance voltage amplitude of the harmonic power signal is 1% to 5% of the rated voltage amplitude of the power electronic semi-physical device or the actual equipment. The frequency interval is as follows: When the frequency is 1-10Hz, the step size is 0.1Hz, and each step size lasts no less than 10s; When the frequency is 10-100 Hz, the step size is 1 Hz, and each step size lasts no less than 5 seconds; When the frequency is 100-2500 Hz, the step size is 10 Hz, and each step size lasts no less than 2 seconds.

5. The method according to claim 3, characterized in that The measuring of the first impedance characteristic curve of the power electronic hardware-in-the-loop device or the actual equipment includes: The positive-sequence voltage, positive-sequence current, negative-sequence voltage, and negative-sequence current of a power electronic semi-physical device or actual equipment at a corresponding frequency are calculated using an FFT algorithm. The positive-sequence impedance and negative-sequence impedance are calculated based on the positive-sequence voltage, positive-sequence current, negative-sequence voltage, and negative-sequence current. A first impedance characteristic curve is drawn based on the positive-sequence impedance and negative-sequence impedance.

6. The method according to claim 3, characterized in that The first impedance characteristics include: impedance characteristics when P=0.1-0.9, Q=maximum inductive reactive power and Q=maximum capacitive reactive power.

7. The method according to claim 1, characterized in that The measuring of the second impedance characteristic of the power electronic hardware-in-the-loop device or the actual equipment simulation model includes: A preset method is used to inject a harmonic power signal into the power electronic semi-physical device or the actual equipment simulation model, and the system equivalent impedance and the box transformer parameters are kept consistent. After the harmonic power signal is injected, the second impedance characteristic curve of the simulation model is measured, and the second impedance characteristic is determined based on the second impedance characteristic curve.

8. The method according to claim 7, characterized in that The injected harmonic power signal is divided into a positive sequence harmonic signal fp and a negative sequence harmonic signal fn. The disturbance voltage amplitude of the harmonic power signal is 1% to 5% of the rated voltage amplitude of the power electronic semi-physical device or the actual equipment. The frequency interval is as follows: When the frequency is 1-10Hz, the step size is 0.1Hz, and each step size lasts no less than 10s; When the frequency is 10-100 Hz, the step size is 1 Hz, and each step size lasts no less than 5 seconds; When the frequency is 100-2500 Hz, the step size is 10 Hz, and each step size lasts no less than 2 seconds.

9. The method according to claim 7, characterized in that The measuring of the second impedance characteristic curve of the power electronic hardware-in-the-loop device or the actual equipment includes: The FFT algorithm is used to calculate the positive-sequence voltage, positive-sequence current, negative-sequence voltage and negative-sequence current of the simulation model at the corresponding frequency. The positive-sequence impedance and negative-sequence impedance are calculated based on the positive-sequence voltage, positive-sequence current, negative-sequence voltage and negative-sequence current. A second impedance characteristic curve is drawn based on the positive-sequence impedance and negative-sequence impedance.

10. The method according to claim 7, characterized in that The second impedance characteristics include: impedance characteristics when P=0.1-0.9, Q=maximum inductive reactive power and Q=maximum capacitive reactive power.

11. The method according to claim 1, wherein The method of using a sliding error method to verify the accuracy of the power electronic hardware-in-the-loop device or the actual equipment simulation model according to the first impedance characteristic and the second impedance characteristic includes: A sliding error method is adopted, the number of sliding window sampling points is set, and based on the set number of sliding window sampling points and according to the first impedance characteristic, a first sliding average value of the impedance amplitude and the impedance phase of the power electronic semi-physical device or the actual equipment is calculated; based on the set number of sliding window sampling points and according to the second impedance characteristic, a second sliding average value of the impedance amplitude and the impedance phase of the simulation model is calculated; based on the first sliding average value and the second sliding average value, a sliding error is calculated; and based on the sliding error, the accuracy of the simulation model is verified.

12. The method according to claim 11, characterized in that The sliding error includes: a sliding error of the positive / negative sequence impedance amplitude and a sliding error of the positive / negative sequence impedance phase; If the sliding error of the positive-sequence impedance amplitude and the sliding error of the negative-sequence impedance amplitude are both required to be less than 5 dB, and the sliding error of the positive-sequence impedance phase and the sliding error of the negative-sequence impedance phase are both less than 5°, then it is determined that the simulation model meets the error requirements, that is, the simulation model meets the accuracy requirements.

13. A system for verifying the accuracy of an impedance model of a power electronic device, characterized in that: include: A first measuring unit is used to measure a first impedance characteristic of a power electronic hardware-in-the-loop device or an actual device; a second measuring unit for measuring a second impedance characteristic of a power electronic hardware-in-the-loop device or a simulation model of an actual device; The verification unit is configured to verify the accuracy of the power electronic hardware-in-the-loop device or the actual equipment simulation model based on the first impedance characteristic and the second impedance characteristic by using a sliding error method.

14. The system according to claim 13, wherein: The power electronics semi-physical device or actual equipment includes: wind power, photovoltaic, energy storage or SVG semi-physical device or actual equipment.

15. The system according to claim 13, wherein: The measuring of the first impedance characteristic of the power electronic hardware-in-the-loop device or the actual equipment includes: A preset method is used to inject a harmonic power signal into the power electronic semi-physical device or actual equipment. After the harmonic power signal is injected, a first impedance characteristic curve of the power electronic semi-physical device or actual equipment is measured, and the first impedance characteristic is determined based on the first impedance characteristic curve.

16. The system according to claim 15, wherein: The injected harmonic power signal is divided into a positive sequence harmonic signal fp and a negative sequence harmonic signal fn. The disturbance voltage amplitude of the harmonic power signal is 1% to 5% of the rated voltage amplitude of the power electronic semi-physical device or the actual equipment. The frequency interval is as follows: When the frequency is 1-10Hz, the step size is 0.1Hz, and each step size lasts no less than 10s; When the frequency is 10-100 Hz, the step size is 1 Hz, and each step size lasts no less than 5 seconds; When the frequency is 100-2500 Hz, the step size is 10 Hz, and each step size lasts no less than 2 seconds.

17. The system according to claim 15, wherein: The measuring of the first impedance characteristic curve of the power electronic hardware-in-the-loop device or the actual equipment includes: The positive-sequence voltage, positive-sequence current, negative-sequence voltage, and negative-sequence current of a power electronic semi-physical device or actual equipment at a corresponding frequency are calculated using an FFT algorithm. The positive-sequence impedance and negative-sequence impedance are calculated based on the positive-sequence voltage, positive-sequence current, negative-sequence voltage, and negative-sequence current. A first impedance characteristic curve is drawn based on the positive-sequence impedance and negative-sequence impedance.

18. The system according to claim 15, wherein: The first impedance characteristics include: impedance characteristics when P=0.1-0.9, Q=maximum inductive reactive power and Q=maximum capacitive reactive power.

19. The system according to claim 15, wherein: The measuring of the second impedance characteristic of the power electronic hardware-in-the-loop device or the actual equipment simulation model includes: A preset method is used to inject a harmonic power signal into the power electronic semi-physical device or the actual equipment simulation model, and the system equivalent impedance and the box transformer parameters are kept consistent. After the harmonic power signal is injected, the second impedance characteristic curve of the simulation model is measured, and the second impedance characteristic is determined based on the second impedance characteristic curve.

20. The system according to claim 19, wherein: The injected harmonic power signal is divided into a positive sequence harmonic signal fp and a negative sequence harmonic signal fn. The disturbance voltage amplitude of the harmonic power signal is 1% to 5% of the rated voltage amplitude of the power electronic semi-physical device or the actual equipment. The frequency interval is as follows: When the frequency is 1-10Hz, the step size is 0.1Hz, and each step size lasts no less than 10s; When the frequency is 10-100 Hz, the step size is 1 Hz, and each step size lasts no less than 5 seconds; When the frequency is 100-2500 Hz, the step size is 10 Hz, and each step size lasts no less than 2 seconds.

21. The system according to claim 19, wherein: The measuring of the second impedance characteristic curve of the power electronic hardware-in-the-loop device or the actual equipment includes: The FFT algorithm is used to calculate the positive-sequence voltage, positive-sequence current, negative-sequence voltage and negative-sequence current of the simulation model at the corresponding frequency. The positive-sequence impedance and negative-sequence impedance are calculated based on the positive-sequence voltage, positive-sequence current, negative-sequence voltage and negative-sequence current. A second impedance characteristic curve is drawn based on the positive-sequence impedance and negative-sequence impedance.

22. The system according to claim 19, wherein: The second impedance characteristics include: impedance characteristics when P=0.1-0.9, Q=maximum inductive reactive power and Q=maximum capacitive reactive power.

23. The system according to claim 13, wherein: The method of using a sliding error method to verify the accuracy of the power electronic hardware-in-the-loop device or the actual equipment simulation model according to the first impedance characteristic and the second impedance characteristic includes: A sliding error method is adopted, the number of sliding window sampling points is set, and based on the set number of sliding window sampling points and according to the first impedance characteristic, a first sliding average value of the impedance amplitude and the impedance phase of the power electronic semi-physical device or the actual equipment is calculated; based on the set number of sliding window sampling points and according to the second impedance characteristic, a second sliding average value of the impedance amplitude and the impedance phase of the simulation model is calculated; based on the first sliding average value and the second sliding average value, a sliding error is calculated; and based on the sliding error, the accuracy of the simulation model is verified.

24. The system according to claim 23, wherein: The sliding error includes: a sliding error of the positive / negative sequence impedance amplitude and a sliding error of the positive / negative sequence impedance phase; If the sliding error of the positive-sequence impedance amplitude and the sliding error of the negative-sequence impedance amplitude are both required to be less than 5 dB, and the sliding error of the positive-sequence impedance phase and the sliding error of the negative-sequence impedance phase are both less than 5°, then it is determined that the simulation model meets the error requirements, that is, the simulation model meets the accuracy requirements.

25. A computer device, characterized in that: include: one or more processors; a processor for executing one or more programs; When the one or more programs are executed by the one or more processors, the method according to any one of claims 1 to 12 is implemented.

26. A computer-readable storage medium, characterized in that A computer program is stored thereon, and when the computer program is executed, the method according to any one of claims 1 to 12 is implemented.

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